Lee Kai Xuan / mbed-os

mbed-os

Fork of mbed-os by erkin yucel

targets/TARGET_NXP/TARGET_LPC43XX/device/LPC43xx.h@1:3deb71413561, 2017-07-20 (annotated)

Committer:
xuaner
Date:
Thu Jul 20 14:26:57 2017 +0000
Revision:
1:3deb71413561
Parent:
0:f269e3021894 
mbed_os

Who changed what in which revision?

UserRevisionLine numberNew contents of line
elessair 0:f269e3021894 1 /*
elessair 0:f269e3021894 2 * LPC43xx/LPC18xx MCU header
elessair 0:f269e3021894 3 *
elessair 0:f269e3021894 4 * Copyright(C) NXP Semiconductors, 2012
elessair 0:f269e3021894 5 * All rights reserved.
elessair 0:f269e3021894 6 *
elessair 0:f269e3021894 7 * Software that is described herein is for illustrative purposes only
elessair 0:f269e3021894 8 * which provides customers with programming information regarding the
elessair 0:f269e3021894 9 * LPC products. This software is supplied "AS IS" without any warranties of
elessair 0:f269e3021894 10 * any kind, and NXP Semiconductors and its licensor disclaim any and
elessair 0:f269e3021894 11 * all warranties, express or implied, including all implied warranties of
elessair 0:f269e3021894 12 * merchantability, fitness for a particular purpose and non-infringement of
elessair 0:f269e3021894 13 * intellectual property rights. NXP Semiconductors assumes no responsibility
elessair 0:f269e3021894 14 * or liability for the use of the software, conveys no license or rights under any
elessair 0:f269e3021894 15 * patent, copyright, mask work right, or any other intellectual property rights in
elessair 0:f269e3021894 16 * or to any products. NXP Semiconductors reserves the right to make changes
elessair 0:f269e3021894 17 * in the software without notification. NXP Semiconductors also makes no
elessair 0:f269e3021894 18 * representation or warranty that such application will be suitable for the
elessair 0:f269e3021894 19 * specified use without further testing or modification.
elessair 0:f269e3021894 20 *
elessair 0:f269e3021894 21 * Permission to use, copy, modify, and distribute this software and its
elessair 0:f269e3021894 22 * documentation is hereby granted, under NXP Semiconductors' and its
elessair 0:f269e3021894 23 * licensor's relevant copyrights in the software, without fee, provided that it
elessair 0:f269e3021894 24 * is used in conjunction with NXP Semiconductors microcontrollers. This
elessair 0:f269e3021894 25 * copyright, permission, and disclaimer notice must appear in all copies of
elessair 0:f269e3021894 26 * this code.
elessair 0:f269e3021894 27 *
elessair 0:f269e3021894 28 * Simplified version of NXP LPCOPEN LPC43XX/LPC18XX headers
elessair 0:f269e3021894 29 * 05/15/13 Micromint USA <support@micromint.com>
elessair 0:f269e3021894 30 */
elessair 0:f269e3021894 31
elessair 0:f269e3021894 32 #ifndef __LPC43XX_H
elessair 0:f269e3021894 33 #define __LPC43XX_H
elessair 0:f269e3021894 34
elessair 0:f269e3021894 35 #ifdef __cplusplus
elessair 0:f269e3021894 36 extern "C" {
elessair 0:f269e3021894 37 #endif
elessair 0:f269e3021894 38
elessair 0:f269e3021894 39 /* Treat __CORE_Mx as CORE_Mx */
elessair 0:f269e3021894 40 #if defined(__CORTEX_M0) && !defined(CORE_M0)
elessair 0:f269e3021894 41 #define CORE_M0
elessair 0:f269e3021894 42 #endif
elessair 0:f269e3021894 43 #if defined(__CORTEX_M3) && !defined(CORE_M3)
elessair 0:f269e3021894 44 #define CORE_M3
elessair 0:f269e3021894 45 #endif
elessair 0:f269e3021894 46 /* Default to M4 core if no core explicitly declared */
elessair 0:f269e3021894 47 #if !defined(CORE_M0) && !defined(CORE_M3)
elessair 0:f269e3021894 48 #define CORE_M4
elessair 0:f269e3021894 49 #endif
elessair 0:f269e3021894 50
elessair 0:f269e3021894 51 /* Define LPC18XX or LPC43XX according to core type */
elessair 0:f269e3021894 52 #if (defined(CORE_M4) || defined(CORE_M0)) && !defined(__LPC43XX__)
elessair 0:f269e3021894 53 #define __LPC43XX__
elessair 0:f269e3021894 54 #endif
elessair 0:f269e3021894 55 #if defined(CORE_M3) && !defined(__LPC18XX__)
elessair 0:f269e3021894 56 #define __LPC18XX__
elessair 0:f269e3021894 57 #endif
elessair 0:f269e3021894 58
elessair 0:f269e3021894 59 /* Start of section using anonymous unions */
elessair 0:f269e3021894 60 #if defined(__ARMCC_VERSION)
elessair 0:f269e3021894 61 // Kill warning "#pragma push with no matching #pragma pop"
elessair 0:f269e3021894 62 #pragma diag_suppress 2525
elessair 0:f269e3021894 63 #pragma push
elessair 0:f269e3021894 64 #pragma anon_unions
elessair 0:f269e3021894 65 #elif defined(__CWCC__)
elessair 0:f269e3021894 66 #pragma push
elessair 0:f269e3021894 67 #pragma cpp_extensions on
elessair 0:f269e3021894 68 #elif defined(__IAR_SYSTEMS_ICC__)
elessair 0:f269e3021894 69 //#pragma push // FIXME not usable for IAR
elessair 0:f269e3021894 70 #pragma language=extended
elessair 0:f269e3021894 71 #else /* defined(__GNUC__) and others */
elessair 0:f269e3021894 72 /* Assume anonymous unions are enabled by default */
elessair 0:f269e3021894 73 #endif
elessair 0:f269e3021894 74
elessair 0:f269e3021894 75 #if defined(CORE_M4)
elessair 0:f269e3021894 76 /* ---------------------------------------------------------------------------
elessair 0:f269e3021894 77 * LPC43xx (M4 Core) Cortex CMSIS definitions
elessair 0:f269e3021894 78 */
elessair 0:f269e3021894 79
elessair 0:f269e3021894 80 #define __CM4_REV 0x0000 /* Cortex-M4 Core Revision */
elessair 0:f269e3021894 81 #define __MPU_PRESENT 1 /* MPU present or not */
elessair 0:f269e3021894 82 #define __NVIC_PRIO_BITS 3 /* Number of Bits used for Priority Levels */
elessair 0:f269e3021894 83 #define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
elessair 0:f269e3021894 84 #define __FPU_PRESENT 1 /* FPU present or not */
elessair 0:f269e3021894 85 #define CHIP_LPC43XX /* LPCOPEN compatibility */
elessair 0:f269e3021894 86
elessair 0:f269e3021894 87 /* ---------------------------------------------------------------------------
elessair 0:f269e3021894 88 * LPC43xx peripheral interrupt numbers
elessair 0:f269e3021894 89 */
elessair 0:f269e3021894 90
elessair 0:f269e3021894 91 typedef enum {
elessair 0:f269e3021894 92 /* --------------- Cortex-M4 Processor Exceptions Numbers ------------------- */
elessair 0:f269e3021894 93 Reset_IRQn = -15,/* 1 Reset Vector, invoked on Power up and warm reset */
elessair 0:f269e3021894 94 NonMaskableInt_IRQn = -14,/* 2 Non maskable Interrupt, cannot be stopped or preempted */
elessair 0:f269e3021894 95 HardFault_IRQn = -13,/* 3 Hard Fault, all classes of Fault */
elessair 0:f269e3021894 96 MemoryManagement_IRQn = -12,/* 4 Memory Management, MPU mismatch, including Access Violation and No Match */
elessair 0:f269e3021894 97 BusFault_IRQn = -11,/* 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
elessair 0:f269e3021894 98 UsageFault_IRQn = -10,/* 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
elessair 0:f269e3021894 99 SVCall_IRQn = -5,/* 11 System Service Call via SVC instruction */
elessair 0:f269e3021894 100 DebugMonitor_IRQn = -4,/* 12 Debug Monitor */
elessair 0:f269e3021894 101 PendSV_IRQn = -2,/* 14 Pendable request for system service */
elessair 0:f269e3021894 102 SysTick_IRQn = -1,/* 15 System Tick Timer */
elessair 0:f269e3021894 103
elessair 0:f269e3021894 104 /* ----------------- LPC18xx/43xx Specific Interrupt Numbers --------------------- */
elessair 0:f269e3021894 105 DAC_IRQn = 0,/* 0 DAC */
elessair 0:f269e3021894 106 M0CORE_IRQn = 1,/* 1 M0a */
elessair 0:f269e3021894 107 DMA_IRQn = 2,/* 2 DMA */
elessair 0:f269e3021894 108 RESERVED1_IRQn = 3,/* 3 EZH/EDM */
elessair 0:f269e3021894 109 RESERVED2_IRQn = 4,
elessair 0:f269e3021894 110 ETHERNET_IRQn = 5,/* 5 ETHERNET */
elessair 0:f269e3021894 111 SDIO_IRQn = 6,/* 6 SDIO */
elessair 0:f269e3021894 112 LCD_IRQn = 7,/* 7 LCD */
elessair 0:f269e3021894 113 USB0_IRQn = 8,/* 8 USB0 */
elessair 0:f269e3021894 114 USB1_IRQn = 9,/* 9 USB1 */
elessair 0:f269e3021894 115 SCT_IRQn = 10,/* 10 SCT */
elessair 0:f269e3021894 116 RITIMER_IRQn = 11,/* 11 RITIMER */
elessair 0:f269e3021894 117 TIMER0_IRQn = 12,/* 12 TIMER0 */
elessair 0:f269e3021894 118 TIMER1_IRQn = 13,/* 13 TIMER1 */
elessair 0:f269e3021894 119 TIMER2_IRQn = 14,/* 14 TIMER2 */
elessair 0:f269e3021894 120 TIMER3_IRQn = 15,/* 15 TIMER3 */
elessair 0:f269e3021894 121 MCPWM_IRQn = 16,/* 16 MCPWM */
elessair 0:f269e3021894 122 ADC0_IRQn = 17,/* 17 ADC0 */
elessair 0:f269e3021894 123 I2C0_IRQn = 18,/* 18 I2C0 */
elessair 0:f269e3021894 124 I2C1_IRQn = 19,/* 19 I2C1 */
elessair 0:f269e3021894 125 SPI_INT_IRQn = 20,/* 20 SPI_INT */
elessair 0:f269e3021894 126 ADC1_IRQn = 21,/* 21 ADC1 */
elessair 0:f269e3021894 127 SSP0_IRQn = 22,/* 22 SSP0 */
elessair 0:f269e3021894 128 SSP1_IRQn = 23,/* 23 SSP1 */
elessair 0:f269e3021894 129 USART0_IRQn = 24,/* 24 USART0 */
elessair 0:f269e3021894 130 UART1_IRQn = 25,/* 25 UART1 */
elessair 0:f269e3021894 131 USART2_IRQn = 26,/* 26 USART2 */
elessair 0:f269e3021894 132 USART3_IRQn = 27,/* 27 USART3 */
elessair 0:f269e3021894 133 I2S0_IRQn = 28,/* 28 I2S0 */
elessair 0:f269e3021894 134 I2S1_IRQn = 29,/* 29 I2S1 */
elessair 0:f269e3021894 135 RESERVED4_IRQn = 30,
elessair 0:f269e3021894 136 SGPIO_INT_IRQn = 31,/* 31 SGPIO_IINT */
elessair 0:f269e3021894 137 PIN_INT0_IRQn = 32,/* 32 PIN_INT0 */
elessair 0:f269e3021894 138 PIN_INT1_IRQn = 33,/* 33 PIN_INT1 */
elessair 0:f269e3021894 139 PIN_INT2_IRQn = 34,/* 34 PIN_INT2 */
elessair 0:f269e3021894 140 PIN_INT3_IRQn = 35,/* 35 PIN_INT3 */
elessair 0:f269e3021894 141 PIN_INT4_IRQn = 36,/* 36 PIN_INT4 */
elessair 0:f269e3021894 142 PIN_INT5_IRQn = 37,/* 37 PIN_INT5 */
elessair 0:f269e3021894 143 PIN_INT6_IRQn = 38,/* 38 PIN_INT6 */
elessair 0:f269e3021894 144 PIN_INT7_IRQn = 39,/* 39 PIN_INT7 */
elessair 0:f269e3021894 145 GINT0_IRQn = 40,/* 40 GINT0 */
elessair 0:f269e3021894 146 GINT1_IRQn = 41,/* 41 GINT1 */
elessair 0:f269e3021894 147 EVENTROUTER_IRQn = 42,/* 42 EVENTROUTER */
elessair 0:f269e3021894 148 C_CAN1_IRQn = 43,/* 43 C_CAN1 */
elessair 0:f269e3021894 149 RESERVED6_IRQn = 44,
elessair 0:f269e3021894 150 RESERVED7_IRQn = 45,/* 45 VADC */
elessair 0:f269e3021894 151 ATIMER_IRQn = 46,/* 46 ATIMER */
elessair 0:f269e3021894 152 RTC_IRQn = 47,/* 47 RTC */
elessair 0:f269e3021894 153 RESERVED8_IRQn = 48,
elessair 0:f269e3021894 154 WWDT_IRQn = 49,/* 49 WWDT */
elessair 0:f269e3021894 155 RESERVED9_IRQn = 50,
elessair 0:f269e3021894 156 C_CAN0_IRQn = 51,/* 51 C_CAN0 */
elessair 0:f269e3021894 157 QEI_IRQn = 52,/* 52 QEI */
elessair 0:f269e3021894 158 } IRQn_Type;
elessair 0:f269e3021894 159
elessair 0:f269e3021894 160 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
elessair 0:f269e3021894 161
elessair 0:f269e3021894 162 #elif defined(CORE_M3)
elessair 0:f269e3021894 163 /* ---------------------------------------------------------------------------
elessair 0:f269e3021894 164 * LPC18xx (M3 Core) Cortex CMSIS definitions
elessair 0:f269e3021894 165 */
elessair 0:f269e3021894 166 #define __MPU_PRESENT 1 /* MPU present or not */
elessair 0:f269e3021894 167 #define __NVIC_PRIO_BITS 3 /* Number of Bits used for Priority Levels */
elessair 0:f269e3021894 168 #define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
elessair 0:f269e3021894 169 #define __FPU_PRESENT 0 /* FPU present or not */
elessair 0:f269e3021894 170 #define CHIP_LPC18XX /* LPCOPEN compatibility */
elessair 0:f269e3021894 171
elessair 0:f269e3021894 172 /* ---------------------------------------------------------------------------
elessair 0:f269e3021894 173 * LPC18xx peripheral interrupt numbers
elessair 0:f269e3021894 174 */
elessair 0:f269e3021894 175
elessair 0:f269e3021894 176 typedef enum {
elessair 0:f269e3021894 177 /* --------------- Cortex-M3 Processor Exceptions Numbers ------------------- */
elessair 0:f269e3021894 178 Reset_IRQn = -15,/* 1 Reset Vector, invoked on Power up and warm reset */
elessair 0:f269e3021894 179 NonMaskableInt_IRQn = -14,/* 2 Non maskable Interrupt, cannot be stopped or preempted */
elessair 0:f269e3021894 180 HardFault_IRQn = -13,/* 3 Hard Fault, all classes of Fault */
elessair 0:f269e3021894 181 MemoryManagement_IRQn = -12,/* 4 Memory Management, MPU mismatch, including Access Violation and No Match */
elessair 0:f269e3021894 182 BusFault_IRQn = -11,/* 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
elessair 0:f269e3021894 183 UsageFault_IRQn = -10,/* 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
elessair 0:f269e3021894 184 SVCall_IRQn = -5,/* 11 System Service Call via SVC instruction */
elessair 0:f269e3021894 185 DebugMonitor_IRQn = -4,/* 12 Debug Monitor */
elessair 0:f269e3021894 186 PendSV_IRQn = -2,/* 14 Pendable request for system service */
elessair 0:f269e3021894 187 SysTick_IRQn = -1,/* 15 System Tick Timer */
elessair 0:f269e3021894 188
elessair 0:f269e3021894 189 /* ----------------- LPC18xx/43xx Specific Interrupt Numbers --------------------- */
elessair 0:f269e3021894 190 DAC_IRQn = 0,/* 0 DAC */
elessair 0:f269e3021894 191 RESERVED0_IRQn = 1,
elessair 0:f269e3021894 192 DMA_IRQn = 2,/* 2 DMA */
elessair 0:f269e3021894 193 RESERVED1_IRQn = 3,/* 3 EZH/EDM */
elessair 0:f269e3021894 194 RESERVED2_IRQn = 4,
elessair 0:f269e3021894 195 ETHERNET_IRQn = 5,/* 5 ETHERNET */
elessair 0:f269e3021894 196 SDIO_IRQn = 6,/* 6 SDIO */
elessair 0:f269e3021894 197 LCD_IRQn = 7,/* 7 LCD */
elessair 0:f269e3021894 198 USB0_IRQn = 8,/* 8 USB0 */
elessair 0:f269e3021894 199 USB1_IRQn = 9,/* 9 USB1 */
elessair 0:f269e3021894 200 SCT_IRQn = 10,/* 10 SCT */
elessair 0:f269e3021894 201 RITIMER_IRQn = 11,/* 11 RITIMER */
elessair 0:f269e3021894 202 TIMER0_IRQn = 12,/* 12 TIMER0 */
elessair 0:f269e3021894 203 TIMER1_IRQn = 13,/* 13 TIMER1 */
elessair 0:f269e3021894 204 TIMER2_IRQn = 14,/* 14 TIMER2 */
elessair 0:f269e3021894 205 TIMER3_IRQn = 15,/* 15 TIMER3 */
elessair 0:f269e3021894 206 MCPWM_IRQn = 16,/* 16 MCPWM */
elessair 0:f269e3021894 207 ADC0_IRQn = 17,/* 17 ADC0 */
elessair 0:f269e3021894 208 I2C0_IRQn = 18,/* 18 I2C0 */
elessair 0:f269e3021894 209 I2C1_IRQn = 19,/* 19 I2C1 */
elessair 0:f269e3021894 210 RESERVED3_IRQn = 20,
elessair 0:f269e3021894 211 ADC1_IRQn = 21,/* 21 ADC1 */
elessair 0:f269e3021894 212 SSP0_IRQn = 22,/* 22 SSP0 */
elessair 0:f269e3021894 213 SSP1_IRQn = 23,/* 23 SSP1 */
elessair 0:f269e3021894 214 USART0_IRQn = 24,/* 24 USART0 */
elessair 0:f269e3021894 215 UART1_IRQn = 25,/* 25 UART1 */
elessair 0:f269e3021894 216 USART2_IRQn = 26,/* 26 USART2 */
elessair 0:f269e3021894 217 USART3_IRQn = 27,/* 27 USART3 */
elessair 0:f269e3021894 218 I2S0_IRQn = 28,/* 28 I2S0 */
elessair 0:f269e3021894 219 I2S1_IRQn = 29,/* 29 I2S1 */
elessair 0:f269e3021894 220 RESERVED4_IRQn = 30,
elessair 0:f269e3021894 221 RESERVED5_IRQn = 31,
elessair 0:f269e3021894 222 PIN_INT0_IRQn = 32,/* 32 PIN_INT0 */
elessair 0:f269e3021894 223 PIN_INT1_IRQn = 33,/* 33 PIN_INT1 */
elessair 0:f269e3021894 224 PIN_INT2_IRQn = 34,/* 34 PIN_INT2 */
elessair 0:f269e3021894 225 PIN_INT3_IRQn = 35,/* 35 PIN_INT3 */
elessair 0:f269e3021894 226 PIN_INT4_IRQn = 36,/* 36 PIN_INT4 */
elessair 0:f269e3021894 227 PIN_INT5_IRQn = 37,/* 37 PIN_INT5 */
elessair 0:f269e3021894 228 PIN_INT6_IRQn = 38,/* 38 PIN_INT6 */
elessair 0:f269e3021894 229 PIN_INT7_IRQn = 39,/* 39 PIN_INT7 */
elessair 0:f269e3021894 230 GINT0_IRQn = 40,/* 40 GINT0 */
elessair 0:f269e3021894 231 GINT1_IRQn = 41,/* 41 GINT1 */
elessair 0:f269e3021894 232 EVENTROUTER_IRQn = 42,/* 42 EVENTROUTER */
elessair 0:f269e3021894 233 C_CAN1_IRQn = 43,/* 43 C_CAN1 */
elessair 0:f269e3021894 234 RESERVED6_IRQn = 44,
elessair 0:f269e3021894 235 RESERVED7_IRQn = 45,/* 45 VADC */
elessair 0:f269e3021894 236 ATIMER_IRQn = 46,/* 46 ATIMER */
elessair 0:f269e3021894 237 RTC_IRQn = 47,/* 47 RTC */
elessair 0:f269e3021894 238 RESERVED8_IRQn = 48,
elessair 0:f269e3021894 239 WWDT_IRQn = 49,/* 49 WWDT */
elessair 0:f269e3021894 240 RESERVED9_IRQn = 50,
elessair 0:f269e3021894 241 C_CAN0_IRQn = 51,/* 51 C_CAN0 */
elessair 0:f269e3021894 242 QEI_IRQn = 52,/* 52 QEI */
elessair 0:f269e3021894 243 } IRQn_Type;
elessair 0:f269e3021894 244
elessair 0:f269e3021894 245 #include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
elessair 0:f269e3021894 246
elessair 0:f269e3021894 247 #elif defined(CORE_M0)
elessair 0:f269e3021894 248 /* ---------------------------------------------------------------------------
elessair 0:f269e3021894 249 * LPC43xx (M0 Core) Cortex CMSIS definitions
elessair 0:f269e3021894 250 */
elessair 0:f269e3021894 251
elessair 0:f269e3021894 252 #define __MPU_PRESENT 0 /* MPU present or not */
elessair 0:f269e3021894 253 #define __NVIC_PRIO_BITS 2 /* Number of Bits used for Priority Levels */
elessair 0:f269e3021894 254 #define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
elessair 0:f269e3021894 255 #define __FPU_PRESENT 0 /* FPU present or not */
elessair 0:f269e3021894 256 #define CHIP_LPC43XX /* LPCOPEN compatibility */
elessair 0:f269e3021894 257
elessair 0:f269e3021894 258 /* ---------------------------------------------------------------------------
elessair 0:f269e3021894 259 * LPC43xx (M0 Core) peripheral interrupt numbers
elessair 0:f269e3021894 260 */
elessair 0:f269e3021894 261
elessair 0:f269e3021894 262 typedef enum {
elessair 0:f269e3021894 263 /* --------------- Cortex-M0 Processor Exceptions Numbers ------------------- */
elessair 0:f269e3021894 264 Reset_IRQn = -15,/* 1 Reset Vector, invoked on Power up and warm reset */
elessair 0:f269e3021894 265 NonMaskableInt_IRQn = -14,/* 2 Non maskable Interrupt, cannot be stopped or preempted */
elessair 0:f269e3021894 266 HardFault_IRQn = -13,/* 3 Hard Fault, all classes of Fault */
elessair 0:f269e3021894 267 SVCall_IRQn = -5,/* 11 System Service Call via SVC instruction */
elessair 0:f269e3021894 268 DebugMonitor_IRQn = -4,/* 12 Debug Monitor */
elessair 0:f269e3021894 269 PendSV_IRQn = -2,/* 14 Pendable request for system service */
elessair 0:f269e3021894 270 SysTick_IRQn = -1,/* 15 System Tick Timer */
elessair 0:f269e3021894 271
elessair 0:f269e3021894 272 /* ----------------- LPC18xx/43xx Specific Interrupt Numbers --------------------- */
elessair 0:f269e3021894 273 DAC_IRQn = 0,/* 0 DAC */
elessair 0:f269e3021894 274 M0_M4CORE_IRQn = 1,/* 1 M0a */
elessair 0:f269e3021894 275 DMA_IRQn = 2,/* 2 DMA r */
elessair 0:f269e3021894 276 RESERVED1_IRQn = 3,/* 3 EZH/EDM */
elessair 0:f269e3021894 277 FLASHEEPROM_IRQn = 4,/* 4 ORed Flash EEPROM Bank A, B, EEPROM */
elessair 0:f269e3021894 278 ETHERNET_IRQn = 5,/* 5 ETHERNET */
elessair 0:f269e3021894 279 SDIO_IRQn = 6,/* 6 SDIO */
elessair 0:f269e3021894 280 LCD_IRQn = 7,/* 7 LCD */
elessair 0:f269e3021894 281 USB0_IRQn = 8,/* 8 USB0 */
elessair 0:f269e3021894 282 USB1_IRQn = 9,/* 9 USB1 */
elessair 0:f269e3021894 283 SCT_IRQn = 10,/* 10 SCT */
elessair 0:f269e3021894 284 RITIMER_IRQn = 11,/* 11 ORed RITIMER, WDT */
elessair 0:f269e3021894 285 TIMER0_IRQn = 12,/* 12 TIMER0 */
elessair 0:f269e3021894 286 GINT1_IRQn = 13,/* 13 GINT1 */
elessair 0:f269e3021894 287 PIN_INT4_IRQn = 14,/* 14 GPIO 4 */
elessair 0:f269e3021894 288 TIMER3_IRQn = 15,/* 15 TIMER3 */
elessair 0:f269e3021894 289 MCPWM_IRQn = 16,/* 16 MCPWM */
elessair 0:f269e3021894 290 ADC0_IRQn = 17,/* 17 ADC0 */
elessair 0:f269e3021894 291 I2C0_IRQn = 18,/* 18 ORed I2C0, I2C1 */
elessair 0:f269e3021894 292 SGPIO_INT_IRQn = 19,/* 19 SGPIO */
elessair 0:f269e3021894 293 SPI_INT_IRQn = 20,/* 20 SPI_INT */
elessair 0:f269e3021894 294 ADC1_IRQn = 21,/* 21 ADC1 */
elessair 0:f269e3021894 295 SSP0_IRQn = 22,/* 22 ORed SSP0, SSP1 */
elessair 0:f269e3021894 296 EVENTROUTER_IRQn = 23,/* 23 EVENTROUTER */
elessair 0:f269e3021894 297 USART0_IRQn = 24,/* 24 USART0 */
elessair 0:f269e3021894 298 UART1_IRQn = 25,/* 25 UART1 */
elessair 0:f269e3021894 299 USART2_IRQn = 26,/* 26 USART2 */
elessair 0:f269e3021894 300 USART3_IRQn = 27,/* 27 USART3 */
elessair 0:f269e3021894 301 I2S0_IRQn = 28,/* 28 ORed I2S0, I2S1 */
elessair 0:f269e3021894 302 C_CAN0_IRQn = 29,/* 29 C_CAN0 */
elessair 0:f269e3021894 303 I2S1_IRQn = 29,/* 29 I2S1 */
elessair 0:f269e3021894 304 RESERVED2_IRQn = 30,
elessair 0:f269e3021894 305 RESERVED3_IRQn = 31,
elessair 0:f269e3021894 306 } IRQn_Type;
elessair 0:f269e3021894 307
elessair 0:f269e3021894 308 #include "core_cm0.h" /* Cortex-M4 processor and core peripherals */
elessair 0:f269e3021894 309 #else
elessair 0:f269e3021894 310 #error Please #define CORE_M0, CORE_M3 or CORE_M4
elessair 0:f269e3021894 311 #endif
elessair 0:f269e3021894 312
elessair 0:f269e3021894 313 #include "system_LPC43xx.h"
elessair 0:f269e3021894 314
elessair 0:f269e3021894 315 /* ---------------------------------------------------------------------------
elessair 0:f269e3021894 316 * State Configurable Timer register block structure
elessair 0:f269e3021894 317 */
elessair 0:f269e3021894 318 #define LPC_SCT_BASE 0x40000000
elessair 0:f269e3021894 319 #define CONFIG_SCT_nEV (16) /* Number of events */
elessair 0:f269e3021894 320 #define CONFIG_SCT_nRG (16) /* Number of match/compare registers */
elessair 0:f269e3021894 321 #define CONFIG_SCT_nOU (16) /* Number of outputs */
elessair 0:f269e3021894 322
elessair 0:f269e3021894 323 typedef struct {
elessair 0:f269e3021894 324 __IO uint32_t CONFIG; /* Configuration Register */
elessair 0:f269e3021894 325 union {
elessair 0:f269e3021894 326 __IO uint32_t CTRL_U; /* Control Register */
elessair 0:f269e3021894 327 struct {
elessair 0:f269e3021894 328 __IO uint16_t CTRL_L; /* Low control register */
elessair 0:f269e3021894 329 __IO uint16_t CTRL_H; /* High control register */
elessair 0:f269e3021894 330 };
elessair 0:f269e3021894 331
elessair 0:f269e3021894 332 };
elessair 0:f269e3021894 333
elessair 0:f269e3021894 334 __IO uint16_t LIMIT_L; /* limit register for counter L */
elessair 0:f269e3021894 335 __IO uint16_t LIMIT_H; /* limit register for counter H */
elessair 0:f269e3021894 336 __IO uint16_t HALT_L; /* halt register for counter L */
elessair 0:f269e3021894 337 __IO uint16_t HALT_H; /* halt register for counter H */
elessair 0:f269e3021894 338 __IO uint16_t STOP_L; /* stop register for counter L */
elessair 0:f269e3021894 339 __IO uint16_t STOP_H; /* stop register for counter H */
elessair 0:f269e3021894 340 __IO uint16_t START_L; /* start register for counter L */
elessair 0:f269e3021894 341 __IO uint16_t START_H; /* start register for counter H */
elessair 0:f269e3021894 342 uint32_t RESERVED1[10]; /* 0x03C reserved */
elessair 0:f269e3021894 343 union {
elessair 0:f269e3021894 344 __IO uint32_t COUNT_U; /* counter register */
elessair 0:f269e3021894 345 struct {
elessair 0:f269e3021894 346 __IO uint16_t COUNT_L; /* counter register for counter L */
elessair 0:f269e3021894 347 __IO uint16_t COUNT_H; /* counter register for counter H */
elessair 0:f269e3021894 348 };
elessair 0:f269e3021894 349
elessair 0:f269e3021894 350 };
elessair 0:f269e3021894 351
elessair 0:f269e3021894 352 __IO uint16_t STATE_L; /* state register for counter L */
elessair 0:f269e3021894 353 __IO uint16_t STATE_H; /* state register for counter H */
elessair 0:f269e3021894 354 __I uint32_t INPUT; /* input register */
elessair 0:f269e3021894 355 __IO uint16_t REGMODE_L; /* match - capture registers mode register L */
elessair 0:f269e3021894 356 __IO uint16_t REGMODE_H; /* match - capture registers mode register H */
elessair 0:f269e3021894 357 __IO uint32_t OUTPUT; /* output register */
elessair 0:f269e3021894 358 __IO uint32_t OUTPUTDIRCTRL; /* output counter direction Control Register */
elessair 0:f269e3021894 359 __IO uint32_t RES; /* conflict resolution register */
elessair 0:f269e3021894 360 __IO uint32_t DMA0REQUEST; /* DMA0 Request Register */
elessair 0:f269e3021894 361 __IO uint32_t DMA1REQUEST; /* DMA1 Request Register */
elessair 0:f269e3021894 362 uint32_t RESERVED2[35];
elessair 0:f269e3021894 363 __IO uint32_t EVEN; /* event enable register */
elessair 0:f269e3021894 364 __IO uint32_t EVFLAG; /* event flag register */
elessair 0:f269e3021894 365 __IO uint32_t CONEN; /* conflict enable register */
elessair 0:f269e3021894 366 __IO uint32_t CONFLAG; /* conflict flag register */
elessair 0:f269e3021894 367 union {
elessair 0:f269e3021894 368 __IO union { /* ... Match / Capture value */
elessair 0:f269e3021894 369 uint32_t U; /* SCTMATCH[i].U Unified 32-bit register */
elessair 0:f269e3021894 370 struct {
elessair 0:f269e3021894 371 uint16_t L; /* SCTMATCH[i].L Access to L value */
elessair 0:f269e3021894 372 uint16_t H; /* SCTMATCH[i].H Access to H value */
elessair 0:f269e3021894 373 };
elessair 0:f269e3021894 374
elessair 0:f269e3021894 375 } MATCH[CONFIG_SCT_nRG];
elessair 0:f269e3021894 376
elessair 0:f269e3021894 377 __I union {
elessair 0:f269e3021894 378 uint32_t U; /* SCTCAP[i].U Unified 32-bit register */
elessair 0:f269e3021894 379 struct {
elessair 0:f269e3021894 380 uint16_t L; /* SCTCAP[i].L Access to L value */
elessair 0:f269e3021894 381 uint16_t H; /* SCTCAP[i].H Access to H value */
elessair 0:f269e3021894 382 };
elessair 0:f269e3021894 383
elessair 0:f269e3021894 384 } CAP[CONFIG_SCT_nRG];
elessair 0:f269e3021894 385
elessair 0:f269e3021894 386 };
elessair 0:f269e3021894 387
elessair 0:f269e3021894 388 uint32_t RESERVED3[32 - CONFIG_SCT_nRG]; /* ...-0x17C reserved */
elessair 0:f269e3021894 389 union {
elessair 0:f269e3021894 390 __IO uint16_t MATCH_L[CONFIG_SCT_nRG]; /* 0x180-... Match Value L counter */
elessair 0:f269e3021894 391 __I uint16_t CAP_L[CONFIG_SCT_nRG]; /* 0x180-... Capture Value L counter */
elessair 0:f269e3021894 392 };
elessair 0:f269e3021894 393
elessair 0:f269e3021894 394 uint16_t RESERVED4[32 - CONFIG_SCT_nRG]; /* ...-0x1BE reserved */
elessair 0:f269e3021894 395 union {
elessair 0:f269e3021894 396 __IO uint16_t MATCH_H[CONFIG_SCT_nRG]; /* 0x1C0-... Match Value H counter */
elessair 0:f269e3021894 397 __I uint16_t CAP_H[CONFIG_SCT_nRG]; /* 0x1C0-... Capture Value H counter */
elessair 0:f269e3021894 398 };
elessair 0:f269e3021894 399
elessair 0:f269e3021894 400 uint16_t RESERVED5[32 - CONFIG_SCT_nRG]; /* ...-0x1FE reserved */
elessair 0:f269e3021894 401 union {
elessair 0:f269e3021894 402 __IO union { /* 0x200-... Match Reload / Capture Control value */
elessair 0:f269e3021894 403 uint32_t U; /* SCTMATCHREL[i].U Unified 32-bit register */
elessair 0:f269e3021894 404 struct {
elessair 0:f269e3021894 405 uint16_t L; /* SCTMATCHREL[i].L Access to L value */
elessair 0:f269e3021894 406 uint16_t H; /* SCTMATCHREL[i].H Access to H value */
elessair 0:f269e3021894 407 };
elessair 0:f269e3021894 408
elessair 0:f269e3021894 409 } MATCHREL[CONFIG_SCT_nRG];
elessair 0:f269e3021894 410
elessair 0:f269e3021894 411 __IO union {
elessair 0:f269e3021894 412 uint32_t U; /* SCTCAPCTRL[i].U Unified 32-bit register */
elessair 0:f269e3021894 413 struct {
elessair 0:f269e3021894 414 uint16_t L; /* SCTCAPCTRL[i].L Access to L value */
elessair 0:f269e3021894 415 uint16_t H; /* SCTCAPCTRL[i].H Access to H value */
elessair 0:f269e3021894 416 };
elessair 0:f269e3021894 417
elessair 0:f269e3021894 418 } CAPCTRL[CONFIG_SCT_nRG];
elessair 0:f269e3021894 419
elessair 0:f269e3021894 420 };
elessair 0:f269e3021894 421
elessair 0:f269e3021894 422 uint32_t RESERVED6[32 - CONFIG_SCT_nRG]; /* ...-0x27C reserved */
elessair 0:f269e3021894 423 union {
elessair 0:f269e3021894 424 __IO uint16_t MATCHREL_L[CONFIG_SCT_nRG]; /* 0x280-... Match Reload value L counter */
elessair 0:f269e3021894 425 __IO uint16_t CAPCTRL_L[CONFIG_SCT_nRG]; /* 0x280-... Capture Control value L counter */
elessair 0:f269e3021894 426 };
elessair 0:f269e3021894 427
elessair 0:f269e3021894 428 uint16_t RESERVED7[32 - CONFIG_SCT_nRG]; /* ...-0x2BE reserved */
elessair 0:f269e3021894 429 union {
elessair 0:f269e3021894 430 __IO uint16_t MATCHREL_H[CONFIG_SCT_nRG]; /* 0x2C0-... Match Reload value H counter */
elessair 0:f269e3021894 431 __IO uint16_t CAPCTRL_H[CONFIG_SCT_nRG]; /* 0x2C0-... Capture Control value H counter */
elessair 0:f269e3021894 432 };
elessair 0:f269e3021894 433
elessair 0:f269e3021894 434 uint16_t RESERVED8[32 - CONFIG_SCT_nRG]; /* ...-0x2FE reserved */
elessair 0:f269e3021894 435 __IO struct { /* 0x300-0x3FC SCTEVENT[i].STATE / SCTEVENT[i].CTRL*/
elessair 0:f269e3021894 436 uint32_t STATE; /* Event State Register */
elessair 0:f269e3021894 437 uint32_t CTRL; /* Event Control Register */
elessair 0:f269e3021894 438 } EVENT[CONFIG_SCT_nEV];
elessair 0:f269e3021894 439
elessair 0:f269e3021894 440 uint32_t RESERVED9[128 - 2 * CONFIG_SCT_nEV]; /* ...-0x4FC reserved */
elessair 0:f269e3021894 441 __IO struct { /* 0x500-0x57C SCTOUT[i].SET / SCTOUT[i].CLR */
elessair 0:f269e3021894 442 uint32_t SET; /* Output n Set Register */
elessair 0:f269e3021894 443 uint32_t CLR; /* Output n Clear Register */
elessair 0:f269e3021894 444 } OUT[CONFIG_SCT_nOU];
elessair 0:f269e3021894 445
elessair 0:f269e3021894 446 uint32_t RESERVED10[191 - 2 * CONFIG_SCT_nOU]; /* ...-0x7F8 reserved */
elessair 0:f269e3021894 447 __I uint32_t MODULECONTENT; /* 0x7FC Module Content */
elessair 0:f269e3021894 448 } LPC_SCT_T;
elessair 0:f269e3021894 449
elessair 0:f269e3021894 450 /* Macro defines for SCT configuration register */
elessair 0:f269e3021894 451 #define SCT_CONFIG_16BIT_COUNTER 0x00000000 /* Operate as 2 16-bit counters */
elessair 0:f269e3021894 452 #define SCT_CONFIG_32BIT_COUNTER 0x00000001 /* Operate as 1 32-bit counter */
elessair 0:f269e3021894 453
elessair 0:f269e3021894 454 #define SCT_CONFIG_CLKMODE_BUSCLK (0x0 << 1) /* Bus clock */
elessair 0:f269e3021894 455 #define SCT_CONFIG_CLKMODE_SCTCLK (0x1 << 1) /* SCT clock */
elessair 0:f269e3021894 456 #define SCT_CONFIG_CLKMODE_INCLK (0x2 << 1) /* Input clock selected in CLKSEL field */
elessair 0:f269e3021894 457 #define SCT_CONFIG_CLKMODE_INEDGECLK (0x3 << 1) /* Input clock edge selected in CLKSEL field */
elessair 0:f269e3021894 458
elessair 0:f269e3021894 459 #define SCT_CONFIG_NORELOADL_U (0x1 << 7) /* Operate as 1 32-bit counter */
elessair 0:f269e3021894 460 #define SCT_CONFIG_NORELOADH (0x1 << 8) /* Operate as 1 32-bit counter */
elessair 0:f269e3021894 461
elessair 0:f269e3021894 462 /* Macro defines for SCT control register */
elessair 0:f269e3021894 463 #define COUNTUP_TO_LIMIT_THEN_CLEAR_TO_ZERO 0 /* Direction for low or unified counter */
elessair 0:f269e3021894 464 #define COUNTUP_TO LIMIT_THEN_COUNTDOWN_TO_ZERO 1
elessair 0:f269e3021894 465
elessair 0:f269e3021894 466 #define SCT_CTRL_STOP_L (1 << 1) /* Stop low counter */
elessair 0:f269e3021894 467 #define SCT_CTRL_HALT_L (1 << 2) /* Halt low counter */
elessair 0:f269e3021894 468 #define SCT_CTRL_CLRCTR_L (1 << 3) /* Clear low or unified counter */
elessair 0:f269e3021894 469 #define SCT_CTRL_BIDIR_L(x) (((x) & 0x01) << 4) /* Bidirectional bit */
elessair 0:f269e3021894 470 #define SCT_CTRL_PRE_L(x) (((x) & 0xFF) << 5) /* Prescale clock for low or unified counter */
elessair 0:f269e3021894 471
elessair 0:f269e3021894 472 #define COUNTUP_TO_LIMIT_THEN_CLEAR_TO_ZERO 0 /* Direction for high counter */
elessair 0:f269e3021894 473 #define COUNTUP_TO LIMIT_THEN_COUNTDOWN_TO_ZERO 1
elessair 0:f269e3021894 474 #define SCT_CTRL_STOP_H (1 << 17) /* Stop high counter */
elessair 0:f269e3021894 475 #define SCT_CTRL_HALT_H (1 << 18) /* Halt high counter */
elessair 0:f269e3021894 476 #define SCT_CTRL_CLRCTR_H (1 << 19) /* Clear high counter */
elessair 0:f269e3021894 477 #define SCT_CTRL_BIDIR_H(x) (((x) & 0x01) << 20)
elessair 0:f269e3021894 478 #define SCT_CTRL_PRE_H(x) (((x) & 0xFF) << 21) /* Prescale clock for high counter */
elessair 0:f269e3021894 479
elessair 0:f269e3021894 480 /* Macro defines for SCT Conflict resolution register */
elessair 0:f269e3021894 481 #define SCT_RES_NOCHANGE (0)
elessair 0:f269e3021894 482 #define SCT_RES_SET_OUTPUT (1)
elessair 0:f269e3021894 483 #define SCT_RES_CLEAR_OUTPUT (2)
elessair 0:f269e3021894 484 #define SCT_RES_TOGGLE_OUTPUT (3)
elessair 0:f269e3021894 485
elessair 0:f269e3021894 486 /* ---------------------------------------------------------------------------
elessair 0:f269e3021894 487 * GPDMA Channel register block structure
elessair 0:f269e3021894 488 */
elessair 0:f269e3021894 489 #define LPC_GPDMA_BASE 0x40002000
elessair 0:f269e3021894 490
elessair 0:f269e3021894 491 typedef struct {
elessair 0:f269e3021894 492 __IO uint32_t SRCADDR; /* DMA Channel Source Address Register */
elessair 0:f269e3021894 493 __IO uint32_t DESTADDR; /* DMA Channel Destination Address Register */
elessair 0:f269e3021894 494 __IO uint32_t LLI; /* DMA Channel Linked List Item Register */
elessair 0:f269e3021894 495 __IO uint32_t CONTROL; /* DMA Channel Control Register */
elessair 0:f269e3021894 496 __IO uint32_t CONFIG; /* DMA Channel Configuration Register */
elessair 0:f269e3021894 497 __I uint32_t RESERVED1[3];
elessair 0:f269e3021894 498 } LPC_GPDMA_CH_T;
elessair 0:f269e3021894 499
elessair 0:f269e3021894 500 #define GPDMA_CHANNELS 8
elessair 0:f269e3021894 501
elessair 0:f269e3021894 502 /* ---------------------------------------------------------------------------
elessair 0:f269e3021894 503 * GPDMA register block
elessair 0:f269e3021894 504 */
elessair 0:f269e3021894 505 typedef struct { /* GPDMA Structure */
elessair 0:f269e3021894 506 __I uint32_t INTSTAT; /* DMA Interrupt Status Register */
elessair 0:f269e3021894 507 __I uint32_t INTTCSTAT; /* DMA Interrupt Terminal Count Request Status Register */
elessair 0:f269e3021894 508 __O uint32_t INTTCCLEAR; /* DMA Interrupt Terminal Count Request Clear Register */
elessair 0:f269e3021894 509 __I uint32_t INTERRSTAT; /* DMA Interrupt Error Status Register */
elessair 0:f269e3021894 510 __O uint32_t INTERRCLR; /* DMA Interrupt Error Clear Register */
elessair 0:f269e3021894 511 __I uint32_t RAWINTTCSTAT; /* DMA Raw Interrupt Terminal Count Status Register */
elessair 0:f269e3021894 512 __I uint32_t RAWINTERRSTAT; /* DMA Raw Error Interrupt Status Register */
elessair 0:f269e3021894 513 __I uint32_t ENBLDCHNS; /* DMA Enabled Channel Register */
elessair 0:f269e3021894 514 __IO uint32_t SOFTBREQ; /* DMA Software Burst Request Register */
elessair 0:f269e3021894 515 __IO uint32_t SOFTSREQ; /* DMA Software Single Request Register */
elessair 0:f269e3021894 516 __IO uint32_t SOFTLBREQ; /* DMA Software Last Burst Request Register */
elessair 0:f269e3021894 517 __IO uint32_t SOFTLSREQ; /* DMA Software Last Single Request Register */
elessair 0:f269e3021894 518 __IO uint32_t CONFIG; /* DMA Configuration Register */
elessair 0:f269e3021894 519 __IO uint32_t SYNC; /* DMA Synchronization Register */
elessair 0:f269e3021894 520 __I uint32_t RESERVED0[50];
elessair 0:f269e3021894 521 LPC_GPDMA_CH_T CH[GPDMA_CHANNELS];
elessair 0:f269e3021894 522 } LPC_GPDMA_T;
elessair 0:f269e3021894 523
elessair 0:f269e3021894 524 /* ---------------------------------------------------------------------------
elessair 0:f269e3021894 525 * SPIFI register block structure
elessair 0:f269e3021894 526 */
elessair 0:f269e3021894 527 #define LPC_SPIFI_BASE 0x40003000
elessair 0:f269e3021894 528
elessair 0:f269e3021894 529 typedef struct { /* SPIFI Structure */
elessair 0:f269e3021894 530 __IO uint32_t CTRL; /* Control register */
elessair 0:f269e3021894 531 __IO uint32_t CMD; /* Command register */
elessair 0:f269e3021894 532 __IO uint32_t ADDR; /* Address register */
elessair 0:f269e3021894 533 __IO uint32_t IDATA; /* Intermediate data register */
elessair 0:f269e3021894 534 __IO uint32_t CLIMIT; /* Cache limit register */
elessair 0:f269e3021894 535 union {
elessair 0:f269e3021894 536 __IO uint32_t DATA;
elessair 0:f269e3021894 537 __IO uint16_t DATA_HWORD;
elessair 0:f269e3021894 538 __IO uint8_t DATA_BYTE;
elessair 0:f269e3021894 539 }; /* Data register */
elessair 0:f269e3021894 540 __IO uint32_t MCMD; /* Memory command register */
elessair 0:f269e3021894 541 __IO uint32_t STAT; /* Status register */
elessair 0:f269e3021894 542 } LPC_SPIFI_T;
elessair 0:f269e3021894 543
elessair 0:f269e3021894 544 /* ---------------------------------------------------------------------------
elessair 0:f269e3021894 545 * SD/MMC & SDIO register block structure
elessair 0:f269e3021894 546 */
elessair 0:f269e3021894 547 #define LPC_SDMMC_BASE 0x40004000
elessair 0:f269e3021894 548
elessair 0:f269e3021894 549 typedef struct { /* SDMMC Structure */
elessair 0:f269e3021894 550 __IO uint32_t CTRL; /* Control Register */
elessair 0:f269e3021894 551 __IO uint32_t PWREN; /* Power Enable Register */
elessair 0:f269e3021894 552 __IO uint32_t CLKDIV; /* Clock Divider Register */
elessair 0:f269e3021894 553 __IO uint32_t CLKSRC; /* SD Clock Source Register */
elessair 0:f269e3021894 554 __IO uint32_t CLKENA; /* Clock Enable Register */
elessair 0:f269e3021894 555 __IO uint32_t TMOUT; /* Timeout Register */
elessair 0:f269e3021894 556 __IO uint32_t CTYPE; /* Card Type Register */
elessair 0:f269e3021894 557 __IO uint32_t BLKSIZ; /* Block Size Register */
elessair 0:f269e3021894 558 __IO uint32_t BYTCNT; /* Byte Count Register */
elessair 0:f269e3021894 559 __IO uint32_t INTMASK; /* Interrupt Mask Register */
elessair 0:f269e3021894 560 __IO uint32_t CMDARG; /* Command Argument Register */
elessair 0:f269e3021894 561 __IO uint32_t CMD; /* Command Register */
elessair 0:f269e3021894 562 __I uint32_t RESP0; /* Response Register 0 */
elessair 0:f269e3021894 563 __I uint32_t RESP1; /* Response Register 1 */
elessair 0:f269e3021894 564 __I uint32_t RESP2; /* Response Register 2 */
elessair 0:f269e3021894 565 __I uint32_t RESP3; /* Response Register 3 */
elessair 0:f269e3021894 566 __I uint32_t MINTSTS; /* Masked Interrupt Status Register */
elessair 0:f269e3021894 567 __IO uint32_t RINTSTS; /* Raw Interrupt Status Register */
elessair 0:f269e3021894 568 __I uint32_t STATUS; /* Status Register */
elessair 0:f269e3021894 569 __IO uint32_t FIFOTH; /* FIFO Threshold Watermark Register */
elessair 0:f269e3021894 570 __I uint32_t CDETECT; /* Card Detect Register */
elessair 0:f269e3021894 571 __I uint32_t WRTPRT; /* Write Protect Register */
elessair 0:f269e3021894 572 __IO uint32_t GPIO; /* General Purpose Input/Output Register */
elessair 0:f269e3021894 573 __I uint32_t TCBCNT; /* Transferred CIU Card Byte Count Register */
elessair 0:f269e3021894 574 __I uint32_t TBBCNT; /* Transferred Host to BIU-FIFO Byte Count Register */
elessair 0:f269e3021894 575 __IO uint32_t DEBNCE; /* Debounce Count Register */
elessair 0:f269e3021894 576 __IO uint32_t USRID; /* User ID Register */
elessair 0:f269e3021894 577 __I uint32_t VERID; /* Version ID Register */
elessair 0:f269e3021894 578 __I uint32_t RESERVED0;
elessair 0:f269e3021894 579 __IO uint32_t UHS_REG; /* UHS-1 Register */
elessair 0:f269e3021894 580 __IO uint32_t RST_N; /* Hardware Reset */
elessair 0:f269e3021894 581 __I uint32_t RESERVED1;
elessair 0:f269e3021894 582 __IO uint32_t BMOD; /* Bus Mode Register */
elessair 0:f269e3021894 583 __O uint32_t PLDMND; /* Poll Demand Register */
elessair 0:f269e3021894 584 __IO uint32_t DBADDR; /* Descriptor List Base Address Register */
elessair 0:f269e3021894 585 __IO uint32_t IDSTS; /* Internal DMAC Status Register */
elessair 0:f269e3021894 586 __IO uint32_t IDINTEN; /* Internal DMAC Interrupt Enable Register */
elessair 0:f269e3021894 587 __I uint32_t DSCADDR; /* Current Host Descriptor Address Register */
elessair 0:f269e3021894 588 __I uint32_t BUFADDR; /* Current Buffer Descriptor Address Register */
elessair 0:f269e3021894 589 } LPC_SDMMC_T;
elessair 0:f269e3021894 590
elessair 0:f269e3021894 591 /* ---------------------------------------------------------------------------
elessair 0:f269e3021894 592 * External Memory Controller (EMC) register block structure
elessair 0:f269e3021894 593 */
elessair 0:f269e3021894 594 #define LPC_EMC_BASE 0x40005000
elessair 0:f269e3021894 595
elessair 0:f269e3021894 596 typedef struct { /* EMC Structure */
elessair 0:f269e3021894 597 __IO uint32_t CONTROL; /* Controls operation of the memory controller. */
elessair 0:f269e3021894 598 __I uint32_t STATUS; /* Provides EMC status information. */
elessair 0:f269e3021894 599 __IO uint32_t CONFIG; /* Configures operation of the memory controller. */
elessair 0:f269e3021894 600 __I uint32_t RESERVED0[5];
elessair 0:f269e3021894 601 __IO uint32_t DYNAMICCONTROL; /* Controls dynamic memory operation. */
elessair 0:f269e3021894 602 __IO uint32_t DYNAMICREFRESH; /* Configures dynamic memory refresh operation. */
elessair 0:f269e3021894 603 __IO uint32_t DYNAMICREADCONFIG; /* Configures the dynamic memory read strategy. */
elessair 0:f269e3021894 604 __I uint32_t RESERVED1;
elessair 0:f269e3021894 605 __IO uint32_t DYNAMICRP; /* Selects the precharge command period. */
elessair 0:f269e3021894 606 __IO uint32_t DYNAMICRAS; /* Selects the active to precharge command period. */
elessair 0:f269e3021894 607 __IO uint32_t DYNAMICSREX; /* Selects the self-refresh exit time. */
elessair 0:f269e3021894 608 __IO uint32_t DYNAMICAPR; /* Selects the last-data-out to active command time. */
elessair 0:f269e3021894 609 __IO uint32_t DYNAMICDAL; /* Selects the data-in to active command time. */
elessair 0:f269e3021894 610 __IO uint32_t DYNAMICWR; /* Selects the write recovery time. */
elessair 0:f269e3021894 611 __IO uint32_t DYNAMICRC; /* Selects the active to active command period. */
elessair 0:f269e3021894 612 __IO uint32_t DYNAMICRFC; /* Selects the auto-refresh period. */
elessair 0:f269e3021894 613 __IO uint32_t DYNAMICXSR; /* Selects the exit self-refresh to active command time. */
elessair 0:f269e3021894 614 __IO uint32_t DYNAMICRRD; /* Selects the active bank A to active bank B latency. */
elessair 0:f269e3021894 615 __IO uint32_t DYNAMICMRD; /* Selects the load mode register to active command time. */
elessair 0:f269e3021894 616 __I uint32_t RESERVED2[9];
elessair 0:f269e3021894 617 __IO uint32_t STATICEXTENDEDWAIT; /* Selects time for long static memory read and write transfers. */
elessair 0:f269e3021894 618 __I uint32_t RESERVED3[31];
elessair 0:f269e3021894 619 __IO uint32_t DYNAMICCONFIG0; /* Selects the configuration information for dynamic memory chip select n. */
elessair 0:f269e3021894 620 __IO uint32_t DYNAMICRASCAS0; /* Selects the RAS and CAS latencies for dynamic memory chip select n. */
elessair 0:f269e3021894 621 __I uint32_t RESERVED4[6];
elessair 0:f269e3021894 622 __IO uint32_t DYNAMICCONFIG1; /* Selects the configuration information for dynamic memory chip select n. */
elessair 0:f269e3021894 623 __IO uint32_t DYNAMICRASCAS1; /* Selects the RAS and CAS latencies for dynamic memory chip select n. */
elessair 0:f269e3021894 624 __I uint32_t RESERVED5[6];
elessair 0:f269e3021894 625 __IO uint32_t DYNAMICCONFIG2; /* Selects the configuration information for dynamic memory chip select n. */
elessair 0:f269e3021894 626 __IO uint32_t DYNAMICRASCAS2; /* Selects the RAS and CAS latencies for dynamic memory chip select n. */
elessair 0:f269e3021894 627 __I uint32_t RESERVED6[6];
elessair 0:f269e3021894 628 __IO uint32_t DYNAMICCONFIG3; /* Selects the configuration information for dynamic memory chip select n. */
elessair 0:f269e3021894 629 __IO uint32_t DYNAMICRASCAS3; /* Selects the RAS and CAS latencies for dynamic memory chip select n. */
elessair 0:f269e3021894 630 __I uint32_t RESERVED7[38];
elessair 0:f269e3021894 631 __IO uint32_t STATICCONFIG0; /* Selects the memory configuration for static chip select n. */
elessair 0:f269e3021894 632 __IO uint32_t STATICWAITWEN0; /* Selects the delay from chip select n to write enable. */
elessair 0:f269e3021894 633 __IO uint32_t STATICWAITOEN0; /* Selects the delay from chip select n or address change, whichever is later, to output enable. */
elessair 0:f269e3021894 634 __IO uint32_t STATICWAITRD0; /* Selects the delay from chip select n to a read access. */
elessair 0:f269e3021894 635 __IO uint32_t STATICWAITPAG0; /* Selects the delay for asynchronous page mode sequential accesses for chip select n. */
elessair 0:f269e3021894 636 __IO uint32_t STATICWAITWR0; /* Selects the delay from chip select n to a write access. */
elessair 0:f269e3021894 637 __IO uint32_t STATICWAITTURN0; /* Selects bus turnaround cycles */
elessair 0:f269e3021894 638 __I uint32_t RESERVED8;
elessair 0:f269e3021894 639 __IO uint32_t STATICCONFIG1; /* Selects the memory configuration for static chip select n. */
elessair 0:f269e3021894 640 __IO uint32_t STATICWAITWEN1; /* Selects the delay from chip select n to write enable. */
elessair 0:f269e3021894 641 __IO uint32_t STATICWAITOEN1; /* Selects the delay from chip select n or address change, whichever is later, to output enable. */
elessair 0:f269e3021894 642 __IO uint32_t STATICWAITRD1; /* Selects the delay from chip select n to a read access. */
elessair 0:f269e3021894 643 __IO uint32_t STATICWAITPAG1; /* Selects the delay for asynchronous page mode sequential accesses for chip select n. */
elessair 0:f269e3021894 644 __IO uint32_t STATICWAITWR1; /* Selects the delay from chip select n to a write access. */
elessair 0:f269e3021894 645 __IO uint32_t STATICWAITTURN1; /* Selects bus turnaround cycles */
elessair 0:f269e3021894 646 __I uint32_t RESERVED9;
elessair 0:f269e3021894 647 __IO uint32_t STATICCONFIG2; /* Selects the memory configuration for static chip select n. */
elessair 0:f269e3021894 648 __IO uint32_t STATICWAITWEN2; /* Selects the delay from chip select n to write enable. */
elessair 0:f269e3021894 649 __IO uint32_t STATICWAITOEN2; /* Selects the delay from chip select n or address change, whichever is later, to output enable. */
elessair 0:f269e3021894 650 __IO uint32_t STATICWAITRD2; /* Selects the delay from chip select n to a read access. */
elessair 0:f269e3021894 651 __IO uint32_t STATICWAITPAG2; /* Selects the delay for asynchronous page mode sequential accesses for chip select n. */
elessair 0:f269e3021894 652 __IO uint32_t STATICWAITWR2; /* Selects the delay from chip select n to a write access. */
elessair 0:f269e3021894 653 __IO uint32_t STATICWAITTURN2; /* Selects bus turnaround cycles */
elessair 0:f269e3021894 654 __I uint32_t RESERVED10;
elessair 0:f269e3021894 655 __IO uint32_t STATICCONFIG3; /* Selects the memory configuration for static chip select n. */
elessair 0:f269e3021894 656 __IO uint32_t STATICWAITWEN3; /* Selects the delay from chip select n to write enable. */
elessair 0:f269e3021894 657 __IO uint32_t STATICWAITOEN3; /* Selects the delay from chip select n or address change, whichever is later, to output enable. */
elessair 0:f269e3021894 658 __IO uint32_t STATICWAITRD3; /* Selects the delay from chip select n to a read access. */
elessair 0:f269e3021894 659 __IO uint32_t STATICWAITPAG3; /* Selects the delay for asynchronous page mode sequential accesses for chip select n. */
elessair 0:f269e3021894 660 __IO uint32_t STATICWAITWR3; /* Selects the delay from chip select n to a write access. */
elessair 0:f269e3021894 661 __IO uint32_t STATICWAITTURN3; /* Selects bus turnaround cycles */
elessair 0:f269e3021894 662 } LPC_EMC_T;
elessair 0:f269e3021894 663
elessair 0:f269e3021894 664 /* ---------------------------------------------------------------------------
elessair 0:f269e3021894 665 * USB High-Speed register block structure
elessair 0:f269e3021894 666 */
elessair 0:f269e3021894 667 #define LPC_USB0_BASE 0x40006000
elessair 0:f269e3021894 668 #define LPC_USB1_BASE 0x40007000
elessair 0:f269e3021894 669
elessair 0:f269e3021894 670 typedef struct { /* USB Structure */
elessair 0:f269e3021894 671 __I uint32_t RESERVED0[64];
elessair 0:f269e3021894 672 __I uint32_t CAPLENGTH; /* Capability register length */
elessair 0:f269e3021894 673 __I uint32_t HCSPARAMS; /* Host controller structural parameters */
elessair 0:f269e3021894 674 __I uint32_t HCCPARAMS; /* Host controller capability parameters */
elessair 0:f269e3021894 675 __I uint32_t RESERVED1[5];
elessair 0:f269e3021894 676 __I uint32_t DCIVERSION; /* Device interface version number */
elessair 0:f269e3021894 677 __I uint32_t RESERVED2[7];
elessair 0:f269e3021894 678 union {
elessair 0:f269e3021894 679 __IO uint32_t USBCMD_H; /* USB command (host mode) */
elessair 0:f269e3021894 680 __IO uint32_t USBCMD_D; /* USB command (device mode) */
elessair 0:f269e3021894 681 };
elessair 0:f269e3021894 682
elessair 0:f269e3021894 683 union {
elessair 0:f269e3021894 684 __IO uint32_t USBSTS_H; /* USB status (host mode) */
elessair 0:f269e3021894 685 __IO uint32_t USBSTS_D; /* USB status (device mode) */
elessair 0:f269e3021894 686 };
elessair 0:f269e3021894 687
elessair 0:f269e3021894 688 union {
elessair 0:f269e3021894 689 __IO uint32_t USBINTR_H; /* USB interrupt enable (host mode) */
elessair 0:f269e3021894 690 __IO uint32_t USBINTR_D; /* USB interrupt enable (device mode) */
elessair 0:f269e3021894 691 };
elessair 0:f269e3021894 692
elessair 0:f269e3021894 693 union {
elessair 0:f269e3021894 694 __IO uint32_t FRINDEX_H; /* USB frame index (host mode) */
elessair 0:f269e3021894 695 __I uint32_t FRINDEX_D; /* USB frame index (device mode) */
elessair 0:f269e3021894 696 };
elessair 0:f269e3021894 697
elessair 0:f269e3021894 698 __I uint32_t RESERVED3;
elessair 0:f269e3021894 699 union {
elessair 0:f269e3021894 700 __IO uint32_t PERIODICLISTBASE; /* Frame list base address */
elessair 0:f269e3021894 701 __IO uint32_t DEVICEADDR; /* USB device address */
elessair 0:f269e3021894 702 };
elessair 0:f269e3021894 703
elessair 0:f269e3021894 704 union {
elessair 0:f269e3021894 705 __IO uint32_t ASYNCLISTADDR; /* Address of endpoint list in memory (host mode) */
elessair 0:f269e3021894 706 __IO uint32_t ENDPOINTLISTADDR; /* Address of endpoint list in memory (device mode) */
elessair 0:f269e3021894 707 };
elessair 0:f269e3021894 708
elessair 0:f269e3021894 709 __IO uint32_t TTCTRL; /* Asynchronous buffer status for embedded TT (host mode) */
elessair 0:f269e3021894 710 __IO uint32_t BURSTSIZE; /* Programmable burst size */
elessair 0:f269e3021894 711 __IO uint32_t TXFILLTUNING; /* Host transmit pre-buffer packet tuning (host mode) */
elessair 0:f269e3021894 712 __I uint32_t RESERVED4[2];
elessair 0:f269e3021894 713 __IO uint32_t ULPIVIEWPORT; /* ULPI viewport */
elessair 0:f269e3021894 714 __IO uint32_t BINTERVAL; /* Length of virtual frame */
elessair 0:f269e3021894 715 __IO uint32_t ENDPTNAK; /* Endpoint NAK (device mode) */
elessair 0:f269e3021894 716 __IO uint32_t ENDPTNAKEN; /* Endpoint NAK Enable (device mode) */
elessair 0:f269e3021894 717 __I uint32_t RESERVED5;
elessair 0:f269e3021894 718 union {
elessair 0:f269e3021894 719 __IO uint32_t PORTSC1_H; /* Port 1 status/control (host mode) */
elessair 0:f269e3021894 720 __IO uint32_t PORTSC1_D; /* Port 1 status/control (device mode) */
elessair 0:f269e3021894 721 };
elessair 0:f269e3021894 722
elessair 0:f269e3021894 723 __I uint32_t RESERVED6[7];
elessair 0:f269e3021894 724 __IO uint32_t OTGSC; /* OTG status and control */
elessair 0:f269e3021894 725 union {
elessair 0:f269e3021894 726 __IO uint32_t USBMODE_H; /* USB mode (host mode) */
elessair 0:f269e3021894 727 __IO uint32_t USBMODE_D; /* USB mode (device mode) */
elessair 0:f269e3021894 728 };
elessair 0:f269e3021894 729
elessair 0:f269e3021894 730 __IO uint32_t ENDPTSETUPSTAT; /* Endpoint setup status */
elessair 0:f269e3021894 731 __IO uint32_t ENDPTPRIME; /* Endpoint initialization */
elessair 0:f269e3021894 732 __IO uint32_t ENDPTFLUSH; /* Endpoint de-initialization */
elessair 0:f269e3021894 733 __I uint32_t ENDPTSTAT; /* Endpoint status */
elessair 0:f269e3021894 734 __IO uint32_t ENDPTCOMPLETE; /* Endpoint complete */
elessair 0:f269e3021894 735 __IO uint32_t ENDPTCTRL[6]; /* Endpoint control 0 */
elessair 0:f269e3021894 736 } LPC_USBHS_T;
elessair 0:f269e3021894 737
elessair 0:f269e3021894 738 /* ---------------------------------------------------------------------------
elessair 0:f269e3021894 739 * LCD Controller register block structure
elessair 0:f269e3021894 740 */
elessair 0:f269e3021894 741 #define LPC_LCD_BASE 0x40008000
elessair 0:f269e3021894 742
elessair 0:f269e3021894 743 typedef struct { /* LCD Structure */
elessair 0:f269e3021894 744 __IO uint32_t TIMH; /* Horizontal Timing Control register */
elessair 0:f269e3021894 745 __IO uint32_t TIMV; /* Vertical Timing Control register */
elessair 0:f269e3021894 746 __IO uint32_t POL; /* Clock and Signal Polarity Control register */
elessair 0:f269e3021894 747 __IO uint32_t LE; /* Line End Control register */
elessair 0:f269e3021894 748 __IO uint32_t UPBASE; /* Upper Panel Frame Base Address register */
elessair 0:f269e3021894 749 __IO uint32_t LPBASE; /* Lower Panel Frame Base Address register */
elessair 0:f269e3021894 750 __IO uint32_t CTRL; /* LCD Control register */
elessair 0:f269e3021894 751 __IO uint32_t INTMSK; /* Interrupt Mask register */
elessair 0:f269e3021894 752 __I uint32_t INTRAW; /* Raw Interrupt Status register */
elessair 0:f269e3021894 753 __I uint32_t INTSTAT; /* Masked Interrupt Status register */
elessair 0:f269e3021894 754 __O uint32_t INTCLR; /* Interrupt Clear register */
elessair 0:f269e3021894 755 __I uint32_t UPCURR; /* Upper Panel Current Address Value register */
elessair 0:f269e3021894 756 __I uint32_t LPCURR; /* Lower Panel Current Address Value register */
elessair 0:f269e3021894 757 __I uint32_t RESERVED0[115];
elessair 0:f269e3021894 758 __IO uint16_t PAL[256]; /* 256x16-bit Color Palette registers */
elessair 0:f269e3021894 759 __I uint32_t RESERVED1[256];
elessair 0:f269e3021894 760 __IO uint32_t CRSR_IMG[256];/* Cursor Image registers */
elessair 0:f269e3021894 761 __IO uint32_t CRSR_CTRL; /* Cursor Control register */
elessair 0:f269e3021894 762 __IO uint32_t CRSR_CFG; /* Cursor Configuration register */
elessair 0:f269e3021894 763 __IO uint32_t CRSR_PAL0; /* Cursor Palette register 0 */
elessair 0:f269e3021894 764 __IO uint32_t CRSR_PAL1; /* Cursor Palette register 1 */
elessair 0:f269e3021894 765 __IO uint32_t CRSR_XY; /* Cursor XY Position register */
elessair 0:f269e3021894 766 __IO uint32_t CRSR_CLIP; /* Cursor Clip Position register */
elessair 0:f269e3021894 767 __I uint32_t RESERVED2[2];
elessair 0:f269e3021894 768 __IO uint32_t CRSR_INTMSK; /* Cursor Interrupt Mask register */
elessair 0:f269e3021894 769 __O uint32_t CRSR_INTCLR; /* Cursor Interrupt Clear register */
elessair 0:f269e3021894 770 __I uint32_t CRSR_INTRAW; /* Cursor Raw Interrupt Status register */
elessair 0:f269e3021894 771 __I uint32_t CRSR_INTSTAT;/* Cursor Masked Interrupt Status register */
elessair 0:f269e3021894 772 } LPC_LCD_T;
elessair 0:f269e3021894 773
elessair 0:f269e3021894 774 /* ---------------------------------------------------------------------------
elessair 0:f269e3021894 775 * EEPROM register block structure
elessair 0:f269e3021894 776 */
elessair 0:f269e3021894 777 #define LPC_EEPROM_BASE 0x4000E000
elessair 0:f269e3021894 778
elessair 0:f269e3021894 779 typedef struct { /* EEPROM Structure */
elessair 0:f269e3021894 780 __IO uint32_t CMD; /* EEPROM command register */
elessair 0:f269e3021894 781 uint32_t RESERVED0;
elessair 0:f269e3021894 782 __IO uint32_t RWSTATE; /* EEPROM read wait state register */
elessair 0:f269e3021894 783 __IO uint32_t AUTOPROG; /* EEPROM auto programming register */
elessair 0:f269e3021894 784 __IO uint32_t WSTATE; /* EEPROM wait state register */
elessair 0:f269e3021894 785 __IO uint32_t CLKDIV; /* EEPROM clock divider register */
elessair 0:f269e3021894 786 __IO uint32_t PWRDWN; /* EEPROM power-down register */
elessair 0:f269e3021894 787 uint32_t RESERVED2[1007];
elessair 0:f269e3021894 788 __O uint32_t INTENCLR; /* EEPROM interrupt enable clear */
elessair 0:f269e3021894 789 __O uint32_t INTENSET; /* EEPROM interrupt enable set */
elessair 0:f269e3021894 790 __I uint32_t INTSTAT; /* EEPROM interrupt status */
elessair 0:f269e3021894 791 __I uint32_t INTEN; /* EEPROM interrupt enable */
elessair 0:f269e3021894 792 __O uint32_t INTSTATCLR; /* EEPROM interrupt status clear */
elessair 0:f269e3021894 793 __O uint32_t INTSTATSET; /* EEPROM interrupt status set */
elessair 0:f269e3021894 794 } LPC_EEPROM_T;
elessair 0:f269e3021894 795
elessair 0:f269e3021894 796 /* ---------------------------------------------------------------------------
elessair 0:f269e3021894 797 * 10/100 MII & RMII Ethernet with timestamping register block structure
elessair 0:f269e3021894 798 */
elessair 0:f269e3021894 799 #define LPC_ETHERNET_BASE 0x40010000
elessair 0:f269e3021894 800
elessair 0:f269e3021894 801 typedef struct { /* ETHERNET Structure */
elessair 0:f269e3021894 802 __IO uint32_t MAC_CONFIG; /* MAC configuration register */
elessair 0:f269e3021894 803 __IO uint32_t MAC_FRAME_FILTER; /* MAC frame filter */
elessair 0:f269e3021894 804 __IO uint32_t MAC_HASHTABLE_HIGH; /* Hash table high register */
elessair 0:f269e3021894 805 __IO uint32_t MAC_HASHTABLE_LOW; /* Hash table low register */
elessair 0:f269e3021894 806 __IO uint32_t MAC_MII_ADDR; /* MII address register */
elessair 0:f269e3021894 807 __IO uint32_t MAC_MII_DATA; /* MII data register */
elessair 0:f269e3021894 808 __IO uint32_t MAC_FLOW_CTRL; /* Flow control register */
elessair 0:f269e3021894 809 __IO uint32_t MAC_VLAN_TAG; /* VLAN tag register */
elessair 0:f269e3021894 810 __I uint32_t RESERVED0;
elessair 0:f269e3021894 811 __I uint32_t MAC_DEBUG; /* Debug register */
elessair 0:f269e3021894 812 __IO uint32_t MAC_RWAKE_FRFLT; /* Remote wake-up frame filter */
elessair 0:f269e3021894 813 __IO uint32_t MAC_PMT_CTRL_STAT; /* PMT control and status */
elessair 0:f269e3021894 814 __I uint32_t RESERVED1[2];
elessair 0:f269e3021894 815 __I uint32_t MAC_INTR; /* Interrupt status register */
elessair 0:f269e3021894 816 __IO uint32_t MAC_INTR_MASK; /* Interrupt mask register */
elessair 0:f269e3021894 817 __IO uint32_t MAC_ADDR0_HIGH; /* MAC address 0 high register */
elessair 0:f269e3021894 818 __IO uint32_t MAC_ADDR0_LOW; /* MAC address 0 low register */
elessair 0:f269e3021894 819 __I uint32_t RESERVED2[430];
elessair 0:f269e3021894 820 __IO uint32_t MAC_TIMESTP_CTRL; /* Time stamp control register */
elessair 0:f269e3021894 821 __IO uint32_t SUBSECOND_INCR; /* Sub-second increment register */
elessair 0:f269e3021894 822 __I uint32_t SECONDS; /* System time seconds register */
elessair 0:f269e3021894 823 __I uint32_t NANOSECONDS; /* System time nanoseconds register */
elessair 0:f269e3021894 824 __IO uint32_t SECONDSUPDATE; /* System time seconds update register */
elessair 0:f269e3021894 825 __IO uint32_t NANOSECONDSUPDATE; /* System time nanoseconds update register */
elessair 0:f269e3021894 826 __IO uint32_t ADDEND; /* Time stamp addend register */
elessair 0:f269e3021894 827 __IO uint32_t TARGETSECONDS; /* Target time seconds register */
elessair 0:f269e3021894 828 __IO uint32_t TARGETNANOSECONDS; /* Target time nanoseconds register */
elessair 0:f269e3021894 829 __IO uint32_t HIGHWORD; /* System time higher word seconds register */
elessair 0:f269e3021894 830 __I uint32_t TIMESTAMPSTAT; /* Time stamp status register */
elessair 0:f269e3021894 831 __IO uint32_t PPSCTRL; /* PPS control register */
elessair 0:f269e3021894 832 __I uint32_t AUXNANOSECONDS; /* Auxiliary time stamp nanoseconds register */
elessair 0:f269e3021894 833 __I uint32_t AUXSECONDS; /* Auxiliary time stamp seconds register */
elessair 0:f269e3021894 834 __I uint32_t RESERVED3[562];
elessair 0:f269e3021894 835 __IO uint32_t DMA_BUS_MODE; /* Bus Mode Register */
elessair 0:f269e3021894 836 __IO uint32_t DMA_TRANS_POLL_DEMAND; /* Transmit poll demand register */
elessair 0:f269e3021894 837 __IO uint32_t DMA_REC_POLL_DEMAND; /* Receive poll demand register */
elessair 0:f269e3021894 838 __IO uint32_t DMA_REC_DES_ADDR; /* Receive descriptor list address register */
elessair 0:f269e3021894 839 __IO uint32_t DMA_TRANS_DES_ADDR; /* Transmit descriptor list address register */
elessair 0:f269e3021894 840 __IO uint32_t DMA_STAT; /* Status register */
elessair 0:f269e3021894 841 __IO uint32_t DMA_OP_MODE; /* Operation mode register */
elessair 0:f269e3021894 842 __IO uint32_t DMA_INT_EN; /* Interrupt enable register */
elessair 0:f269e3021894 843 __I uint32_t DMA_MFRM_BUFOF; /* Missed frame and buffer overflow register */
elessair 0:f269e3021894 844 __IO uint32_t DMA_REC_INT_WDT; /* Receive interrupt watchdog timer register */
elessair 0:f269e3021894 845 __I uint32_t RESERVED4[8];
elessair 0:f269e3021894 846 __I uint32_t DMA_CURHOST_TRANS_DES; /* Current host transmit descriptor register */
elessair 0:f269e3021894 847 __I uint32_t DMA_CURHOST_REC_DES; /* Current host receive descriptor register */
elessair 0:f269e3021894 848 __I uint32_t DMA_CURHOST_TRANS_BUF; /* Current host transmit buffer address register */
elessair 0:f269e3021894 849 __I uint32_t DMA_CURHOST_REC_BUF; /* Current host receive buffer address register */
elessair 0:f269e3021894 850 } LPC_ENET_T;
elessair 0:f269e3021894 851
elessair 0:f269e3021894 852 /* ---------------------------------------------------------------------------
elessair 0:f269e3021894 853 * Alarm Timer register block structure
elessair 0:f269e3021894 854 */
elessair 0:f269e3021894 855 #define LPC_ATIMER_BASE 0x40040000
elessair 0:f269e3021894 856
elessair 0:f269e3021894 857 typedef struct { /* ATIMER Structure */
elessair 0:f269e3021894 858 __IO uint32_t DOWNCOUNTER; /* Downcounter register */
elessair 0:f269e3021894 859 __IO uint32_t PRESET; /* Preset value register */
elessair 0:f269e3021894 860 __I uint32_t RESERVED0[1012];
elessair 0:f269e3021894 861 __O uint32_t CLR_EN; /* Interrupt clear enable register */
elessair 0:f269e3021894 862 __O uint32_t SET_EN; /* Interrupt set enable register */
elessair 0:f269e3021894 863 __I uint32_t STATUS; /* Status register */
elessair 0:f269e3021894 864 __I uint32_t ENABLE; /* Enable register */
elessair 0:f269e3021894 865 __O uint32_t CLR_STAT; /* Clear register */
elessair 0:f269e3021894 866 __O uint32_t SET_STAT; /* Set register */
elessair 0:f269e3021894 867 } LPC_ATIMER_T;
elessair 0:f269e3021894 868
elessair 0:f269e3021894 869 /* ---------------------------------------------------------------------------
elessair 0:f269e3021894 870 * Register File register block structure
elessair 0:f269e3021894 871 */
elessair 0:f269e3021894 872 #define LPC_REGFILE_BASE 0x40041000
elessair 0:f269e3021894 873
elessair 0:f269e3021894 874 typedef struct {
elessair 0:f269e3021894 875 __IO uint32_t REGFILE[64]; /* General purpose storage register */
elessair 0:f269e3021894 876 } LPC_REGFILE_T;
elessair 0:f269e3021894 877
elessair 0:f269e3021894 878 /* ---------------------------------------------------------------------------
elessair 0:f269e3021894 879 * Power Management Controller register block structure
elessair 0:f269e3021894 880 */
elessair 0:f269e3021894 881 #define LPC_PMC_BASE 0x40042000
elessair 0:f269e3021894 882
elessair 0:f269e3021894 883 typedef struct { /* PMC Structure */
elessair 0:f269e3021894 884 __IO uint32_t PD0_SLEEP0_HW_ENA; /* Hardware sleep event enable register */
elessair 0:f269e3021894 885 __I uint32_t RESERVED0[6];
elessair 0:f269e3021894 886 __IO uint32_t PD0_SLEEP0_MODE; /* Sleep power mode register */
elessair 0:f269e3021894 887 } LPC_PMC_T;
elessair 0:f269e3021894 888
elessair 0:f269e3021894 889 /* ---------------------------------------------------------------------------
elessair 0:f269e3021894 890 * CREG Register Block
elessair 0:f269e3021894 891 */
elessair 0:f269e3021894 892 #define LPC_CREG_BASE 0x40043000
elessair 0:f269e3021894 893
elessair 0:f269e3021894 894 typedef struct { /* CREG Structure */
elessair 0:f269e3021894 895 __I uint32_t RESERVED0;
elessair 0:f269e3021894 896 __IO uint32_t CREG0; /* Chip configuration register 32 kHz oscillator output and BOD control register. */
elessair 0:f269e3021894 897 __I uint32_t RESERVED1[62];
elessair 0:f269e3021894 898 __IO uint32_t MXMEMMAP; /* ARM Cortex-M3/M4 memory mapping */
elessair 0:f269e3021894 899 #if defined(CHIP_LPC18XX)
elessair 0:f269e3021894 900 __I uint32_t RESERVED2[5];
elessair 0:f269e3021894 901 #else
elessair 0:f269e3021894 902 __I uint32_t RESERVED2;
elessair 0:f269e3021894 903 __I uint32_t CREG1; /* Configuration Register 1 */
elessair 0:f269e3021894 904 __I uint32_t CREG2; /* Configuration Register 2 */
elessair 0:f269e3021894 905 __I uint32_t CREG3; /* Configuration Register 3 */
elessair 0:f269e3021894 906 __I uint32_t CREG4; /* Configuration Register 4 */
elessair 0:f269e3021894 907 #endif
elessair 0:f269e3021894 908 __IO uint32_t CREG5; /* Chip configuration register 5. Controls JTAG access. */
elessair 0:f269e3021894 909 __IO uint32_t DMAMUX; /* DMA muxing control */
elessair 0:f269e3021894 910 __IO uint32_t FLASHCFGA; /* Flash accelerator configuration register for flash bank A */
elessair 0:f269e3021894 911 __IO uint32_t FLASHCFGB; /* Flash accelerator configuration register for flash bank B */
elessair 0:f269e3021894 912 __IO uint32_t ETBCFG; /* ETB RAM configuration */
elessair 0:f269e3021894 913 __IO uint32_t CREG6; /* Chip configuration register 6. */
elessair 0:f269e3021894 914 #if defined(CHIP_LPC18XX)
elessair 0:f269e3021894 915 __I uint32_t RESERVED4[52];
elessair 0:f269e3021894 916 #else
elessair 0:f269e3021894 917 __IO uint32_t M4TXEVENT; /* M4 IPC event register */
elessair 0:f269e3021894 918 __I uint32_t RESERVED4[51];
elessair 0:f269e3021894 919 #endif
elessair 0:f269e3021894 920 __I uint32_t CHIPID; /* Part ID */
elessair 0:f269e3021894 921 #if defined(CHIP_LPC18XX)
elessair 0:f269e3021894 922 __I uint32_t RESERVED5[191];
elessair 0:f269e3021894 923 #else
elessair 0:f269e3021894 924 __I uint32_t RESERVED5[127];
elessair 0:f269e3021894 925 __IO uint32_t M0TXEVENT; /* M0 IPC Event register */
elessair 0:f269e3021894 926 __IO uint32_t M0APPMEMMAP; /* ARM Cortex M0 memory mapping */
elessair 0:f269e3021894 927 __I uint32_t RESERVED6[62];
elessair 0:f269e3021894 928 #endif
elessair 0:f269e3021894 929 __IO uint32_t USB0FLADJ; /* USB0 frame length adjust register */
elessair 0:f269e3021894 930 __I uint32_t RESERVED7[63];
elessair 0:f269e3021894 931 __IO uint32_t USB1FLADJ; /* USB1 frame length adjust register */
elessair 0:f269e3021894 932 } LPC_CREG_T;
elessair 0:f269e3021894 933
elessair 0:f269e3021894 934 /* ---------------------------------------------------------------------------
elessair 0:f269e3021894 935 * Event Router register structure
elessair 0:f269e3021894 936 */
elessair 0:f269e3021894 937 #define LPC_EVRT_BASE 0x40044000
elessair 0:f269e3021894 938
elessair 0:f269e3021894 939 typedef struct { /* EVENTROUTER Structure */
elessair 0:f269e3021894 940 __IO uint32_t HILO; /* Level configuration register */
elessair 0:f269e3021894 941 __IO uint32_t EDGE; /* Edge configuration */
elessair 0:f269e3021894 942 __I uint32_t RESERVED0[1012];
elessair 0:f269e3021894 943 __O uint32_t CLR_EN; /* Event clear enable register */
elessair 0:f269e3021894 944 __O uint32_t SET_EN; /* Event set enable register */
elessair 0:f269e3021894 945 __I uint32_t STATUS; /* Status register */
elessair 0:f269e3021894 946 __I uint32_t ENABLE; /* Enable register */
elessair 0:f269e3021894 947 __O uint32_t CLR_STAT; /* Clear register */
elessair 0:f269e3021894 948 __O uint32_t SET_STAT; /* Set register */
elessair 0:f269e3021894 949 } LPC_EVRT_T;
elessair 0:f269e3021894 950
elessair 0:f269e3021894 951 /* ---------------------------------------------------------------------------
elessair 0:f269e3021894 952 * Real Time Clock register block structure
elessair 0:f269e3021894 953 */
elessair 0:f269e3021894 954 #define LPC_RTC_BASE 0x40046000
elessair 0:f269e3021894 955 #define RTC_EV_SUPPORT 1 /* Event Monitor/Recorder support */
elessair 0:f269e3021894 956
elessair 0:f269e3021894 957 typedef enum RTC_TIMEINDEX {
elessair 0:f269e3021894 958 RTC_TIMETYPE_SECOND, /* Second */
elessair 0:f269e3021894 959 RTC_TIMETYPE_MINUTE, /* Month */
elessair 0:f269e3021894 960 RTC_TIMETYPE_HOUR, /* Hour */
elessair 0:f269e3021894 961 RTC_TIMETYPE_DAYOFMONTH, /* Day of month */
elessair 0:f269e3021894 962 RTC_TIMETYPE_DAYOFWEEK, /* Day of week */
elessair 0:f269e3021894 963 RTC_TIMETYPE_DAYOFYEAR, /* Day of year */
elessair 0:f269e3021894 964 RTC_TIMETYPE_MONTH, /* Month */
elessair 0:f269e3021894 965 RTC_TIMETYPE_YEAR, /* Year */
elessair 0:f269e3021894 966 RTC_TIMETYPE_LAST
elessair 0:f269e3021894 967 } RTC_TIMEINDEX_T;
elessair 0:f269e3021894 968
elessair 0:f269e3021894 969 #if RTC_EV_SUPPORT
elessair 0:f269e3021894 970 typedef enum LPC_RTC_EV_CHANNEL {
elessair 0:f269e3021894 971 RTC_EV_CHANNEL_1 = 0,
elessair 0:f269e3021894 972 RTC_EV_CHANNEL_2,
elessair 0:f269e3021894 973 RTC_EV_CHANNEL_3,
elessair 0:f269e3021894 974 RTC_EV_CHANNEL_NUM,
elessair 0:f269e3021894 975 } LPC_RTC_EV_CHANNEL_T;
elessair 0:f269e3021894 976 #endif /*RTC_EV_SUPPORT*/
elessair 0:f269e3021894 977
elessair 0:f269e3021894 978 typedef struct { /* RTC Structure */
elessair 0:f269e3021894 979 __IO uint32_t ILR; /* Interrupt Location Register */
elessair 0:f269e3021894 980 __I uint32_t RESERVED0;
elessair 0:f269e3021894 981 __IO uint32_t CCR; /* Clock Control Register */
elessair 0:f269e3021894 982 __IO uint32_t CIIR; /* Counter Increment Interrupt Register */
elessair 0:f269e3021894 983 __IO uint32_t AMR; /* Alarm Mask Register */
elessair 0:f269e3021894 984 __I uint32_t CTIME[3]; /* Consolidated Time Register 0,1,2 */
elessair 0:f269e3021894 985 __IO uint32_t TIME[RTC_TIMETYPE_LAST]; /* Timer field registers */
elessair 0:f269e3021894 986 __IO uint32_t CALIBRATION; /* Calibration Value Register */
elessair 0:f269e3021894 987 __I uint32_t RESERVED1[7];
elessair 0:f269e3021894 988 __IO uint32_t ALRM[RTC_TIMETYPE_LAST]; /* Alarm field registers */
elessair 0:f269e3021894 989 #if RTC_EV_SUPPORT
elessair 0:f269e3021894 990 __IO uint32_t ERSTATUS; /* Event Monitor/Recorder Status register*/
elessair 0:f269e3021894 991 __IO uint32_t ERCONTROL; /* Event Monitor/Recorder Control register*/
elessair 0:f269e3021894 992 __I uint32_t ERCOUNTERS; /* Event Monitor/Recorder Counters register*/
elessair 0:f269e3021894 993 __I uint32_t RESERVED2;
elessair 0:f269e3021894 994 __I uint32_t ERFIRSTSTAMP[RTC_EV_CHANNEL_NUM]; /* Event Monitor/Recorder First Stamp registers*/
elessair 0:f269e3021894 995 __I uint32_t RESERVED3;
elessair 0:f269e3021894 996 __I uint32_t ERLASTSTAMP[RTC_EV_CHANNEL_NUM]; /* Event Monitor/Recorder Last Stamp registers*/
elessair 0:f269e3021894 997 #endif /*RTC_EV_SUPPORT*/
elessair 0:f269e3021894 998 } LPC_RTC_T;
elessair 0:f269e3021894 999
elessair 0:f269e3021894 1000 /* ---------------------------------------------------------------------------
elessair 0:f269e3021894 1001 * LPC18XX/43XX CGU register block structure
elessair 0:f269e3021894 1002 */
elessair 0:f269e3021894 1003 #define LPC_CGU_BASE 0x40050000
elessair 0:f269e3021894 1004 #define LPC_CCU1_BASE 0x40051000
elessair 0:f269e3021894 1005 #define LPC_CCU2_BASE 0x40052000
elessair 0:f269e3021894 1006 /*
elessair 0:f269e3021894 1007 * Input clocks for the CGU and can come from both external (crystal) and
elessair 0:f269e3021894 1008 * internal (PLL) sources. Can be routed to the base clocks.
elessair 0:f269e3021894 1009 */
elessair 0:f269e3021894 1010 typedef enum CGU_CLKIN {
elessair 0:f269e3021894 1011 CLKIN_32K, /* External 32KHz input */
elessair 0:f269e3021894 1012 CLKIN_IRC, /* Internal IRC (12MHz) input */
elessair 0:f269e3021894 1013 CLKIN_ENET_RX, /* External ENET_RX pin input */
elessair 0:f269e3021894 1014 CLKIN_ENET_TX, /* External ENET_TX pin input */
elessair 0:f269e3021894 1015 CLKIN_CLKIN, /* External GPCLKIN pin input */
elessair 0:f269e3021894 1016 CLKIN_RESERVED1,
elessair 0:f269e3021894 1017 CLKIN_CRYSTAL, /* External (main) crystal pin input */
elessair 0:f269e3021894 1018 CLKIN_USBPLL, /* Internal USB PLL input */
elessair 0:f269e3021894 1019 CLKIN_AUDIOPLL, /* Internal Audio PLL input */
elessair 0:f269e3021894 1020 CLKIN_MAINPLL, /* Internal Main PLL input */
elessair 0:f269e3021894 1021 CLKIN_RESERVED2,
elessair 0:f269e3021894 1022 CLKIN_RESERVED3,
elessair 0:f269e3021894 1023 CLKIN_IDIVA, /* Internal divider A input */
elessair 0:f269e3021894 1024 CLKIN_IDIVB, /* Internal divider B input */
elessair 0:f269e3021894 1025 CLKIN_IDIVC, /* Internal divider C input */
elessair 0:f269e3021894 1026 CLKIN_IDIVD, /* Internal divider D input */
elessair 0:f269e3021894 1027 CLKIN_IDIVE, /* Internal divider E input */
elessair 0:f269e3021894 1028 CLKINPUT_PD /* External 32KHz input */
elessair 0:f269e3021894 1029 } CGU_CLKIN_T;
elessair 0:f269e3021894 1030
elessair 0:f269e3021894 1031 #define CLKIN_PLL0USB CLKIN_USBPLL
elessair 0:f269e3021894 1032 #define CLKIN_PLL0AUDIO CLKIN_AUDIOPLL
elessair 0:f269e3021894 1033 #define CLKIN_PLL1 CLKIN_MAINPLL
elessair 0:f269e3021894 1034
elessair 0:f269e3021894 1035 /*
elessair 0:f269e3021894 1036 * CGU base clocks are clocks that are associated with a single input clock
elessair 0:f269e3021894 1037 * and are routed out to 1 or more peripherals. For example, the CLK_BASE_PERIPH
elessair 0:f269e3021894 1038 * clock can be configured to use the CLKIN_MAINPLL input clock, which will in
elessair 0:f269e3021894 1039 * turn route that clock to the CLK_PERIPH_BUS, CLK_PERIPH_CORE, and
elessair 0:f269e3021894 1040 * CLK_PERIPH_SGPIO periphral clocks.
elessair 0:f269e3021894 1041 */
elessair 0:f269e3021894 1042 typedef enum CGU_BASE_CLK {
elessair 0:f269e3021894 1043 CLK_BASE_SAFE, /* Base clock for WDT oscillator, IRC input only */
elessair 0:f269e3021894 1044 CLK_BASE_USB0, /* Base USB clock for USB0, USB PLL input only */
elessair 0:f269e3021894 1045 #if defined(CHIP_LPC43XX)
elessair 0:f269e3021894 1046 CLK_BASE_PERIPH, /* Base clock for SGPIO */
elessair 0:f269e3021894 1047 #else
elessair 0:f269e3021894 1048 CLK_BASE_RESERVED1,
elessair 0:f269e3021894 1049 #endif
elessair 0:f269e3021894 1050 CLK_BASE_USB1, /* Base USB clock for USB1 */
elessair 0:f269e3021894 1051 CLK_BASE_MX, /* Base clock for CPU core */
elessair 0:f269e3021894 1052 CLK_BASE_SPIFI, /* Base clock for SPIFI */
elessair 0:f269e3021894 1053 #if defined(CHIP_LPC43XX)
elessair 0:f269e3021894 1054 CLK_BASE_SPI, /* Base clock for SPI */
elessair 0:f269e3021894 1055 #else
elessair 0:f269e3021894 1056 CLK_BASE_RESERVED2,
elessair 0:f269e3021894 1057 #endif
elessair 0:f269e3021894 1058 CLK_BASE_PHY_RX, /* Base clock for PHY RX */
elessair 0:f269e3021894 1059 CLK_BASE_PHY_TX, /* Base clock for PHY TX */
elessair 0:f269e3021894 1060 CLK_BASE_APB1, /* Base clock for APB1 group */
elessair 0:f269e3021894 1061 CLK_BASE_APB3, /* Base clock for APB3 group */
elessair 0:f269e3021894 1062 CLK_BASE_LCD, /* Base clock for LCD pixel clock */
elessair 0:f269e3021894 1063 #if defined(CHIP_LPC43XX)
elessair 0:f269e3021894 1064 CLK_BASE_VADC, /* Base clock for VADC */
elessair 0:f269e3021894 1065 #else
elessair 0:f269e3021894 1066 CLK_BASE_RESERVED3,
elessair 0:f269e3021894 1067 #endif
elessair 0:f269e3021894 1068 CLK_BASE_SDIO, /* Base clock for SDIO */
elessair 0:f269e3021894 1069 CLK_BASE_SSP0, /* Base clock for SSP0 */
elessair 0:f269e3021894 1070 CLK_BASE_SSP1, /* Base clock for SSP1 */
elessair 0:f269e3021894 1071 CLK_BASE_UART0, /* Base clock for UART0 */
elessair 0:f269e3021894 1072 CLK_BASE_UART1, /* Base clock for UART1 */
elessair 0:f269e3021894 1073 CLK_BASE_UART2, /* Base clock for UART2 */
elessair 0:f269e3021894 1074 CLK_BASE_UART3, /* Base clock for UART3 */
elessair 0:f269e3021894 1075 CLK_BASE_OUT, /* Base clock for CLKOUT pin */
elessair 0:f269e3021894 1076 CLK_BASE_RESERVED4,
elessair 0:f269e3021894 1077 CLK_BASE_RESERVED5,
elessair 0:f269e3021894 1078 CLK_BASE_RESERVED6,
elessair 0:f269e3021894 1079 CLK_BASE_RESERVED7,
elessair 0:f269e3021894 1080 CLK_BASE_APLL, /* Base clock for audio PLL */
elessair 0:f269e3021894 1081 CLK_BASE_CGU_OUT0, /* Base clock for CGUOUT0 pin */
elessair 0:f269e3021894 1082 CLK_BASE_CGU_OUT1, /* Base clock for CGUOUT1 pin */
elessair 0:f269e3021894 1083 CLK_BASE_LAST,
elessair 0:f269e3021894 1084 CLK_BASE_NONE = CLK_BASE_LAST
elessair 0:f269e3021894 1085 } CGU_BASE_CLK_T;
elessair 0:f269e3021894 1086
elessair 0:f269e3021894 1087 /*
elessair 0:f269e3021894 1088 * CGU dividers provide an extra clock state where a specific clock can be
elessair 0:f269e3021894 1089 * divided before being routed to a peripheral group. A divider accepts an
elessair 0:f269e3021894 1090 * input clock and then divides it. To use the divided clock for a base clock
elessair 0:f269e3021894 1091 * group, use the divider as the input clock for the base clock (for example,
elessair 0:f269e3021894 1092 * use CLKIN_IDIVB, where CLKIN_MAINPLL might be the input into the divider).
elessair 0:f269e3021894 1093 */
elessair 0:f269e3021894 1094 typedef enum CGU_IDIV {
elessair 0:f269e3021894 1095 CLK_IDIV_A, /* CGU clock divider A */
elessair 0:f269e3021894 1096 CLK_IDIV_B, /* CGU clock divider B */
elessair 0:f269e3021894 1097 CLK_IDIV_C, /* CGU clock divider A */
elessair 0:f269e3021894 1098 CLK_IDIV_D, /* CGU clock divider D */
elessair 0:f269e3021894 1099 CLK_IDIV_E, /* CGU clock divider E */
elessair 0:f269e3021894 1100 CLK_IDIV_LAST
elessair 0:f269e3021894 1101 } CGU_IDIV_T;
elessair 0:f269e3021894 1102
elessair 0:f269e3021894 1103 /*
elessair 0:f269e3021894 1104 * Peripheral clocks are individual clocks routed to peripherals. Although
elessair 0:f269e3021894 1105 * multiple peripherals may share a same base clock, each peripheral's clock
elessair 0:f269e3021894 1106 * can be enabled or disabled individually. Some peripheral clocks also have
elessair 0:f269e3021894 1107 * additional dividers associated with them.
elessair 0:f269e3021894 1108 */
elessair 0:f269e3021894 1109 typedef enum CCU_CLK {
elessair 0:f269e3021894 1110 /* CCU1 clocks */
elessair 0:f269e3021894 1111 CLK_APB3_BUS, /* APB3 bus clock from base clock CLK_BASE_APB3 */
elessair 0:f269e3021894 1112 CLK_APB3_I2C1, /* I2C1 register/perigheral clock from base clock CLK_BASE_APB3 */
elessair 0:f269e3021894 1113 CLK_APB3_DAC, /* DAC peripheral clock from base clock CLK_BASE_APB3 */
elessair 0:f269e3021894 1114 CLK_APB3_ADC0, /* ADC0 register/perigheral clock from base clock CLK_BASE_APB3 */
elessair 0:f269e3021894 1115 CLK_APB3_ADC1, /* ADC1 register/perigheral clock from base clock CLK_BASE_APB3 */
elessair 0:f269e3021894 1116 CLK_APB3_CAN0, /* CAN0 register/perigheral clock from base clock CLK_BASE_APB3 */
elessair 0:f269e3021894 1117 CLK_APB1_BUS = 32, /* APB1 bus clock clock from base clock CLK_BASE_APB1 */
elessair 0:f269e3021894 1118 CLK_APB1_MOTOCON, /* Motor controller register/perigheral clock from base clock CLK_BASE_APB1 */
elessair 0:f269e3021894 1119 CLK_APB1_I2C0, /* I2C0 register/perigheral clock from base clock CLK_BASE_APB1 */
elessair 0:f269e3021894 1120 CLK_APB1_I2S, /* I2S register/perigheral clock from base clock CLK_BASE_APB1 */
elessair 0:f269e3021894 1121 CLK_APB1_CAN1, /* CAN1 register/perigheral clock from base clock CLK_BASE_APB1 */
elessair 0:f269e3021894 1122 CLK_SPIFI = 64, /* SPIFI SCKI input clock from base clock CLK_BASE_SPIFI */
elessair 0:f269e3021894 1123 CLK_MX_BUS = 96, /* M3/M4 BUS core clock from base clock CLK_BASE_MX */
elessair 0:f269e3021894 1124 CLK_MX_SPIFI, /* SPIFI register clock from base clock CLK_BASE_MX */
elessair 0:f269e3021894 1125 CLK_MX_GPIO, /* GPIO register clock from base clock CLK_BASE_MX */
elessair 0:f269e3021894 1126 CLK_MX_LCD, /* LCD register clock from base clock CLK_BASE_MX */
elessair 0:f269e3021894 1127 CLK_MX_ETHERNET, /* ETHERNET register clock from base clock CLK_BASE_MX */
elessair 0:f269e3021894 1128 CLK_MX_USB0, /* USB0 register clock from base clock CLK_BASE_MX */
elessair 0:f269e3021894 1129 CLK_MX_EMC, /* EMC clock from base clock CLK_BASE_MX */
elessair 0:f269e3021894 1130 CLK_MX_SDIO, /* SDIO register clock from base clock CLK_BASE_MX */
elessair 0:f269e3021894 1131 CLK_MX_DMA, /* DMA register clock from base clock CLK_BASE_MX */
elessair 0:f269e3021894 1132 CLK_MX_MXCORE, /* M3/M4 CPU core clock from base clock CLK_BASE_MX */
elessair 0:f269e3021894 1133 RESERVED_ALIGN = CLK_MX_MXCORE + 3,
elessair 0:f269e3021894 1134 CLK_MX_SCT, /* SCT register clock from base clock CLK_BASE_MX */
elessair 0:f269e3021894 1135 CLK_MX_USB1, /* USB1 register clock from base clock CLK_BASE_MX */
elessair 0:f269e3021894 1136 CLK_MX_EMC_DIV, /* ENC divider clock from base clock CLK_BASE_MX */
elessair 0:f269e3021894 1137 CLK_MX_FLASHA, /* FLASHA bank clock from base clock CLK_BASE_MX */
elessair 0:f269e3021894 1138 CLK_MX_FLASHB, /* FLASHB bank clock from base clock CLK_BASE_MX */
elessair 0:f269e3021894 1139 #if defined(CHIP_LPC43XX)
elessair 0:f269e3021894 1140 CLK_M4_M0APP, /* M0 app CPU core clock from base clock CLK_BASE_MX */
elessair 0:f269e3021894 1141 CLK_MX_VADC, /* VADC clock from base clock CLK_BASE_MX */
elessair 0:f269e3021894 1142 #else
elessair 0:f269e3021894 1143 CLK_RESERVED1,
elessair 0:f269e3021894 1144 CLK_RESERVED2,
elessair 0:f269e3021894 1145 #endif
elessair 0:f269e3021894 1146 CLK_MX_EEPROM, /* EEPROM clock from base clock CLK_BASE_MX */
elessair 0:f269e3021894 1147 CLK_MX_WWDT = 128, /* WWDT register clock from base clock CLK_BASE_MX */
elessair 0:f269e3021894 1148 CLK_MX_UART0, /* UART0 register clock from base clock CLK_BASE_MX */
elessair 0:f269e3021894 1149 CLK_MX_UART1, /* UART1 register clock from base clock CLK_BASE_MX */
elessair 0:f269e3021894 1150 CLK_MX_SSP0, /* SSP0 register clock from base clock CLK_BASE_MX */
elessair 0:f269e3021894 1151 CLK_MX_TIMER0, /* TIMER0 register/perigheral clock from base clock CLK_BASE_MX */
elessair 0:f269e3021894 1152 CLK_MX_TIMER1, /* TIMER1 register/perigheral clock from base clock CLK_BASE_MX */
elessair 0:f269e3021894 1153 CLK_MX_SCU, /* SCU register/perigheral clock from base clock CLK_BASE_MX */
elessair 0:f269e3021894 1154 CLK_MX_CREG, /* CREG clock from base clock CLK_BASE_MX */
elessair 0:f269e3021894 1155 CLK_MX_RITIMER = 160, /* RITIMER register/perigheral clock from base clock CLK_BASE_MX */
elessair 0:f269e3021894 1156 CLK_MX_UART2, /* UART3 register clock from base clock CLK_BASE_MX */
elessair 0:f269e3021894 1157 CLK_MX_UART3, /* UART4 register clock from base clock CLK_BASE_MX */
elessair 0:f269e3021894 1158 CLK_MX_TIMER2, /* TIMER2 register/perigheral clock from base clock CLK_BASE_MX */
elessair 0:f269e3021894 1159 CLK_MX_TIMER3, /* TIMER3 register/perigheral clock from base clock CLK_BASE_MX */
elessair 0:f269e3021894 1160 CLK_MX_SSP1, /* SSP1 register clock from base clock CLK_BASE_MX */
elessair 0:f269e3021894 1161 CLK_MX_QEI, /* QEI register/perigheral clock from base clock CLK_BASE_MX */
elessair 0:f269e3021894 1162 #if defined(CHIP_LPC43XX)
elessair 0:f269e3021894 1163 CLK_PERIPH_BUS = 192, /* Peripheral bus clock from base clock CLK_BASE_PERIPH */
elessair 0:f269e3021894 1164 CLK_RESERVED3,
elessair 0:f269e3021894 1165 CLK_PERIPH_CORE, /* Peripheral core clock from base clock CLK_BASE_PERIPH */
elessair 0:f269e3021894 1166 CLK_PERIPH_SGPIO, /* SGPIO clock from base clock CLK_BASE_PERIPH */
elessair 0:f269e3021894 1167 #else
elessair 0:f269e3021894 1168 CLK_RESERVED3 = 192,
elessair 0:f269e3021894 1169 CLK_RESERVED3A,
elessair 0:f269e3021894 1170 CLK_RESERVED4,
elessair 0:f269e3021894 1171 CLK_RESERVED5,
elessair 0:f269e3021894 1172 #endif
elessair 0:f269e3021894 1173 CLK_USB0 = 224, /* USB0 clock from base clock CLK_BASE_USB0 */
elessair 0:f269e3021894 1174 CLK_USB1 = 256, /* USB1 clock from base clock CLK_BASE_USB1 */
elessair 0:f269e3021894 1175 #if defined(CHIP_LPC43XX)
elessair 0:f269e3021894 1176 CLK_SPI = 288, /* SPI clock from base clock CLK_BASE_SPI */
elessair 0:f269e3021894 1177 CLK_VADC, /* VADC clock from base clock CLK_BASE_VADC */
elessair 0:f269e3021894 1178 #else
elessair 0:f269e3021894 1179 CLK_RESERVED7 = 320,
elessair 0:f269e3021894 1180 CLK_RESERVED8,
elessair 0:f269e3021894 1181 #endif
elessair 0:f269e3021894 1182 CLK_CCU1_LAST,
elessair 0:f269e3021894 1183
elessair 0:f269e3021894 1184 /* CCU2 clocks */
elessair 0:f269e3021894 1185 CLK_CCU2_START,
elessair 0:f269e3021894 1186 CLK_APLL = CLK_CCU2_START, /* Audio PLL clock from base clock CLK_BASE_APLL */
elessair 0:f269e3021894 1187 RESERVED_ALIGNB = CLK_CCU2_START + 31,
elessair 0:f269e3021894 1188 CLK_APB2_UART3, /* UART3 clock from base clock CLK_BASE_UART3 */
elessair 0:f269e3021894 1189 RESERVED_ALIGNC = CLK_CCU2_START + 63,
elessair 0:f269e3021894 1190 CLK_APB2_UART2, /* UART2 clock from base clock CLK_BASE_UART2 */
elessair 0:f269e3021894 1191 RESERVED_ALIGND = CLK_CCU2_START + 95,
elessair 0:f269e3021894 1192 CLK_APB0_UART1, /* UART1 clock from base clock CLK_BASE_UART1 */
elessair 0:f269e3021894 1193 RESERVED_ALIGNE = CLK_CCU2_START + 127,
elessair 0:f269e3021894 1194 CLK_APB0_UART0, /* UART0 clock from base clock CLK_BASE_UART0 */
elessair 0:f269e3021894 1195 RESERVED_ALIGNF = CLK_CCU2_START + 159,
elessair 0:f269e3021894 1196 CLK_APB2_SSP1, /* SSP1 clock from base clock CLK_BASE_SSP1 */
elessair 0:f269e3021894 1197 RESERVED_ALIGNG = CLK_CCU2_START + 191,
elessair 0:f269e3021894 1198 CLK_APB0_SSP0, /* SSP0 clock from base clock CLK_BASE_SSP0 */
elessair 0:f269e3021894 1199 RESERVED_ALIGNH = CLK_CCU2_START + 223,
elessair 0:f269e3021894 1200 CLK_APB2_SDIO, /* SDIO clock from base clock CLK_BASE_SDIO */
elessair 0:f269e3021894 1201 CLK_CCU2_LAST
elessair 0:f269e3021894 1202 } CCU_CLK_T;
elessair 0:f269e3021894 1203
elessair 0:f269e3021894 1204 /*
elessair 0:f269e3021894 1205 * Audio or USB PLL selection
elessair 0:f269e3021894 1206 */
elessair 0:f269e3021894 1207 typedef enum CGU_USB_AUDIO_PLL {
elessair 0:f269e3021894 1208 CGU_USB_PLL,
elessair 0:f269e3021894 1209 CGU_AUDIO_PLL
elessair 0:f269e3021894 1210 } CGU_USB_AUDIO_PLL_T;
elessair 0:f269e3021894 1211
elessair 0:f269e3021894 1212 /*
elessair 0:f269e3021894 1213 * PLL register block
elessair 0:f269e3021894 1214 */
elessair 0:f269e3021894 1215 typedef struct {
elessair 0:f269e3021894 1216 __I uint32_t PLL_STAT; /* PLL status register */
elessair 0:f269e3021894 1217 __IO uint32_t PLL_CTRL; /* PLL control register */
elessair 0:f269e3021894 1218 __IO uint32_t PLL_MDIV; /* PLL M-divider register */
elessair 0:f269e3021894 1219 __IO uint32_t PLL_NP_DIV; /* PLL N/P-divider register */
elessair 0:f269e3021894 1220 } CGU_PLL_REG_T;
elessair 0:f269e3021894 1221
elessair 0:f269e3021894 1222 typedef struct { /* (@ 0x40050000) CGU Structure */
elessair 0:f269e3021894 1223 __I uint32_t RESERVED0[5];
elessair 0:f269e3021894 1224 __IO uint32_t FREQ_MON; /* (@ 0x40050014) Frequency monitor register */
elessair 0:f269e3021894 1225 __IO uint32_t XTAL_OSC_CTRL; /* (@ 0x40050018) Crystal oscillator control register */
elessair 0:f269e3021894 1226 CGU_PLL_REG_T PLL[CGU_AUDIO_PLL + 1]; /* (@ 0x4005001C) USB and audio PLL blocks */
elessair 0:f269e3021894 1227 __IO uint32_t PLL0AUDIO_FRAC; /* (@ 0x4005003C) PLL0 (audio) */
elessair 0:f269e3021894 1228 __I uint32_t PLL1_STAT; /* (@ 0x40050040) PLL1 status register */
elessair 0:f269e3021894 1229 __IO uint32_t PLL1_CTRL; /* (@ 0x40050044) PLL1 control register */
elessair 0:f269e3021894 1230 __IO uint32_t IDIV_CTRL[CLK_IDIV_LAST];/* (@ 0x40050048) Integer divider A-E control registers */
elessair 0:f269e3021894 1231 __IO uint32_t BASE_CLK[CLK_BASE_LAST]; /* (@ 0x4005005C) Start of base clock registers */
elessair 0:f269e3021894 1232 } LPC_CGU_T;
elessair 0:f269e3021894 1233
elessair 0:f269e3021894 1234 /* ---------------------------------------------------------------------------
elessair 0:f269e3021894 1235 * CCU clock config/status register pair
elessair 0:f269e3021894 1236 */
elessair 0:f269e3021894 1237 typedef struct {
elessair 0:f269e3021894 1238 __IO uint32_t CFG; /* CCU clock configuration register */
elessair 0:f269e3021894 1239 __I uint32_t STAT; /* CCU clock status register */
elessair 0:f269e3021894 1240 } CCU_CFGSTAT_T;
elessair 0:f269e3021894 1241
elessair 0:f269e3021894 1242 /* ---------------------------------------------------------------------------
elessair 0:f269e3021894 1243 * CCU1 register block structure
elessair 0:f269e3021894 1244 */
elessair 0:f269e3021894 1245 typedef struct { /* (@ 0x40051000) CCU1 Structure */
elessair 0:f269e3021894 1246 __IO uint32_t PM; /* (@ 0x40051000) CCU1 power mode register */
elessair 0:f269e3021894 1247 __I uint32_t BASE_STAT; /* (@ 0x40051004) CCU1 base clocks status register */
elessair 0:f269e3021894 1248 __I uint32_t RESERVED0[62];
elessair 0:f269e3021894 1249 CCU_CFGSTAT_T CLKCCU[CLK_CCU1_LAST]; /* (@ 0x40051100) Start of CCU1 clock registers */
elessair 0:f269e3021894 1250 } LPC_CCU1_T;
elessair 0:f269e3021894 1251
elessair 0:f269e3021894 1252 /* ---------------------------------------------------------------------------
elessair 0:f269e3021894 1253 * CCU2 register block structure
elessair 0:f269e3021894 1254 */
elessair 0:f269e3021894 1255 typedef struct { /* (@ 0x40052000) CCU2 Structure */
elessair 0:f269e3021894 1256 __IO uint32_t PM; /* (@ 0x40052000) Power mode register */
elessair 0:f269e3021894 1257 __I uint32_t BASE_STAT; /* (@ 0x40052004) CCU base clocks status register */
elessair 0:f269e3021894 1258 __I uint32_t RESERVED0[62];
elessair 0:f269e3021894 1259 CCU_CFGSTAT_T CLKCCU[CLK_CCU2_LAST - CLK_CCU1_LAST]; /* (@ 0x40052100) Start of CCU2 clock registers */
elessair 0:f269e3021894 1260 } LPC_CCU2_T;
elessair 0:f269e3021894 1261
elessair 0:f269e3021894 1262 /* ---------------------------------------------------------------------------
elessair 0:f269e3021894 1263 * RGU register structure
elessair 0:f269e3021894 1264 */
elessair 0:f269e3021894 1265 #define LPC_RGU_BASE 0x40053000
elessair 0:f269e3021894 1266
elessair 0:f269e3021894 1267 typedef enum RGU_RST {
elessair 0:f269e3021894 1268 RGU_CORE_RST,
elessair 0:f269e3021894 1269 RGU_PERIPH_RST,
elessair 0:f269e3021894 1270 RGU_MASTER_RST,
elessair 0:f269e3021894 1271 RGU_WWDT_RST = 4,
elessair 0:f269e3021894 1272 RGU_CREG_RST,
elessair 0:f269e3021894 1273 RGU_BUS_RST = 8,
elessair 0:f269e3021894 1274 RGU_SCU_RST,
elessair 0:f269e3021894 1275 RGU_M3_RST = 13,
elessair 0:f269e3021894 1276 RGU_LCD_RST = 16,
elessair 0:f269e3021894 1277 RGU_USB0_RST,
elessair 0:f269e3021894 1278 RGU_USB1_RST,
elessair 0:f269e3021894 1279 RGU_DMA_RST,
elessair 0:f269e3021894 1280 RGU_SDIO_RST,
elessair 0:f269e3021894 1281 RGU_EMC_RST,
elessair 0:f269e3021894 1282 RGU_ETHERNET_RST,
elessair 0:f269e3021894 1283 RGU_FLASHA_RST = 25,
elessair 0:f269e3021894 1284 RGU_EEPROM_RST = 27,
elessair 0:f269e3021894 1285 RGU_GPIO_RST,
elessair 0:f269e3021894 1286 RGU_FLASHB_RST,
elessair 0:f269e3021894 1287 RGU_TIMER0_RST = 32,
elessair 0:f269e3021894 1288 RGU_TIMER1_RST,
elessair 0:f269e3021894 1289 RGU_TIMER2_RST,
elessair 0:f269e3021894 1290 RGU_TIMER3_RST,
elessair 0:f269e3021894 1291 RGU_RITIMER_RST,
elessair 0:f269e3021894 1292 RGU_SCT_RST,
elessair 0:f269e3021894 1293 RGU_MOTOCONPWM_RST,
elessair 0:f269e3021894 1294 RGU_QEI_RST,
elessair 0:f269e3021894 1295 RGU_ADC0_RST,
elessair 0:f269e3021894 1296 RGU_ADC1_RST,
elessair 0:f269e3021894 1297 RGU_DAC_RST,
elessair 0:f269e3021894 1298 RGU_UART0_RST = 44,
elessair 0:f269e3021894 1299 RGU_UART1_RST,
elessair 0:f269e3021894 1300 RGU_UART2_RST,
elessair 0:f269e3021894 1301 RGU_UART3_RST,
elessair 0:f269e3021894 1302 RGU_I2C0_RST,
elessair 0:f269e3021894 1303 RGU_I2C1_RST,
elessair 0:f269e3021894 1304 RGU_SSP0_RST,
elessair 0:f269e3021894 1305 RGU_SSP1_RST,
elessair 0:f269e3021894 1306 RGU_I2S_RST,
elessair 0:f269e3021894 1307 RGU_SPIFI_RST,
elessair 0:f269e3021894 1308 RGU_CAN1_RST,
elessair 0:f269e3021894 1309 RGU_CAN0_RST,
elessair 0:f269e3021894 1310 #ifdef CHIP_LPC43XX
elessair 0:f269e3021894 1311 RGU_M0APP_RST,
elessair 0:f269e3021894 1312 RGU_SGPIO_RST,
elessair 0:f269e3021894 1313 RGU_SPI_RST,
elessair 0:f269e3021894 1314 #endif
elessair 0:f269e3021894 1315 RGU_LAST_RST = 63,
elessair 0:f269e3021894 1316 } RGU_RST_T;
elessair 0:f269e3021894 1317
elessair 0:f269e3021894 1318 typedef struct { /* RGU Structure */
elessair 0:f269e3021894 1319 __I uint32_t RESERVED0[64];
elessair 0:f269e3021894 1320 __O uint32_t RESET_CTRL0; /* Reset control register 0 */
elessair 0:f269e3021894 1321 __O uint32_t RESET_CTRL1; /* Reset control register 1 */
elessair 0:f269e3021894 1322 __I uint32_t RESERVED1[2];
elessair 0:f269e3021894 1323 __IO uint32_t RESET_STATUS0; /* Reset status register 0 */
elessair 0:f269e3021894 1324 __IO uint32_t RESET_STATUS1; /* Reset status register 1 */
elessair 0:f269e3021894 1325 __IO uint32_t RESET_STATUS2; /* Reset status register 2 */
elessair 0:f269e3021894 1326 __IO uint32_t RESET_STATUS3; /* Reset status register 3 */
elessair 0:f269e3021894 1327 __I uint32_t RESERVED2[12];
elessair 0:f269e3021894 1328 __I uint32_t RESET_ACTIVE_STATUS0;/* Reset active status register 0 */
elessair 0:f269e3021894 1329 __I uint32_t RESET_ACTIVE_STATUS1;/* Reset active status register 1 */
elessair 0:f269e3021894 1330 __I uint32_t RESERVED3[170];
elessair 0:f269e3021894 1331 __IO uint32_t RESET_EXT_STAT[RGU_LAST_RST + 1];/* Reset external status registers */
elessair 0:f269e3021894 1332 } LPC_RGU_T;
elessair 0:f269e3021894 1333
elessair 0:f269e3021894 1334 /* ---------------------------------------------------------------------------
elessair 0:f269e3021894 1335 * Windowed Watchdog register block structure
elessair 0:f269e3021894 1336 */
elessair 0:f269e3021894 1337 #define LPC_WWDT_BASE 0x40080000
elessair 0:f269e3021894 1338
elessair 0:f269e3021894 1339 typedef struct { /* WWDT Structure */
elessair 0:f269e3021894 1340 __IO uint32_t MOD; /* Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */
elessair 0:f269e3021894 1341 __IO uint32_t TC; /* Watchdog timer constant register. This register determines the time-out value. */
elessair 0:f269e3021894 1342 __O uint32_t FEED; /* Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC. */
elessair 0:f269e3021894 1343 __I uint32_t TV; /* Watchdog timer value register. This register reads out the current value of the Watchdog timer. */
elessair 0:f269e3021894 1344 #ifdef WATCHDOG_CLKSEL_SUPPORT
elessair 0:f269e3021894 1345 __IO uint32_t CLKSEL; /* Watchdog clock select register. */
elessair 0:f269e3021894 1346 #else
elessair 0:f269e3021894 1347 __I uint32_t RESERVED0;
elessair 0:f269e3021894 1348 #endif
elessair 0:f269e3021894 1349 #ifdef WATCHDOG_WINDOW_SUPPORT
elessair 0:f269e3021894 1350 __IO uint32_t WARNINT; /* Watchdog warning interrupt register. This register contains the Watchdog warning interrupt compare value. */
elessair 0:f269e3021894 1351 __IO uint32_t WINDOW; /* Watchdog timer window register. This register contains the Watchdog window value. */
elessair 0:f269e3021894 1352 #endif
elessair 0:f269e3021894 1353 } LPC_WWDT_T;
elessair 0:f269e3021894 1354
elessair 0:f269e3021894 1355 /* ---------------------------------------------------------------------------
elessair 0:f269e3021894 1356 * USART register block structure
elessair 0:f269e3021894 1357 */
elessair 0:f269e3021894 1358 #define LPC_USART0_BASE 0x40081000
elessair 0:f269e3021894 1359 #define LPC_UART1_BASE 0x40082000
elessair 0:f269e3021894 1360 #define LPC_USART2_BASE 0x400C1000
elessair 0:f269e3021894 1361 #define LPC_USART3_BASE 0x400C2000
elessair 0:f269e3021894 1362
elessair 0:f269e3021894 1363 typedef struct { /* USARTn Structure */
elessair 0:f269e3021894 1364
elessair 0:f269e3021894 1365 union {
elessair 0:f269e3021894 1366 __IO uint32_t DLL; /* Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). */
elessair 0:f269e3021894 1367 __O uint32_t THR; /* Transmit Holding Register. The next character to be transmitted is written here (DLAB = 0). */
elessair 0:f269e3021894 1368 __I uint32_t RBR; /* Receiver Buffer Register. Contains the next received character to be read (DLAB = 0). */
elessair 0:f269e3021894 1369 };
elessair 0:f269e3021894 1370
elessair 0:f269e3021894 1371 union {
elessair 0:f269e3021894 1372 __IO uint32_t IER; /* Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB = 0). */
elessair 0:f269e3021894 1373 __IO uint32_t DLM; /* Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). */
elessair 0:f269e3021894 1374 };
elessair 0:f269e3021894 1375
elessair 0:f269e3021894 1376 union {
elessair 0:f269e3021894 1377 __O uint32_t FCR; /* FIFO Control Register. Controls UART FIFO usage and modes. */
elessair 0:f269e3021894 1378 __I uint32_t IIR; /* Interrupt ID Register. Identifies which interrupt(s) are pending. */
elessair 0:f269e3021894 1379 };
elessair 0:f269e3021894 1380
elessair 0:f269e3021894 1381 __IO uint32_t LCR; /* Line Control Register. Contains controls for frame formatting and break generation. */
elessair 0:f269e3021894 1382 __IO uint32_t MCR; /* Modem Control Register. Only present on USART ports with full modem support. */
elessair 0:f269e3021894 1383 __I uint32_t LSR; /* Line Status Register. Contains flags for transmit and receive status, including line errors. */
elessair 0:f269e3021894 1384 __I uint32_t MSR; /* Modem Status Register. Only present on USART ports with full modem support. */
elessair 0:f269e3021894 1385 __IO uint32_t SCR; /* Scratch Pad Register. Eight-bit temporary storage for software. */
elessair 0:f269e3021894 1386 __IO uint32_t ACR; /* Auto-baud Control Register. Contains controls for the auto-baud feature. */
elessair 0:f269e3021894 1387 __IO uint32_t ICR; /* IrDA control register (not all UARTS) */
elessair 0:f269e3021894 1388 __IO uint32_t FDR; /* Fractional Divider Register. Generates a clock input for the baud rate divider. */
elessair 0:f269e3021894 1389 __IO uint32_t OSR; /* Oversampling Register. Controls the degree of oversampling during each bit time. Only on some UARTS. */
elessair 0:f269e3021894 1390 __IO uint32_t TER1; /* Transmit Enable Register. Turns off USART transmitter for use with software flow control. */
elessair 0:f269e3021894 1391 uint32_t RESERVED0[3];
elessair 0:f269e3021894 1392 __IO uint32_t HDEN; /* Half-duplex enable Register- only on some UARTs */
elessair 0:f269e3021894 1393 __I uint32_t RESERVED1[1];
elessair 0:f269e3021894 1394 __IO uint32_t SCICTRL; /* Smart card interface control register- only on some UARTs */
elessair 0:f269e3021894 1395 __IO uint32_t RS485CTRL; /* RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */
elessair 0:f269e3021894 1396 __IO uint32_t RS485ADRMATCH; /* RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */
elessair 0:f269e3021894 1397 __IO uint32_t RS485DLY; /* RS-485/EIA-485 direction control delay. */
elessair 0:f269e3021894 1398 union {
elessair 0:f269e3021894 1399 __IO uint32_t SYNCCTRL; /* Synchronous mode control register. Only on USARTs. */
elessair 0:f269e3021894 1400 __I uint32_t FIFOLVL; /* FIFO Level register. Provides the current fill levels of the transmit and receive FIFOs. */
elessair 0:f269e3021894 1401 };
elessair 0:f269e3021894 1402
elessair 0:f269e3021894 1403 __IO uint32_t TER2; /* Transmit Enable Register. Only on LPC177X_8X UART4 and LPC18XX/43XX USART0/2/3. */
elessair 0:f269e3021894 1404 } LPC_USART_T;
elessair 0:f269e3021894 1405
elessair 0:f269e3021894 1406 /* ---------------------------------------------------------------------------
elessair 0:f269e3021894 1407 * SSP register block structure
elessair 0:f269e3021894 1408 */
elessair 0:f269e3021894 1409 #define LPC_SSP0_BASE 0x40083000
elessair 0:f269e3021894 1410 #define LPC_SSP1_BASE 0x400C5000
elessair 0:f269e3021894 1411
elessair 0:f269e3021894 1412 typedef struct { /* SSPn Structure */
elessair 0:f269e3021894 1413 __IO uint32_t CR0; /* Control Register 0. Selects the serial clock rate, bus type, and data size. */
elessair 0:f269e3021894 1414 __IO uint32_t CR1; /* Control Register 1. Selects master/slave and other modes. */
elessair 0:f269e3021894 1415 __IO uint32_t DR; /* Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */
elessair 0:f269e3021894 1416 __I uint32_t SR; /* Status Register */
elessair 0:f269e3021894 1417 __IO uint32_t CPSR; /* Clock Prescale Register */
elessair 0:f269e3021894 1418 __IO uint32_t IMSC; /* Interrupt Mask Set and Clear Register */
elessair 0:f269e3021894 1419 __I uint32_t RIS; /* Raw Interrupt Status Register */
elessair 0:f269e3021894 1420 __I uint32_t MIS; /* Masked Interrupt Status Register */
elessair 0:f269e3021894 1421 __O uint32_t ICR; /* SSPICR Interrupt Clear Register */
elessair 0:f269e3021894 1422 __IO uint32_t DMACR; /* SSPn DMA control register */
elessair 0:f269e3021894 1423 } LPC_SSP_T;
elessair 0:f269e3021894 1424
elessair 0:f269e3021894 1425 /* ---------------------------------------------------------------------------
elessair 0:f269e3021894 1426 * 32-bit Standard timer register block structure
elessair 0:f269e3021894 1427 */
elessair 0:f269e3021894 1428 #define LPC_TIMER0_BASE 0x40084000
elessair 0:f269e3021894 1429 #define LPC_TIMER1_BASE 0x40085000
elessair 0:f269e3021894 1430 #define LPC_TIMER2_BASE 0x400C3000
elessair 0:f269e3021894 1431 #define LPC_TIMER3_BASE 0x400C4000
elessair 0:f269e3021894 1432
elessair 0:f269e3021894 1433 typedef struct { /* TIMERn Structure */
elessair 0:f269e3021894 1434 __IO uint32_t IR; /* Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
elessair 0:f269e3021894 1435 __IO uint32_t TCR; /* Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
elessair 0:f269e3021894 1436 __IO uint32_t TC; /* Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
elessair 0:f269e3021894 1437 __IO uint32_t PR; /* Prescale Register. The Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
elessair 0:f269e3021894 1438 __IO uint32_t PC; /* Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
elessair 0:f269e3021894 1439 __IO uint32_t MCR; /* Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
elessair 0:f269e3021894 1440 __IO uint32_t MR[4]; /* Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
elessair 0:f269e3021894 1441 __IO uint32_t CCR; /* Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
elessair 0:f269e3021894 1442 __IO uint32_t CR[4]; /* Capture Register. CR is loaded with the value of TC when there is an event on the CAPn.0 input. */
elessair 0:f269e3021894 1443 __IO uint32_t EMR; /* External Match Register. The EMR controls the external match pins MATn.0-3 (MAT0.0-3 and MAT1.0-3 respectively). */
elessair 0:f269e3021894 1444 __I uint32_t RESERVED0[12];
elessair 0:f269e3021894 1445 __IO uint32_t CTCR; /* Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
elessair 0:f269e3021894 1446 } LPC_TIMER_T;
elessair 0:f269e3021894 1447
elessair 0:f269e3021894 1448 /* ---------------------------------------------------------------------------
elessair 0:f269e3021894 1449 * System Control Unit register block
elessair 0:f269e3021894 1450 */
elessair 0:f269e3021894 1451 #define LPC_SCU_BASE 0x40086000
elessair 0:f269e3021894 1452
elessair 0:f269e3021894 1453 typedef struct {
elessair 0:f269e3021894 1454 __IO uint32_t SFSP[16][32];
elessair 0:f269e3021894 1455 __I uint32_t RESERVED0[256];
elessair 0:f269e3021894 1456 __IO uint32_t SFSCLK[4]; /* Pin configuration register for pins CLK0-3 */
elessair 0:f269e3021894 1457 __I uint32_t RESERVED16[28];
elessair 0:f269e3021894 1458 __IO uint32_t SFSUSB; /* Pin configuration register for USB */
elessair 0:f269e3021894 1459 __IO uint32_t SFSI2C0; /* Pin configuration register for I2C0-bus pins */
elessair 0:f269e3021894 1460 __IO uint32_t ENAIO[3]; /* Analog function select registers */
elessair 0:f269e3021894 1461 __I uint32_t RESERVED17[27];
elessair 0:f269e3021894 1462 __IO uint32_t EMCDELAYCLK; /* EMC clock delay register */
elessair 0:f269e3021894 1463 __I uint32_t RESERVED18[63];
elessair 0:f269e3021894 1464 __IO uint32_t PINTSEL0; /* Pin interrupt select register for pin interrupts 0 to 3. */
elessair 0:f269e3021894 1465 __IO uint32_t PINTSEL1; /* Pin interrupt select register for pin interrupts 4 to 7. */
elessair 0:f269e3021894 1466 } LPC_SCU_T;
elessair 0:f269e3021894 1467
elessair 0:f269e3021894 1468 /*
elessair 0:f269e3021894 1469 * SCU function and mode selection definitions
elessair 0:f269e3021894 1470 * See the User Manual for specific modes and functions supoprted by the
elessair 0:f269e3021894 1471 * various LPC18xx/43xx devices. Functionality can vary per device.
elessair 0:f269e3021894 1472 */
elessair 0:f269e3021894 1473 #define SCU_MODE_PULLUP (0x0 << 3) /* Enable pull-up resistor at pad */
elessair 0:f269e3021894 1474 #define SCU_MODE_REPEATER (0x1 << 3) /* Enable pull-down and pull-up resistor at resistor at pad (repeater mode) */
elessair 0:f269e3021894 1475 #define SCU_MODE_INACT (0x2 << 3) /* Disable pull-down and pull-up resistor at resistor at pad */
elessair 0:f269e3021894 1476 #define SCU_MODE_PULLDOWN (0x3 << 3) /* Enable pull-down resistor at pad */
elessair 0:f269e3021894 1477 #define SCU_MODE_HIGHSPEEDSLEW_EN (0x1 << 5) /* Enable high-speed slew */
elessair 0:f269e3021894 1478 #define SCU_MODE_INBUFF_EN (0x1 << 6) /* Enable Input buffer */
elessair 0:f269e3021894 1479 #define SCU_MODE_ZIF_DIS (0x1 << 7) /* Disable input glitch filter */
elessair 0:f269e3021894 1480 #define SCU_MODE_4MA_DRIVESTR (0x0 << 8) /* Normal drive: 4mA drive strength */
elessair 0:f269e3021894 1481 #define SCU_MODE_8MA_DRIVESTR (0x1 << 8) /* Medium drive: 8mA drive strength */
elessair 0:f269e3021894 1482 #define SCU_MODE_14MA_DRIVESTR (0x2 << 8) /* High drive: 14mA drive strength */
elessair 0:f269e3021894 1483 #define SCU_MODE_20MA_DRIVESTR (0x3 << 8) /* Ultra high- drive: 20mA drive strength */
elessair 0:f269e3021894 1484
elessair 0:f269e3021894 1485 #define SCU_MODE_FUNC0 0x0 /* Selects pin function 0 */
elessair 0:f269e3021894 1486 #define SCU_MODE_FUNC1 0x1 /* Selects pin function 1 */
elessair 0:f269e3021894 1487 #define SCU_MODE_FUNC2 0x2 /* Selects pin function 2 */
elessair 0:f269e3021894 1488 #define SCU_MODE_FUNC3 0x3 /* Selects pin function 3 */
elessair 0:f269e3021894 1489 #define SCU_MODE_FUNC4 0x4 /* Selects pin function 4 */
elessair 0:f269e3021894 1490 #define SCU_MODE_FUNC5 0x5 /* Selects pin function 5 */
elessair 0:f269e3021894 1491 #define SCU_MODE_FUNC6 0x6 /* Selects pin function 6 */
elessair 0:f269e3021894 1492 #define SCU_MODE_FUNC7 0x7 /* Selects pin function 7 */
elessair 0:f269e3021894 1493
elessair 0:f269e3021894 1494 /* Common SCU configurations */
elessair 0:f269e3021894 1495 #define SCU_PINIO_FAST (SCU_MODE_INACT | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS)
elessair 0:f269e3021894 1496 #define SCU_PINIO_PULLUP (SCU_MODE_INBUFF_EN)
elessair 0:f269e3021894 1497 #define SCU_PINIO_PULLDOWN (SCU_MODE_PULLDOWN | SCU_MODE_INACT | SCU_MODE_INBUFF_EN)
elessair 0:f269e3021894 1498 #define SCU_PINIO_PULLNONE (SCU_MODE_INACT | SCU_MODE_INBUFF_EN)
elessair 0:f269e3021894 1499
elessair 0:f269e3021894 1500 /* Calculate SCU offset and register address from group and pin number */
elessair 0:f269e3021894 1501 #define SCU_OFF(group, num) ((group << 7) + (num << 2))
elessair 0:f269e3021894 1502 #define SCU_REG(group, num) ((__IO uint32_t *)(LPC_SCU_BASE + SCU_OFF(group, num)))
elessair 0:f269e3021894 1503
elessair 0:f269e3021894 1504 /**
elessair 0:f269e3021894 1505 * SCU function and mode selection definitions (old)
elessair 0:f269e3021894 1506 * For backwards compatibility.
elessair 0:f269e3021894 1507 */
elessair 0:f269e3021894 1508 #define MD_PUP (0x0 << 3) /* Enable pull-up resistor at pad */
elessair 0:f269e3021894 1509 #define MD_BUK (0x1 << 3) /* Enable pull-down and pull-up resistor at resistor at pad (repeater mode) */
elessair 0:f269e3021894 1510 #define MD_PLN (0x2 << 3) /* Disable pull-down and pull-up resistor at resistor at pad */
elessair 0:f269e3021894 1511 #define MD_PDN (0x3 << 3) /* Enable pull-down resistor at pad */
elessair 0:f269e3021894 1512 #define MD_EHS (0x1 << 5) /* Enable fast slew rate */
elessair 0:f269e3021894 1513 #define MD_EZI (0x1 << 6) /* Input buffer enable */
elessair 0:f269e3021894 1514 #define MD_ZI (0x1 << 7) /* Disable input glitch filter */
elessair 0:f269e3021894 1515 #define MD_EHD0 (0x1 << 8) /* EHD driver strength low bit */
elessair 0:f269e3021894 1516 #define MD_EHD1 (0x1 << 8) /* EHD driver strength high bit */
elessair 0:f269e3021894 1517 #define MD_PLN_FAST (MD_PLN | MD_EZI | MD_ZI | MD_EHS)
elessair 0:f269e3021894 1518 #define I2C0_STANDARD_FAST_MODE (1 << 3 | 1 << 11) /* Pin configuration for STANDARD/FAST mode I2C */
elessair 0:f269e3021894 1519 #define I2C0_FAST_MODE_PLUS (2 << 1 | 1 << 3 | 1 << 7 | 1 << 10 | 1 << 11) /* Pin configuration for Fast-mode Plus I2C */
elessair 0:f269e3021894 1520
elessair 0:f269e3021894 1521 #define FUNC0 0x0 /* Pin function 0 */
elessair 0:f269e3021894 1522 #define FUNC1 0x1 /* Pin function 1 */
elessair 0:f269e3021894 1523 #define FUNC2 0x2 /* Pin function 2 */
elessair 0:f269e3021894 1524 #define FUNC3 0x3 /* Pin function 3 */
elessair 0:f269e3021894 1525 #define FUNC4 0x4 /* Pin function 4 */
elessair 0:f269e3021894 1526 #define FUNC5 0x5 /* Pin function 5 */
elessair 0:f269e3021894 1527 #define FUNC6 0x6 /* Pin function 6 */
elessair 0:f269e3021894 1528 #define FUNC7 0x7 /* Pin function 7 */
elessair 0:f269e3021894 1529
elessair 0:f269e3021894 1530 #define PORT_OFFSET 0x80 /* Port offset definition */
elessair 0:f269e3021894 1531 #define PIN_OFFSET 0x04 /* Pin offset definition */
elessair 0:f269e3021894 1532
elessair 0:f269e3021894 1533 /* Returns the SFSP register address in the SCU for a pin and port,
elessair 0:f269e3021894 1534 recommend using (*(volatile int *) &LPC_SCU->SFSP[po][pi];) */
elessair 0:f269e3021894 1535 #define LPC_SCU_PIN(LPC_SCU_BASE, po, pi) \
elessair 0:f269e3021894 1536 (*(volatile int *) ((LPC_SCU_BASE) + ((po) * 0x80) + ((pi) * 0x4))
elessair 0:f269e3021894 1537
elessair 0:f269e3021894 1538 /* Returns the address in the SCU for a SFSCLK clock register,
elessair 0:f269e3021894 1539 recommend using (*(volatile int *) &LPC_SCU->SFSCLK[c];) */
elessair 0:f269e3021894 1540 #define LPC_SCU_CLK(LPC_SCU_BASE, c) \
elessair 0:f269e3021894 1541 (*(volatile int *) ((LPC_SCU_BASE) +0xC00 + ((c) * 0x4)))
elessair 0:f269e3021894 1542
elessair 0:f269e3021894 1543 /* ---------------------------------------------------------------------------
elessair 0:f269e3021894 1544 * GPIO pin interrupt register block structure
elessair 0:f269e3021894 1545 */
elessair 0:f269e3021894 1546 #define LPC_GPIO_PIN_INT_BASE 0x40087000
elessair 0:f269e3021894 1547
elessair 0:f269e3021894 1548 typedef struct { /* GPIO_PIN_INT Structure */
elessair 0:f269e3021894 1549 __IO uint32_t ISEL; /* Pin Interrupt Mode register */
elessair 0:f269e3021894 1550 __IO uint32_t IENR; /* Pin Interrupt Enable (Rising) register */
elessair 0:f269e3021894 1551 __O uint32_t SIENR; /* Set Pin Interrupt Enable (Rising) register */
elessair 0:f269e3021894 1552 __O uint32_t CIENR; /* Clear Pin Interrupt Enable (Rising) register */
elessair 0:f269e3021894 1553 __IO uint32_t IENF; /* Pin Interrupt Enable Falling Edge / Active Level register */
elessair 0:f269e3021894 1554 __O uint32_t SIENF; /* Set Pin Interrupt Enable Falling Edge / Active Level register */
elessair 0:f269e3021894 1555 __O uint32_t CIENF; /* Clear Pin Interrupt Enable Falling Edge / Active Level address */
elessair 0:f269e3021894 1556 __IO uint32_t RISE; /* Pin Interrupt Rising Edge register */
elessair 0:f269e3021894 1557 __IO uint32_t FALL; /* Pin Interrupt Falling Edge register */
elessair 0:f269e3021894 1558 __IO uint32_t IST; /* Pin Interrupt Status register */
elessair 0:f269e3021894 1559 } LPC_GPIOPININT_T;
elessair 0:f269e3021894 1560
elessair 0:f269e3021894 1561 typedef enum LPC_GPIOPININT_MODE {
elessair 0:f269e3021894 1562 GPIOPININT_RISING_EDGE = 0x01,
elessair 0:f269e3021894 1563 GPIOPININT_FALLING_EDGE = 0x02,
elessair 0:f269e3021894 1564 GPIOPININT_ACTIVE_HIGH_LEVEL = 0x04,
elessair 0:f269e3021894 1565 GPIOPININT_ACTIVE_LOW_LEVEL = 0x08
elessair 0:f269e3021894 1566 } LPC_GPIOPININT_MODE_T;
elessair 0:f269e3021894 1567
elessair 0:f269e3021894 1568 /* ---------------------------------------------------------------------------
elessair 0:f269e3021894 1569 * GPIO grouped interrupt register block structure
elessair 0:f269e3021894 1570 */
elessair 0:f269e3021894 1571 #define LPC_GPIO_GROUP_INT0_BASE 0x40088000
elessair 0:f269e3021894 1572 #define LPC_GPIO_GROUP_INT1_BASE 0x40089000
elessair 0:f269e3021894 1573
elessair 0:f269e3021894 1574 typedef struct { /* GPIO_GROUP_INTn Structure */
elessair 0:f269e3021894 1575 __IO uint32_t CTRL; /* GPIO grouped interrupt control register */
elessair 0:f269e3021894 1576 __I uint32_t RESERVED0[7];
elessair 0:f269e3021894 1577 __IO uint32_t PORT_POL[8]; /* GPIO grouped interrupt port polarity register */
elessair 0:f269e3021894 1578 __IO uint32_t PORT_ENA[8]; /* GPIO grouped interrupt port m enable register */
elessair 0:f269e3021894 1579 } LPC_GPIOGROUPINT_T;
elessair 0:f269e3021894 1580
elessair 0:f269e3021894 1581 /* ---------------------------------------------------------------------------
elessair 0:f269e3021894 1582 * Motor Control PWM register block structure
elessair 0:f269e3021894 1583 */
elessair 0:f269e3021894 1584 #define LPC_MCPWM_BASE 0x400A0000
elessair 0:f269e3021894 1585
elessair 0:f269e3021894 1586 typedef struct { /* MCPWM Structure */
elessair 0:f269e3021894 1587 __I uint32_t CON; /* PWM Control read address */
elessair 0:f269e3021894 1588 __O uint32_t CON_SET; /* PWM Control set address */
elessair 0:f269e3021894 1589 __O uint32_t CON_CLR; /* PWM Control clear address */
elessair 0:f269e3021894 1590 __I uint32_t CAPCON; /* Capture Control read address */
elessair 0:f269e3021894 1591 __O uint32_t CAPCON_SET; /* Capture Control set address */
elessair 0:f269e3021894 1592 __O uint32_t CAPCON_CLR; /* Event Control clear address */
elessair 0:f269e3021894 1593 __IO uint32_t TC[3]; /* Timer Counter register */
elessair 0:f269e3021894 1594 __IO uint32_t LIM[3]; /* Limit register */
elessair 0:f269e3021894 1595 __IO uint32_t MAT[3]; /* Match register */
elessair 0:f269e3021894 1596 __IO uint32_t DT; /* Dead time register */
elessair 0:f269e3021894 1597 __IO uint32_t CCP; /* Communication Pattern register */
elessair 0:f269e3021894 1598 __I uint32_t CAP[3]; /* Capture register */
elessair 0:f269e3021894 1599 __I uint32_t INTEN; /* Interrupt Enable read address */
elessair 0:f269e3021894 1600 __O uint32_t INTEN_SET; /* Interrupt Enable set address */
elessair 0:f269e3021894 1601 __O uint32_t INTEN_CLR; /* Interrupt Enable clear address */
elessair 0:f269e3021894 1602 __I uint32_t CNTCON; /* Count Control read address */
elessair 0:f269e3021894 1603 __O uint32_t CNTCON_SET; /* Count Control set address */
elessair 0:f269e3021894 1604 __O uint32_t CNTCON_CLR; /* Count Control clear address */
elessair 0:f269e3021894 1605 __I uint32_t INTF; /* Interrupt flags read address */
elessair 0:f269e3021894 1606 __O uint32_t INTF_SET; /* Interrupt flags set address */
elessair 0:f269e3021894 1607 __O uint32_t INTF_CLR; /* Interrupt flags clear address */
elessair 0:f269e3021894 1608 __O uint32_t CAP_CLR; /* Capture clear address */
elessair 0:f269e3021894 1609 } LPC_MCPWM_T;
elessair 0:f269e3021894 1610
elessair 0:f269e3021894 1611 /* ---------------------------------------------------------------------------
elessair 0:f269e3021894 1612 * I2C register block structure
elessair 0:f269e3021894 1613 */
elessair 0:f269e3021894 1614 #define LPC_I2C0_BASE 0x400A1000
elessair 0:f269e3021894 1615 #define LPC_I2C1_BASE 0x400E0000
elessair 0:f269e3021894 1616
elessair 0:f269e3021894 1617 typedef struct { /* I2C0 Structure */
elessair 0:f269e3021894 1618 __IO uint32_t CONSET; /* I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register. */
elessair 0:f269e3021894 1619 __I uint32_t STAT; /* I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed. */
elessair 0:f269e3021894 1620 __IO uint32_t DAT; /* I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register. */
elessair 0:f269e3021894 1621 __IO uint32_t ADR0; /* I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
elessair 0:f269e3021894 1622 __IO uint32_t SCLH; /* SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock. */
elessair 0:f269e3021894 1623 __IO uint32_t SCLL; /* SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode. */
elessair 0:f269e3021894 1624 __O uint32_t CONCLR; /* I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register. */
elessair 0:f269e3021894 1625 __IO uint32_t MMCTRL; /* Monitor mode control register. */
elessair 0:f269e3021894 1626 __IO uint32_t ADR1; /* I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
elessair 0:f269e3021894 1627 __IO uint32_t ADR2; /* I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
elessair 0:f269e3021894 1628 __IO uint32_t ADR3; /* I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
elessair 0:f269e3021894 1629 __I uint32_t DATA_BUFFER; /* Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus. */
elessair 0:f269e3021894 1630 __IO uint32_t MASK[4]; /* I2C Slave address mask register */
elessair 0:f269e3021894 1631 } LPC_I2C_T;
elessair 0:f269e3021894 1632
elessair 0:f269e3021894 1633 /* ---------------------------------------------------------------------------
elessair 0:f269e3021894 1634 * I2S register block structure
elessair 0:f269e3021894 1635 */
elessair 0:f269e3021894 1636 #define LPC_I2S0_BASE 0x400A2000
elessair 0:f269e3021894 1637 #define LPC_I2S1_BASE 0x400A3000
elessair 0:f269e3021894 1638
elessair 0:f269e3021894 1639 typedef struct { /* I2S Structure */
elessair 0:f269e3021894 1640 __IO uint32_t DAO; /* I2S Digital Audio Output Register. Contains control bits for the I2S transmit channel */
elessair 0:f269e3021894 1641 __IO uint32_t DAI; /* I2S Digital Audio Input Register. Contains control bits for the I2S receive channel */
elessair 0:f269e3021894 1642 __O uint32_t TXFIFO; /* I2S Transmit FIFO. Access register for the 8 x 32-bit transmitter FIFO */
elessair 0:f269e3021894 1643 __I uint32_t RXFIFO; /* I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO */
elessair 0:f269e3021894 1644 __I uint32_t STATE; /* I2S Status Feedback Register. Contains status information about the I2S interface */
elessair 0:f269e3021894 1645 __IO uint32_t DMA1; /* I2S DMA Configuration Register 1. Contains control information for DMA request 1 */
elessair 0:f269e3021894 1646 __IO uint32_t DMA2; /* I2S DMA Configuration Register 2. Contains control information for DMA request 2 */
elessair 0:f269e3021894 1647 __IO uint32_t IRQ; /* I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated */
elessair 0:f269e3021894 1648 __IO uint32_t TXRATE; /* I2S Transmit MCLK divider. This register determines the I2S TX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK */
elessair 0:f269e3021894 1649 __IO uint32_t RXRATE; /* I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK */
elessair 0:f269e3021894 1650 __IO uint32_t TXBITRATE; /* I2S Transmit bit rate divider. This register determines the I2S transmit bit rate by specifying the value to divide TX_MCLK by in order to produce the transmit bit clock */
elessair 0:f269e3021894 1651 __IO uint32_t RXBITRATE; /* I2S Receive bit rate divider. This register determines the I2S receive bit rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock */
elessair 0:f269e3021894 1652 __IO uint32_t TXMODE; /* I2S Transmit mode control */
elessair 0:f269e3021894 1653 __IO uint32_t RXMODE; /* I2S Receive mode control */
elessair 0:f269e3021894 1654 } LPC_I2S_T;
elessair 0:f269e3021894 1655
elessair 0:f269e3021894 1656 /* ---------------------------------------------------------------------------
elessair 0:f269e3021894 1657 * CCAN Controller Area Network register block structure
elessair 0:f269e3021894 1658 */
elessair 0:f269e3021894 1659 #define LPC_C_CAN1_BASE 0x400A4000
elessair 0:f269e3021894 1660 #define LPC_C_CAN0_BASE 0x400E2000
elessair 0:f269e3021894 1661
elessair 0:f269e3021894 1662 typedef struct { /* C_CAN message interface Structure */
elessair 0:f269e3021894 1663 __IO uint32_t IF_CMDREQ; /* Message interface command request */
elessair 0:f269e3021894 1664 union {
elessair 0:f269e3021894 1665 __IO uint32_t IF_CMDMSK_R; /* Message interface command mask (read direction) */
elessair 0:f269e3021894 1666 __IO uint32_t IF_CMDMSK_W; /* Message interface command mask (write direction) */
elessair 0:f269e3021894 1667 };
elessair 0:f269e3021894 1668
elessair 0:f269e3021894 1669 __IO uint32_t IF_MSK1; /* Message interface mask 1 */
elessair 0:f269e3021894 1670 __IO uint32_t IF_MSK2; /* Message interface mask 2 */
elessair 0:f269e3021894 1671 __IO uint32_t IF_ARB1; /* Message interface arbitration 1 */
elessair 0:f269e3021894 1672 __IO uint32_t IF_ARB2; /* Message interface arbitration 2 */
elessair 0:f269e3021894 1673 __IO uint32_t IF_MCTRL; /* Message interface message control */
elessair 0:f269e3021894 1674 __IO uint32_t IF_DA1; /* Message interface data A1 */
elessair 0:f269e3021894 1675 __IO uint32_t IF_DA2; /* Message interface data A2 */
elessair 0:f269e3021894 1676 __IO uint32_t IF_DB1; /* Message interface data B1 */
elessair 0:f269e3021894 1677 __IO uint32_t IF_DB2; /* Message interface data B2 */
elessair 0:f269e3021894 1678 __I uint32_t RESERVED[13];
elessair 0:f269e3021894 1679 } LPC_CCAN_IF_T;
elessair 0:f269e3021894 1680
elessair 0:f269e3021894 1681 typedef struct { /* C_CAN Structure */
elessair 0:f269e3021894 1682 __IO uint32_t CNTL; /* CAN control */
elessair 0:f269e3021894 1683 __IO uint32_t STAT; /* Status register */
elessair 0:f269e3021894 1684 __I uint32_t EC; /* Error counter */
elessair 0:f269e3021894 1685 __IO uint32_t BT; /* Bit timing register */
elessair 0:f269e3021894 1686 __I uint32_t INT; /* Interrupt register */
elessair 0:f269e3021894 1687 __IO uint32_t TEST; /* Test register */
elessair 0:f269e3021894 1688 __IO uint32_t BRPE; /* Baud rate prescaler extension register */
elessair 0:f269e3021894 1689 __I uint32_t RESERVED0;
elessair 0:f269e3021894 1690 LPC_CCAN_IF_T IF[2];
elessair 0:f269e3021894 1691 __I uint32_t RESERVED2[8];
elessair 0:f269e3021894 1692 __I uint32_t TXREQ1; /* Transmission request 1 */
elessair 0:f269e3021894 1693 __I uint32_t TXREQ2; /* Transmission request 2 */
elessair 0:f269e3021894 1694 __I uint32_t RESERVED3[6];
elessair 0:f269e3021894 1695 __I uint32_t ND1; /* New data 1 */
elessair 0:f269e3021894 1696 __I uint32_t ND2; /* New data 2 */
elessair 0:f269e3021894 1697 __I uint32_t RESERVED4[6];
elessair 0:f269e3021894 1698 __I uint32_t IR1; /* Interrupt pending 1 */
elessair 0:f269e3021894 1699 __I uint32_t IR2; /* Interrupt pending 2 */
elessair 0:f269e3021894 1700 __I uint32_t RESERVED5[6];
elessair 0:f269e3021894 1701 __I uint32_t MSGV1; /* Message valid 1 */
elessair 0:f269e3021894 1702 __I uint32_t MSGV2; /* Message valid 2 */
elessair 0:f269e3021894 1703 __I uint32_t RESERVED6[6];
elessair 0:f269e3021894 1704 __IO uint32_t CLKDIV; /* CAN clock divider register */
elessair 0:f269e3021894 1705 } LPC_CCAN_T;
elessair 0:f269e3021894 1706
elessair 0:f269e3021894 1707 /* ---------------------------------------------------------------------------
elessair 0:f269e3021894 1708 * Repetitive Interrupt Timer register block structure
elessair 0:f269e3021894 1709 */
elessair 0:f269e3021894 1710 #define LPC_RITIMER_BASE 0x400C0000
elessair 0:f269e3021894 1711
elessair 0:f269e3021894 1712 typedef struct { /* RITIMER Structure */
elessair 0:f269e3021894 1713 __IO uint32_t COMPVAL; /* Compare register */
elessair 0:f269e3021894 1714 __IO uint32_t MASK; /* Mask register. This register holds the 32-bit mask value. A 1 written to any bit will force a compare on the corresponding bit of the counter and compare register. */
elessair 0:f269e3021894 1715 __IO uint32_t CTRL; /* Control register. */
elessair 0:f269e3021894 1716 __IO uint32_t COUNTER; /* 32-bit counter */
elessair 0:f269e3021894 1717 } LPC_RITIMER_T;
elessair 0:f269e3021894 1718
elessair 0:f269e3021894 1719 /* ---------------------------------------------------------------------------
elessair 0:f269e3021894 1720 * Quadrature Encoder Interface register block structure
elessair 0:f269e3021894 1721 */
elessair 0:f269e3021894 1722 #define LPC_QEI_BASE 0x400C6000
elessair 0:f269e3021894 1723
elessair 0:f269e3021894 1724 typedef struct { /* QEI Structure */
elessair 0:f269e3021894 1725 __O uint32_t CON; /* Control register */
elessair 0:f269e3021894 1726 __I uint32_t STAT; /* Encoder status register */
elessair 0:f269e3021894 1727 __IO uint32_t CONF; /* Configuration register */
elessair 0:f269e3021894 1728 __I uint32_t POS; /* Position register */
elessair 0:f269e3021894 1729 __IO uint32_t MAXPOS; /* Maximum position register */
elessair 0:f269e3021894 1730 __IO uint32_t CMPOS0; /* position compare register 0 */
elessair 0:f269e3021894 1731 __IO uint32_t CMPOS1; /* position compare register 1 */
elessair 0:f269e3021894 1732 __IO uint32_t CMPOS2; /* position compare register 2 */
elessair 0:f269e3021894 1733 __I uint32_t INXCNT; /* Index count register */
elessair 0:f269e3021894 1734 __IO uint32_t INXCMP0; /* Index compare register 0 */
elessair 0:f269e3021894 1735 __IO uint32_t LOAD; /* Velocity timer reload register */
elessair 0:f269e3021894 1736 __I uint32_t TIME; /* Velocity timer register */
elessair 0:f269e3021894 1737 __I uint32_t VEL; /* Velocity counter register */
elessair 0:f269e3021894 1738 __I uint32_t CAP; /* Velocity capture register */
elessair 0:f269e3021894 1739 __IO uint32_t VELCOMP; /* Velocity compare register */
elessair 0:f269e3021894 1740 __IO uint32_t FILTERPHA; /* Digital filter register on input phase A (QEI_A) */
elessair 0:f269e3021894 1741 __IO uint32_t FILTERPHB; /* Digital filter register on input phase B (QEI_B) */
elessair 0:f269e3021894 1742 __IO uint32_t FILTERINX; /* Digital filter register on input index (QEI_IDX) */
elessair 0:f269e3021894 1743 __IO uint32_t WINDOW; /* Index acceptance window register */
elessair 0:f269e3021894 1744 __IO uint32_t INXCMP1; /* Index compare register 1 */
elessair 0:f269e3021894 1745 __IO uint32_t INXCMP2; /* Index compare register 2 */
elessair 0:f269e3021894 1746 __I uint32_t RESERVED0[993];
elessair 0:f269e3021894 1747 __O uint32_t IEC; /* Interrupt enable clear register */
elessair 0:f269e3021894 1748 __O uint32_t IES; /* Interrupt enable set register */
elessair 0:f269e3021894 1749 __I uint32_t INTSTAT; /* Interrupt status register */
elessair 0:f269e3021894 1750 __I uint32_t IE; /* Interrupt enable register */
elessair 0:f269e3021894 1751 __O uint32_t CLR; /* Interrupt status clear register */
elessair 0:f269e3021894 1752 __O uint32_t SET; /* Interrupt status set register */
elessair 0:f269e3021894 1753 } LPC_QEI_T;
elessair 0:f269e3021894 1754
elessair 0:f269e3021894 1755 /* ---------------------------------------------------------------------------
elessair 0:f269e3021894 1756 * Global Input Multiplexer Array (GIMA) register block structure
elessair 0:f269e3021894 1757 */
elessair 0:f269e3021894 1758 #define LPC_GIMA_BASE 0x400C7000
elessair 0:f269e3021894 1759
elessair 0:f269e3021894 1760 typedef struct { /* GIMA Structure */
elessair 0:f269e3021894 1761 __IO uint32_t CAP0_IN[4][4]; /* Timer x CAP0_y capture input multiplexer (GIMA output ((x*4)+y)) */
elessair 0:f269e3021894 1762 __IO uint32_t CTIN_IN[8]; /* SCT CTIN_x capture input multiplexer (GIMA output (16+x)) */
elessair 0:f269e3021894 1763 __IO uint32_t VADC_TRIGGER_IN; /* VADC trigger input multiplexer (GIMA output 24) */
elessair 0:f269e3021894 1764 __IO uint32_t EVENTROUTER_13_IN; /* Event router input 13 multiplexer (GIMA output 25) */
elessair 0:f269e3021894 1765 __IO uint32_t EVENTROUTER_14_IN; /* Event router input 14 multiplexer (GIMA output 26) */
elessair 0:f269e3021894 1766 __IO uint32_t EVENTROUTER_16_IN; /* Event router input 16 multiplexer (GIMA output 27) */
elessair 0:f269e3021894 1767 __IO uint32_t ADCSTART0_IN; /* ADC start0 input multiplexer (GIMA output 28) */
elessair 0:f269e3021894 1768 __IO uint32_t ADCSTART1_IN; /* ADC start1 input multiplexer (GIMA output 29) */
elessair 0:f269e3021894 1769 } LPC_GIMA_T;
elessair 0:f269e3021894 1770
elessair 0:f269e3021894 1771 /* ---------------------------------------------------------------------------
elessair 0:f269e3021894 1772 * DAC register block structure
elessair 0:f269e3021894 1773 */
elessair 0:f269e3021894 1774 #define LPC_DAC_BASE 0x400E1000
elessair 0:f269e3021894 1775
elessair 0:f269e3021894 1776 typedef struct { /* DAC Structure */
elessair 0:f269e3021894 1777 __IO uint32_t CR; /* DAC register. Holds the conversion data. */
elessair 0:f269e3021894 1778 __IO uint32_t CTRL; /* DAC control register. */
elessair 0:f269e3021894 1779 __IO uint32_t CNTVAL; /* DAC counter value register. */
elessair 0:f269e3021894 1780 } LPC_DAC_T;
elessair 0:f269e3021894 1781
elessair 0:f269e3021894 1782 /* After the selected settling time after this field is written with a
elessair 0:f269e3021894 1783 * new VALUE, the voltage on the AOUT pin (with respect to VSSA)
elessair 0:f269e3021894 1784 * is VALUE/1024 ? VREF
elessair 0:f269e3021894 1785 */
elessair 0:f269e3021894 1786 #define DAC_RANGE 0x3FF
elessair 0:f269e3021894 1787 #define DAC_SET(n) ((uint32_t) ((n & DAC_RANGE) << 6))
elessair 0:f269e3021894 1788 #define DAC_GET(n) ((uint32_t) ((n >> 6) & DAC_RANGE))
elessair 0:f269e3021894 1789 #define DAC_VALUE(n) DAC_SET(n)
elessair 0:f269e3021894 1790 /* If this bit = 0: The settling time of the DAC is 1 microsecond max,
elessair 0:f269e3021894 1791 * and the maximum current is 700 microAmpere
elessair 0:f269e3021894 1792 * If this bit = 1: The settling time of the DAC is 2.5 microsecond
elessair 0:f269e3021894 1793 * and the maximum current is 350 microAmpere
elessair 0:f269e3021894 1794 */
elessair 0:f269e3021894 1795 #define DAC_BIAS_EN ((uint32_t) (1 << 16))
elessair 0:f269e3021894 1796 /* Value to reload interrupt DMA counter */
elessair 0:f269e3021894 1797 #define DAC_CCNT_VALUE(n) ((uint32_t) (n & 0xffff))
elessair 0:f269e3021894 1798
elessair 0:f269e3021894 1799 #define DAC_DBLBUF_ENA ((uint32_t) (1 << 1))
elessair 0:f269e3021894 1800 #define DAC_CNT_ENA ((uint32_t) (1 << 2))
elessair 0:f269e3021894 1801 #define DAC_DMA_ENA ((uint32_t) (1 << 3))
elessair 0:f269e3021894 1802 #define DAC_DACCTRL_MASK ((uint32_t) (0x0F))
elessair 0:f269e3021894 1803
elessair 0:f269e3021894 1804 /* Current option in DAC configuration option */
elessair 0:f269e3021894 1805 typedef enum DAC_CURRENT_OPT {
elessair 0:f269e3021894 1806 DAC_MAX_UPDATE_RATE_1MHz = 0, /* Shorter settling times and higher power consumption;
elessair 0:f269e3021894 1807 allows for a maximum update rate of 1 MHz */
elessair 0:f269e3021894 1808 DAC_MAX_UPDATE_RATE_400kHz /* Longer settling times and lower power consumption;
elessair 0:f269e3021894 1809 allows for a maximum update rate of 400 kHz */
elessair 0:f269e3021894 1810 } DAC_CURRENT_OPT_T;
elessair 0:f269e3021894 1811
elessair 0:f269e3021894 1812 /* ---------------------------------------------------------------------------
elessair 0:f269e3021894 1813 * ADC register block structure
elessair 0:f269e3021894 1814 */
elessair 0:f269e3021894 1815 #define LPC_ADC0_BASE 0x400E3000
elessair 0:f269e3021894 1816 #define LPC_ADC1_BASE 0x400E4000
elessair 0:f269e3021894 1817 #define ADC_ACC_10BITS
elessair 0:f269e3021894 1818
elessair 0:f269e3021894 1819 /* ---------------------------------------------------------------------------
elessair 0:f269e3021894 1820 * 10 or 12-bit ADC register block structure
elessair 0:f269e3021894 1821 */
elessair 0:f269e3021894 1822 typedef struct { /* ADCn Structure */
elessair 0:f269e3021894 1823 __IO uint32_t CR; /* A/D Control Register. The AD0CR register must be written to select the operating mode before A/D conversion can occur. */
elessair 0:f269e3021894 1824 __I uint32_t GDR; /* A/D Global Data Register. Contains the result of the most recent A/D conversion. */
elessair 0:f269e3021894 1825 __I uint32_t RESERVED0;
elessair 0:f269e3021894 1826 __IO uint32_t INTEN; /* A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt. */
elessair 0:f269e3021894 1827 __I uint32_t DR[8]; /* A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n. */
elessair 0:f269e3021894 1828 __I uint32_t STAT; /* A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag. */
elessair 0:f269e3021894 1829 } LPC_ADC_T;
elessair 0:f269e3021894 1830
elessair 0:f269e3021894 1831 /* ADC register support bitfields and mask */
elessair 0:f269e3021894 1832 #define ADC_RANGE 0x3FF
elessair 0:f269e3021894 1833 #define ADC_DR_RESULT(n) ((((n) >> 6) & 0x3FF)) /* Mask for getting the 10 bits ADC data read value */
elessair 0:f269e3021894 1834 #define ADC_CR_BITACC(n) ((((n) & 0x7) << 17)) /* Number of ADC accuracy bits */
elessair 0:f269e3021894 1835 #define ADC_DR_DONE(n) (((n) >> 31)) /* Mask for reading the ADC done status */
elessair 0:f269e3021894 1836 #define ADC_DR_OVERRUN(n) ((((n) >> 30) & (1UL))) /* Mask for reading the ADC overrun status */
elessair 0:f269e3021894 1837 #define ADC_CR_CH_SEL(n) ((1UL << (n))) /* Selects which of the AD0.0:7 pins is (are) to be sampled and converted */
elessair 0:f269e3021894 1838 #define ADC_CR_CLKDIV(n) ((((n) & 0xFF) << 8)) /* The APB clock (PCLK) is divided by (this value plus one) to produce the clock for the A/D */
elessair 0:f269e3021894 1839 #define ADC_CR_BURST ((1UL << 16)) /* Repeated conversions A/D enable bit */
elessair 0:f269e3021894 1840 #define ADC_CR_PDN ((1UL << 21)) /* ADC convert is operational */
elessair 0:f269e3021894 1841 #define ADC_CR_START_MASK ((7UL << 24)) /* ADC start mask bits */
elessair 0:f269e3021894 1842 #define ADC_CR_START_MODE_SEL(SEL) ((SEL << 24)) /* Select Start Mode */
elessair 0:f269e3021894 1843 #define ADC_CR_START_NOW ((1UL << 24)) /* Start conversion now */
elessair 0:f269e3021894 1844 #define ADC_CR_START_CTOUT15 ((2UL << 24)) /* Start conversion when the edge selected by bit 27 occurs on CTOUT_15 */
elessair 0:f269e3021894 1845 #define ADC_CR_START_CTOUT8 ((3UL << 24)) /* Start conversion when the edge selected by bit 27 occurs on CTOUT_8 */
elessair 0:f269e3021894 1846 #define ADC_CR_START_ADCTRIG0 ((4UL << 24)) /* Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 */
elessair 0:f269e3021894 1847 #define ADC_CR_START_ADCTRIG1 ((5UL << 24)) /* Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 */
elessair 0:f269e3021894 1848 #define ADC_CR_START_MCOA2 ((6UL << 24)) /* Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2 */
elessair 0:f269e3021894 1849 #define ADC_CR_EDGE ((1UL << 27)) /* Start conversion on a falling edge on the selected CAP/MAT signal */
elessair 0:f269e3021894 1850 #define ADC_CONFIG_MASK (ADC_CR_CLKDIV(0xFF) | ADC_CR_BITACC(0x07) | ADC_CR_PDN)
elessair 0:f269e3021894 1851
elessair 0:f269e3021894 1852 /* ADC status register used for IP drivers */
elessair 0:f269e3021894 1853 typedef enum ADC_STATUS {
elessair 0:f269e3021894 1854 ADC_DR_DONE_STAT, /* ADC data register staus */
elessair 0:f269e3021894 1855 ADC_DR_OVERRUN_STAT,/* ADC data overrun staus */
elessair 0:f269e3021894 1856 ADC_DR_ADINT_STAT /* ADC interrupt status */
elessair 0:f269e3021894 1857 } ADC_STATUS_T;
elessair 0:f269e3021894 1858
elessair 0:f269e3021894 1859 /** Start mode, which controls the start of an A/D conversion when the BURST bit is 0. */
elessair 0:f269e3021894 1860 typedef enum ADC_START_MODE {
elessair 0:f269e3021894 1861 ADC_NO_START = 0,
elessair 0:f269e3021894 1862 ADC_START_NOW, /* Start conversion now */
elessair 0:f269e3021894 1863 ADC_START_ON_CTOUT15, /* Start conversion when the edge selected by bit 27 occurs on CTOUT_15 */
elessair 0:f269e3021894 1864 ADC_START_ON_CTOUT8, /* Start conversion when the edge selected by bit 27 occurs on CTOUT_8 */
elessair 0:f269e3021894 1865 ADC_START_ON_ADCTRIG0, /* Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 */
elessair 0:f269e3021894 1866 ADC_START_ON_ADCTRIG1, /* Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 */
elessair 0:f269e3021894 1867 ADC_START_ON_MCOA2 /* Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2 */
elessair 0:f269e3021894 1868 } ADC_START_MODE_T;
elessair 0:f269e3021894 1869
elessair 0:f269e3021894 1870 /* ---------------------------------------------------------------------------
elessair 0:f269e3021894 1871 * GPIO port register block structure
elessair 0:f269e3021894 1872 */
elessair 0:f269e3021894 1873 #define LPC_GPIO_PORT_BASE 0x400F4000
elessair 0:f269e3021894 1874 #define LPC_GPIO0_BASE (LPC_GPIO_PORT_BASE)
elessair 0:f269e3021894 1875 #define LPC_GPIO1_BASE (LPC_GPIO_PORT_BASE + 0x04)
elessair 0:f269e3021894 1876 #define LPC_GPIO2_BASE (LPC_GPIO_PORT_BASE + 0x08)
elessair 0:f269e3021894 1877 #define LPC_GPIO3_BASE (LPC_GPIO_PORT_BASE + 0x0C)
elessair 0:f269e3021894 1878 #define LPC_GPIO4_BASE (LPC_GPIO_PORT_BASE + 0x10)
elessair 0:f269e3021894 1879 #define LPC_GPIO5_BASE (LPC_GPIO_PORT_BASE + 0x14)
elessair 0:f269e3021894 1880 #define LPC_GPIO6_BASE (LPC_GPIO_PORT_BASE + 0x18)
elessair 0:f269e3021894 1881 #define LPC_GPIO7_BASE (LPC_GPIO_PORT_BASE + 0x1C)
elessair 0:f269e3021894 1882
elessair 0:f269e3021894 1883 typedef struct { /* GPIO_PORT Structure */
elessair 0:f269e3021894 1884 __IO uint8_t B[128][32]; /* Offset 0x0000: Byte pin registers ports 0 to n; pins PIOn_0 to PIOn_31 */
elessair 0:f269e3021894 1885 __IO uint32_t W[32][32]; /* Offset 0x1000: Word pin registers port 0 to n */
elessair 0:f269e3021894 1886 __IO uint32_t DIR[32]; /* Offset 0x2000: Direction registers port n */
elessair 0:f269e3021894 1887 __IO uint32_t MASK[32]; /* Offset 0x2080: Mask register port n */
elessair 0:f269e3021894 1888 __IO uint32_t PIN[32]; /* Offset 0x2100: Portpin register port n */
elessair 0:f269e3021894 1889 __IO uint32_t MPIN[32]; /* Offset 0x2180: Masked port register port n */
elessair 0:f269e3021894 1890 __IO uint32_t SET[32]; /* Offset 0x2200: Write: Set register for port n Read: output bits for port n */
elessair 0:f269e3021894 1891 __O uint32_t CLR[32]; /* Offset 0x2280: Clear port n */
elessair 0:f269e3021894 1892 __O uint32_t NOT[32]; /* Offset 0x2300: Toggle port n */
elessair 0:f269e3021894 1893 } LPC_GPIO_T;
elessair 0:f269e3021894 1894
elessair 0:f269e3021894 1895 /* Calculate GPIO offset and port register address from group and pin number */
elessair 0:f269e3021894 1896 #define GPIO_OFF(port, pin) ((port << 5) + pin)
elessair 0:f269e3021894 1897 #define GPIO_REG(port, pin) ((__IO uint32_t *)(LPC_GPIO_PORT_BASE + 0x2000 + GPIO_OFF(port, pin)))
elessair 0:f269e3021894 1898
elessair 0:f269e3021894 1899 /* ---------------------------------------------------------------------------
elessair 0:f269e3021894 1900 * SPI register block structure
elessair 0:f269e3021894 1901 */
elessair 0:f269e3021894 1902 #define LPC_SPI_BASE 0x40100000
elessair 0:f269e3021894 1903
elessair 0:f269e3021894 1904 typedef struct { /* SPI Structure */
elessair 0:f269e3021894 1905 __IO uint32_t CR; /* SPI Control Register. This register controls the operation of the SPI. */
elessair 0:f269e3021894 1906 __I uint32_t SR; /* SPI Status Register. This register shows the status of the SPI. */
elessair 0:f269e3021894 1907 __IO uint32_t DR; /* SPI Data Register. This bi-directional register provides the transmit and receive data for the SPI. */
elessair 0:f269e3021894 1908 __IO uint32_t CCR; /* SPI Clock Counter Register. This register controls the frequency of a master's SCK0. */
elessair 0:f269e3021894 1909 __I uint32_t RESERVED0[3];
elessair 0:f269e3021894 1910 __IO uint32_t INT; /* SPI Interrupt Flag. This register contains the interrupt flag for the SPI interface. */
elessair 0:f269e3021894 1911 } LPC_SPI_T;
elessair 0:f269e3021894 1912
elessair 0:f269e3021894 1913 /* SPI CFG Register BitMask */
elessair 0:f269e3021894 1914 #define SPI_CR_BITMASK ((uint32_t) 0xFFC)
elessair 0:f269e3021894 1915 /* Enable of controlling the number of bits per transfer */
elessair 0:f269e3021894 1916 #define SPI_CR_BIT_EN ((uint32_t) (1 << 2))
elessair 0:f269e3021894 1917 /* Mask of field of bit controlling */
elessair 0:f269e3021894 1918 #define SPI_CR_BITS_MASK ((uint32_t) 0xF00)
elessair 0:f269e3021894 1919 /* Set the number of bits per a transfer */
elessair 0:f269e3021894 1920 #define SPI_CR_BITS(n) ((uint32_t) ((n << 8) & 0xF00)) /* n is in range 8-16 */
elessair 0:f269e3021894 1921 /* SPI Clock Phase Select*/
elessair 0:f269e3021894 1922 #define SPI_CR_CPHA_FIRST ((uint32_t) (0)) /*Capture data on the first edge, Change data on the following edge*/
elessair 0:f269e3021894 1923 #define SPI_CR_CPHA_SECOND ((uint32_t) (1 << 3)) /* Change data on the first edge, Capture data on the following edge*/
elessair 0:f269e3021894 1924 /* SPI Clock Polarity Select*/
elessair 0:f269e3021894 1925 #define SPI_CR_CPOL_LO ((uint32_t) (0)) /* The rest state of the clock (between frames) is low.*/
elessair 0:f269e3021894 1926 #define SPI_CR_CPOL_HI ((uint32_t) (1 << 4)) /* The rest state of the clock (between frames) is high.*/
elessair 0:f269e3021894 1927 /* SPI Slave Mode Select */
elessair 0:f269e3021894 1928 #define SPI_CR_SLAVE_EN ((uint32_t) 0)
elessair 0:f269e3021894 1929 /* SPI Master Mode Select */
elessair 0:f269e3021894 1930 #define SPI_CR_MASTER_EN ((uint32_t) (1 << 5))
elessair 0:f269e3021894 1931 /* SPI MSB First mode enable */
elessair 0:f269e3021894 1932 #define SPI_CR_MSB_FIRST_EN ((uint32_t) 0) /* Data will be transmitted and received in standard order (MSB first).*/
elessair 0:f269e3021894 1933 /* SPI LSB First mode enable */
elessair 0:f269e3021894 1934 #define SPI_CR_LSB_FIRST_EN ((uint32_t) (1 << 6)) /* Data will be transmitted and received in reverse order (LSB first).*/
elessair 0:f269e3021894 1935 /* SPI interrupt enable */
elessair 0:f269e3021894 1936 #define SPI_CR_INT_EN ((uint32_t) (1 << 7))
elessair 0:f269e3021894 1937 /* SPI STAT Register BitMask */
elessair 0:f269e3021894 1938 #define SPI_SR_BITMASK ((uint32_t) 0xF8)
elessair 0:f269e3021894 1939 /* Slave abort Flag */
elessair 0:f269e3021894 1940 #define SPI_SR_ABRT ((uint32_t) (1 << 3)) /* When 1, this bit indicates that a slave abort has occurred. */
elessair 0:f269e3021894 1941 /* Mode fault Flag */
elessair 0:f269e3021894 1942 #define SPI_SR_MODF ((uint32_t) (1 << 4)) /* when 1, this bit indicates that a Mode fault error has occurred. */
elessair 0:f269e3021894 1943 /* Read overrun flag*/
elessair 0:f269e3021894 1944 #define SPI_SR_ROVR ((uint32_t) (1 << 5)) /* When 1, this bit indicates that a read overrun has occurred. */
elessair 0:f269e3021894 1945 /* Write collision flag. */
elessair 0:f269e3021894 1946 #define SPI_SR_WCOL ((uint32_t) (1 << 6)) /* When 1, this bit indicates that a write collision has occurred.. */
elessair 0:f269e3021894 1947 /* SPI transfer complete flag. */
elessair 0:f269e3021894 1948 #define SPI_SR_SPIF ((uint32_t) (1 << 7)) /* When 1, this bit indicates when a SPI data transfer is complete.. */
elessair 0:f269e3021894 1949 /* SPI error flag */
elessair 0:f269e3021894 1950 #define SPI_SR_ERROR (SPI_SR_ABRT | SPI_SR_MODF | SPI_SR_ROVR | SPI_SR_WCOL)
elessair 0:f269e3021894 1951 /* Enable SPI Test Mode */
elessair 0:f269e3021894 1952 #define SPI_TCR_TEST(n) ((uint32_t) ((n & 0x3F) << 1))
elessair 0:f269e3021894 1953 /* SPI interrupt flag */
elessair 0:f269e3021894 1954 #define SPI_INT_SPIF ((uint32_t) (1 << 0))
elessair 0:f269e3021894 1955 /* Receiver Data */
elessair 0:f269e3021894 1956 #define SPI_DR_DATA(n) ((uint32_t) ((n) & 0xFFFF))
elessair 0:f269e3021894 1957
elessair 0:f269e3021894 1958 /* SPI Mode*/
elessair 0:f269e3021894 1959 typedef enum LPC_SPI_MODE {
elessair 0:f269e3021894 1960 SPI_MODE_MASTER = SPI_CR_MASTER_EN, /* Master Mode */
elessair 0:f269e3021894 1961 SPI_MODE_SLAVE = SPI_CR_SLAVE_EN, /* Slave Mode */
elessair 0:f269e3021894 1962 } LPC_SPI_MODE_T;
elessair 0:f269e3021894 1963
elessair 0:f269e3021894 1964 /* SPI Clock Mode*/
elessair 0:f269e3021894 1965 typedef enum LPC_SPI_CLOCK_MODE {
elessair 0:f269e3021894 1966 SPI_CLOCK_CPHA0_CPOL0 = SPI_CR_CPOL_LO | SPI_CR_CPHA_FIRST, /* CPHA = 0, CPOL = 0 */
elessair 0:f269e3021894 1967 SPI_CLOCK_CPHA0_CPOL1 = SPI_CR_CPOL_HI | SPI_CR_CPHA_FIRST, /* CPHA = 0, CPOL = 1 */
elessair 0:f269e3021894 1968 SPI_CLOCK_CPHA1_CPOL0 = SPI_CR_CPOL_LO | SPI_CR_CPHA_SECOND, /* CPHA = 1, CPOL = 0 */
elessair 0:f269e3021894 1969 SPI_CLOCK_CPHA1_CPOL1 = SPI_CR_CPOL_HI | SPI_CR_CPHA_SECOND, /* CPHA = 1, CPOL = 1 */
elessair 0:f269e3021894 1970 SPI_CLOCK_MODE0 = SPI_CLOCK_CPHA0_CPOL0, /* alias */
elessair 0:f269e3021894 1971 SPI_CLOCK_MODE1 = SPI_CLOCK_CPHA1_CPOL0, /* alias */
elessair 0:f269e3021894 1972 SPI_CLOCK_MODE2 = SPI_CLOCK_CPHA0_CPOL1, /* alias */
elessair 0:f269e3021894 1973 SPI_CLOCK_MODE3 = SPI_CLOCK_CPHA1_CPOL1, /* alias */
elessair 0:f269e3021894 1974 } LPC_SPI_CLOCK_MODE_T;
elessair 0:f269e3021894 1975
elessair 0:f269e3021894 1976 /* SPI Data Order Mode*/
elessair 0:f269e3021894 1977 typedef enum LPC_SPI_DATA_ORDER {
elessair 0:f269e3021894 1978 SPI_DATA_MSB_FIRST = SPI_CR_MSB_FIRST_EN, /* Standard Order */
elessair 0:f269e3021894 1979 SPI_DATA_LSB_FIRST = SPI_CR_LSB_FIRST_EN, /* Reverse Order */
elessair 0:f269e3021894 1980 } LPC_SPI_DATA_ORDER_T;
elessair 0:f269e3021894 1981
elessair 0:f269e3021894 1982 /* ---------------------------------------------------------------------------
elessair 0:f269e3021894 1983 * Serial GPIO register block structure
elessair 0:f269e3021894 1984 */
elessair 0:f269e3021894 1985 #define LPC_SGPIO_BASE 0x40101000
elessair 0:f269e3021894 1986
elessair 0:f269e3021894 1987 typedef struct { /* SGPIO Structure */
elessair 0:f269e3021894 1988 __IO uint32_t OUT_MUX_CFG[16]; /* Pin multiplexer configurationregisters. */
elessair 0:f269e3021894 1989 __IO uint32_t SGPIO_MUX_CFG[16]; /* SGPIO multiplexer configuration registers. */
elessair 0:f269e3021894 1990 __IO uint32_t SLICE_MUX_CFG[16]; /* Slice multiplexer configuration registers. */
elessair 0:f269e3021894 1991 __IO uint32_t REG[16]; /* Slice data registers. Eachtime COUNT0 reaches 0x0 the register shifts loading bit 31 withdata captured from DIN(n). DOUT(n) is set to REG(0) */
elessair 0:f269e3021894 1992 __IO uint32_t REG_SS[16]; /* Slice data shadow registers. Each time POSreaches 0x0 the contents of REG_SS is exchanged with the contentof REG */
elessair 0:f269e3021894 1993 __IO uint32_t PRESET[16]; /* Reload valueof COUNT0, loaded when COUNT0 reaches 0x0 */
elessair 0:f269e3021894 1994 __IO uint32_t COUNT[16]; /* Down counter, counts down each clock cycle. */
elessair 0:f269e3021894 1995 __IO uint32_t POS[16]; /* Each time COUNT0 reaches 0x0 */
elessair 0:f269e3021894 1996 __IO uint32_t MASK_A; /* Mask for pattern match function of slice A */
elessair 0:f269e3021894 1997 __IO uint32_t MASK_H; /* Mask for pattern match function of slice H */
elessair 0:f269e3021894 1998 __IO uint32_t MASK_I; /* Mask for pattern match function of slice I */
elessair 0:f269e3021894 1999 __IO uint32_t MASK_P; /* Mask for pattern match function of slice P */
elessair 0:f269e3021894 2000 __I uint32_t GPIO_INREG; /* GPIO input status register */
elessair 0:f269e3021894 2001 __IO uint32_t GPIO_OUTREG; /* GPIO output control register */
elessair 0:f269e3021894 2002 __IO uint32_t GPIO_OENREG; /* GPIO OE control register */
elessair 0:f269e3021894 2003 __IO uint32_t CTRL_ENABLED; /* Enables the slice COUNT counter */
elessair 0:f269e3021894 2004 __IO uint32_t CTRL_DISABLED; /* Disables the slice COUNT counter */
elessair 0:f269e3021894 2005 __I uint32_t RESERVED0[823];
elessair 0:f269e3021894 2006 __O uint32_t CLR_EN_0; /* Shift clock interrupt clear mask */
elessair 0:f269e3021894 2007 __O uint32_t SET_EN_0; /* Shift clock interrupt set mask */
elessair 0:f269e3021894 2008 __I uint32_t ENABLE_0; /* Shift clock interrupt enable */
elessair 0:f269e3021894 2009 __I uint32_t STATUS_0; /* Shift clock interrupt status */
elessair 0:f269e3021894 2010 __O uint32_t CTR_STATUS_0; /* Shift clock interrupt clear status */
elessair 0:f269e3021894 2011 __O uint32_t SET_STATUS_0; /* Shift clock interrupt set status */
elessair 0:f269e3021894 2012 __I uint32_t RESERVED1[2];
elessair 0:f269e3021894 2013 __O uint32_t CLR_EN_1; /* Capture clock interrupt clear mask */
elessair 0:f269e3021894 2014 __O uint32_t SET_EN_1; /* Capture clock interrupt set mask */
elessair 0:f269e3021894 2015 __I uint32_t ENABLE_1; /* Capture clock interrupt enable */
elessair 0:f269e3021894 2016 __I uint32_t STATUS_1; /* Capture clock interrupt status */
elessair 0:f269e3021894 2017 __O uint32_t CTR_STATUS_1; /* Capture clock interrupt clear status */
elessair 0:f269e3021894 2018 __O uint32_t SET_STATUS_1; /* Capture clock interrupt set status */
elessair 0:f269e3021894 2019 __I uint32_t RESERVED2[2];
elessair 0:f269e3021894 2020 __O uint32_t CLR_EN_2; /* Pattern match interrupt clear mask */
elessair 0:f269e3021894 2021 __O uint32_t SET_EN_2; /* Pattern match interrupt set mask */
elessair 0:f269e3021894 2022 __I uint32_t ENABLE_2; /* Pattern match interrupt enable */
elessair 0:f269e3021894 2023 __I uint32_t STATUS_2; /* Pattern match interrupt status */
elessair 0:f269e3021894 2024 __O uint32_t CTR_STATUS_2; /* Pattern match interrupt clear status */
elessair 0:f269e3021894 2025 __O uint32_t SET_STATUS_2; /* Pattern match interrupt set status */
elessair 0:f269e3021894 2026 __I uint32_t RESERVED3[2];
elessair 0:f269e3021894 2027 __O uint32_t CLR_EN_3; /* Input interrupt clear mask */
elessair 0:f269e3021894 2028 __O uint32_t SET_EN_3; /* Input bit match interrupt set mask */
elessair 0:f269e3021894 2029 __I uint32_t ENABLE_3; /* Input bit match interrupt enable */
elessair 0:f269e3021894 2030 __I uint32_t STATUS_3; /* Input bit match interrupt status */
elessair 0:f269e3021894 2031 __O uint32_t CTR_STATUS_3; /* Input bit match interrupt clear status */
elessair 0:f269e3021894 2032 __O uint32_t SET_STATUS_3; /* Shift clock interrupt set status */
elessair 0:f269e3021894 2033 } LPC_SGPIO_T;
elessair 0:f269e3021894 2034
elessair 0:f269e3021894 2035 /* End of section using anonymous unions */
elessair 0:f269e3021894 2036 #if defined(__ARMCC_VERSION)
elessair 0:f269e3021894 2037 #pragma pop
elessair 0:f269e3021894 2038 #elif defined(__CWCC__)
elessair 0:f269e3021894 2039 #pragma pop
elessair 0:f269e3021894 2040 #elif defined(__IAR_SYSTEMS_ICC__)
elessair 0:f269e3021894 2041 //#pragma pop // FIXME not usable for IAR
elessair 0:f269e3021894 2042 #else /* defined(__GNUC__) and others */
elessair 0:f269e3021894 2043 /* Leave anonymous unions enabled */
elessair 0:f269e3021894 2044 #endif
elessair 0:f269e3021894 2045
elessair 0:f269e3021894 2046 /* ---------------------------------------------------------------------------
elessair 0:f269e3021894 2047 * LPC43xx Peripheral register set declarations
elessair 0:f269e3021894 2048 */
elessair 0:f269e3021894 2049 #define LPC_SCT ((LPC_SCT_T *) LPC_SCT_BASE)
elessair 0:f269e3021894 2050 #define LPC_GPDMA ((LPC_GPDMA_T *) LPC_GPDMA_BASE)
elessair 0:f269e3021894 2051 #define LPC_SPIFI ((LPC_SPIFI_T *) LPC_SPIFI_BASE)
elessair 0:f269e3021894 2052 #define LPC_SDMMC ((LPC_SDMMC_T *) LPC_SDMMC_BASE)
elessair 0:f269e3021894 2053 #define LPC_EMC ((LPC_EMC_T *) LPC_EMC_BASE)
elessair 0:f269e3021894 2054 #define LPC_USB0 ((LPC_USBHS_T *) LPC_USB0_BASE)
elessair 0:f269e3021894 2055 #define LPC_USB1 ((LPC_USBHS_T *) LPC_USB1_BASE)
elessair 0:f269e3021894 2056 #define LPC_LCD ((LPC_LCD_T *) LPC_LCD_BASE)
elessair 0:f269e3021894 2057 #define LPC_EEPROM ((LPC_EEPROM_T *) LPC_EEPROM_BASE)
elessair 0:f269e3021894 2058 #define LPC_ETHERNET ((LPC_ENET_T *) LPC_ETHERNET_BASE)
elessair 0:f269e3021894 2059 #define LPC_ATIMER ((LPC_ATIMER_T *) LPC_ATIMER_BASE)
elessair 0:f269e3021894 2060 #define LPC_REGFILE ((LPC_REGFILE_T *) LPC_REGFILE_BASE)
elessair 0:f269e3021894 2061 #define LPC_PMC ((LPC_PMC_T *) LPC_PMC_BASE)
elessair 0:f269e3021894 2062 #define LPC_CREG ((LPC_CREG_T *) LPC_CREG_BASE)
elessair 0:f269e3021894 2063 #define LPC_EVRT ((LPC_EVRT_T *) LPC_EVRT_BASE)
elessair 0:f269e3021894 2064 #define LPC_RTC ((LPC_RTC_T *) LPC_RTC_BASE)
elessair 0:f269e3021894 2065 #define LPC_CGU ((LPC_CGU_T *) LPC_CGU_BASE)
elessair 0:f269e3021894 2066 #define LPC_CCU1 ((LPC_CCU1_T *) LPC_CCU1_BASE)
elessair 0:f269e3021894 2067 #define LPC_CCU2 ((LPC_CCU2_T *) LPC_CCU2_BASE)
elessair 0:f269e3021894 2068 #define LPC_RGU ((LPC_RGU_T *) LPC_RGU_BASE)
elessair 0:f269e3021894 2069 #define LPC_WWDT ((LPC_WWDT_T *) LPC_WWDT_BASE)
elessair 0:f269e3021894 2070 #define LPC_USART0 ((LPC_USART_T *) LPC_USART0_BASE)
elessair 0:f269e3021894 2071 #define LPC_USART2 ((LPC_USART_T *) LPC_USART2_BASE)
elessair 0:f269e3021894 2072 #define LPC_USART3 ((LPC_USART_T *) LPC_USART3_BASE)
elessair 0:f269e3021894 2073 #define LPC_UART1 ((LPC_USART_T *) LPC_UART1_BASE)
elessair 0:f269e3021894 2074 #define LPC_SSP0 ((LPC_SSP_T *) LPC_SSP0_BASE)
elessair 0:f269e3021894 2075 #define LPC_SSP1 ((LPC_SSP_T *) LPC_SSP1_BASE)
elessair 0:f269e3021894 2076 #define LPC_TIMER0 ((LPC_TIMER_T *) LPC_TIMER0_BASE)
elessair 0:f269e3021894 2077 #define LPC_TIMER1 ((LPC_TIMER_T *) LPC_TIMER1_BASE)
elessair 0:f269e3021894 2078 #define LPC_TIMER2 ((LPC_TIMER_T *) LPC_TIMER2_BASE)
elessair 0:f269e3021894 2079 #define LPC_TIMER3 ((LPC_TIMER_T *) LPC_TIMER3_BASE)
elessair 0:f269e3021894 2080 #define LPC_SCU ((LPC_SCU_T *) LPC_SCU_BASE)
elessair 0:f269e3021894 2081 #define LPC_GPIO_PIN_INT ((LPC_GPIOPININT_T *) LPC_GPIO_PIN_INT_BASE)
elessair 0:f269e3021894 2082 #define LPC_GPIO_GROUP_INT0 ((IP_GPIOGROUPINT_T *) LPC_GPIO_GROUP_INT0_BASE)
elessair 0:f269e3021894 2083 #define LPC_GPIO_GROUP_INT1 ((IP_GPIOGROUPINT_T *) LPC_GPIO_GROUP_INT1_BASE)
elessair 0:f269e3021894 2084 #define LPC_MCPWM ((LPC_MCPWM_T *) LPC_MCPWM_BASE)
elessair 0:f269e3021894 2085 #define LPC_I2C0 ((LPC_I2C_T *) LPC_I2C0_BASE)
elessair 0:f269e3021894 2086 #define LPC_I2C1 ((LPC_I2C_T *) LPC_I2C1_BASE)
elessair 0:f269e3021894 2087 #define LPC_I2S0 ((LPC_I2S_T *) LPC_I2S0_BASE)
elessair 0:f269e3021894 2088 #define LPC_I2S1 ((LPC_I2S_T *) LPC_I2S1_BASE)
elessair 0:f269e3021894 2089 #define LPC_C_CAN1 ((LPC_CCAN_T *) LPC_C_CAN1_BASE)
elessair 0:f269e3021894 2090 #define LPC_RITIMER ((LPC_RITIMER_T *) LPC_RITIMER_BASE)
elessair 0:f269e3021894 2091 #define LPC_QEI ((LPC_QEI_T *) LPC_QEI_BASE)
elessair 0:f269e3021894 2092 #define LPC_GIMA ((LPC_GIMA_T *) LPC_GIMA_BASE)
elessair 0:f269e3021894 2093 #define LPC_DAC ((LPC_DAC_T *) LPC_DAC_BASE)
elessair 0:f269e3021894 2094 #define LPC_C_CAN0 ((LPC_CCAN_T *) LPC_C_CAN0_BASE)
elessair 0:f269e3021894 2095 #define LPC_ADC0 ((LPC_ADC_T *) LPC_ADC0_BASE)
elessair 0:f269e3021894 2096 #define LPC_ADC1 ((LPC_ADC_T *) LPC_ADC1_BASE)
elessair 0:f269e3021894 2097 #define LPC_GPIO_PORT ((LPC_GPIO_T *) LPC_GPIO_PORT_BASE)
elessair 0:f269e3021894 2098 #define LPC_GPIO0 ((LPC_GPIO_T *) LPC_GPIO0_BASE)
elessair 0:f269e3021894 2099 #define LPC_GPIO1 ((LPC_GPIO_T *) LPC_GPIO1_BASE)
elessair 0:f269e3021894 2100 #define LPC_GPIO2 ((LPC_GPIO_T *) LPC_GPIO2_BASE)
elessair 0:f269e3021894 2101 #define LPC_GPIO3 ((LPC_GPIO_T *) LPC_GPIO3_BASE)
elessair 0:f269e3021894 2102 #define LPC_GPIO4 ((LPC_GPIO_T *) LPC_GPIO4_BASE)
elessair 0:f269e3021894 2103 #define LPC_GPIO5 ((LPC_GPIO_T *) LPC_GPIO5_BASE)
elessair 0:f269e3021894 2104 #define LPC_GPIO6 ((LPC_GPIO_T *) LPC_GPIO6_BASE)
elessair 0:f269e3021894 2105 #define LPC_GPIO7 ((LPC_GPIO_T *) LPC_GPIO7_BASE)
elessair 0:f269e3021894 2106 #define LPC_SPI ((LPC_SPI_T *) LPC_SPI_BASE)
elessair 0:f269e3021894 2107 #define LPC_SGPIO ((LPC_SGPIO_T *) LPC_SGPIO_BASE)
elessair 0:f269e3021894 2108
elessair 0:f269e3021894 2109 #ifdef __cplusplus
elessair 0:f269e3021894 2110 }
elessair 0:f269e3021894 2111 #endif
elessair 0:f269e3021894 2112
elessair 0:f269e3021894 2113 #endif /* __LPC43XX_H */