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targets/TARGET_ONSEMI/TARGET_NCS36510/test_map.h@0:f269e3021894, 2016-10-23 (annotated)

Committer:
elessair
Date:
Sun Oct 23 15:10:02 2016 +0000
Revision:
0:f269e3021894
Initial commit

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elessair 0:f269e3021894 1 /**
elessair 0:f269e3021894 2 ******************************************************************************
elessair 0:f269e3021894 3 * @file test_map.h
elessair 0:f269e3021894 4 * @brief Test hw module register map
elessair 0:f269e3021894 5 * @internal
elessair 0:f269e3021894 6 * @author ON Semiconductor
elessair 0:f269e3021894 7 * $Rev: 2848 $
elessair 0:f269e3021894 8 * $Date: 2014-04-01 22:48:18 +0530 (Tue, 01 Apr 2014) $
elessair 0:f269e3021894 9 ******************************************************************************
elessair 0:f269e3021894 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
elessair 0:f269e3021894 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
elessair 0:f269e3021894 12 * under limited terms and conditions. The terms and conditions pertaining to the software
elessair 0:f269e3021894 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
elessair 0:f269e3021894 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
elessair 0:f269e3021894 15 * if applicable the software license agreement. Do not use this software and/or
elessair 0:f269e3021894 16 * documentation unless you have carefully read and you agree to the limited terms and
elessair 0:f269e3021894 17 * conditions. By using this software and/or documentation, you agree to the limited
elessair 0:f269e3021894 18 * terms and conditions.
elessair 0:f269e3021894 19 *
elessair 0:f269e3021894 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
elessair 0:f269e3021894 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
elessair 0:f269e3021894 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
elessair 0:f269e3021894 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
elessair 0:f269e3021894 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
elessair 0:f269e3021894 25 * @endinternal
elessair 0:f269e3021894 26 *
elessair 0:f269e3021894 27 * @ingroup test
elessair 0:f269e3021894 28 *
elessair 0:f269e3021894 29 * @details
elessair 0:f269e3021894 30 */
elessair 0:f269e3021894 31
elessair 0:f269e3021894 32 #ifndef TEST_MAP_H_
elessair 0:f269e3021894 33 #define TEST_MAP_H_
elessair 0:f269e3021894 34
elessair 0:f269e3021894 35 /*************************************************************************************************
elessair 0:f269e3021894 36 * *
elessair 0:f269e3021894 37 * Header files *
elessair 0:f269e3021894 38 * *
elessair 0:f269e3021894 39 *************************************************************************************************/
elessair 0:f269e3021894 40
elessair 0:f269e3021894 41 #include "architecture.h"
elessair 0:f269e3021894 42
elessair 0:f269e3021894 43 /**************************************************************************************************
elessair 0:f269e3021894 44 * *
elessair 0:f269e3021894 45 * Type definitions *
elessair 0:f269e3021894 46 * *
elessair 0:f269e3021894 47 **************************************************************************************************/
elessair 0:f269e3021894 48
elessair 0:f269e3021894 49 /** General test registers
elessair 0:f269e3021894 50 *
elessair 0:f269e3021894 51 */
elessair 0:f269e3021894 52 typedef struct {
elessair 0:f269e3021894 53 __IO uint32_t UNLOCK;
elessair 0:f269e3021894 54 __IO uint32_t ANA_TEST_MUX;
elessair 0:f269e3021894 55 __IO uint32_t OVD_ENA_MODE;
elessair 0:f269e3021894 56 __IO uint32_t OVD_VAL;
elessair 0:f269e3021894 57 __IO uint32_t ANA_TEST_MODE;
elessair 0:f269e3021894 58 __IO uint32_t CLK_TEST_MODE;
elessair 0:f269e3021894 59 union {
elessair 0:f269e3021894 60 struct {
elessair 0:f269e3021894 61 __IO uint32_t PAD0:1;
elessair 0:f269e3021894 62 __IO uint32_t PAD1:1;
elessair 0:f269e3021894 63 __IO uint32_t FORCE_SOURCE:1;
elessair 0:f269e3021894 64 __IO uint32_t FORCE_SINK:1;
elessair 0:f269e3021894 65 __IO uint32_t PD_CONTROL:3;
elessair 0:f269e3021894 66 __IO uint32_t PAD3:1;
elessair 0:f269e3021894 67 __IO uint32_t BYPASS_PLL_REG:1;
elessair 0:f269e3021894 68 __IO uint32_t PAD4:4;
elessair 0:f269e3021894 69 __IO uint32_t DITHER_MODE:1;
elessair 0:f269e3021894 70 __IO uint32_t PLL_MODE:1;
elessair 0:f269e3021894 71 __IO uint32_t FORCE_LOCK:1;
elessair 0:f269e3021894 72 } BITS;
elessair 0:f269e3021894 73 __IO uint32_t WORD;
elessair 0:f269e3021894 74 } PLL_TEST_MODE;
elessair 0:f269e3021894 75 __IO uint32_t RX_TEST_MODE;
elessair 0:f269e3021894 76 __IO uint32_t PMU_TEST_MODE;
elessair 0:f269e3021894 77 } TestReg_t, *TestReg_pt;
elessair 0:f269e3021894 78
elessair 0:f269e3021894 79 /** Digital test registers
elessair 0:f269e3021894 80 *
elessair 0:f269e3021894 81 */
elessair 0:f269e3021894 82 typedef struct {
elessair 0:f269e3021894 83 union {
elessair 0:f269e3021894 84 struct {
elessair 0:f269e3021894 85 __IO uint32_t PAD0 :4; /**< */
elessair 0:f269e3021894 86 __IO uint32_t DIO4 :4; /**< DIO4 Test Mux Control */
elessair 0:f269e3021894 87 __IO uint32_t DIO5 :4; /**< DIO5 Test Mux Control */
elessair 0:f269e3021894 88 __IO uint32_t DIO6 :4; /**< DIO6 Test Mux Control */
elessair 0:f269e3021894 89 __IO uint32_t DIO7 :4; /**< DIO7 Test Mux Control */
elessair 0:f269e3021894 90 __IO uint32_t DIO8 :4; /**< DIO8 Test Mux Control */
elessair 0:f269e3021894 91 __IO uint32_t DIO9 :4; /**< DIO9 Test Mux Control */
elessair 0:f269e3021894 92 __IO uint32_t DIO10 :4; /**< DIO10 Test Mux Control */
elessair 0:f269e3021894 93 } BITS;
elessair 0:f269e3021894 94 __IO uint32_t WORD;
elessair 0:f269e3021894 95 } DIG_TEST_MUX;
elessair 0:f269e3021894 96 __IO uint32_t DIG_TEST_MODE;
elessair 0:f269e3021894 97 union {
elessair 0:f269e3021894 98 struct {
elessair 0:f269e3021894 99 __IO uint32_t PAD0 :12; /**< */
elessair 0:f269e3021894 100 __IO uint32_t DIO5 :3; /**< DIO5 Input Test Mux Control */
elessair 0:f269e3021894 101 __IO uint32_t DIO6 :3; /**< DIO6 Input Test Mux Control */
elessair 0:f269e3021894 102 __IO uint32_t DIO7 :3; /**< DIO7 Input Test Mux Control */
elessair 0:f269e3021894 103 __IO uint32_t DIO8 :3; /**< DIO8 Input Test Mux Control */
elessair 0:f269e3021894 104 __IO uint32_t DIO9 :3; /**< DIO9 Input Test Mux Control */
elessair 0:f269e3021894 105 __IO uint32_t DIO10 :3; /**< DIO10 Input Test Mux Control */
elessair 0:f269e3021894 106 } BITS;
elessair 0:f269e3021894 107 __IO uint32_t WORD;
elessair 0:f269e3021894 108 } DIG_IN_TEST_MUX;
elessair 0:f269e3021894 109 __IO uint32_t SCAN_MODE;
elessair 0:f269e3021894 110 __IO uint32_t BIST_TEST_MUX;
elessair 0:f269e3021894 111 __IO uint32_t RAM_DIAG_ADDR;
elessair 0:f269e3021894 112 __IO uint32_t RAM_DIAG_DATA;
elessair 0:f269e3021894 113 __IO uint32_t SRAMA_DIAG_COMP;
elessair 0:f269e3021894 114 __IO uint32_t SRAMB_DIAG_COMP;
elessair 0:f269e3021894 115 __IO uint32_t RAM_BUF_TEST_MODE;
elessair 0:f269e3021894 116 } TestDigReg_t, *TestDigReg_pt;
elessair 0:f269e3021894 117
elessair 0:f269e3021894 118 /** NVM test registers
elessair 0:f269e3021894 119 *
elessair 0:f269e3021894 120 */
elessair 0:f269e3021894 121 typedef struct {
elessair 0:f269e3021894 122 __O uint32_t PAD;
elessair 0:f269e3021894 123 } TestNvmReg_t, *TestNvmReg_pt;
elessair 0:f269e3021894 124
elessair 0:f269e3021894 125 #endif /* TEST_MAP_H_ */