Lee Kai Xuan / mbed-os

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targets/TARGET_ONSEMI/TARGET_NCS36510/gpio_map.h@0:f269e3021894, 2016-10-23 (annotated)

Committer:
elessair
Date:
Sun Oct 23 15:10:02 2016 +0000
Revision:
0:f269e3021894
Initial commit

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elessair 0:f269e3021894 1 /**
elessair 0:f269e3021894 2 ******************************************************************************
elessair 0:f269e3021894 3 * @file gpio_map.h
elessair 0:f269e3021894 4 * @brief GPIO HW register map
elessair 0:f269e3021894 5 * @internal
elessair 0:f269e3021894 6 * @author ON Semiconductor
elessair 0:f269e3021894 7 * $Rev: 2115 $
elessair 0:f269e3021894 8 * $Date: 2013-07-17 18:08:17 +0530 (Wed, 17 Jul 2013) $
elessair 0:f269e3021894 9 ******************************************************************************
elessair 0:f269e3021894 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
elessair 0:f269e3021894 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
elessair 0:f269e3021894 12 * under limited terms and conditions. The terms and conditions pertaining to the software
elessair 0:f269e3021894 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
elessair 0:f269e3021894 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
elessair 0:f269e3021894 15 * if applicable the software license agreement. Do not use this software and/or
elessair 0:f269e3021894 16 * documentation unless you have carefully read and you agree to the limited terms and
elessair 0:f269e3021894 17 * conditions. By using this software and/or documentation, you agree to the limited
elessair 0:f269e3021894 18 * terms and conditions.
elessair 0:f269e3021894 19 *
elessair 0:f269e3021894 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
elessair 0:f269e3021894 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
elessair 0:f269e3021894 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
elessair 0:f269e3021894 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
elessair 0:f269e3021894 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
elessair 0:f269e3021894 25 * @endinternal
elessair 0:f269e3021894 26 *
elessair 0:f269e3021894 27 * @ingroup gpio
elessair 0:f269e3021894 28 *
elessair 0:f269e3021894 29 * @details
elessair 0:f269e3021894 30 * <p>
elessair 0:f269e3021894 31 * GPIO HW register map description
elessair 0:f269e3021894 32 * </p>
elessair 0:f269e3021894 33 *
elessair 0:f269e3021894 34 * <h1> Reference document(s) </h1>
elessair 0:f269e3021894 35 * <p>
elessair 0:f269e3021894 36 * <a href="../pdf/IPC7203_GPIO_APB_DS_v1P1.pdf" target="_blank">
elessair 0:f269e3021894 37 * Reference document: IPC7203 APB GPIO Design Specification v1.2</a>
elessair 0:f269e3021894 38 * </p>
elessair 0:f269e3021894 39 */
elessair 0:f269e3021894 40
elessair 0:f269e3021894 41 #ifndef GPIO_MAP_H_
elessair 0:f269e3021894 42 #define GPIO_MAP_H_
elessair 0:f269e3021894 43
elessair 0:f269e3021894 44 #include "architecture.h"
elessair 0:f269e3021894 45
elessair 0:f269e3021894 46 /** Structure overlay for GPIO control registers, see memory_map.h
elessair 0:f269e3021894 47 * For most registers, bit lockations match GPIO numbers.*/
elessair 0:f269e3021894 48 typedef struct {
elessair 0:f269e3021894 49 __IO uint32_t R_STATE_W_SET; /**< Read synchronized input / Write ones to bits to set corresponding output IO's*/
elessair 0:f269e3021894 50 __IO uint32_t R_IRQ_W_CLEAR; /**< Read state of irq / Write ones to bits to clear corresponging output IO's */
elessair 0:f269e3021894 51 __IO uint32_t W_OUT; /**< Write ones to set direction to output */
elessair 0:f269e3021894 52 __IO uint32_t W_IN; /**< Write ones to set direction to input */
elessair 0:f269e3021894 53 __IO uint32_t IRQ_ENABLE_SET; /**< Read active high irq enable / Write ones to enable irq */
elessair 0:f269e3021894 54 __IO uint32_t IRQ_ENABLE_CLEAR; /**< Read active high irq enable / Write ones to disable irq */
elessair 0:f269e3021894 55 __IO uint32_t IRQ_EDGE; /**< Read irq configuration (edge or level) / Write ones to set irq to edge-sensitive */
elessair 0:f269e3021894 56 __IO uint32_t IRQ_LEVEL; /**< Read irq configuration (edge or level) / Write ones to set irq to level-sensitive */
elessair 0:f269e3021894 57 __IO uint32_t IRQ_POLARITY_SET; /**< Read irq polarity / Write ones to set irq to active high or rising edge */
elessair 0:f269e3021894 58 __IO uint32_t IRQ_POLARITY_CLEAR; /**< Read irq polarity / Write ones to set interrupts to active low or falling edge */
elessair 0:f269e3021894 59 __IO uint32_t ANYEDGE_SET; /**< Read irq anyedge configuration / Write ones to override irq edge selection & irq on any edge */
elessair 0:f269e3021894 60 __IO uint32_t ANYEDGE_CLEAR; /**< Read irq anyedge configuration / Write ones to clear edge selection override */
elessair 0:f269e3021894 61 __IO uint32_t IRQ_CLEAR; /**< Write ones to clear edge-sensitive irq */
elessair 0:f269e3021894 62 __IO uint32_t CONTROL; /**< Controls loopback/normal mode selection */
elessair 0:f269e3021894 63 } GpioReg_t, *GpioReg_pt;
elessair 0:f269e3021894 64
elessair 0:f269e3021894 65 #endif /* GPIO_MAP_H_ */