Lee Kai Xuan / mbed-os

mbed-os

Fork of mbed-os by erkin yucel

targets/TARGET_ONSEMI/TARGET_NCS36510/device/NCS36510.h@0:f269e3021894, 2016-10-23 (annotated)

Committer:
elessair
Date:
Sun Oct 23 15:10:02 2016 +0000
Revision:
0:f269e3021894
Initial commit

Who changed what in which revision?

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elessair 0:f269e3021894 1 /**************************************************************************/
elessair 0:f269e3021894 2 /**
elessair 0:f269e3021894 3 * @file NCS36510.h
elessair 0:f269e3021894 4 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
elessair 0:f269e3021894 5 * for CM3 Device Series
elessair 0:f269e3021894 6 * @version V1.05
elessair 0:f269e3021894 7 * @date 26. July 2011
elessair 0:f269e3021894 8 *
elessair 0:f269e3021894 9 * @note
elessair 0:f269e3021894 10 * Copyright (C) 2010-2011 ARM Limited. All rights reserved.
elessair 0:f269e3021894 11 *
elessair 0:f269e3021894 12 * @par
elessair 0:f269e3021894 13 * ARM Limited (ARM) is supplying this software for use with Cortex-M
elessair 0:f269e3021894 14 * processor based microcontrollers. This file can be freely distributed
elessair 0:f269e3021894 15 * within development tools that are supporting such ARM based processors.
elessair 0:f269e3021894 16 *
elessair 0:f269e3021894 17 * @par
elessair 0:f269e3021894 18 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
elessair 0:f269e3021894 19 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
elessair 0:f269e3021894 20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
elessair 0:f269e3021894 21 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
elessair 0:f269e3021894 22 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
elessair 0:f269e3021894 23 *
elessair 0:f269e3021894 24 ******************************************************************************/
elessair 0:f269e3021894 25
elessair 0:f269e3021894 26 #ifndef ARMCM3_H
elessair 0:f269e3021894 27 #define ARMCM3_H
elessair 0:f269e3021894 28
elessair 0:f269e3021894 29 /**
elessair 0:f269e3021894 30 * ==========================================================================
elessair 0:f269e3021894 31 * ---------- Interrupt Number Definition -----------------------------------
elessair 0:f269e3021894 32 * ==========================================================================
elessair 0:f269e3021894 33 */
elessair 0:f269e3021894 34 typedef enum IRQn {
elessair 0:f269e3021894 35 /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
elessair 0:f269e3021894 36 NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M3 Non Maskable Interrupt */
elessair 0:f269e3021894 37 HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */
elessair 0:f269e3021894 38 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
elessair 0:f269e3021894 39 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
elessair 0:f269e3021894 40 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
elessair 0:f269e3021894 41 SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
elessair 0:f269e3021894 42 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
elessair 0:f269e3021894 43 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
elessair 0:f269e3021894 44 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
elessair 0:f269e3021894 45
elessair 0:f269e3021894 46 /****** ARMCM3 specific Interrupt Numbers ********************************************************/
elessair 0:f269e3021894 47 Tim0_IRQn = 0,
elessair 0:f269e3021894 48 Tim1_IRQn = 1,
elessair 0:f269e3021894 49 Tim2_IRQn = 2,
elessair 0:f269e3021894 50 Uart1_IRQn = 3,
elessair 0:f269e3021894 51 Spi_IRQn = 4,
elessair 0:f269e3021894 52 I2C_IRQn = 5,
elessair 0:f269e3021894 53 Gpio_IRQn = 6,
elessair 0:f269e3021894 54 Rtc_IRQn = 7,
elessair 0:f269e3021894 55 Flash_IRQn = 8,
elessair 0:f269e3021894 56 MacHw_IRQn = 9,
elessair 0:f269e3021894 57 Aes_IRQn = 10,
elessair 0:f269e3021894 58 Adc_IRQn = 11,
elessair 0:f269e3021894 59 ClockCal_IRQn = 12,
elessair 0:f269e3021894 60 Uart2_IRQn = 13,
elessair 0:f269e3021894 61 Uvi_IRQn = 14,
elessair 0:f269e3021894 62 Dma_IRQn = 15,
elessair 0:f269e3021894 63 DbgPwrUp_IRQn = 16,
elessair 0:f269e3021894 64 Spi2_IRQn = 17,
elessair 0:f269e3021894 65 I2C2_IRQn = 18,
elessair 0:f269e3021894 66 FVDDHComp_IRQn = 19
elessair 0:f269e3021894 67 } IRQn_Type;
elessair 0:f269e3021894 68
elessair 0:f269e3021894 69 /**
elessair 0:f269e3021894 70 * ==========================================================================
elessair 0:f269e3021894 71 * ----------- Processor and Core Peripheral Section ------------------------
elessair 0:f269e3021894 72 * ==========================================================================
elessair 0:f269e3021894 73 */
elessair 0:f269e3021894 74
elessair 0:f269e3021894 75 /** Configuration of the Cortex-M3 Processor and Core Peripherals */
elessair 0:f269e3021894 76 #define __CM3_REV 0x0201 /*!< Core Revision r2p1 */
elessair 0:f269e3021894 77 #define __MPU_PRESENT 1 /*!< MPU present or not */
elessair 0:f269e3021894 78 #define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */
elessair 0:f269e3021894 79 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
elessair 0:f269e3021894 80
elessair 0:f269e3021894 81 //#define YOTTA_CFG_CMSIS_NVIC_USER_IRQ_OFFSET 16
elessair 0:f269e3021894 82 //#define YOTTA_CFG_CMSIS_NVIC_USER_IRQ_NUMBER 20
elessair 0:f269e3021894 83 //#define NVIC_NUM_VECTORS (NVIC_USER_IRQ_OFFSET + NVIC_USER_IRQ_NUMBER)
elessair 0:f269e3021894 84
elessair 0:f269e3021894 85 //#define YOTTA_CFG_CMSIS_NVIC_RAM_VECTOR_ADDRESS
elessair 0:f269e3021894 86 //#define YOTTA_CFG_CMSIS_NVIC_FLASH_VECTOR_ADDRESS 0x3000
elessair 0:f269e3021894 87
elessair 0:f269e3021894 88 #include <core_cm3.h> /* Cortex-M3 processor and core peripherals */
elessair 0:f269e3021894 89 #include "system_NCS36510.h" /* System Header */
elessair 0:f269e3021894 90
elessair 0:f269e3021894 91 #endif /* ARMCM3_H */