Lee Kai Xuan / mbed-os

mbed-os

Fork of mbed-os by erkin yucel

targets/TARGET_NXP/TARGET_LPC176X/device/LPC17xx.h@0:f269e3021894, 2016-10-23 (annotated)

Committer:
elessair
Date:
Sun Oct 23 15:10:02 2016 +0000
Revision:
0:f269e3021894
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
elessair 0:f269e3021894 1 /**************************************************************************//**
elessair 0:f269e3021894 2 * @file LPC17xx.h
elessair 0:f269e3021894 3 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
elessair 0:f269e3021894 4 * NXP LPC17xx Device Series
elessair 0:f269e3021894 5 * @version: V1.09
elessair 0:f269e3021894 6 * @date: 17. March 2010
elessair 0:f269e3021894 7
elessair 0:f269e3021894 8 *
elessair 0:f269e3021894 9 * @note
elessair 0:f269e3021894 10 * Copyright (C) 2009 ARM Limited. All rights reserved.
elessair 0:f269e3021894 11 *
elessair 0:f269e3021894 12 * @par
elessair 0:f269e3021894 13 * ARM Limited (ARM) is supplying this software for use with Cortex-M
elessair 0:f269e3021894 14 * processor based microcontrollers. This file can be freely distributed
elessair 0:f269e3021894 15 * within development tools that are supporting such ARM based processors.
elessair 0:f269e3021894 16 *
elessair 0:f269e3021894 17 * @par
elessair 0:f269e3021894 18 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
elessair 0:f269e3021894 19 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
elessair 0:f269e3021894 20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
elessair 0:f269e3021894 21 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
elessair 0:f269e3021894 22 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
elessair 0:f269e3021894 23 *
elessair 0:f269e3021894 24 ******************************************************************************/
elessair 0:f269e3021894 25
elessair 0:f269e3021894 26
elessair 0:f269e3021894 27 #ifndef __LPC17xx_H__
elessair 0:f269e3021894 28 #define __LPC17xx_H__
elessair 0:f269e3021894 29
elessair 0:f269e3021894 30 /*
elessair 0:f269e3021894 31 * ==========================================================================
elessair 0:f269e3021894 32 * ---------- Interrupt Number Definition -----------------------------------
elessair 0:f269e3021894 33 * ==========================================================================
elessair 0:f269e3021894 34 */
elessair 0:f269e3021894 35
elessair 0:f269e3021894 36 typedef enum IRQn
elessair 0:f269e3021894 37 {
elessair 0:f269e3021894 38 /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
elessair 0:f269e3021894 39 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
elessair 0:f269e3021894 40 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
elessair 0:f269e3021894 41 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
elessair 0:f269e3021894 42 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
elessair 0:f269e3021894 43 SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
elessair 0:f269e3021894 44 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
elessair 0:f269e3021894 45 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
elessair 0:f269e3021894 46 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
elessair 0:f269e3021894 47
elessair 0:f269e3021894 48 /****** LPC17xx Specific Interrupt Numbers *******************************************************/
elessair 0:f269e3021894 49 WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
elessair 0:f269e3021894 50 TIMER0_IRQn = 1, /*!< Timer0 Interrupt */
elessair 0:f269e3021894 51 TIMER1_IRQn = 2, /*!< Timer1 Interrupt */
elessair 0:f269e3021894 52 TIMER2_IRQn = 3, /*!< Timer2 Interrupt */
elessair 0:f269e3021894 53 TIMER3_IRQn = 4, /*!< Timer3 Interrupt */
elessair 0:f269e3021894 54 UART0_IRQn = 5, /*!< UART0 Interrupt */
elessair 0:f269e3021894 55 UART1_IRQn = 6, /*!< UART1 Interrupt */
elessair 0:f269e3021894 56 UART2_IRQn = 7, /*!< UART2 Interrupt */
elessair 0:f269e3021894 57 UART3_IRQn = 8, /*!< UART3 Interrupt */
elessair 0:f269e3021894 58 PWM1_IRQn = 9, /*!< PWM1 Interrupt */
elessair 0:f269e3021894 59 I2C0_IRQn = 10, /*!< I2C0 Interrupt */
elessair 0:f269e3021894 60 I2C1_IRQn = 11, /*!< I2C1 Interrupt */
elessair 0:f269e3021894 61 I2C2_IRQn = 12, /*!< I2C2 Interrupt */
elessair 0:f269e3021894 62 SPI_IRQn = 13, /*!< SPI Interrupt */
elessair 0:f269e3021894 63 SSP0_IRQn = 14, /*!< SSP0 Interrupt */
elessair 0:f269e3021894 64 SSP1_IRQn = 15, /*!< SSP1 Interrupt */
elessair 0:f269e3021894 65 PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */
elessair 0:f269e3021894 66 RTC_IRQn = 17, /*!< Real Time Clock Interrupt */
elessair 0:f269e3021894 67 EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */
elessair 0:f269e3021894 68 EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */
elessair 0:f269e3021894 69 EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */
elessair 0:f269e3021894 70 EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */
elessair 0:f269e3021894 71 ADC_IRQn = 22, /*!< A/D Converter Interrupt */
elessair 0:f269e3021894 72 BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */
elessair 0:f269e3021894 73 USB_IRQn = 24, /*!< USB Interrupt */
elessair 0:f269e3021894 74 CAN_IRQn = 25, /*!< CAN Interrupt */
elessair 0:f269e3021894 75 DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */
elessair 0:f269e3021894 76 I2S_IRQn = 27, /*!< I2S Interrupt */
elessair 0:f269e3021894 77 ENET_IRQn = 28, /*!< Ethernet Interrupt */
elessair 0:f269e3021894 78 RIT_IRQn = 29, /*!< Repetitive Interrupt Timer Interrupt */
elessair 0:f269e3021894 79 MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */
elessair 0:f269e3021894 80 QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */
elessair 0:f269e3021894 81 PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */
elessair 0:f269e3021894 82 USBActivity_IRQn = 33, /* USB Activity interrupt */
elessair 0:f269e3021894 83 CANActivity_IRQn = 34, /* CAN Activity interrupt */
elessair 0:f269e3021894 84 } IRQn_Type;
elessair 0:f269e3021894 85
elessair 0:f269e3021894 86
elessair 0:f269e3021894 87 /*
elessair 0:f269e3021894 88 * ==========================================================================
elessair 0:f269e3021894 89 * ----------- Processor and Core Peripheral Section ------------------------
elessair 0:f269e3021894 90 * ==========================================================================
elessair 0:f269e3021894 91 */
elessair 0:f269e3021894 92
elessair 0:f269e3021894 93 /* Configuration of the Cortex-M3 Processor and Core Peripherals */
elessair 0:f269e3021894 94 #define __MPU_PRESENT 1 /*!< MPU present or not */
elessair 0:f269e3021894 95 #define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */
elessair 0:f269e3021894 96 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
elessair 0:f269e3021894 97
elessair 0:f269e3021894 98
elessair 0:f269e3021894 99 #include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
elessair 0:f269e3021894 100 #include "system_LPC17xx.h" /* System Header */
elessair 0:f269e3021894 101
elessair 0:f269e3021894 102
elessair 0:f269e3021894 103 /******************************************************************************/
elessair 0:f269e3021894 104 /* Device Specific Peripheral registers structures */
elessair 0:f269e3021894 105 /******************************************************************************/
elessair 0:f269e3021894 106
elessair 0:f269e3021894 107 #if defined ( __CC_ARM )
elessair 0:f269e3021894 108 #pragma anon_unions
elessair 0:f269e3021894 109 #endif
elessair 0:f269e3021894 110
elessair 0:f269e3021894 111 /*------------- System Control (SC) ------------------------------------------*/
elessair 0:f269e3021894 112 typedef struct
elessair 0:f269e3021894 113 {
elessair 0:f269e3021894 114 __IO uint32_t FLASHCFG; /* Flash Accelerator Module */
elessair 0:f269e3021894 115 uint32_t RESERVED0[31];
elessair 0:f269e3021894 116 __IO uint32_t PLL0CON; /* Clocking and Power Control */
elessair 0:f269e3021894 117 __IO uint32_t PLL0CFG;
elessair 0:f269e3021894 118 __I uint32_t PLL0STAT;
elessair 0:f269e3021894 119 __O uint32_t PLL0FEED;
elessair 0:f269e3021894 120 uint32_t RESERVED1[4];
elessair 0:f269e3021894 121 __IO uint32_t PLL1CON;
elessair 0:f269e3021894 122 __IO uint32_t PLL1CFG;
elessair 0:f269e3021894 123 __I uint32_t PLL1STAT;
elessair 0:f269e3021894 124 __O uint32_t PLL1FEED;
elessair 0:f269e3021894 125 uint32_t RESERVED2[4];
elessair 0:f269e3021894 126 __IO uint32_t PCON;
elessair 0:f269e3021894 127 __IO uint32_t PCONP;
elessair 0:f269e3021894 128 uint32_t RESERVED3[15];
elessair 0:f269e3021894 129 __IO uint32_t CCLKCFG;
elessair 0:f269e3021894 130 __IO uint32_t USBCLKCFG;
elessair 0:f269e3021894 131 __IO uint32_t CLKSRCSEL;
elessair 0:f269e3021894 132 __IO uint32_t CANSLEEPCLR;
elessair 0:f269e3021894 133 __IO uint32_t CANWAKEFLAGS;
elessair 0:f269e3021894 134 uint32_t RESERVED4[10];
elessair 0:f269e3021894 135 __IO uint32_t EXTINT; /* External Interrupts */
elessair 0:f269e3021894 136 uint32_t RESERVED5;
elessair 0:f269e3021894 137 __IO uint32_t EXTMODE;
elessair 0:f269e3021894 138 __IO uint32_t EXTPOLAR;
elessair 0:f269e3021894 139 uint32_t RESERVED6[12];
elessair 0:f269e3021894 140 __IO uint32_t RSID; /* Reset */
elessair 0:f269e3021894 141 uint32_t RESERVED7[7];
elessair 0:f269e3021894 142 __IO uint32_t SCS; /* Syscon Miscellaneous Registers */
elessair 0:f269e3021894 143 __IO uint32_t IRCTRIM; /* Clock Dividers */
elessair 0:f269e3021894 144 __IO uint32_t PCLKSEL0;
elessair 0:f269e3021894 145 __IO uint32_t PCLKSEL1;
elessair 0:f269e3021894 146 uint32_t RESERVED8[4];
elessair 0:f269e3021894 147 __IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */
elessair 0:f269e3021894 148 __IO uint32_t DMAREQSEL;
elessair 0:f269e3021894 149 __IO uint32_t CLKOUTCFG; /* Clock Output Configuration */
elessair 0:f269e3021894 150 } LPC_SC_TypeDef;
elessair 0:f269e3021894 151
elessair 0:f269e3021894 152 /*------------- Pin Connect Block (PINCON) -----------------------------------*/
elessair 0:f269e3021894 153 typedef struct
elessair 0:f269e3021894 154 {
elessair 0:f269e3021894 155 __IO uint32_t PINSEL0;
elessair 0:f269e3021894 156 __IO uint32_t PINSEL1;
elessair 0:f269e3021894 157 __IO uint32_t PINSEL2;
elessair 0:f269e3021894 158 __IO uint32_t PINSEL3;
elessair 0:f269e3021894 159 __IO uint32_t PINSEL4;
elessair 0:f269e3021894 160 __IO uint32_t PINSEL5;
elessair 0:f269e3021894 161 __IO uint32_t PINSEL6;
elessair 0:f269e3021894 162 __IO uint32_t PINSEL7;
elessair 0:f269e3021894 163 __IO uint32_t PINSEL8;
elessair 0:f269e3021894 164 __IO uint32_t PINSEL9;
elessair 0:f269e3021894 165 __IO uint32_t PINSEL10;
elessair 0:f269e3021894 166 uint32_t RESERVED0[5];
elessair 0:f269e3021894 167 __IO uint32_t PINMODE0;
elessair 0:f269e3021894 168 __IO uint32_t PINMODE1;
elessair 0:f269e3021894 169 __IO uint32_t PINMODE2;
elessair 0:f269e3021894 170 __IO uint32_t PINMODE3;
elessair 0:f269e3021894 171 __IO uint32_t PINMODE4;
elessair 0:f269e3021894 172 __IO uint32_t PINMODE5;
elessair 0:f269e3021894 173 __IO uint32_t PINMODE6;
elessair 0:f269e3021894 174 __IO uint32_t PINMODE7;
elessair 0:f269e3021894 175 __IO uint32_t PINMODE8;
elessair 0:f269e3021894 176 __IO uint32_t PINMODE9;
elessair 0:f269e3021894 177 __IO uint32_t PINMODE_OD0;
elessair 0:f269e3021894 178 __IO uint32_t PINMODE_OD1;
elessair 0:f269e3021894 179 __IO uint32_t PINMODE_OD2;
elessair 0:f269e3021894 180 __IO uint32_t PINMODE_OD3;
elessair 0:f269e3021894 181 __IO uint32_t PINMODE_OD4;
elessair 0:f269e3021894 182 __IO uint32_t I2CPADCFG;
elessair 0:f269e3021894 183 } LPC_PINCON_TypeDef;
elessair 0:f269e3021894 184
elessair 0:f269e3021894 185 /*------------- General Purpose Input/Output (GPIO) --------------------------*/
elessair 0:f269e3021894 186 typedef struct
elessair 0:f269e3021894 187 {
elessair 0:f269e3021894 188 union {
elessair 0:f269e3021894 189 __IO uint32_t FIODIR;
elessair 0:f269e3021894 190 struct {
elessair 0:f269e3021894 191 __IO uint16_t FIODIRL;
elessair 0:f269e3021894 192 __IO uint16_t FIODIRH;
elessair 0:f269e3021894 193 };
elessair 0:f269e3021894 194 struct {
elessair 0:f269e3021894 195 __IO uint8_t FIODIR0;
elessair 0:f269e3021894 196 __IO uint8_t FIODIR1;
elessair 0:f269e3021894 197 __IO uint8_t FIODIR2;
elessair 0:f269e3021894 198 __IO uint8_t FIODIR3;
elessair 0:f269e3021894 199 };
elessair 0:f269e3021894 200 };
elessair 0:f269e3021894 201 uint32_t RESERVED0[3];
elessair 0:f269e3021894 202 union {
elessair 0:f269e3021894 203 __IO uint32_t FIOMASK;
elessair 0:f269e3021894 204 struct {
elessair 0:f269e3021894 205 __IO uint16_t FIOMASKL;
elessair 0:f269e3021894 206 __IO uint16_t FIOMASKH;
elessair 0:f269e3021894 207 };
elessair 0:f269e3021894 208 struct {
elessair 0:f269e3021894 209 __IO uint8_t FIOMASK0;
elessair 0:f269e3021894 210 __IO uint8_t FIOMASK1;
elessair 0:f269e3021894 211 __IO uint8_t FIOMASK2;
elessair 0:f269e3021894 212 __IO uint8_t FIOMASK3;
elessair 0:f269e3021894 213 };
elessair 0:f269e3021894 214 };
elessair 0:f269e3021894 215 union {
elessair 0:f269e3021894 216 __IO uint32_t FIOPIN;
elessair 0:f269e3021894 217 struct {
elessair 0:f269e3021894 218 __IO uint16_t FIOPINL;
elessair 0:f269e3021894 219 __IO uint16_t FIOPINH;
elessair 0:f269e3021894 220 };
elessair 0:f269e3021894 221 struct {
elessair 0:f269e3021894 222 __IO uint8_t FIOPIN0;
elessair 0:f269e3021894 223 __IO uint8_t FIOPIN1;
elessair 0:f269e3021894 224 __IO uint8_t FIOPIN2;
elessair 0:f269e3021894 225 __IO uint8_t FIOPIN3;
elessair 0:f269e3021894 226 };
elessair 0:f269e3021894 227 };
elessair 0:f269e3021894 228 union {
elessair 0:f269e3021894 229 __IO uint32_t FIOSET;
elessair 0:f269e3021894 230 struct {
elessair 0:f269e3021894 231 __IO uint16_t FIOSETL;
elessair 0:f269e3021894 232 __IO uint16_t FIOSETH;
elessair 0:f269e3021894 233 };
elessair 0:f269e3021894 234 struct {
elessair 0:f269e3021894 235 __IO uint8_t FIOSET0;
elessair 0:f269e3021894 236 __IO uint8_t FIOSET1;
elessair 0:f269e3021894 237 __IO uint8_t FIOSET2;
elessair 0:f269e3021894 238 __IO uint8_t FIOSET3;
elessair 0:f269e3021894 239 };
elessair 0:f269e3021894 240 };
elessair 0:f269e3021894 241 union {
elessair 0:f269e3021894 242 __O uint32_t FIOCLR;
elessair 0:f269e3021894 243 struct {
elessair 0:f269e3021894 244 __O uint16_t FIOCLRL;
elessair 0:f269e3021894 245 __O uint16_t FIOCLRH;
elessair 0:f269e3021894 246 };
elessair 0:f269e3021894 247 struct {
elessair 0:f269e3021894 248 __O uint8_t FIOCLR0;
elessair 0:f269e3021894 249 __O uint8_t FIOCLR1;
elessair 0:f269e3021894 250 __O uint8_t FIOCLR2;
elessair 0:f269e3021894 251 __O uint8_t FIOCLR3;
elessair 0:f269e3021894 252 };
elessair 0:f269e3021894 253 };
elessair 0:f269e3021894 254 } LPC_GPIO_TypeDef;
elessair 0:f269e3021894 255
elessair 0:f269e3021894 256 typedef struct
elessair 0:f269e3021894 257 {
elessair 0:f269e3021894 258 __I uint32_t IntStatus;
elessair 0:f269e3021894 259 __I uint32_t IO0IntStatR;
elessair 0:f269e3021894 260 __I uint32_t IO0IntStatF;
elessair 0:f269e3021894 261 __O uint32_t IO0IntClr;
elessair 0:f269e3021894 262 __IO uint32_t IO0IntEnR;
elessair 0:f269e3021894 263 __IO uint32_t IO0IntEnF;
elessair 0:f269e3021894 264 uint32_t RESERVED0[3];
elessair 0:f269e3021894 265 __I uint32_t IO2IntStatR;
elessair 0:f269e3021894 266 __I uint32_t IO2IntStatF;
elessair 0:f269e3021894 267 __O uint32_t IO2IntClr;
elessair 0:f269e3021894 268 __IO uint32_t IO2IntEnR;
elessair 0:f269e3021894 269 __IO uint32_t IO2IntEnF;
elessair 0:f269e3021894 270 } LPC_GPIOINT_TypeDef;
elessair 0:f269e3021894 271
elessair 0:f269e3021894 272 /*------------- Timer (TIM) --------------------------------------------------*/
elessair 0:f269e3021894 273 typedef struct
elessair 0:f269e3021894 274 {
elessair 0:f269e3021894 275 __IO uint32_t IR;
elessair 0:f269e3021894 276 __IO uint32_t TCR;
elessair 0:f269e3021894 277 __IO uint32_t TC;
elessair 0:f269e3021894 278 __IO uint32_t PR;
elessair 0:f269e3021894 279 __IO uint32_t PC;
elessair 0:f269e3021894 280 __IO uint32_t MCR;
elessair 0:f269e3021894 281 __IO uint32_t MR0;
elessair 0:f269e3021894 282 __IO uint32_t MR1;
elessair 0:f269e3021894 283 __IO uint32_t MR2;
elessair 0:f269e3021894 284 __IO uint32_t MR3;
elessair 0:f269e3021894 285 __IO uint32_t CCR;
elessair 0:f269e3021894 286 __I uint32_t CR0;
elessair 0:f269e3021894 287 __I uint32_t CR1;
elessair 0:f269e3021894 288 uint32_t RESERVED0[2];
elessair 0:f269e3021894 289 __IO uint32_t EMR;
elessair 0:f269e3021894 290 uint32_t RESERVED1[12];
elessair 0:f269e3021894 291 __IO uint32_t CTCR;
elessair 0:f269e3021894 292 } LPC_TIM_TypeDef;
elessair 0:f269e3021894 293
elessair 0:f269e3021894 294 /*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
elessair 0:f269e3021894 295 typedef struct
elessair 0:f269e3021894 296 {
elessair 0:f269e3021894 297 __IO uint32_t IR;
elessair 0:f269e3021894 298 __IO uint32_t TCR;
elessair 0:f269e3021894 299 __IO uint32_t TC;
elessair 0:f269e3021894 300 __IO uint32_t PR;
elessair 0:f269e3021894 301 __IO uint32_t PC;
elessair 0:f269e3021894 302 __IO uint32_t MCR;
elessair 0:f269e3021894 303 __IO uint32_t MR0;
elessair 0:f269e3021894 304 __IO uint32_t MR1;
elessair 0:f269e3021894 305 __IO uint32_t MR2;
elessair 0:f269e3021894 306 __IO uint32_t MR3;
elessair 0:f269e3021894 307 __IO uint32_t CCR;
elessair 0:f269e3021894 308 __I uint32_t CR0;
elessair 0:f269e3021894 309 __I uint32_t CR1;
elessair 0:f269e3021894 310 __I uint32_t CR2;
elessair 0:f269e3021894 311 __I uint32_t CR3;
elessair 0:f269e3021894 312 uint32_t RESERVED0;
elessair 0:f269e3021894 313 __IO uint32_t MR4;
elessair 0:f269e3021894 314 __IO uint32_t MR5;
elessair 0:f269e3021894 315 __IO uint32_t MR6;
elessair 0:f269e3021894 316 __IO uint32_t PCR;
elessair 0:f269e3021894 317 __IO uint32_t LER;
elessair 0:f269e3021894 318 uint32_t RESERVED1[7];
elessair 0:f269e3021894 319 __IO uint32_t CTCR;
elessair 0:f269e3021894 320 } LPC_PWM_TypeDef;
elessair 0:f269e3021894 321
elessair 0:f269e3021894 322 /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
elessair 0:f269e3021894 323 typedef struct
elessair 0:f269e3021894 324 {
elessair 0:f269e3021894 325 union {
elessair 0:f269e3021894 326 __I uint8_t RBR;
elessair 0:f269e3021894 327 __O uint8_t THR;
elessair 0:f269e3021894 328 __IO uint8_t DLL;
elessair 0:f269e3021894 329 uint32_t RESERVED0;
elessair 0:f269e3021894 330 };
elessair 0:f269e3021894 331 union {
elessair 0:f269e3021894 332 __IO uint8_t DLM;
elessair 0:f269e3021894 333 __IO uint32_t IER;
elessair 0:f269e3021894 334 };
elessair 0:f269e3021894 335 union {
elessair 0:f269e3021894 336 __I uint32_t IIR;
elessair 0:f269e3021894 337 __O uint8_t FCR;
elessair 0:f269e3021894 338 };
elessair 0:f269e3021894 339 __IO uint8_t LCR;
elessair 0:f269e3021894 340 uint8_t RESERVED1[7];
elessair 0:f269e3021894 341 __I uint8_t LSR;
elessair 0:f269e3021894 342 uint8_t RESERVED2[7];
elessair 0:f269e3021894 343 __IO uint8_t SCR;
elessair 0:f269e3021894 344 uint8_t RESERVED3[3];
elessair 0:f269e3021894 345 __IO uint32_t ACR;
elessair 0:f269e3021894 346 __IO uint8_t ICR;
elessair 0:f269e3021894 347 uint8_t RESERVED4[3];
elessair 0:f269e3021894 348 __IO uint8_t FDR;
elessair 0:f269e3021894 349 uint8_t RESERVED5[7];
elessair 0:f269e3021894 350 __IO uint8_t TER;
elessair 0:f269e3021894 351 uint8_t RESERVED6[39];
elessair 0:f269e3021894 352 __IO uint32_t FIFOLVL;
elessair 0:f269e3021894 353 } LPC_UART_TypeDef;
elessair 0:f269e3021894 354
elessair 0:f269e3021894 355 typedef struct
elessair 0:f269e3021894 356 {
elessair 0:f269e3021894 357 union {
elessair 0:f269e3021894 358 __I uint8_t RBR;
elessair 0:f269e3021894 359 __O uint8_t THR;
elessair 0:f269e3021894 360 __IO uint8_t DLL;
elessair 0:f269e3021894 361 uint32_t RESERVED0;
elessair 0:f269e3021894 362 };
elessair 0:f269e3021894 363 union {
elessair 0:f269e3021894 364 __IO uint8_t DLM;
elessair 0:f269e3021894 365 __IO uint32_t IER;
elessair 0:f269e3021894 366 };
elessair 0:f269e3021894 367 union {
elessair 0:f269e3021894 368 __I uint32_t IIR;
elessair 0:f269e3021894 369 __O uint8_t FCR;
elessair 0:f269e3021894 370 };
elessair 0:f269e3021894 371 __IO uint8_t LCR;
elessair 0:f269e3021894 372 uint8_t RESERVED1[7];
elessair 0:f269e3021894 373 __I uint8_t LSR;
elessair 0:f269e3021894 374 uint8_t RESERVED2[7];
elessair 0:f269e3021894 375 __IO uint8_t SCR;
elessair 0:f269e3021894 376 uint8_t RESERVED3[3];
elessair 0:f269e3021894 377 __IO uint32_t ACR;
elessair 0:f269e3021894 378 __IO uint8_t ICR;
elessair 0:f269e3021894 379 uint8_t RESERVED4[3];
elessair 0:f269e3021894 380 __IO uint8_t FDR;
elessair 0:f269e3021894 381 uint8_t RESERVED5[7];
elessair 0:f269e3021894 382 __IO uint8_t TER;
elessair 0:f269e3021894 383 uint8_t RESERVED6[39];
elessair 0:f269e3021894 384 __IO uint32_t FIFOLVL;
elessair 0:f269e3021894 385 } LPC_UART0_TypeDef;
elessair 0:f269e3021894 386
elessair 0:f269e3021894 387 typedef struct
elessair 0:f269e3021894 388 {
elessair 0:f269e3021894 389 union {
elessair 0:f269e3021894 390 __I uint8_t RBR;
elessair 0:f269e3021894 391 __O uint8_t THR;
elessair 0:f269e3021894 392 __IO uint8_t DLL;
elessair 0:f269e3021894 393 uint32_t RESERVED0;
elessair 0:f269e3021894 394 };
elessair 0:f269e3021894 395 union {
elessair 0:f269e3021894 396 __IO uint8_t DLM;
elessair 0:f269e3021894 397 __IO uint32_t IER;
elessair 0:f269e3021894 398 };
elessair 0:f269e3021894 399 union {
elessair 0:f269e3021894 400 __I uint32_t IIR;
elessair 0:f269e3021894 401 __O uint8_t FCR;
elessair 0:f269e3021894 402 };
elessair 0:f269e3021894 403 __IO uint8_t LCR;
elessair 0:f269e3021894 404 uint8_t RESERVED1[3];
elessair 0:f269e3021894 405 __IO uint8_t MCR;
elessair 0:f269e3021894 406 uint8_t RESERVED2[3];
elessair 0:f269e3021894 407 __I uint8_t LSR;
elessair 0:f269e3021894 408 uint8_t RESERVED3[3];
elessair 0:f269e3021894 409 __I uint8_t MSR;
elessair 0:f269e3021894 410 uint8_t RESERVED4[3];
elessair 0:f269e3021894 411 __IO uint8_t SCR;
elessair 0:f269e3021894 412 uint8_t RESERVED5[3];
elessair 0:f269e3021894 413 __IO uint32_t ACR;
elessair 0:f269e3021894 414 uint32_t RESERVED6;
elessair 0:f269e3021894 415 __IO uint32_t FDR;
elessair 0:f269e3021894 416 uint32_t RESERVED7;
elessair 0:f269e3021894 417 __IO uint8_t TER;
elessair 0:f269e3021894 418 uint8_t RESERVED8[27];
elessair 0:f269e3021894 419 __IO uint8_t RS485CTRL;
elessair 0:f269e3021894 420 uint8_t RESERVED9[3];
elessair 0:f269e3021894 421 __IO uint8_t ADRMATCH;
elessair 0:f269e3021894 422 uint8_t RESERVED10[3];
elessair 0:f269e3021894 423 __IO uint8_t RS485DLY;
elessair 0:f269e3021894 424 uint8_t RESERVED11[3];
elessair 0:f269e3021894 425 __IO uint32_t FIFOLVL;
elessair 0:f269e3021894 426 } LPC_UART1_TypeDef;
elessair 0:f269e3021894 427
elessair 0:f269e3021894 428 /*------------- Serial Peripheral Interface (SPI) ----------------------------*/
elessair 0:f269e3021894 429 typedef struct
elessair 0:f269e3021894 430 {
elessair 0:f269e3021894 431 __IO uint32_t SPCR;
elessair 0:f269e3021894 432 __I uint32_t SPSR;
elessair 0:f269e3021894 433 __IO uint32_t SPDR;
elessair 0:f269e3021894 434 __IO uint32_t SPCCR;
elessair 0:f269e3021894 435 uint32_t RESERVED0[3];
elessair 0:f269e3021894 436 __IO uint32_t SPINT;
elessair 0:f269e3021894 437 } LPC_SPI_TypeDef;
elessair 0:f269e3021894 438
elessair 0:f269e3021894 439 /*------------- Synchronous Serial Communication (SSP) -----------------------*/
elessair 0:f269e3021894 440 typedef struct
elessair 0:f269e3021894 441 {
elessair 0:f269e3021894 442 __IO uint32_t CR0;
elessair 0:f269e3021894 443 __IO uint32_t CR1;
elessair 0:f269e3021894 444 __IO uint32_t DR;
elessair 0:f269e3021894 445 __I uint32_t SR;
elessair 0:f269e3021894 446 __IO uint32_t CPSR;
elessair 0:f269e3021894 447 __IO uint32_t IMSC;
elessair 0:f269e3021894 448 __IO uint32_t RIS;
elessair 0:f269e3021894 449 __IO uint32_t MIS;
elessair 0:f269e3021894 450 __IO uint32_t ICR;
elessair 0:f269e3021894 451 __IO uint32_t DMACR;
elessair 0:f269e3021894 452 } LPC_SSP_TypeDef;
elessair 0:f269e3021894 453
elessair 0:f269e3021894 454 /*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
elessair 0:f269e3021894 455 typedef struct
elessair 0:f269e3021894 456 {
elessair 0:f269e3021894 457 __IO uint32_t I2CONSET;
elessair 0:f269e3021894 458 __I uint32_t I2STAT;
elessair 0:f269e3021894 459 __IO uint32_t I2DAT;
elessair 0:f269e3021894 460 __IO uint32_t I2ADR0;
elessair 0:f269e3021894 461 __IO uint32_t I2SCLH;
elessair 0:f269e3021894 462 __IO uint32_t I2SCLL;
elessair 0:f269e3021894 463 __O uint32_t I2CONCLR;
elessair 0:f269e3021894 464 __IO uint32_t MMCTRL;
elessair 0:f269e3021894 465 __IO uint32_t I2ADR1;
elessair 0:f269e3021894 466 __IO uint32_t I2ADR2;
elessair 0:f269e3021894 467 __IO uint32_t I2ADR3;
elessair 0:f269e3021894 468 __I uint32_t I2DATA_BUFFER;
elessair 0:f269e3021894 469 __IO uint32_t I2MASK0;
elessair 0:f269e3021894 470 __IO uint32_t I2MASK1;
elessair 0:f269e3021894 471 __IO uint32_t I2MASK2;
elessair 0:f269e3021894 472 __IO uint32_t I2MASK3;
elessair 0:f269e3021894 473 } LPC_I2C_TypeDef;
elessair 0:f269e3021894 474
elessair 0:f269e3021894 475 /*------------- Inter IC Sound (I2S) -----------------------------------------*/
elessair 0:f269e3021894 476 typedef struct
elessair 0:f269e3021894 477 {
elessair 0:f269e3021894 478 __IO uint32_t I2SDAO;
elessair 0:f269e3021894 479 __IO uint32_t I2SDAI;
elessair 0:f269e3021894 480 __O uint32_t I2STXFIFO;
elessair 0:f269e3021894 481 __I uint32_t I2SRXFIFO;
elessair 0:f269e3021894 482 __I uint32_t I2SSTATE;
elessair 0:f269e3021894 483 __IO uint32_t I2SDMA1;
elessair 0:f269e3021894 484 __IO uint32_t I2SDMA2;
elessair 0:f269e3021894 485 __IO uint32_t I2SIRQ;
elessair 0:f269e3021894 486 __IO uint32_t I2STXRATE;
elessair 0:f269e3021894 487 __IO uint32_t I2SRXRATE;
elessair 0:f269e3021894 488 __IO uint32_t I2STXBITRATE;
elessair 0:f269e3021894 489 __IO uint32_t I2SRXBITRATE;
elessair 0:f269e3021894 490 __IO uint32_t I2STXMODE;
elessair 0:f269e3021894 491 __IO uint32_t I2SRXMODE;
elessair 0:f269e3021894 492 } LPC_I2S_TypeDef;
elessair 0:f269e3021894 493
elessair 0:f269e3021894 494 /*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/
elessair 0:f269e3021894 495 typedef struct
elessair 0:f269e3021894 496 {
elessair 0:f269e3021894 497 __IO uint32_t RICOMPVAL;
elessair 0:f269e3021894 498 __IO uint32_t RIMASK;
elessair 0:f269e3021894 499 __IO uint8_t RICTRL;
elessair 0:f269e3021894 500 uint8_t RESERVED0[3];
elessair 0:f269e3021894 501 __IO uint32_t RICOUNTER;
elessair 0:f269e3021894 502 } LPC_RIT_TypeDef;
elessair 0:f269e3021894 503
elessair 0:f269e3021894 504 /*------------- Real-Time Clock (RTC) ----------------------------------------*/
elessair 0:f269e3021894 505 typedef struct
elessair 0:f269e3021894 506 {
elessair 0:f269e3021894 507 __IO uint8_t ILR;
elessair 0:f269e3021894 508 uint8_t RESERVED0[7];
elessair 0:f269e3021894 509 __IO uint8_t CCR;
elessair 0:f269e3021894 510 uint8_t RESERVED1[3];
elessair 0:f269e3021894 511 __IO uint8_t CIIR;
elessair 0:f269e3021894 512 uint8_t RESERVED2[3];
elessair 0:f269e3021894 513 __IO uint8_t AMR;
elessair 0:f269e3021894 514 uint8_t RESERVED3[3];
elessair 0:f269e3021894 515 __I uint32_t CTIME0;
elessair 0:f269e3021894 516 __I uint32_t CTIME1;
elessair 0:f269e3021894 517 __I uint32_t CTIME2;
elessair 0:f269e3021894 518 __IO uint8_t SEC;
elessair 0:f269e3021894 519 uint8_t RESERVED4[3];
elessair 0:f269e3021894 520 __IO uint8_t MIN;
elessair 0:f269e3021894 521 uint8_t RESERVED5[3];
elessair 0:f269e3021894 522 __IO uint8_t HOUR;
elessair 0:f269e3021894 523 uint8_t RESERVED6[3];
elessair 0:f269e3021894 524 __IO uint8_t DOM;
elessair 0:f269e3021894 525 uint8_t RESERVED7[3];
elessair 0:f269e3021894 526 __IO uint8_t DOW;
elessair 0:f269e3021894 527 uint8_t RESERVED8[3];
elessair 0:f269e3021894 528 __IO uint16_t DOY;
elessair 0:f269e3021894 529 uint16_t RESERVED9;
elessair 0:f269e3021894 530 __IO uint8_t MONTH;
elessair 0:f269e3021894 531 uint8_t RESERVED10[3];
elessair 0:f269e3021894 532 __IO uint16_t YEAR;
elessair 0:f269e3021894 533 uint16_t RESERVED11;
elessair 0:f269e3021894 534 __IO uint32_t CALIBRATION;
elessair 0:f269e3021894 535 __IO uint32_t GPREG0;
elessair 0:f269e3021894 536 __IO uint32_t GPREG1;
elessair 0:f269e3021894 537 __IO uint32_t GPREG2;
elessair 0:f269e3021894 538 __IO uint32_t GPREG3;
elessair 0:f269e3021894 539 __IO uint32_t GPREG4;
elessair 0:f269e3021894 540 __IO uint8_t RTC_AUXEN;
elessair 0:f269e3021894 541 uint8_t RESERVED12[3];
elessair 0:f269e3021894 542 __IO uint8_t RTC_AUX;
elessair 0:f269e3021894 543 uint8_t RESERVED13[3];
elessair 0:f269e3021894 544 __IO uint8_t ALSEC;
elessair 0:f269e3021894 545 uint8_t RESERVED14[3];
elessair 0:f269e3021894 546 __IO uint8_t ALMIN;
elessair 0:f269e3021894 547 uint8_t RESERVED15[3];
elessair 0:f269e3021894 548 __IO uint8_t ALHOUR;
elessair 0:f269e3021894 549 uint8_t RESERVED16[3];
elessair 0:f269e3021894 550 __IO uint8_t ALDOM;
elessair 0:f269e3021894 551 uint8_t RESERVED17[3];
elessair 0:f269e3021894 552 __IO uint8_t ALDOW;
elessair 0:f269e3021894 553 uint8_t RESERVED18[3];
elessair 0:f269e3021894 554 __IO uint16_t ALDOY;
elessair 0:f269e3021894 555 uint16_t RESERVED19;
elessair 0:f269e3021894 556 __IO uint8_t ALMON;
elessair 0:f269e3021894 557 uint8_t RESERVED20[3];
elessair 0:f269e3021894 558 __IO uint16_t ALYEAR;
elessair 0:f269e3021894 559 uint16_t RESERVED21;
elessair 0:f269e3021894 560 } LPC_RTC_TypeDef;
elessair 0:f269e3021894 561
elessair 0:f269e3021894 562 /*------------- Watchdog Timer (WDT) -----------------------------------------*/
elessair 0:f269e3021894 563 typedef struct
elessair 0:f269e3021894 564 {
elessair 0:f269e3021894 565 __IO uint8_t WDMOD;
elessair 0:f269e3021894 566 uint8_t RESERVED0[3];
elessair 0:f269e3021894 567 __IO uint32_t WDTC;
elessair 0:f269e3021894 568 __O uint8_t WDFEED;
elessair 0:f269e3021894 569 uint8_t RESERVED1[3];
elessair 0:f269e3021894 570 __I uint32_t WDTV;
elessair 0:f269e3021894 571 __IO uint32_t WDCLKSEL;
elessair 0:f269e3021894 572 } LPC_WDT_TypeDef;
elessair 0:f269e3021894 573
elessair 0:f269e3021894 574 /*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
elessair 0:f269e3021894 575 typedef struct
elessair 0:f269e3021894 576 {
elessair 0:f269e3021894 577 __IO uint32_t ADCR;
elessair 0:f269e3021894 578 __IO uint32_t ADGDR;
elessair 0:f269e3021894 579 uint32_t RESERVED0;
elessair 0:f269e3021894 580 __IO uint32_t ADINTEN;
elessair 0:f269e3021894 581 __I uint32_t ADDR0;
elessair 0:f269e3021894 582 __I uint32_t ADDR1;
elessair 0:f269e3021894 583 __I uint32_t ADDR2;
elessair 0:f269e3021894 584 __I uint32_t ADDR3;
elessair 0:f269e3021894 585 __I uint32_t ADDR4;
elessair 0:f269e3021894 586 __I uint32_t ADDR5;
elessair 0:f269e3021894 587 __I uint32_t ADDR6;
elessair 0:f269e3021894 588 __I uint32_t ADDR7;
elessair 0:f269e3021894 589 __I uint32_t ADSTAT;
elessair 0:f269e3021894 590 __IO uint32_t ADTRM;
elessair 0:f269e3021894 591 } LPC_ADC_TypeDef;
elessair 0:f269e3021894 592
elessair 0:f269e3021894 593 /*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
elessair 0:f269e3021894 594 typedef struct
elessair 0:f269e3021894 595 {
elessair 0:f269e3021894 596 __IO uint32_t DACR;
elessair 0:f269e3021894 597 __IO uint32_t DACCTRL;
elessair 0:f269e3021894 598 __IO uint16_t DACCNTVAL;
elessair 0:f269e3021894 599 } LPC_DAC_TypeDef;
elessair 0:f269e3021894 600
elessair 0:f269e3021894 601 /*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/
elessair 0:f269e3021894 602 typedef struct
elessair 0:f269e3021894 603 {
elessair 0:f269e3021894 604 __I uint32_t MCCON;
elessair 0:f269e3021894 605 __O uint32_t MCCON_SET;
elessair 0:f269e3021894 606 __O uint32_t MCCON_CLR;
elessair 0:f269e3021894 607 __I uint32_t MCCAPCON;
elessair 0:f269e3021894 608 __O uint32_t MCCAPCON_SET;
elessair 0:f269e3021894 609 __O uint32_t MCCAPCON_CLR;
elessair 0:f269e3021894 610 __IO uint32_t MCTIM0;
elessair 0:f269e3021894 611 __IO uint32_t MCTIM1;
elessair 0:f269e3021894 612 __IO uint32_t MCTIM2;
elessair 0:f269e3021894 613 __IO uint32_t MCPER0;
elessair 0:f269e3021894 614 __IO uint32_t MCPER1;
elessair 0:f269e3021894 615 __IO uint32_t MCPER2;
elessair 0:f269e3021894 616 __IO uint32_t MCPW0;
elessair 0:f269e3021894 617 __IO uint32_t MCPW1;
elessair 0:f269e3021894 618 __IO uint32_t MCPW2;
elessair 0:f269e3021894 619 __IO uint32_t MCDEADTIME;
elessair 0:f269e3021894 620 __IO uint32_t MCCCP;
elessair 0:f269e3021894 621 __IO uint32_t MCCR0;
elessair 0:f269e3021894 622 __IO uint32_t MCCR1;
elessair 0:f269e3021894 623 __IO uint32_t MCCR2;
elessair 0:f269e3021894 624 __I uint32_t MCINTEN;
elessair 0:f269e3021894 625 __O uint32_t MCINTEN_SET;
elessair 0:f269e3021894 626 __O uint32_t MCINTEN_CLR;
elessair 0:f269e3021894 627 __I uint32_t MCCNTCON;
elessair 0:f269e3021894 628 __O uint32_t MCCNTCON_SET;
elessair 0:f269e3021894 629 __O uint32_t MCCNTCON_CLR;
elessair 0:f269e3021894 630 __I uint32_t MCINTFLAG;
elessair 0:f269e3021894 631 __O uint32_t MCINTFLAG_SET;
elessair 0:f269e3021894 632 __O uint32_t MCINTFLAG_CLR;
elessair 0:f269e3021894 633 __O uint32_t MCCAP_CLR;
elessair 0:f269e3021894 634 } LPC_MCPWM_TypeDef;
elessair 0:f269e3021894 635
elessair 0:f269e3021894 636 /*------------- Quadrature Encoder Interface (QEI) ---------------------------*/
elessair 0:f269e3021894 637 typedef struct
elessair 0:f269e3021894 638 {
elessair 0:f269e3021894 639 __O uint32_t QEICON;
elessair 0:f269e3021894 640 __I uint32_t QEISTAT;
elessair 0:f269e3021894 641 __IO uint32_t QEICONF;
elessair 0:f269e3021894 642 __I uint32_t QEIPOS;
elessair 0:f269e3021894 643 __IO uint32_t QEIMAXPOS;
elessair 0:f269e3021894 644 __IO uint32_t CMPOS0;
elessair 0:f269e3021894 645 __IO uint32_t CMPOS1;
elessair 0:f269e3021894 646 __IO uint32_t CMPOS2;
elessair 0:f269e3021894 647 __I uint32_t INXCNT;
elessair 0:f269e3021894 648 __IO uint32_t INXCMP;
elessair 0:f269e3021894 649 __IO uint32_t QEILOAD;
elessair 0:f269e3021894 650 __I uint32_t QEITIME;
elessair 0:f269e3021894 651 __I uint32_t QEIVEL;
elessair 0:f269e3021894 652 __I uint32_t QEICAP;
elessair 0:f269e3021894 653 __IO uint32_t VELCOMP;
elessair 0:f269e3021894 654 __IO uint32_t FILTER;
elessair 0:f269e3021894 655 uint32_t RESERVED0[998];
elessair 0:f269e3021894 656 __O uint32_t QEIIEC;
elessair 0:f269e3021894 657 __O uint32_t QEIIES;
elessair 0:f269e3021894 658 __I uint32_t QEIINTSTAT;
elessair 0:f269e3021894 659 __I uint32_t QEIIE;
elessair 0:f269e3021894 660 __O uint32_t QEICLR;
elessair 0:f269e3021894 661 __O uint32_t QEISET;
elessair 0:f269e3021894 662 } LPC_QEI_TypeDef;
elessair 0:f269e3021894 663
elessair 0:f269e3021894 664 /*------------- Controller Area Network (CAN) --------------------------------*/
elessair 0:f269e3021894 665 typedef struct
elessair 0:f269e3021894 666 {
elessair 0:f269e3021894 667 __IO uint32_t mask[512]; /* ID Masks */
elessair 0:f269e3021894 668 } LPC_CANAF_RAM_TypeDef;
elessair 0:f269e3021894 669
elessair 0:f269e3021894 670 typedef struct /* Acceptance Filter Registers */
elessair 0:f269e3021894 671 {
elessair 0:f269e3021894 672 __IO uint32_t AFMR;
elessair 0:f269e3021894 673 __IO uint32_t SFF_sa;
elessair 0:f269e3021894 674 __IO uint32_t SFF_GRP_sa;
elessair 0:f269e3021894 675 __IO uint32_t EFF_sa;
elessair 0:f269e3021894 676 __IO uint32_t EFF_GRP_sa;
elessair 0:f269e3021894 677 __IO uint32_t ENDofTable;
elessair 0:f269e3021894 678 __I uint32_t LUTerrAd;
elessair 0:f269e3021894 679 __I uint32_t LUTerr;
elessair 0:f269e3021894 680 __IO uint32_t FCANIE;
elessair 0:f269e3021894 681 __IO uint32_t FCANIC0;
elessair 0:f269e3021894 682 __IO uint32_t FCANIC1;
elessair 0:f269e3021894 683 } LPC_CANAF_TypeDef;
elessair 0:f269e3021894 684
elessair 0:f269e3021894 685 typedef struct /* Central Registers */
elessair 0:f269e3021894 686 {
elessair 0:f269e3021894 687 __I uint32_t CANTxSR;
elessair 0:f269e3021894 688 __I uint32_t CANRxSR;
elessair 0:f269e3021894 689 __I uint32_t CANMSR;
elessair 0:f269e3021894 690 } LPC_CANCR_TypeDef;
elessair 0:f269e3021894 691
elessair 0:f269e3021894 692 typedef struct /* Controller Registers */
elessair 0:f269e3021894 693 {
elessair 0:f269e3021894 694 __IO uint32_t MOD;
elessair 0:f269e3021894 695 __O uint32_t CMR;
elessair 0:f269e3021894 696 __IO uint32_t GSR;
elessair 0:f269e3021894 697 __I uint32_t ICR;
elessair 0:f269e3021894 698 __IO uint32_t IER;
elessair 0:f269e3021894 699 __IO uint32_t BTR;
elessair 0:f269e3021894 700 __IO uint32_t EWL;
elessair 0:f269e3021894 701 __I uint32_t SR;
elessair 0:f269e3021894 702 __IO uint32_t RFS;
elessair 0:f269e3021894 703 __IO uint32_t RID;
elessair 0:f269e3021894 704 __IO uint32_t RDA;
elessair 0:f269e3021894 705 __IO uint32_t RDB;
elessair 0:f269e3021894 706 __IO uint32_t TFI1;
elessair 0:f269e3021894 707 __IO uint32_t TID1;
elessair 0:f269e3021894 708 __IO uint32_t TDA1;
elessair 0:f269e3021894 709 __IO uint32_t TDB1;
elessair 0:f269e3021894 710 __IO uint32_t TFI2;
elessair 0:f269e3021894 711 __IO uint32_t TID2;
elessair 0:f269e3021894 712 __IO uint32_t TDA2;
elessair 0:f269e3021894 713 __IO uint32_t TDB2;
elessair 0:f269e3021894 714 __IO uint32_t TFI3;
elessair 0:f269e3021894 715 __IO uint32_t TID3;
elessair 0:f269e3021894 716 __IO uint32_t TDA3;
elessair 0:f269e3021894 717 __IO uint32_t TDB3;
elessair 0:f269e3021894 718 } LPC_CAN_TypeDef;
elessair 0:f269e3021894 719
elessair 0:f269e3021894 720 /*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
elessair 0:f269e3021894 721 typedef struct /* Common Registers */
elessair 0:f269e3021894 722 {
elessair 0:f269e3021894 723 __I uint32_t DMACIntStat;
elessair 0:f269e3021894 724 __I uint32_t DMACIntTCStat;
elessair 0:f269e3021894 725 __O uint32_t DMACIntTCClear;
elessair 0:f269e3021894 726 __I uint32_t DMACIntErrStat;
elessair 0:f269e3021894 727 __O uint32_t DMACIntErrClr;
elessair 0:f269e3021894 728 __I uint32_t DMACRawIntTCStat;
elessair 0:f269e3021894 729 __I uint32_t DMACRawIntErrStat;
elessair 0:f269e3021894 730 __I uint32_t DMACEnbldChns;
elessair 0:f269e3021894 731 __IO uint32_t DMACSoftBReq;
elessair 0:f269e3021894 732 __IO uint32_t DMACSoftSReq;
elessair 0:f269e3021894 733 __IO uint32_t DMACSoftLBReq;
elessair 0:f269e3021894 734 __IO uint32_t DMACSoftLSReq;
elessair 0:f269e3021894 735 __IO uint32_t DMACConfig;
elessair 0:f269e3021894 736 __IO uint32_t DMACSync;
elessair 0:f269e3021894 737 } LPC_GPDMA_TypeDef;
elessair 0:f269e3021894 738
elessair 0:f269e3021894 739 typedef struct /* Channel Registers */
elessair 0:f269e3021894 740 {
elessair 0:f269e3021894 741 __IO uint32_t DMACCSrcAddr;
elessair 0:f269e3021894 742 __IO uint32_t DMACCDestAddr;
elessair 0:f269e3021894 743 __IO uint32_t DMACCLLI;
elessair 0:f269e3021894 744 __IO uint32_t DMACCControl;
elessair 0:f269e3021894 745 __IO uint32_t DMACCConfig;
elessair 0:f269e3021894 746 } LPC_GPDMACH_TypeDef;
elessair 0:f269e3021894 747
elessair 0:f269e3021894 748 /*------------- Universal Serial Bus (USB) -----------------------------------*/
elessair 0:f269e3021894 749 typedef struct
elessair 0:f269e3021894 750 {
elessair 0:f269e3021894 751 __I uint32_t HcRevision; /* USB Host Registers */
elessair 0:f269e3021894 752 __IO uint32_t HcControl;
elessair 0:f269e3021894 753 __IO uint32_t HcCommandStatus;
elessair 0:f269e3021894 754 __IO uint32_t HcInterruptStatus;
elessair 0:f269e3021894 755 __IO uint32_t HcInterruptEnable;
elessair 0:f269e3021894 756 __IO uint32_t HcInterruptDisable;
elessair 0:f269e3021894 757 __IO uint32_t HcHCCA;
elessair 0:f269e3021894 758 __I uint32_t HcPeriodCurrentED;
elessair 0:f269e3021894 759 __IO uint32_t HcControlHeadED;
elessair 0:f269e3021894 760 __IO uint32_t HcControlCurrentED;
elessair 0:f269e3021894 761 __IO uint32_t HcBulkHeadED;
elessair 0:f269e3021894 762 __IO uint32_t HcBulkCurrentED;
elessair 0:f269e3021894 763 __I uint32_t HcDoneHead;
elessair 0:f269e3021894 764 __IO uint32_t HcFmInterval;
elessair 0:f269e3021894 765 __I uint32_t HcFmRemaining;
elessair 0:f269e3021894 766 __I uint32_t HcFmNumber;
elessair 0:f269e3021894 767 __IO uint32_t HcPeriodicStart;
elessair 0:f269e3021894 768 __IO uint32_t HcLSTreshold;
elessair 0:f269e3021894 769 __IO uint32_t HcRhDescriptorA;
elessair 0:f269e3021894 770 __IO uint32_t HcRhDescriptorB;
elessair 0:f269e3021894 771 __IO uint32_t HcRhStatus;
elessair 0:f269e3021894 772 __IO uint32_t HcRhPortStatus1;
elessair 0:f269e3021894 773 __IO uint32_t HcRhPortStatus2;
elessair 0:f269e3021894 774 uint32_t RESERVED0[40];
elessair 0:f269e3021894 775 __I uint32_t Module_ID;
elessair 0:f269e3021894 776
elessair 0:f269e3021894 777 __I uint32_t OTGIntSt; /* USB On-The-Go Registers */
elessair 0:f269e3021894 778 __IO uint32_t OTGIntEn;
elessair 0:f269e3021894 779 __O uint32_t OTGIntSet;
elessair 0:f269e3021894 780 __O uint32_t OTGIntClr;
elessair 0:f269e3021894 781 __IO uint32_t OTGStCtrl;
elessair 0:f269e3021894 782 __IO uint32_t OTGTmr;
elessair 0:f269e3021894 783 uint32_t RESERVED1[58];
elessair 0:f269e3021894 784
elessair 0:f269e3021894 785 __I uint32_t USBDevIntSt; /* USB Device Interrupt Registers */
elessair 0:f269e3021894 786 __IO uint32_t USBDevIntEn;
elessair 0:f269e3021894 787 __O uint32_t USBDevIntClr;
elessair 0:f269e3021894 788 __O uint32_t USBDevIntSet;
elessair 0:f269e3021894 789
elessair 0:f269e3021894 790 __O uint32_t USBCmdCode; /* USB Device SIE Command Registers */
elessair 0:f269e3021894 791 __I uint32_t USBCmdData;
elessair 0:f269e3021894 792
elessair 0:f269e3021894 793 __I uint32_t USBRxData; /* USB Device Transfer Registers */
elessair 0:f269e3021894 794 __O uint32_t USBTxData;
elessair 0:f269e3021894 795 __I uint32_t USBRxPLen;
elessair 0:f269e3021894 796 __O uint32_t USBTxPLen;
elessair 0:f269e3021894 797 __IO uint32_t USBCtrl;
elessair 0:f269e3021894 798 __O uint32_t USBDevIntPri;
elessair 0:f269e3021894 799
elessair 0:f269e3021894 800 __I uint32_t USBEpIntSt; /* USB Device Endpoint Interrupt Regs */
elessair 0:f269e3021894 801 __IO uint32_t USBEpIntEn;
elessair 0:f269e3021894 802 __O uint32_t USBEpIntClr;
elessair 0:f269e3021894 803 __O uint32_t USBEpIntSet;
elessair 0:f269e3021894 804 __O uint32_t USBEpIntPri;
elessair 0:f269e3021894 805
elessair 0:f269e3021894 806 __IO uint32_t USBReEp; /* USB Device Endpoint Realization Reg*/
elessair 0:f269e3021894 807 __O uint32_t USBEpInd;
elessair 0:f269e3021894 808 __IO uint32_t USBMaxPSize;
elessair 0:f269e3021894 809
elessair 0:f269e3021894 810 __I uint32_t USBDMARSt; /* USB Device DMA Registers */
elessair 0:f269e3021894 811 __O uint32_t USBDMARClr;
elessair 0:f269e3021894 812 __O uint32_t USBDMARSet;
elessair 0:f269e3021894 813 uint32_t RESERVED2[9];
elessair 0:f269e3021894 814 __IO uint32_t USBUDCAH;
elessair 0:f269e3021894 815 __I uint32_t USBEpDMASt;
elessair 0:f269e3021894 816 __O uint32_t USBEpDMAEn;
elessair 0:f269e3021894 817 __O uint32_t USBEpDMADis;
elessair 0:f269e3021894 818 __I uint32_t USBDMAIntSt;
elessair 0:f269e3021894 819 __IO uint32_t USBDMAIntEn;
elessair 0:f269e3021894 820 uint32_t RESERVED3[2];
elessair 0:f269e3021894 821 __I uint32_t USBEoTIntSt;
elessair 0:f269e3021894 822 __O uint32_t USBEoTIntClr;
elessair 0:f269e3021894 823 __O uint32_t USBEoTIntSet;
elessair 0:f269e3021894 824 __I uint32_t USBNDDRIntSt;
elessair 0:f269e3021894 825 __O uint32_t USBNDDRIntClr;
elessair 0:f269e3021894 826 __O uint32_t USBNDDRIntSet;
elessair 0:f269e3021894 827 __I uint32_t USBSysErrIntSt;
elessair 0:f269e3021894 828 __O uint32_t USBSysErrIntClr;
elessair 0:f269e3021894 829 __O uint32_t USBSysErrIntSet;
elessair 0:f269e3021894 830 uint32_t RESERVED4[15];
elessair 0:f269e3021894 831
elessair 0:f269e3021894 832 union {
elessair 0:f269e3021894 833 __I uint32_t I2C_RX; /* USB OTG I2C Registers */
elessair 0:f269e3021894 834 __O uint32_t I2C_TX;
elessair 0:f269e3021894 835 };
elessair 0:f269e3021894 836 __I uint32_t I2C_STS;
elessair 0:f269e3021894 837 __IO uint32_t I2C_CTL;
elessair 0:f269e3021894 838 __IO uint32_t I2C_CLKHI;
elessair 0:f269e3021894 839 __O uint32_t I2C_CLKLO;
elessair 0:f269e3021894 840 uint32_t RESERVED5[824];
elessair 0:f269e3021894 841
elessair 0:f269e3021894 842 union {
elessair 0:f269e3021894 843 __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */
elessair 0:f269e3021894 844 __IO uint32_t OTGClkCtrl;
elessair 0:f269e3021894 845 };
elessair 0:f269e3021894 846 union {
elessair 0:f269e3021894 847 __I uint32_t USBClkSt;
elessair 0:f269e3021894 848 __I uint32_t OTGClkSt;
elessair 0:f269e3021894 849 };
elessair 0:f269e3021894 850 } LPC_USB_TypeDef;
elessair 0:f269e3021894 851
elessair 0:f269e3021894 852 /*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
elessair 0:f269e3021894 853 typedef struct
elessair 0:f269e3021894 854 {
elessair 0:f269e3021894 855 __IO uint32_t MAC1; /* MAC Registers */
elessair 0:f269e3021894 856 __IO uint32_t MAC2;
elessair 0:f269e3021894 857 __IO uint32_t IPGT;
elessair 0:f269e3021894 858 __IO uint32_t IPGR;
elessair 0:f269e3021894 859 __IO uint32_t CLRT;
elessair 0:f269e3021894 860 __IO uint32_t MAXF;
elessair 0:f269e3021894 861 __IO uint32_t SUPP;
elessair 0:f269e3021894 862 __IO uint32_t TEST;
elessair 0:f269e3021894 863 __IO uint32_t MCFG;
elessair 0:f269e3021894 864 __IO uint32_t MCMD;
elessair 0:f269e3021894 865 __IO uint32_t MADR;
elessair 0:f269e3021894 866 __O uint32_t MWTD;
elessair 0:f269e3021894 867 __I uint32_t MRDD;
elessair 0:f269e3021894 868 __I uint32_t MIND;
elessair 0:f269e3021894 869 uint32_t RESERVED0[2];
elessair 0:f269e3021894 870 __IO uint32_t SA0;
elessair 0:f269e3021894 871 __IO uint32_t SA1;
elessair 0:f269e3021894 872 __IO uint32_t SA2;
elessair 0:f269e3021894 873 uint32_t RESERVED1[45];
elessair 0:f269e3021894 874 __IO uint32_t Command; /* Control Registers */
elessair 0:f269e3021894 875 __I uint32_t Status;
elessair 0:f269e3021894 876 __IO uint32_t RxDescriptor;
elessair 0:f269e3021894 877 __IO uint32_t RxStatus;
elessair 0:f269e3021894 878 __IO uint32_t RxDescriptorNumber;
elessair 0:f269e3021894 879 __I uint32_t RxProduceIndex;
elessair 0:f269e3021894 880 __IO uint32_t RxConsumeIndex;
elessair 0:f269e3021894 881 __IO uint32_t TxDescriptor;
elessair 0:f269e3021894 882 __IO uint32_t TxStatus;
elessair 0:f269e3021894 883 __IO uint32_t TxDescriptorNumber;
elessair 0:f269e3021894 884 __IO uint32_t TxProduceIndex;
elessair 0:f269e3021894 885 __I uint32_t TxConsumeIndex;
elessair 0:f269e3021894 886 uint32_t RESERVED2[10];
elessair 0:f269e3021894 887 __I uint32_t TSV0;
elessair 0:f269e3021894 888 __I uint32_t TSV1;
elessair 0:f269e3021894 889 __I uint32_t RSV;
elessair 0:f269e3021894 890 uint32_t RESERVED3[3];
elessair 0:f269e3021894 891 __IO uint32_t FlowControlCounter;
elessair 0:f269e3021894 892 __I uint32_t FlowControlStatus;
elessair 0:f269e3021894 893 uint32_t RESERVED4[34];
elessair 0:f269e3021894 894 __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */
elessair 0:f269e3021894 895 __IO uint32_t RxFilterWoLStatus;
elessair 0:f269e3021894 896 __IO uint32_t RxFilterWoLClear;
elessair 0:f269e3021894 897 uint32_t RESERVED5;
elessair 0:f269e3021894 898 __IO uint32_t HashFilterL;
elessair 0:f269e3021894 899 __IO uint32_t HashFilterH;
elessair 0:f269e3021894 900 uint32_t RESERVED6[882];
elessair 0:f269e3021894 901 __I uint32_t IntStatus; /* Module Control Registers */
elessair 0:f269e3021894 902 __IO uint32_t IntEnable;
elessair 0:f269e3021894 903 __O uint32_t IntClear;
elessair 0:f269e3021894 904 __O uint32_t IntSet;
elessair 0:f269e3021894 905 uint32_t RESERVED7;
elessair 0:f269e3021894 906 __IO uint32_t PowerDown;
elessair 0:f269e3021894 907 uint32_t RESERVED8;
elessair 0:f269e3021894 908 __IO uint32_t Module_ID;
elessair 0:f269e3021894 909 } LPC_EMAC_TypeDef;
elessair 0:f269e3021894 910
elessair 0:f269e3021894 911 #if defined ( __CC_ARM )
elessair 0:f269e3021894 912 #pragma no_anon_unions
elessair 0:f269e3021894 913 #endif
elessair 0:f269e3021894 914
elessair 0:f269e3021894 915
elessair 0:f269e3021894 916 /******************************************************************************/
elessair 0:f269e3021894 917 /* Peripheral memory map */
elessair 0:f269e3021894 918 /******************************************************************************/
elessair 0:f269e3021894 919 /* Base addresses */
elessair 0:f269e3021894 920 #define LPC_FLASH_BASE (0x00000000UL)
elessair 0:f269e3021894 921 #define LPC_RAM_BASE (0x10000000UL)
elessair 0:f269e3021894 922 #define LPC_GPIO_BASE (0x2009C000UL)
elessair 0:f269e3021894 923 #define LPC_APB0_BASE (0x40000000UL)
elessair 0:f269e3021894 924 #define LPC_APB1_BASE (0x40080000UL)
elessair 0:f269e3021894 925 #define LPC_AHB_BASE (0x50000000UL)
elessair 0:f269e3021894 926 #define LPC_CM3_BASE (0xE0000000UL)
elessair 0:f269e3021894 927
elessair 0:f269e3021894 928 /* APB0 peripherals */
elessair 0:f269e3021894 929 #define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000)
elessair 0:f269e3021894 930 #define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000)
elessair 0:f269e3021894 931 #define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000)
elessair 0:f269e3021894 932 #define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000)
elessair 0:f269e3021894 933 #define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000)
elessair 0:f269e3021894 934 #define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000)
elessair 0:f269e3021894 935 #define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000)
elessair 0:f269e3021894 936 #define LPC_SPI_BASE (LPC_APB0_BASE + 0x20000)
elessair 0:f269e3021894 937 #define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000)
elessair 0:f269e3021894 938 #define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080)
elessair 0:f269e3021894 939 #define LPC_PINCON_BASE (LPC_APB0_BASE + 0x2C000)
elessair 0:f269e3021894 940 #define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000)
elessair 0:f269e3021894 941 #define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000)
elessair 0:f269e3021894 942 #define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000)
elessair 0:f269e3021894 943 #define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000)
elessair 0:f269e3021894 944 #define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000)
elessair 0:f269e3021894 945 #define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000)
elessair 0:f269e3021894 946 #define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000)
elessair 0:f269e3021894 947 #define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000)
elessair 0:f269e3021894 948
elessair 0:f269e3021894 949 /* APB1 peripherals */
elessair 0:f269e3021894 950 #define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000)
elessair 0:f269e3021894 951 #define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000)
elessair 0:f269e3021894 952 #define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000)
elessair 0:f269e3021894 953 #define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000)
elessair 0:f269e3021894 954 #define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000)
elessair 0:f269e3021894 955 #define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000)
elessair 0:f269e3021894 956 #define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000)
elessair 0:f269e3021894 957 #define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000)
elessair 0:f269e3021894 958 #define LPC_RIT_BASE (LPC_APB1_BASE + 0x30000)
elessair 0:f269e3021894 959 #define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000)
elessair 0:f269e3021894 960 #define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000)
elessair 0:f269e3021894 961 #define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000)
elessair 0:f269e3021894 962
elessair 0:f269e3021894 963 /* AHB peripherals */
elessair 0:f269e3021894 964 #define LPC_EMAC_BASE (LPC_AHB_BASE + 0x00000)
elessair 0:f269e3021894 965 #define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x04000)
elessair 0:f269e3021894 966 #define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x04100)
elessair 0:f269e3021894 967 #define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x04120)
elessair 0:f269e3021894 968 #define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x04140)
elessair 0:f269e3021894 969 #define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x04160)
elessair 0:f269e3021894 970 #define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x04180)
elessair 0:f269e3021894 971 #define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x041A0)
elessair 0:f269e3021894 972 #define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x041C0)
elessair 0:f269e3021894 973 #define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x041E0)
elessair 0:f269e3021894 974 #define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000)
elessair 0:f269e3021894 975
elessair 0:f269e3021894 976 /* GPIOs */
elessair 0:f269e3021894 977 #define LPC_GPIO0_BASE (LPC_GPIO_BASE + 0x00000)
elessair 0:f269e3021894 978 #define LPC_GPIO1_BASE (LPC_GPIO_BASE + 0x00020)
elessair 0:f269e3021894 979 #define LPC_GPIO2_BASE (LPC_GPIO_BASE + 0x00040)
elessair 0:f269e3021894 980 #define LPC_GPIO3_BASE (LPC_GPIO_BASE + 0x00060)
elessair 0:f269e3021894 981 #define LPC_GPIO4_BASE (LPC_GPIO_BASE + 0x00080)
elessair 0:f269e3021894 982
elessair 0:f269e3021894 983
elessair 0:f269e3021894 984 /******************************************************************************/
elessair 0:f269e3021894 985 /* Peripheral declaration */
elessair 0:f269e3021894 986 /******************************************************************************/
elessair 0:f269e3021894 987 #define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE )
elessair 0:f269e3021894 988 #define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE )
elessair 0:f269e3021894 989 #define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE )
elessair 0:f269e3021894 990 #define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE )
elessair 0:f269e3021894 991 #define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE )
elessair 0:f269e3021894 992 #define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE )
elessair 0:f269e3021894 993 #define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE )
elessair 0:f269e3021894 994 #define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE )
elessair 0:f269e3021894 995 #define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE )
elessair 0:f269e3021894 996 #define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE )
elessair 0:f269e3021894 997 #define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE )
elessair 0:f269e3021894 998 #define LPC_RIT ((LPC_RIT_TypeDef *) LPC_RIT_BASE )
elessair 0:f269e3021894 999 #define LPC_UART0 ((LPC_UART0_TypeDef *) LPC_UART0_BASE )
elessair 0:f269e3021894 1000 #define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE )
elessair 0:f269e3021894 1001 #define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE )
elessair 0:f269e3021894 1002 #define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE )
elessair 0:f269e3021894 1003 #define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE )
elessair 0:f269e3021894 1004 #define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE )
elessair 0:f269e3021894 1005 #define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE )
elessair 0:f269e3021894 1006 #define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE )
elessair 0:f269e3021894 1007 #define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE )
elessair 0:f269e3021894 1008 #define LPC_SPI ((LPC_SPI_TypeDef *) LPC_SPI_BASE )
elessair 0:f269e3021894 1009 #define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE )
elessair 0:f269e3021894 1010 #define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE )
elessair 0:f269e3021894 1011 #define LPC_PINCON ((LPC_PINCON_TypeDef *) LPC_PINCON_BASE )
elessair 0:f269e3021894 1012 #define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE )
elessair 0:f269e3021894 1013 #define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE )
elessair 0:f269e3021894 1014 #define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE )
elessair 0:f269e3021894 1015 #define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE )
elessair 0:f269e3021894 1016 #define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
elessair 0:f269e3021894 1017 #define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE )
elessair 0:f269e3021894 1018 #define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE )
elessair 0:f269e3021894 1019 #define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE )
elessair 0:f269e3021894 1020 #define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE )
elessair 0:f269e3021894 1021 #define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE )
elessair 0:f269e3021894 1022 #define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE )
elessair 0:f269e3021894 1023 #define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE )
elessair 0:f269e3021894 1024 #define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE )
elessair 0:f269e3021894 1025 #define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE )
elessair 0:f269e3021894 1026 #define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE )
elessair 0:f269e3021894 1027 #define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE )
elessair 0:f269e3021894 1028 #define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE )
elessair 0:f269e3021894 1029 #define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE )
elessair 0:f269e3021894 1030 #define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE )
elessair 0:f269e3021894 1031 #define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE )
elessair 0:f269e3021894 1032 #define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE )
elessair 0:f269e3021894 1033 #define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE )
elessair 0:f269e3021894 1034
elessair 0:f269e3021894 1035 #endif // __LPC17xx_H__