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targets/TARGET_NUVOTON/TARGET_NUC472/serial_api.c@0:f269e3021894, 2016-10-23 (annotated)

Committer:
elessair
Date:
Sun Oct 23 15:10:02 2016 +0000
Revision:
0:f269e3021894
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
elessair 0:f269e3021894 1 /* mbed Microcontroller Library
elessair 0:f269e3021894 2 * Copyright (c) 2015-2016 Nuvoton
elessair 0:f269e3021894 3 *
elessair 0:f269e3021894 4 * Licensed under the Apache License, Version 2.0 (the "License");
elessair 0:f269e3021894 5 * you may not use this file except in compliance with the License.
elessair 0:f269e3021894 6 * You may obtain a copy of the License at
elessair 0:f269e3021894 7 *
elessair 0:f269e3021894 8 * http://www.apache.org/licenses/LICENSE-2.0
elessair 0:f269e3021894 9 *
elessair 0:f269e3021894 10 * Unless required by applicable law or agreed to in writing, software
elessair 0:f269e3021894 11 * distributed under the License is distributed on an "AS IS" BASIS,
elessair 0:f269e3021894 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
elessair 0:f269e3021894 13 * See the License for the specific language governing permissions and
elessair 0:f269e3021894 14 * limitations under the License.
elessair 0:f269e3021894 15 */
elessair 0:f269e3021894 16
elessair 0:f269e3021894 17 #include "serial_api.h"
elessair 0:f269e3021894 18
elessair 0:f269e3021894 19 #if DEVICE_SERIAL
elessair 0:f269e3021894 20
elessair 0:f269e3021894 21 #include "cmsis.h"
elessair 0:f269e3021894 22 #include "mbed_error.h"
elessair 0:f269e3021894 23 #include "mbed_assert.h"
elessair 0:f269e3021894 24 #include "PeripheralPins.h"
elessair 0:f269e3021894 25 #include "nu_modutil.h"
elessair 0:f269e3021894 26 #include "nu_bitutil.h"
elessair 0:f269e3021894 27
elessair 0:f269e3021894 28 #if DEVICE_SERIAL_ASYNCH
elessair 0:f269e3021894 29 #include "dma_api.h"
elessair 0:f269e3021894 30 #include "dma.h"
elessair 0:f269e3021894 31 #endif
elessair 0:f269e3021894 32
elessair 0:f269e3021894 33 struct nu_uart_var {
elessair 0:f269e3021894 34 serial_t * obj;
elessair 0:f269e3021894 35 uint32_t fifo_size_tx;
elessair 0:f269e3021894 36 uint32_t fifo_size_rx;
elessair 0:f269e3021894 37 void (*vec)(void);
elessair 0:f269e3021894 38 #if DEVICE_SERIAL_ASYNCH
elessair 0:f269e3021894 39 void (*vec_async)(void);
elessair 0:f269e3021894 40 uint8_t pdma_perp_tx;
elessair 0:f269e3021894 41 uint8_t pdma_perp_rx;
elessair 0:f269e3021894 42 #endif
elessair 0:f269e3021894 43 };
elessair 0:f269e3021894 44
elessair 0:f269e3021894 45 static void uart0_vec(void);
elessair 0:f269e3021894 46 static void uart1_vec(void);
elessair 0:f269e3021894 47 static void uart2_vec(void);
elessair 0:f269e3021894 48 static void uart3_vec(void);
elessair 0:f269e3021894 49 static void uart4_vec(void);
elessair 0:f269e3021894 50 static void uart5_vec(void);
elessair 0:f269e3021894 51 static void uart_irq(serial_t *obj);
elessair 0:f269e3021894 52
elessair 0:f269e3021894 53 #if DEVICE_SERIAL_ASYNCH
elessair 0:f269e3021894 54 static void uart0_vec_async(void);
elessair 0:f269e3021894 55 static void uart1_vec_async(void);
elessair 0:f269e3021894 56 static void uart2_vec_async(void);
elessair 0:f269e3021894 57 static void uart3_vec_async(void);
elessair 0:f269e3021894 58 static void uart4_vec_async(void);
elessair 0:f269e3021894 59 static void uart5_vec_async(void);
elessair 0:f269e3021894 60 static void uart_irq_async(serial_t *obj);
elessair 0:f269e3021894 61
elessair 0:f269e3021894 62 static void uart_dma_handler_tx(uint32_t id, uint32_t event);
elessair 0:f269e3021894 63 static void uart_dma_handler_rx(uint32_t id, uint32_t event);
elessair 0:f269e3021894 64
elessair 0:f269e3021894 65 static void serial_tx_enable_interrupt(serial_t *obj, uint32_t address, uint8_t enable);
elessair 0:f269e3021894 66 static void serial_rx_enable_interrupt(serial_t *obj, uint32_t address, uint8_t enable);
elessair 0:f269e3021894 67 static int serial_write_async(serial_t *obj);
elessair 0:f269e3021894 68 static int serial_read_async(serial_t *obj);
elessair 0:f269e3021894 69
elessair 0:f269e3021894 70 static uint32_t serial_rx_event_check(serial_t *obj);
elessair 0:f269e3021894 71 static uint32_t serial_tx_event_check(serial_t *obj);
elessair 0:f269e3021894 72
elessair 0:f269e3021894 73 static int serial_is_tx_complete(serial_t *obj);
elessair 0:f269e3021894 74 static void serial_tx_enable_event(serial_t *obj, int event, uint8_t enable);
elessair 0:f269e3021894 75
elessair 0:f269e3021894 76 static void serial_tx_buffer_set(serial_t *obj, const void *tx, size_t length, uint8_t width);
elessair 0:f269e3021894 77 static void serial_rx_buffer_set(serial_t *obj, void *rx, size_t length, uint8_t width);
elessair 0:f269e3021894 78 static void serial_rx_set_char_match(serial_t *obj, uint8_t char_match);
elessair 0:f269e3021894 79 static void serial_rx_enable_event(serial_t *obj, int event, uint8_t enable);
elessair 0:f269e3021894 80 static int serial_is_rx_complete(serial_t *obj);
elessair 0:f269e3021894 81
elessair 0:f269e3021894 82 static void serial_check_dma_usage(DMAUsage *dma_usage, int *dma_ch);
elessair 0:f269e3021894 83 static int serial_is_irq_en(serial_t *obj, SerialIrq irq);
elessair 0:f269e3021894 84 #endif
elessair 0:f269e3021894 85
elessair 0:f269e3021894 86 static struct nu_uart_var uart0_var = {
elessair 0:f269e3021894 87 .obj = NULL,
elessair 0:f269e3021894 88 .fifo_size_tx = 64,
elessair 0:f269e3021894 89 .fifo_size_rx = 64,
elessair 0:f269e3021894 90 .vec = uart0_vec,
elessair 0:f269e3021894 91 #if DEVICE_SERIAL_ASYNCH
elessair 0:f269e3021894 92 .vec_async = uart0_vec_async,
elessair 0:f269e3021894 93 .pdma_perp_tx = PDMA_UART0_TX,
elessair 0:f269e3021894 94 .pdma_perp_rx = PDMA_UART0_RX
elessair 0:f269e3021894 95 #endif
elessair 0:f269e3021894 96 };
elessair 0:f269e3021894 97 static struct nu_uart_var uart1_var = {
elessair 0:f269e3021894 98 .obj = NULL,
elessair 0:f269e3021894 99 .fifo_size_tx = 16,
elessair 0:f269e3021894 100 .fifo_size_rx = 16,
elessair 0:f269e3021894 101 .vec = uart1_vec,
elessair 0:f269e3021894 102 #if DEVICE_SERIAL_ASYNCH
elessair 0:f269e3021894 103 .vec_async = uart1_vec_async,
elessair 0:f269e3021894 104 .pdma_perp_tx = PDMA_UART1_TX,
elessair 0:f269e3021894 105 .pdma_perp_rx = PDMA_UART1_RX
elessair 0:f269e3021894 106 #endif
elessair 0:f269e3021894 107 };
elessair 0:f269e3021894 108 static struct nu_uart_var uart2_var = {
elessair 0:f269e3021894 109 .obj = NULL,
elessair 0:f269e3021894 110 .fifo_size_tx = 16,
elessair 0:f269e3021894 111 .fifo_size_rx = 16,
elessair 0:f269e3021894 112 .vec = uart2_vec,
elessair 0:f269e3021894 113 #if DEVICE_SERIAL_ASYNCH
elessair 0:f269e3021894 114 .vec_async = uart2_vec_async,
elessair 0:f269e3021894 115 .pdma_perp_tx = PDMA_UART2_TX,
elessair 0:f269e3021894 116 .pdma_perp_rx = PDMA_UART2_RX
elessair 0:f269e3021894 117 #endif
elessair 0:f269e3021894 118 };
elessair 0:f269e3021894 119 static struct nu_uart_var uart3_var = {
elessair 0:f269e3021894 120 .obj = NULL,
elessair 0:f269e3021894 121 .fifo_size_tx = 16,
elessair 0:f269e3021894 122 .fifo_size_rx = 16,
elessair 0:f269e3021894 123 .vec = uart3_vec,
elessair 0:f269e3021894 124 #if DEVICE_SERIAL_ASYNCH
elessair 0:f269e3021894 125 .vec_async = uart3_vec_async,
elessair 0:f269e3021894 126 .pdma_perp_tx = PDMA_UART3_TX,
elessair 0:f269e3021894 127 .pdma_perp_rx = PDMA_UART3_RX
elessair 0:f269e3021894 128 #endif
elessair 0:f269e3021894 129 };
elessair 0:f269e3021894 130 static struct nu_uart_var uart4_var = {
elessair 0:f269e3021894 131 .obj = NULL,
elessair 0:f269e3021894 132 .fifo_size_tx = 16,
elessair 0:f269e3021894 133 .fifo_size_rx = 16,
elessair 0:f269e3021894 134 .vec = uart4_vec,
elessair 0:f269e3021894 135 #if DEVICE_SERIAL_ASYNCH
elessair 0:f269e3021894 136 .vec_async = uart4_vec_async,
elessair 0:f269e3021894 137 .pdma_perp_tx = PDMA_UART4_TX,
elessair 0:f269e3021894 138 .pdma_perp_rx = PDMA_UART4_RX
elessair 0:f269e3021894 139 #endif
elessair 0:f269e3021894 140 };
elessair 0:f269e3021894 141 static struct nu_uart_var uart5_var = {
elessair 0:f269e3021894 142 .obj = NULL,
elessair 0:f269e3021894 143 .fifo_size_tx = 16,
elessair 0:f269e3021894 144 .fifo_size_rx = 16,
elessair 0:f269e3021894 145 .vec = uart5_vec,
elessair 0:f269e3021894 146 #if DEVICE_SERIAL_ASYNCH
elessair 0:f269e3021894 147 .vec_async = uart5_vec_async,
elessair 0:f269e3021894 148 .pdma_perp_tx = PDMA_UART5_TX,
elessair 0:f269e3021894 149 .pdma_perp_rx = PDMA_UART5_RX
elessair 0:f269e3021894 150 #endif
elessair 0:f269e3021894 151 };
elessair 0:f269e3021894 152
elessair 0:f269e3021894 153
elessair 0:f269e3021894 154 int stdio_uart_inited = 0;
elessair 0:f269e3021894 155 serial_t stdio_uart;
elessair 0:f269e3021894 156 static uint32_t uart_modinit_mask = 0;
elessair 0:f269e3021894 157
elessair 0:f269e3021894 158 static const struct nu_modinit_s uart_modinit_tab[] = {
elessair 0:f269e3021894 159 {UART_0, UART0_MODULE, CLK_CLKSEL1_UARTSEL_HIRC, CLK_CLKDIV0_UART(1), UART0_RST, UART0_IRQn, &uart0_var},
elessair 0:f269e3021894 160 {UART_1, UART1_MODULE, CLK_CLKSEL1_UARTSEL_HIRC, CLK_CLKDIV0_UART(1), UART1_RST, UART1_IRQn, &uart1_var},
elessair 0:f269e3021894 161 {UART_2, UART2_MODULE, CLK_CLKSEL1_UARTSEL_HIRC, CLK_CLKDIV0_UART(1), UART2_RST, UART2_IRQn, &uart2_var},
elessair 0:f269e3021894 162 {UART_3, UART3_MODULE, CLK_CLKSEL1_UARTSEL_HIRC, CLK_CLKDIV0_UART(1), UART3_RST, UART3_IRQn, &uart3_var},
elessair 0:f269e3021894 163 {UART_4, UART4_MODULE, CLK_CLKSEL1_UARTSEL_HIRC, CLK_CLKDIV0_UART(1), UART4_RST, UART4_IRQn, &uart4_var},
elessair 0:f269e3021894 164 {UART_5, UART5_MODULE, CLK_CLKSEL1_UARTSEL_HIRC, CLK_CLKDIV0_UART(1), UART5_RST, UART5_IRQn, &uart5_var},
elessair 0:f269e3021894 165
elessair 0:f269e3021894 166 {NC, 0, 0, 0, 0, (IRQn_Type) 0, NULL}
elessair 0:f269e3021894 167 };
elessair 0:f269e3021894 168
elessair 0:f269e3021894 169 extern void mbed_sdk_init(void);
elessair 0:f269e3021894 170
elessair 0:f269e3021894 171 void serial_init(serial_t *obj, PinName tx, PinName rx)
elessair 0:f269e3021894 172 {
elessair 0:f269e3021894 173 // NOTE: serial_init() gets called from _sys_open() timing of which is before main()/mbed_sdk_init().
elessair 0:f269e3021894 174 mbed_sdk_init();
elessair 0:f269e3021894 175
elessair 0:f269e3021894 176 // Determine which UART_x the pins are used for
elessair 0:f269e3021894 177 uint32_t uart_tx = pinmap_peripheral(tx, PinMap_UART_TX);
elessair 0:f269e3021894 178 uint32_t uart_rx = pinmap_peripheral(rx, PinMap_UART_RX);
elessair 0:f269e3021894 179 // Get the peripheral name (UART_x) from the pins and assign it to the object
elessair 0:f269e3021894 180 obj->serial.uart = (UARTName) pinmap_merge(uart_tx, uart_rx);
elessair 0:f269e3021894 181 MBED_ASSERT((int)obj->serial.uart != NC);
elessair 0:f269e3021894 182
elessair 0:f269e3021894 183 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
elessair 0:f269e3021894 184 MBED_ASSERT(modinit != NULL);
elessair 0:f269e3021894 185 MBED_ASSERT(modinit->modname == obj->serial.uart);
elessair 0:f269e3021894 186
elessair 0:f269e3021894 187 // Reset this module
elessair 0:f269e3021894 188 SYS_ResetModule(modinit->rsetidx);
elessair 0:f269e3021894 189
elessair 0:f269e3021894 190 // Select IP clock source
elessair 0:f269e3021894 191 CLK_SetModuleClock(modinit->clkidx, modinit->clksrc, modinit->clkdiv);
elessair 0:f269e3021894 192 // Enable IP clock
elessair 0:f269e3021894 193 CLK_EnableModuleClock(modinit->clkidx);
elessair 0:f269e3021894 194
elessair 0:f269e3021894 195 pinmap_pinout(tx, PinMap_UART_TX);
elessair 0:f269e3021894 196 pinmap_pinout(rx, PinMap_UART_RX);
elessair 0:f269e3021894 197 // FIXME: Why PullUp?
elessair 0:f269e3021894 198 //if (tx != NC) {
elessair 0:f269e3021894 199 // pin_mode(tx, PullUp);
elessair 0:f269e3021894 200 //}
elessair 0:f269e3021894 201 //if (rx != NC) {
elessair 0:f269e3021894 202 // pin_mode(rx, PullUp);
elessair 0:f269e3021894 203 //}
elessair 0:f269e3021894 204 obj->serial.pin_tx = tx;
elessair 0:f269e3021894 205 obj->serial.pin_rx = rx;
elessair 0:f269e3021894 206
elessair 0:f269e3021894 207 // Configure the UART module and set its baudrate
elessair 0:f269e3021894 208 serial_baud(obj, 9600);
elessair 0:f269e3021894 209 // Configure data bits, parity, and stop bits
elessair 0:f269e3021894 210 serial_format(obj, 8, ParityNone, 1);
elessair 0:f269e3021894 211
elessair 0:f269e3021894 212 obj->serial.vec = ((struct nu_uart_var *) modinit->var)->vec;
elessair 0:f269e3021894 213
elessair 0:f269e3021894 214 #if DEVICE_SERIAL_ASYNCH
elessair 0:f269e3021894 215 obj->serial.dma_usage_tx = DMA_USAGE_NEVER;
elessair 0:f269e3021894 216 obj->serial.dma_usage_rx = DMA_USAGE_NEVER;
elessair 0:f269e3021894 217 obj->serial.event = 0;
elessair 0:f269e3021894 218 obj->serial.dma_chn_id_tx = DMA_ERROR_OUT_OF_CHANNELS;
elessair 0:f269e3021894 219 obj->serial.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS;
elessair 0:f269e3021894 220 #endif
elessair 0:f269e3021894 221
elessair 0:f269e3021894 222 // For stdio management
elessair 0:f269e3021894 223 if (obj == &stdio_uart) {
elessair 0:f269e3021894 224 stdio_uart_inited = 1;
elessair 0:f269e3021894 225 /* NOTE: Not required anymore because stdio_uart will be manually initialized in mbed-drivers/source/retarget.cpp from mbed beta */
elessair 0:f269e3021894 226 //memcpy(&stdio_uart, obj, sizeof(serial_t));
elessair 0:f269e3021894 227 }
elessair 0:f269e3021894 228
elessair 0:f269e3021894 229 // Mark this module to be inited.
elessair 0:f269e3021894 230 int i = modinit - uart_modinit_tab;
elessair 0:f269e3021894 231 uart_modinit_mask |= 1 << i;
elessair 0:f269e3021894 232 }
elessair 0:f269e3021894 233
elessair 0:f269e3021894 234 void serial_free(serial_t *obj)
elessair 0:f269e3021894 235 {
elessair 0:f269e3021894 236 #if DEVICE_SERIAL_ASYNCH
elessair 0:f269e3021894 237 if (obj->serial.dma_chn_id_tx != DMA_ERROR_OUT_OF_CHANNELS) {
elessair 0:f269e3021894 238 dma_channel_free(obj->serial.dma_chn_id_tx);
elessair 0:f269e3021894 239 obj->serial.dma_chn_id_tx = DMA_ERROR_OUT_OF_CHANNELS;
elessair 0:f269e3021894 240 }
elessair 0:f269e3021894 241 if (obj->serial.dma_chn_id_rx != DMA_ERROR_OUT_OF_CHANNELS) {
elessair 0:f269e3021894 242 dma_channel_free(obj->serial.dma_chn_id_rx);
elessair 0:f269e3021894 243 obj->serial.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS;
elessair 0:f269e3021894 244 }
elessair 0:f269e3021894 245 #endif
elessair 0:f269e3021894 246
elessair 0:f269e3021894 247 UART_Close((UART_T *) NU_MODBASE(obj->serial.uart));
elessair 0:f269e3021894 248
elessair 0:f269e3021894 249 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
elessair 0:f269e3021894 250 MBED_ASSERT(modinit != NULL);
elessair 0:f269e3021894 251 MBED_ASSERT(modinit->modname == obj->serial.uart);
elessair 0:f269e3021894 252
elessair 0:f269e3021894 253 UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_THREIEN_Msk | UART_INTEN_RXTOIEN_Msk));
elessair 0:f269e3021894 254 NVIC_DisableIRQ(modinit->irq_n);
elessair 0:f269e3021894 255
elessair 0:f269e3021894 256 // Disable IP clock
elessair 0:f269e3021894 257 CLK_DisableModuleClock(modinit->clkidx);
elessair 0:f269e3021894 258
elessair 0:f269e3021894 259 ((struct nu_uart_var *) modinit->var)->obj = NULL;
elessair 0:f269e3021894 260
elessair 0:f269e3021894 261 if (obj == &stdio_uart) {
elessair 0:f269e3021894 262 stdio_uart_inited = 0;
elessair 0:f269e3021894 263 }
elessair 0:f269e3021894 264
elessair 0:f269e3021894 265 // Mark this module to be deinited.
elessair 0:f269e3021894 266 int i = modinit - uart_modinit_tab;
elessair 0:f269e3021894 267 uart_modinit_mask &= ~(1 << i);
elessair 0:f269e3021894 268 }
elessair 0:f269e3021894 269
elessair 0:f269e3021894 270 void serial_baud(serial_t *obj, int baudrate) {
elessair 0:f269e3021894 271 // Flush Tx FIFO. Otherwise, output data may get lost on this change.
elessair 0:f269e3021894 272 while (! UART_IS_TX_EMPTY(((UART_T *) obj->serial.uart)));
elessair 0:f269e3021894 273
elessair 0:f269e3021894 274 obj->serial.baudrate = baudrate;
elessair 0:f269e3021894 275 UART_Open((UART_T *) NU_MODBASE(obj->serial.uart), baudrate);
elessair 0:f269e3021894 276 }
elessair 0:f269e3021894 277
elessair 0:f269e3021894 278 void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
elessair 0:f269e3021894 279 // Flush Tx FIFO. Otherwise, output data may get lost on this change.
elessair 0:f269e3021894 280 while (! UART_IS_TX_EMPTY(((UART_T *) obj->serial.uart)));
elessair 0:f269e3021894 281
elessair 0:f269e3021894 282 // TODO: Assert for not supported parity and data bits
elessair 0:f269e3021894 283 obj->serial.databits = data_bits;
elessair 0:f269e3021894 284 obj->serial.parity = parity;
elessair 0:f269e3021894 285 obj->serial.stopbits = stop_bits;
elessair 0:f269e3021894 286
elessair 0:f269e3021894 287 uint32_t databits_intern = (data_bits == 5) ? UART_WORD_LEN_5 :
elessair 0:f269e3021894 288 (data_bits == 6) ? UART_WORD_LEN_6 :
elessair 0:f269e3021894 289 (data_bits == 7) ? UART_WORD_LEN_7 :
elessair 0:f269e3021894 290 UART_WORD_LEN_8;
elessair 0:f269e3021894 291 uint32_t parity_intern = (parity == ParityOdd || parity == ParityForced1) ? UART_PARITY_ODD :
elessair 0:f269e3021894 292 (parity == ParityEven || parity == ParityForced0) ? UART_PARITY_EVEN :
elessair 0:f269e3021894 293 UART_PARITY_NONE;
elessair 0:f269e3021894 294 uint32_t stopbits_intern = (stop_bits == 2) ? UART_STOP_BIT_2 : UART_STOP_BIT_1;
elessair 0:f269e3021894 295 UART_SetLine_Config((UART_T *) NU_MODBASE(obj->serial.uart),
elessair 0:f269e3021894 296 0, // Don't change baudrate
elessair 0:f269e3021894 297 databits_intern,
elessair 0:f269e3021894 298 parity_intern,
elessair 0:f269e3021894 299 stopbits_intern);
elessair 0:f269e3021894 300 }
elessair 0:f269e3021894 301
elessair 0:f269e3021894 302 #if DEVICE_SERIAL_FC
elessair 0:f269e3021894 303
elessair 0:f269e3021894 304 void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow)
elessair 0:f269e3021894 305 {
elessair 0:f269e3021894 306 UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart);
elessair 0:f269e3021894 307
elessair 0:f269e3021894 308 // First, disable flow control completely.
elessair 0:f269e3021894 309 uart_base->INTEN &= ~(UART_INTEN_ATORTSEN_Msk | UART_INTEN_ATOCTSEN_Msk);
elessair 0:f269e3021894 310
elessair 0:f269e3021894 311 if ((type == FlowControlRTS || type == FlowControlRTSCTS) && rxflow != NC) {
elessair 0:f269e3021894 312 // Check if RTS pin matches.
elessair 0:f269e3021894 313 uint32_t uart_rts = pinmap_peripheral(rxflow, PinMap_UART_RTS);
elessair 0:f269e3021894 314 MBED_ASSERT(uart_rts == obj->serial.uart);
elessair 0:f269e3021894 315 // Enable the pin for RTS function
elessair 0:f269e3021894 316 pinmap_pinout(rxflow, PinMap_UART_RTS);
elessair 0:f269e3021894 317 // nRTS pin output is high level active
elessair 0:f269e3021894 318 uart_base->MODEM = (uart_base->MODEM & ~UART_MODEM_RTSACTLV_Msk) | UART_MODEM_RTSACTLV_Msk;
elessair 0:f269e3021894 319 uart_base->FIFO = (uart_base->FIFO & ~UART_FIFO_RTSTRGLV_Msk) | UART_FIFO_RTSTRGLV_8BYTES;
elessair 0:f269e3021894 320 // Enable RTS
elessair 0:f269e3021894 321 uart_base->INTEN |= UART_INTEN_ATORTSEN_Msk;
elessair 0:f269e3021894 322 }
elessair 0:f269e3021894 323
elessair 0:f269e3021894 324 if ((type == FlowControlCTS || type == FlowControlRTSCTS) && txflow != NC) {
elessair 0:f269e3021894 325 // Check if CTS pin matches.
elessair 0:f269e3021894 326 uint32_t uart_cts = pinmap_peripheral(txflow, PinMap_UART_CTS);
elessair 0:f269e3021894 327 MBED_ASSERT(uart_cts == obj->serial.uart);
elessair 0:f269e3021894 328 // Enable the pin for CTS function
elessair 0:f269e3021894 329 pinmap_pinout(txflow, PinMap_UART_CTS);
elessair 0:f269e3021894 330 // nCTS pin input is high level active
elessair 0:f269e3021894 331 uart_base->MODEMSTS = (uart_base->MODEMSTS & ~UART_MODEMSTS_CTSACTLV_Msk) | UART_MODEMSTS_CTSACTLV_Msk;
elessair 0:f269e3021894 332 // Enable CTS
elessair 0:f269e3021894 333 uart_base->INTEN |= UART_INTEN_ATOCTSEN_Msk;
elessair 0:f269e3021894 334 }
elessair 0:f269e3021894 335 }
elessair 0:f269e3021894 336
elessair 0:f269e3021894 337 #endif //DEVICE_SERIAL_FC
elessair 0:f269e3021894 338
elessair 0:f269e3021894 339 void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
elessair 0:f269e3021894 340 {
elessair 0:f269e3021894 341 // Flush Tx FIFO. Otherwise, output data may get lost on this change.
elessair 0:f269e3021894 342 while (! UART_IS_TX_EMPTY(((UART_T *) obj->serial.uart)));
elessair 0:f269e3021894 343
elessair 0:f269e3021894 344 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
elessair 0:f269e3021894 345 MBED_ASSERT(modinit != NULL);
elessair 0:f269e3021894 346 MBED_ASSERT(modinit->modname == obj->serial.uart);
elessair 0:f269e3021894 347
elessair 0:f269e3021894 348 ((struct nu_uart_var *) modinit->var)->obj = obj;
elessair 0:f269e3021894 349 obj->serial.irq_handler = (uint32_t) handler;
elessair 0:f269e3021894 350 obj->serial.irq_id = id;
elessair 0:f269e3021894 351
elessair 0:f269e3021894 352 // Restore sync-mode vector
elessair 0:f269e3021894 353 obj->serial.vec = ((struct nu_uart_var *) modinit->var)->vec;
elessair 0:f269e3021894 354 }
elessair 0:f269e3021894 355
elessair 0:f269e3021894 356 void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
elessair 0:f269e3021894 357 {
elessair 0:f269e3021894 358 if (enable) {
elessair 0:f269e3021894 359 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
elessair 0:f269e3021894 360 MBED_ASSERT(modinit != NULL);
elessair 0:f269e3021894 361 MBED_ASSERT(modinit->modname == obj->serial.uart);
elessair 0:f269e3021894 362
elessair 0:f269e3021894 363 NVIC_SetVector(modinit->irq_n, (uint32_t) obj->serial.vec);
elessair 0:f269e3021894 364 NVIC_EnableIRQ(modinit->irq_n);
elessair 0:f269e3021894 365
elessair 0:f269e3021894 366 switch (irq) {
elessair 0:f269e3021894 367 // NOTE: Setting inten_msk first to avoid race condition
elessair 0:f269e3021894 368 case RxIrq:
elessair 0:f269e3021894 369 obj->serial.inten_msk = obj->serial.inten_msk | (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk);
elessair 0:f269e3021894 370 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
elessair 0:f269e3021894 371 break;
elessair 0:f269e3021894 372 case TxIrq:
elessair 0:f269e3021894 373 obj->serial.inten_msk = obj->serial.inten_msk | UART_INTEN_THREIEN_Msk;
elessair 0:f269e3021894 374 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk);
elessair 0:f269e3021894 375 break;
elessair 0:f269e3021894 376 }
elessair 0:f269e3021894 377 } else { // disable
elessair 0:f269e3021894 378 switch (irq) {
elessair 0:f269e3021894 379 case RxIrq:
elessair 0:f269e3021894 380 UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
elessair 0:f269e3021894 381 obj->serial.inten_msk = obj->serial.inten_msk & ~(UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk);
elessair 0:f269e3021894 382 break;
elessair 0:f269e3021894 383 case TxIrq:
elessair 0:f269e3021894 384 UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk);
elessair 0:f269e3021894 385 obj->serial.inten_msk = obj->serial.inten_msk & ~UART_INTEN_THREIEN_Msk;
elessair 0:f269e3021894 386 break;
elessair 0:f269e3021894 387 }
elessair 0:f269e3021894 388 }
elessair 0:f269e3021894 389 }
elessair 0:f269e3021894 390
elessair 0:f269e3021894 391 int serial_getc(serial_t *obj)
elessair 0:f269e3021894 392 {
elessair 0:f269e3021894 393 // TODO: Fix every byte access requires accompaniness of one interrupt. This degrades performance much.
elessair 0:f269e3021894 394 while (! serial_readable(obj));
elessair 0:f269e3021894 395 int c = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart)));
elessair 0:f269e3021894 396
elessair 0:f269e3021894 397 // Simulate clear of the interrupt flag
elessair 0:f269e3021894 398 if (obj->serial.inten_msk & (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)) {
elessair 0:f269e3021894 399 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
elessair 0:f269e3021894 400 }
elessair 0:f269e3021894 401
elessair 0:f269e3021894 402 return c;
elessair 0:f269e3021894 403 }
elessair 0:f269e3021894 404
elessair 0:f269e3021894 405 void serial_putc(serial_t *obj, int c)
elessair 0:f269e3021894 406 {
elessair 0:f269e3021894 407 // TODO: Fix every byte access requires accompaniness of one interrupt. This degrades performance much.
elessair 0:f269e3021894 408 while (! serial_writable(obj));
elessair 0:f269e3021894 409 UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), c);
elessair 0:f269e3021894 410
elessair 0:f269e3021894 411 // Simulate clear of the interrupt flag
elessair 0:f269e3021894 412 if (obj->serial.inten_msk & UART_INTEN_THREIEN_Msk) {
elessair 0:f269e3021894 413 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk);
elessair 0:f269e3021894 414 }
elessair 0:f269e3021894 415 }
elessair 0:f269e3021894 416
elessair 0:f269e3021894 417 int serial_readable(serial_t *obj)
elessair 0:f269e3021894 418 {
elessair 0:f269e3021894 419 //return UART_IS_RX_READY(((UART_T *) NU_MODBASE(obj->serial.uart)));
elessair 0:f269e3021894 420 return ! (((UART_T *) NU_MODBASE(obj->serial.uart))->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk);
elessair 0:f269e3021894 421 }
elessair 0:f269e3021894 422
elessair 0:f269e3021894 423 int serial_writable(serial_t *obj)
elessair 0:f269e3021894 424 {
elessair 0:f269e3021894 425 return ! UART_IS_TX_FULL(((UART_T *) NU_MODBASE(obj->serial.uart)));
elessair 0:f269e3021894 426 }
elessair 0:f269e3021894 427
elessair 0:f269e3021894 428 void serial_pinout_tx(PinName tx)
elessair 0:f269e3021894 429 {
elessair 0:f269e3021894 430 pinmap_pinout(tx, PinMap_UART_TX);
elessair 0:f269e3021894 431 }
elessair 0:f269e3021894 432
elessair 0:f269e3021894 433 void serial_break_set(serial_t *obj)
elessair 0:f269e3021894 434 {
elessair 0:f269e3021894 435 ((UART_T *) NU_MODBASE(obj->serial.uart))->LINE |= UART_LINE_BCB_Msk;
elessair 0:f269e3021894 436 }
elessair 0:f269e3021894 437
elessair 0:f269e3021894 438 void serial_break_clear(serial_t *obj)
elessair 0:f269e3021894 439 {
elessair 0:f269e3021894 440 ((UART_T *) NU_MODBASE(obj->serial.uart))->LINE &= ~UART_LINE_BCB_Msk;
elessair 0:f269e3021894 441 }
elessair 0:f269e3021894 442
elessair 0:f269e3021894 443 static void uart0_vec(void)
elessair 0:f269e3021894 444 {
elessair 0:f269e3021894 445 uart_irq(uart0_var.obj);
elessair 0:f269e3021894 446 }
elessair 0:f269e3021894 447
elessair 0:f269e3021894 448 static void uart1_vec(void)
elessair 0:f269e3021894 449 {
elessair 0:f269e3021894 450 uart_irq(uart1_var.obj);
elessair 0:f269e3021894 451 }
elessair 0:f269e3021894 452
elessair 0:f269e3021894 453 static void uart2_vec(void)
elessair 0:f269e3021894 454 {
elessair 0:f269e3021894 455 uart_irq(uart2_var.obj);
elessair 0:f269e3021894 456 }
elessair 0:f269e3021894 457
elessair 0:f269e3021894 458 static void uart3_vec(void)
elessair 0:f269e3021894 459 {
elessair 0:f269e3021894 460 uart_irq(uart3_var.obj);
elessair 0:f269e3021894 461 }
elessair 0:f269e3021894 462
elessair 0:f269e3021894 463 static void uart4_vec(void)
elessair 0:f269e3021894 464 {
elessair 0:f269e3021894 465 uart_irq(uart4_var.obj);
elessair 0:f269e3021894 466 }
elessair 0:f269e3021894 467
elessair 0:f269e3021894 468 static void uart5_vec(void)
elessair 0:f269e3021894 469 {
elessair 0:f269e3021894 470 uart_irq(uart5_var.obj);
elessair 0:f269e3021894 471 }
elessair 0:f269e3021894 472
elessair 0:f269e3021894 473 static void uart_irq(serial_t *obj)
elessair 0:f269e3021894 474 {
elessair 0:f269e3021894 475 UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart);
elessair 0:f269e3021894 476
elessair 0:f269e3021894 477 if (uart_base->INTSTS & (UART_INTSTS_RDAINT_Msk | UART_INTSTS_RXTOINT_Msk)) {
elessair 0:f269e3021894 478 // Simulate clear of the interrupt flag. Temporarily disable the interrupt here and to be recovered on next read.
elessair 0:f269e3021894 479 UART_DISABLE_INT(uart_base, (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
elessair 0:f269e3021894 480 if (obj->serial.irq_handler) {
elessair 0:f269e3021894 481 ((uart_irq_handler) obj->serial.irq_handler)(obj->serial.irq_id, RxIrq);
elessair 0:f269e3021894 482 }
elessair 0:f269e3021894 483 }
elessair 0:f269e3021894 484
elessair 0:f269e3021894 485 if (uart_base->INTSTS & UART_INTSTS_THREINT_Msk) {
elessair 0:f269e3021894 486 // Simulate clear of the interrupt flag. Temporarily disable the interrupt here and to be recovered on next write.
elessair 0:f269e3021894 487 UART_DISABLE_INT(uart_base, UART_INTEN_THREIEN_Msk);
elessair 0:f269e3021894 488 if (obj->serial.irq_handler) {
elessair 0:f269e3021894 489 ((uart_irq_handler) obj->serial.irq_handler)(obj->serial.irq_id, TxIrq);
elessair 0:f269e3021894 490 }
elessair 0:f269e3021894 491 }
elessair 0:f269e3021894 492
elessair 0:f269e3021894 493 // FIXME: Ignore all other interrupt flags. Clear them. Otherwise, program will get stuck in interrupt.
elessair 0:f269e3021894 494 uart_base->INTSTS = uart_base->INTSTS;
elessair 0:f269e3021894 495 uart_base->FIFOSTS = uart_base->FIFOSTS;
elessair 0:f269e3021894 496 }
elessair 0:f269e3021894 497
elessair 0:f269e3021894 498
elessair 0:f269e3021894 499 #if DEVICE_SERIAL_ASYNCH
elessair 0:f269e3021894 500 int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx_width, uint32_t handler, uint32_t event, DMAUsage hint)
elessair 0:f269e3021894 501 {
elessair 0:f269e3021894 502 // NOTE: tx_width is deprecated. Assume its value is databits ceiled to the nearest number among 8, 16, and 32.
elessair 0:f269e3021894 503 tx_width = (obj->serial.databits <= 8) ? 8 : (obj->serial.databits <= 16) ? 16 : 32;
elessair 0:f269e3021894 504
elessair 0:f269e3021894 505 MBED_ASSERT(tx_width == 8 || tx_width == 16 || tx_width == 32);
elessair 0:f269e3021894 506
elessair 0:f269e3021894 507 obj->serial.dma_usage_tx = hint;
elessair 0:f269e3021894 508 serial_check_dma_usage(&obj->serial.dma_usage_tx, &obj->serial.dma_chn_id_tx);
elessair 0:f269e3021894 509
elessair 0:f269e3021894 510 // UART IRQ is necessary for both interrupt way and DMA way
elessair 0:f269e3021894 511 serial_tx_enable_event(obj, event, 1);
elessair 0:f269e3021894 512 serial_tx_buffer_set(obj, tx, tx_length, tx_width);
elessair 0:f269e3021894 513 //UART_HAL_DisableTransmitter(obj->serial.address);
elessair 0:f269e3021894 514 //UART_HAL_FlushTxFifo(obj->serial.address);
elessair 0:f269e3021894 515 //UART_HAL_EnableTransmitter(obj->serial.address);
elessair 0:f269e3021894 516
elessair 0:f269e3021894 517 int n_word = 0;
elessair 0:f269e3021894 518 if (obj->serial.dma_usage_tx == DMA_USAGE_NEVER) {
elessair 0:f269e3021894 519 // Interrupt way
elessair 0:f269e3021894 520 n_word = serial_write_async(obj);
elessair 0:f269e3021894 521 serial_tx_enable_interrupt(obj, handler, 1);
elessair 0:f269e3021894 522 } else {
elessair 0:f269e3021894 523 // DMA way
elessair 0:f269e3021894 524 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
elessair 0:f269e3021894 525 MBED_ASSERT(modinit != NULL);
elessair 0:f269e3021894 526 MBED_ASSERT(modinit->modname == obj->serial.uart);
elessair 0:f269e3021894 527
elessair 0:f269e3021894 528 PDMA->CHCTL |= 1 << obj->serial.dma_chn_id_tx; // Enable this DMA channel
elessair 0:f269e3021894 529 PDMA_SetTransferMode(obj->serial.dma_chn_id_tx,
elessair 0:f269e3021894 530 ((struct nu_uart_var *) modinit->var)->pdma_perp_tx, // Peripheral connected to this PDMA
elessair 0:f269e3021894 531 0, // Scatter-gather disabled
elessair 0:f269e3021894 532 0); // Scatter-gather descriptor address
elessair 0:f269e3021894 533 PDMA_SetTransferCnt(obj->serial.dma_chn_id_tx,
elessair 0:f269e3021894 534 (tx_width == 8) ? PDMA_WIDTH_8 : (tx_width == 16) ? PDMA_WIDTH_16 : PDMA_WIDTH_32,
elessair 0:f269e3021894 535 tx_length);
elessair 0:f269e3021894 536 PDMA_SetTransferAddr(obj->serial.dma_chn_id_tx,
elessair 0:f269e3021894 537 ((uint32_t) tx) + (tx_width / 8) * tx_length, // NOTE: End of source address
elessair 0:f269e3021894 538 PDMA_SAR_INC, // Source address incremental
elessair 0:f269e3021894 539 (uint32_t) obj->serial.uart, // Destination address
elessair 0:f269e3021894 540 PDMA_DAR_FIX); // Destination address fixed
elessair 0:f269e3021894 541 PDMA_SetBurstType(obj->serial.dma_chn_id_tx,
elessair 0:f269e3021894 542 PDMA_REQ_SINGLE, // Single mode
elessair 0:f269e3021894 543 0); // Burst size
elessair 0:f269e3021894 544 PDMA_EnableInt(obj->serial.dma_chn_id_tx,
elessair 0:f269e3021894 545 0); // Interrupt type. No use here
elessair 0:f269e3021894 546 // Register DMA event handler
elessair 0:f269e3021894 547 dma_set_handler(obj->serial.dma_chn_id_tx, (uint32_t) uart_dma_handler_tx, (uint32_t) obj, DMA_EVENT_ALL);
elessair 0:f269e3021894 548 serial_tx_enable_interrupt(obj, handler, 1);
elessair 0:f269e3021894 549 ((UART_T *) NU_MODBASE(obj->serial.uart))->INTEN |= UART_INTEN_TXPDMAEN_Msk; // Start DMA transfer
elessair 0:f269e3021894 550 }
elessair 0:f269e3021894 551
elessair 0:f269e3021894 552 return n_word;
elessair 0:f269e3021894 553 }
elessair 0:f269e3021894 554
elessair 0:f269e3021894 555 void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_width, uint32_t handler, uint32_t event, uint8_t char_match, DMAUsage hint)
elessair 0:f269e3021894 556 {
elessair 0:f269e3021894 557 // NOTE: rx_width is deprecated. Assume its value is databits ceiled to the nearest number among 8, 16, and 32.
elessair 0:f269e3021894 558 rx_width = (obj->serial.databits <= 8) ? 8 : (obj->serial.databits <= 16) ? 16 : 32;
elessair 0:f269e3021894 559
elessair 0:f269e3021894 560 MBED_ASSERT(rx_width == 8 || rx_width == 16 || rx_width == 32);
elessair 0:f269e3021894 561
elessair 0:f269e3021894 562 obj->serial.dma_usage_rx = hint;
elessair 0:f269e3021894 563 serial_check_dma_usage(&obj->serial.dma_usage_rx, &obj->serial.dma_chn_id_rx);
elessair 0:f269e3021894 564 // DMA doesn't support char match, so fall back to IRQ if it is requested.
elessair 0:f269e3021894 565 if (obj->serial.dma_usage_rx != DMA_USAGE_NEVER &&
elessair 0:f269e3021894 566 (event & SERIAL_EVENT_RX_CHARACTER_MATCH) &&
elessair 0:f269e3021894 567 char_match != SERIAL_RESERVED_CHAR_MATCH) {
elessair 0:f269e3021894 568 obj->serial.dma_usage_rx = DMA_USAGE_NEVER;
elessair 0:f269e3021894 569 dma_channel_free(obj->serial.dma_chn_id_rx);
elessair 0:f269e3021894 570 obj->serial.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS;
elessair 0:f269e3021894 571 }
elessair 0:f269e3021894 572
elessair 0:f269e3021894 573 // UART IRQ is necessary for both interrupt way and DMA way
elessair 0:f269e3021894 574 serial_rx_enable_event(obj, event, 1);
elessair 0:f269e3021894 575 serial_rx_buffer_set(obj, rx, rx_length, rx_width);
elessair 0:f269e3021894 576 serial_rx_set_char_match(obj, char_match);
elessair 0:f269e3021894 577 //UART_HAL_DisableReceiver(obj->serial.address);
elessair 0:f269e3021894 578 //UART_HAL_FlushRxFifo(obj->serial.address);
elessair 0:f269e3021894 579 //UART_HAL_EnableReceiver(obj->serial.address);
elessair 0:f269e3021894 580
elessair 0:f269e3021894 581 if (obj->serial.dma_usage_rx == DMA_USAGE_NEVER) {
elessair 0:f269e3021894 582 // Interrupt way
elessair 0:f269e3021894 583 serial_rx_enable_interrupt(obj, handler, 1);
elessair 0:f269e3021894 584 } else {
elessair 0:f269e3021894 585 // DMA way
elessair 0:f269e3021894 586 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
elessair 0:f269e3021894 587 MBED_ASSERT(modinit != NULL);
elessair 0:f269e3021894 588 MBED_ASSERT(modinit->modname == obj->serial.uart);
elessair 0:f269e3021894 589
elessair 0:f269e3021894 590 PDMA->CHCTL |= 1 << obj->serial.dma_chn_id_rx; // Enable this DMA channel
elessair 0:f269e3021894 591 PDMA_SetTransferMode(obj->serial.dma_chn_id_rx,
elessair 0:f269e3021894 592 ((struct nu_uart_var *) modinit->var)->pdma_perp_rx, // Peripheral connected to this PDMA
elessair 0:f269e3021894 593 0, // Scatter-gather disabled
elessair 0:f269e3021894 594 0); // Scatter-gather descriptor address
elessair 0:f269e3021894 595 PDMA_SetTransferCnt(obj->serial.dma_chn_id_rx,
elessair 0:f269e3021894 596 (rx_width == 8) ? PDMA_WIDTH_8 : (rx_width == 16) ? PDMA_WIDTH_16 : PDMA_WIDTH_32,
elessair 0:f269e3021894 597 rx_length);
elessair 0:f269e3021894 598 PDMA_SetTransferAddr(obj->serial.dma_chn_id_rx,
elessair 0:f269e3021894 599 (uint32_t) obj->serial.uart, // Source address
elessair 0:f269e3021894 600 PDMA_SAR_FIX, // Source address fixed
elessair 0:f269e3021894 601 ((uint32_t) rx) + (rx_width / 8) * rx_length, // NOTE: End of destination address
elessair 0:f269e3021894 602 PDMA_DAR_INC); // Destination address incremental
elessair 0:f269e3021894 603 PDMA_SetBurstType(obj->serial.dma_chn_id_rx,
elessair 0:f269e3021894 604 PDMA_REQ_SINGLE, // Single mode
elessair 0:f269e3021894 605 0); // Burst size
elessair 0:f269e3021894 606 PDMA_EnableInt(obj->serial.dma_chn_id_rx,
elessair 0:f269e3021894 607 0); // Interrupt type. No use here
elessair 0:f269e3021894 608 // Register DMA event handler
elessair 0:f269e3021894 609 dma_set_handler(obj->serial.dma_chn_id_rx, (uint32_t) uart_dma_handler_rx, (uint32_t) obj, DMA_EVENT_ALL);
elessair 0:f269e3021894 610 serial_rx_enable_interrupt(obj, handler, 1);
elessair 0:f269e3021894 611 ((UART_T *) NU_MODBASE(obj->serial.uart))->INTEN |= UART_INTEN_RXPDMAEN_Msk; // Start DMA transfer
elessair 0:f269e3021894 612 }
elessair 0:f269e3021894 613 }
elessair 0:f269e3021894 614
elessair 0:f269e3021894 615 void serial_tx_abort_asynch(serial_t *obj)
elessair 0:f269e3021894 616 {
elessair 0:f269e3021894 617 // Flush Tx FIFO. Otherwise, output data may get lost on this change.
elessair 0:f269e3021894 618 while (! UART_IS_TX_EMPTY(((UART_T *) obj->serial.uart)));
elessair 0:f269e3021894 619
elessair 0:f269e3021894 620 if (obj->serial.dma_usage_tx != DMA_USAGE_NEVER) {
elessair 0:f269e3021894 621 if (obj->serial.dma_chn_id_tx != DMA_ERROR_OUT_OF_CHANNELS) {
elessair 0:f269e3021894 622 PDMA_DisableInt(obj->serial.dma_chn_id_tx, 0);
elessair 0:f269e3021894 623 // FIXME: Next PDMA transfer will fail with PDMA_STOP() called. Cause is unknown.
elessair 0:f269e3021894 624 //PDMA_STOP(obj->serial.dma_chn_id_tx);
elessair 0:f269e3021894 625 PDMA->CHCTL &= ~(1 << obj->serial.dma_chn_id_tx);
elessair 0:f269e3021894 626 }
elessair 0:f269e3021894 627 UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_TXPDMAEN_Msk);
elessair 0:f269e3021894 628 }
elessair 0:f269e3021894 629
elessair 0:f269e3021894 630 // Necessary for both interrupt way and DMA way
elessair 0:f269e3021894 631 serial_irq_set(obj, TxIrq, 0);
elessair 0:f269e3021894 632 // FIXME: more complete abort operation
elessair 0:f269e3021894 633 //UART_HAL_DisableTransmitter(obj->serial.serial.address);
elessair 0:f269e3021894 634 //UART_HAL_FlushTxFifo(obj->serial.serial.address);
elessair 0:f269e3021894 635 }
elessair 0:f269e3021894 636
elessair 0:f269e3021894 637 void serial_rx_abort_asynch(serial_t *obj)
elessair 0:f269e3021894 638 {
elessair 0:f269e3021894 639 if (obj->serial.dma_usage_rx != DMA_USAGE_NEVER) {
elessair 0:f269e3021894 640 if (obj->serial.dma_chn_id_rx != DMA_ERROR_OUT_OF_CHANNELS) {
elessair 0:f269e3021894 641 PDMA_DisableInt(obj->serial.dma_chn_id_rx, 0);
elessair 0:f269e3021894 642 // FIXME: Next PDMA transfer will fail with PDMA_STOP() called. Cause is unknown.
elessair 0:f269e3021894 643 //PDMA_STOP(obj->serial.dma_chn_id_rx);
elessair 0:f269e3021894 644 PDMA->CHCTL &= ~(1 << obj->serial.dma_chn_id_rx);
elessair 0:f269e3021894 645 }
elessair 0:f269e3021894 646 UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_RXPDMAEN_Msk);
elessair 0:f269e3021894 647 }
elessair 0:f269e3021894 648
elessair 0:f269e3021894 649 // Necessary for both interrupt way and DMA way
elessair 0:f269e3021894 650 serial_irq_set(obj, RxIrq, 0);
elessair 0:f269e3021894 651 // FIXME: more complete abort operation
elessair 0:f269e3021894 652 //UART_HAL_DisableReceiver(obj->serial.serial.address);
elessair 0:f269e3021894 653 //UART_HAL_FlushRxFifo(obj->serial.serial.address);
elessair 0:f269e3021894 654 }
elessair 0:f269e3021894 655
elessair 0:f269e3021894 656 uint8_t serial_tx_active(serial_t *obj)
elessair 0:f269e3021894 657 {
elessair 0:f269e3021894 658 return serial_is_irq_en(obj, TxIrq);
elessair 0:f269e3021894 659 }
elessair 0:f269e3021894 660
elessair 0:f269e3021894 661 uint8_t serial_rx_active(serial_t *obj)
elessair 0:f269e3021894 662 {
elessair 0:f269e3021894 663 return serial_is_irq_en(obj, RxIrq);
elessair 0:f269e3021894 664 }
elessair 0:f269e3021894 665
elessair 0:f269e3021894 666 int serial_irq_handler_asynch(serial_t *obj)
elessair 0:f269e3021894 667 {
elessair 0:f269e3021894 668 int event_rx = 0;
elessair 0:f269e3021894 669 int event_tx = 0;
elessair 0:f269e3021894 670
elessair 0:f269e3021894 671 // Necessary for both interrup way and DMA way
elessair 0:f269e3021894 672 if (serial_is_irq_en(obj, RxIrq)) {
elessair 0:f269e3021894 673 event_rx = serial_rx_event_check(obj);
elessair 0:f269e3021894 674 if (event_rx) {
elessair 0:f269e3021894 675 serial_rx_abort_asynch(obj);
elessair 0:f269e3021894 676 }
elessair 0:f269e3021894 677 }
elessair 0:f269e3021894 678
elessair 0:f269e3021894 679 if (serial_is_irq_en(obj, TxIrq)) {
elessair 0:f269e3021894 680 event_tx = serial_tx_event_check(obj);
elessair 0:f269e3021894 681 if (event_tx) {
elessair 0:f269e3021894 682 serial_tx_abort_asynch(obj);
elessair 0:f269e3021894 683 }
elessair 0:f269e3021894 684 }
elessair 0:f269e3021894 685
elessair 0:f269e3021894 686 return (obj->serial.event & (event_rx | event_tx));
elessair 0:f269e3021894 687 }
elessair 0:f269e3021894 688
elessair 0:f269e3021894 689 int serial_allow_powerdown(void)
elessair 0:f269e3021894 690 {
elessair 0:f269e3021894 691 uint32_t modinit_mask = uart_modinit_mask;
elessair 0:f269e3021894 692 while (modinit_mask) {
elessair 0:f269e3021894 693 int uart_idx = nu_ctz(modinit_mask);
elessair 0:f269e3021894 694 const struct nu_modinit_s *modinit = uart_modinit_tab + uart_idx;
elessair 0:f269e3021894 695 if (modinit->modname != NC) {
elessair 0:f269e3021894 696 UART_T *uart_base = (UART_T *) NU_MODBASE(modinit->modname);
elessair 0:f269e3021894 697 // Disallow entering power-down mode if Tx FIFO has data to flush
elessair 0:f269e3021894 698 if (! UART_IS_TX_EMPTY((uart_base))) {
elessair 0:f269e3021894 699 return 0;
elessair 0:f269e3021894 700 }
elessair 0:f269e3021894 701 // Disallow entering power-down mode if async Rx transfer (not PDMA) is on-going
elessair 0:f269e3021894 702 if (uart_base->INTEN & (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)) {
elessair 0:f269e3021894 703 return 0;
elessair 0:f269e3021894 704 }
elessair 0:f269e3021894 705 // Disallow entering power-down mode if async Rx transfer (PDMA) is on-going
elessair 0:f269e3021894 706 if (uart_base->INTEN & UART_INTEN_RXPDMAEN_Msk) {
elessair 0:f269e3021894 707 return 0;
elessair 0:f269e3021894 708 }
elessair 0:f269e3021894 709 }
elessair 0:f269e3021894 710 modinit_mask &= ~(1 << uart_idx);
elessair 0:f269e3021894 711 }
elessair 0:f269e3021894 712
elessair 0:f269e3021894 713 return 1;
elessair 0:f269e3021894 714 }
elessair 0:f269e3021894 715
elessair 0:f269e3021894 716 static void uart0_vec_async(void)
elessair 0:f269e3021894 717 {
elessair 0:f269e3021894 718 uart_irq_async(uart0_var.obj);
elessair 0:f269e3021894 719 }
elessair 0:f269e3021894 720
elessair 0:f269e3021894 721 static void uart1_vec_async(void)
elessair 0:f269e3021894 722 {
elessair 0:f269e3021894 723 uart_irq_async(uart1_var.obj);
elessair 0:f269e3021894 724 }
elessair 0:f269e3021894 725
elessair 0:f269e3021894 726 static void uart2_vec_async(void)
elessair 0:f269e3021894 727 {
elessair 0:f269e3021894 728 uart_irq_async(uart2_var.obj);
elessair 0:f269e3021894 729 }
elessair 0:f269e3021894 730
elessair 0:f269e3021894 731 static void uart3_vec_async(void)
elessair 0:f269e3021894 732 {
elessair 0:f269e3021894 733 uart_irq_async(uart3_var.obj);
elessair 0:f269e3021894 734 }
elessair 0:f269e3021894 735
elessair 0:f269e3021894 736 static void uart4_vec_async(void)
elessair 0:f269e3021894 737 {
elessair 0:f269e3021894 738 uart_irq_async(uart4_var.obj);
elessair 0:f269e3021894 739 }
elessair 0:f269e3021894 740
elessair 0:f269e3021894 741 static void uart5_vec_async(void)
elessair 0:f269e3021894 742 {
elessair 0:f269e3021894 743 uart_irq_async(uart5_var.obj);
elessair 0:f269e3021894 744 }
elessair 0:f269e3021894 745
elessair 0:f269e3021894 746 static void uart_irq_async(serial_t *obj)
elessair 0:f269e3021894 747 {
elessair 0:f269e3021894 748 if (serial_is_irq_en(obj, RxIrq)) {
elessair 0:f269e3021894 749 (*obj->serial.irq_handler_rx_async)();
elessair 0:f269e3021894 750 }
elessair 0:f269e3021894 751 if (serial_is_irq_en(obj, TxIrq)) {
elessair 0:f269e3021894 752 (*obj->serial.irq_handler_tx_async)();
elessair 0:f269e3021894 753 }
elessair 0:f269e3021894 754 }
elessair 0:f269e3021894 755
elessair 0:f269e3021894 756 static void serial_rx_set_char_match(serial_t *obj, uint8_t char_match)
elessair 0:f269e3021894 757 {
elessair 0:f269e3021894 758 obj->char_match = char_match;
elessair 0:f269e3021894 759 obj->char_found = 0;
elessair 0:f269e3021894 760 }
elessair 0:f269e3021894 761
elessair 0:f269e3021894 762 static void serial_tx_enable_event(serial_t *obj, int event, uint8_t enable)
elessair 0:f269e3021894 763 {
elessair 0:f269e3021894 764 obj->serial.event &= ~SERIAL_EVENT_TX_MASK;
elessair 0:f269e3021894 765 obj->serial.event |= (event & SERIAL_EVENT_TX_MASK);
elessair 0:f269e3021894 766
elessair 0:f269e3021894 767 //if (event & SERIAL_EVENT_TX_COMPLETE) {
elessair 0:f269e3021894 768 //}
elessair 0:f269e3021894 769 }
elessair 0:f269e3021894 770
elessair 0:f269e3021894 771 static void serial_rx_enable_event(serial_t *obj, int event, uint8_t enable)
elessair 0:f269e3021894 772 {
elessair 0:f269e3021894 773 obj->serial.event &= ~SERIAL_EVENT_RX_MASK;
elessair 0:f269e3021894 774 obj->serial.event |= (event & SERIAL_EVENT_RX_MASK);
elessair 0:f269e3021894 775
elessair 0:f269e3021894 776 //if (event & SERIAL_EVENT_RX_COMPLETE) {
elessair 0:f269e3021894 777 //}
elessair 0:f269e3021894 778 //if (event & SERIAL_EVENT_RX_OVERRUN_ERROR) {
elessair 0:f269e3021894 779 //}
elessair 0:f269e3021894 780 if (event & SERIAL_EVENT_RX_FRAMING_ERROR) {
elessair 0:f269e3021894 781 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_RLSIEN_Msk);
elessair 0:f269e3021894 782 }
elessair 0:f269e3021894 783 if (event & SERIAL_EVENT_RX_PARITY_ERROR) {
elessair 0:f269e3021894 784 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_RLSIEN_Msk);
elessair 0:f269e3021894 785 }
elessair 0:f269e3021894 786 if (event & SERIAL_EVENT_RX_OVERFLOW) {
elessair 0:f269e3021894 787 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_BUFERRIEN_Msk);
elessair 0:f269e3021894 788 }
elessair 0:f269e3021894 789 //if (event & SERIAL_EVENT_RX_CHARACTER_MATCH) {
elessair 0:f269e3021894 790 //}
elessair 0:f269e3021894 791 }
elessair 0:f269e3021894 792
elessair 0:f269e3021894 793 static int serial_is_tx_complete(serial_t *obj)
elessair 0:f269e3021894 794 {
elessair 0:f269e3021894 795 // NOTE: Exclude tx fifo empty check due to no such interrupt on DMA way
elessair 0:f269e3021894 796 //return (obj->tx_buff.pos == obj->tx_buff.length) && UART_GET_TX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart)));
elessair 0:f269e3021894 797 // FIXME: Premature abort???
elessair 0:f269e3021894 798 return (obj->tx_buff.pos == obj->tx_buff.length);
elessair 0:f269e3021894 799 }
elessair 0:f269e3021894 800
elessair 0:f269e3021894 801 static int serial_is_rx_complete(serial_t *obj)
elessair 0:f269e3021894 802 {
elessair 0:f269e3021894 803 //return (obj->rx_buff.pos == obj->rx_buff.length) && UART_GET_RX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart)));
elessair 0:f269e3021894 804 return (obj->rx_buff.pos == obj->rx_buff.length);
elessair 0:f269e3021894 805 }
elessair 0:f269e3021894 806
elessair 0:f269e3021894 807 static uint32_t serial_tx_event_check(serial_t *obj)
elessair 0:f269e3021894 808 {
elessair 0:f269e3021894 809 UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart);
elessair 0:f269e3021894 810
elessair 0:f269e3021894 811 if (uart_base->INTSTS & UART_INTSTS_THREINT_Msk) {
elessair 0:f269e3021894 812 // Simulate clear of the interrupt flag. Temporarily disable the interrupt here and to be recovered on next write.
elessair 0:f269e3021894 813 UART_DISABLE_INT(uart_base, UART_INTEN_THREIEN_Msk);
elessair 0:f269e3021894 814 }
elessair 0:f269e3021894 815
elessair 0:f269e3021894 816 uint32_t event = 0;
elessair 0:f269e3021894 817
elessair 0:f269e3021894 818 if (obj->serial.dma_usage_tx == DMA_USAGE_NEVER) {
elessair 0:f269e3021894 819 serial_write_async(obj);
elessair 0:f269e3021894 820 }
elessair 0:f269e3021894 821
elessair 0:f269e3021894 822 if (serial_is_tx_complete(obj)) {
elessair 0:f269e3021894 823 event |= SERIAL_EVENT_TX_COMPLETE;
elessair 0:f269e3021894 824 }
elessair 0:f269e3021894 825
elessair 0:f269e3021894 826 return event;
elessair 0:f269e3021894 827 }
elessair 0:f269e3021894 828
elessair 0:f269e3021894 829 static uint32_t serial_rx_event_check(serial_t *obj)
elessair 0:f269e3021894 830 {
elessair 0:f269e3021894 831 UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart);
elessair 0:f269e3021894 832
elessair 0:f269e3021894 833 if (uart_base->INTSTS & (UART_INTSTS_RDAINT_Msk | UART_INTSTS_RXTOINT_Msk)) {
elessair 0:f269e3021894 834 // Simulate clear of the interrupt flag. Temporarily disable the interrupt here and to be recovered on next read.
elessair 0:f269e3021894 835 UART_DISABLE_INT(uart_base, (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
elessair 0:f269e3021894 836 }
elessair 0:f269e3021894 837
elessair 0:f269e3021894 838 uint32_t event = 0;
elessair 0:f269e3021894 839
elessair 0:f269e3021894 840 if (uart_base->FIFOSTS & UART_FIFOSTS_BIF_Msk) {
elessair 0:f269e3021894 841 uart_base->FIFOSTS = UART_FIFOSTS_BIF_Msk;
elessair 0:f269e3021894 842 }
elessair 0:f269e3021894 843 if (uart_base->FIFOSTS & UART_FIFOSTS_FEF_Msk) {
elessair 0:f269e3021894 844 uart_base->FIFOSTS = UART_FIFOSTS_FEF_Msk;
elessair 0:f269e3021894 845 event |= SERIAL_EVENT_RX_FRAMING_ERROR;
elessair 0:f269e3021894 846 }
elessair 0:f269e3021894 847 if (uart_base->FIFOSTS & UART_FIFOSTS_PEF_Msk) {
elessair 0:f269e3021894 848 uart_base->FIFOSTS = UART_FIFOSTS_PEF_Msk;
elessair 0:f269e3021894 849 event |= SERIAL_EVENT_RX_PARITY_ERROR;
elessair 0:f269e3021894 850 }
elessair 0:f269e3021894 851
elessair 0:f269e3021894 852 if (uart_base->FIFOSTS & UART_FIFOSTS_RXOVIF_Msk) {
elessair 0:f269e3021894 853 uart_base->FIFOSTS = UART_FIFOSTS_RXOVIF_Msk;
elessair 0:f269e3021894 854 event |= SERIAL_EVENT_RX_OVERFLOW;
elessair 0:f269e3021894 855 }
elessair 0:f269e3021894 856
elessair 0:f269e3021894 857 if (obj->serial.dma_usage_rx == DMA_USAGE_NEVER) {
elessair 0:f269e3021894 858 serial_read_async(obj);
elessair 0:f269e3021894 859 }
elessair 0:f269e3021894 860
elessair 0:f269e3021894 861 if (serial_is_rx_complete(obj)) {
elessair 0:f269e3021894 862 event |= SERIAL_EVENT_RX_COMPLETE;
elessair 0:f269e3021894 863 }
elessair 0:f269e3021894 864 if ((obj->char_match != SERIAL_RESERVED_CHAR_MATCH) && obj->char_found) {
elessair 0:f269e3021894 865 event |= SERIAL_EVENT_RX_CHARACTER_MATCH;
elessair 0:f269e3021894 866 // FIXME: Timing to reset char_found?
elessair 0:f269e3021894 867 //obj->char_found = 0;
elessair 0:f269e3021894 868 }
elessair 0:f269e3021894 869
elessair 0:f269e3021894 870 return event;
elessair 0:f269e3021894 871 }
elessair 0:f269e3021894 872
elessair 0:f269e3021894 873 static void uart_dma_handler_tx(uint32_t id, uint32_t event_dma)
elessair 0:f269e3021894 874 {
elessair 0:f269e3021894 875 serial_t *obj = (serial_t *) id;
elessair 0:f269e3021894 876
elessair 0:f269e3021894 877 // FIXME: Pass this error to caller
elessair 0:f269e3021894 878 if (event_dma & DMA_EVENT_ABORT) {
elessair 0:f269e3021894 879 }
elessair 0:f269e3021894 880 // Expect UART IRQ will catch this transfer done event
elessair 0:f269e3021894 881 if (event_dma & DMA_EVENT_TRANSFER_DONE) {
elessair 0:f269e3021894 882 obj->tx_buff.pos = obj->tx_buff.length;
elessair 0:f269e3021894 883 }
elessair 0:f269e3021894 884 // FIXME: Pass this error to caller
elessair 0:f269e3021894 885 if (event_dma & DMA_EVENT_TIMEOUT) {
elessair 0:f269e3021894 886 }
elessair 0:f269e3021894 887
elessair 0:f269e3021894 888 uart_irq_async(obj);
elessair 0:f269e3021894 889 }
elessair 0:f269e3021894 890
elessair 0:f269e3021894 891 static void uart_dma_handler_rx(uint32_t id, uint32_t event_dma)
elessair 0:f269e3021894 892 {
elessair 0:f269e3021894 893 serial_t *obj = (serial_t *) id;
elessair 0:f269e3021894 894
elessair 0:f269e3021894 895 // FIXME: Pass this error to caller
elessair 0:f269e3021894 896 if (event_dma & DMA_EVENT_ABORT) {
elessair 0:f269e3021894 897 }
elessair 0:f269e3021894 898 // Expect UART IRQ will catch this transfer done event
elessair 0:f269e3021894 899 if (event_dma & DMA_EVENT_TRANSFER_DONE) {
elessair 0:f269e3021894 900 obj->rx_buff.pos = obj->rx_buff.length;
elessair 0:f269e3021894 901 }
elessair 0:f269e3021894 902 // FIXME: Pass this error to caller
elessair 0:f269e3021894 903 if (event_dma & DMA_EVENT_TIMEOUT) {
elessair 0:f269e3021894 904 }
elessair 0:f269e3021894 905
elessair 0:f269e3021894 906 uart_irq_async(obj);
elessair 0:f269e3021894 907 }
elessair 0:f269e3021894 908
elessair 0:f269e3021894 909 static int serial_write_async(serial_t *obj)
elessair 0:f269e3021894 910 {
elessair 0:f269e3021894 911 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
elessair 0:f269e3021894 912 MBED_ASSERT(modinit != NULL);
elessair 0:f269e3021894 913 MBED_ASSERT(modinit->modname == obj->serial.uart);
elessair 0:f269e3021894 914
elessair 0:f269e3021894 915 UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart);
elessair 0:f269e3021894 916
elessair 0:f269e3021894 917 uint32_t tx_fifo_max = ((struct nu_uart_var *) modinit->var)->fifo_size_tx;
elessair 0:f269e3021894 918 uint32_t tx_fifo_busy = (uart_base->FIFOSTS & UART_FIFOSTS_TXPTR_Msk) >> UART_FIFOSTS_TXPTR_Pos;
elessair 0:f269e3021894 919 if (uart_base->FIFOSTS & UART_FIFOSTS_TXFULL_Msk) {
elessair 0:f269e3021894 920 tx_fifo_busy = tx_fifo_max;
elessair 0:f269e3021894 921 }
elessair 0:f269e3021894 922 uint32_t tx_fifo_free = tx_fifo_max - tx_fifo_busy;
elessair 0:f269e3021894 923 if (tx_fifo_free == 0) {
elessair 0:f269e3021894 924 // Simulate clear of the interrupt flag
elessair 0:f269e3021894 925 if (obj->serial.inten_msk & UART_INTEN_THREIEN_Msk) {
elessair 0:f269e3021894 926 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk);
elessair 0:f269e3021894 927 }
elessair 0:f269e3021894 928 return 0;
elessair 0:f269e3021894 929 }
elessair 0:f269e3021894 930
elessair 0:f269e3021894 931 uint32_t bytes_per_word = obj->tx_buff.width / 8;
elessair 0:f269e3021894 932
elessair 0:f269e3021894 933 uint8_t *tx = (uint8_t *)(obj->tx_buff.buffer) + bytes_per_word * obj->tx_buff.pos;
elessair 0:f269e3021894 934 int n_words = 0;
elessair 0:f269e3021894 935 while (obj->tx_buff.pos < obj->tx_buff.length && tx_fifo_free >= bytes_per_word) {
elessair 0:f269e3021894 936 switch (bytes_per_word) {
elessair 0:f269e3021894 937 case 4:
elessair 0:f269e3021894 938 UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), *tx ++);
elessair 0:f269e3021894 939 UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), *tx ++);
elessair 0:f269e3021894 940 case 2:
elessair 0:f269e3021894 941 UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), *tx ++);
elessair 0:f269e3021894 942 case 1:
elessair 0:f269e3021894 943 UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), *tx ++);
elessair 0:f269e3021894 944 }
elessair 0:f269e3021894 945
elessair 0:f269e3021894 946 n_words ++;
elessair 0:f269e3021894 947 tx_fifo_free -= bytes_per_word;
elessair 0:f269e3021894 948 obj->tx_buff.pos ++;
elessair 0:f269e3021894 949 }
elessair 0:f269e3021894 950
elessair 0:f269e3021894 951 if (n_words) {
elessair 0:f269e3021894 952 // Simulate clear of the interrupt flag
elessair 0:f269e3021894 953 if (obj->serial.inten_msk & UART_INTEN_THREIEN_Msk) {
elessair 0:f269e3021894 954 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk);
elessair 0:f269e3021894 955 }
elessair 0:f269e3021894 956 }
elessair 0:f269e3021894 957
elessair 0:f269e3021894 958 return n_words;
elessair 0:f269e3021894 959 }
elessair 0:f269e3021894 960
elessair 0:f269e3021894 961 static int serial_read_async(serial_t *obj)
elessair 0:f269e3021894 962 {
elessair 0:f269e3021894 963 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
elessair 0:f269e3021894 964 MBED_ASSERT(modinit != NULL);
elessair 0:f269e3021894 965 MBED_ASSERT(modinit->modname == obj->serial.uart);
elessair 0:f269e3021894 966
elessair 0:f269e3021894 967 uint32_t rx_fifo_busy = (((UART_T *) NU_MODBASE(obj->serial.uart))->FIFOSTS & UART_FIFOSTS_RXPTR_Msk) >> UART_FIFOSTS_RXPTR_Pos;
elessair 0:f269e3021894 968 //uint32_t rx_fifo_free = ((struct nu_uart_var *) modinit->var)->fifo_size_rx - rx_fifo_busy;
elessair 0:f269e3021894 969 //if (rx_fifo_free == 0) {
elessair 0:f269e3021894 970 // return 0;
elessair 0:f269e3021894 971 //}
elessair 0:f269e3021894 972
elessair 0:f269e3021894 973 uint32_t bytes_per_word = obj->rx_buff.width / 8;
elessair 0:f269e3021894 974
elessair 0:f269e3021894 975 uint8_t *rx = (uint8_t *)(obj->rx_buff.buffer) + bytes_per_word * obj->rx_buff.pos;
elessair 0:f269e3021894 976 int n_words = 0;
elessair 0:f269e3021894 977 while (obj->rx_buff.pos < obj->rx_buff.length && rx_fifo_busy >= bytes_per_word) {
elessair 0:f269e3021894 978 switch (bytes_per_word) {
elessair 0:f269e3021894 979 case 4:
elessair 0:f269e3021894 980 *rx ++ = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart)));
elessair 0:f269e3021894 981 *rx ++ = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart)));
elessair 0:f269e3021894 982 case 2:
elessair 0:f269e3021894 983 *rx ++ = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart)));
elessair 0:f269e3021894 984 case 1:
elessair 0:f269e3021894 985 *rx ++ = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart)));
elessair 0:f269e3021894 986 }
elessair 0:f269e3021894 987
elessair 0:f269e3021894 988 n_words ++;
elessair 0:f269e3021894 989 rx_fifo_busy -= bytes_per_word;
elessair 0:f269e3021894 990 obj->rx_buff.pos ++;
elessair 0:f269e3021894 991
elessair 0:f269e3021894 992 if ((obj->serial.event & SERIAL_EVENT_RX_CHARACTER_MATCH) &&
elessair 0:f269e3021894 993 obj->char_match != SERIAL_RESERVED_CHAR_MATCH) {
elessair 0:f269e3021894 994 uint8_t *rx_cmp = rx;
elessair 0:f269e3021894 995 switch (bytes_per_word) {
elessair 0:f269e3021894 996 case 4:
elessair 0:f269e3021894 997 rx_cmp -= 2;
elessair 0:f269e3021894 998 case 2:
elessair 0:f269e3021894 999 rx_cmp --;
elessair 0:f269e3021894 1000 case 1:
elessair 0:f269e3021894 1001 rx_cmp --;
elessair 0:f269e3021894 1002 }
elessair 0:f269e3021894 1003 if (*rx_cmp == obj->char_match) {
elessair 0:f269e3021894 1004 obj->char_found = 1;
elessair 0:f269e3021894 1005 break;
elessair 0:f269e3021894 1006 }
elessair 0:f269e3021894 1007 }
elessair 0:f269e3021894 1008 }
elessair 0:f269e3021894 1009
elessair 0:f269e3021894 1010 if (n_words) {
elessair 0:f269e3021894 1011 // Simulate clear of the interrupt flag
elessair 0:f269e3021894 1012 if (obj->serial.inten_msk & (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)) {
elessair 0:f269e3021894 1013 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
elessair 0:f269e3021894 1014 }
elessair 0:f269e3021894 1015 }
elessair 0:f269e3021894 1016
elessair 0:f269e3021894 1017 return n_words;
elessair 0:f269e3021894 1018 }
elessair 0:f269e3021894 1019
elessair 0:f269e3021894 1020 static void serial_tx_buffer_set(serial_t *obj, const void *tx, size_t length, uint8_t width)
elessair 0:f269e3021894 1021 {
elessair 0:f269e3021894 1022 obj->tx_buff.buffer = (void *) tx;
elessair 0:f269e3021894 1023 obj->tx_buff.length = length;
elessair 0:f269e3021894 1024 obj->tx_buff.pos = 0;
elessair 0:f269e3021894 1025 obj->tx_buff.width = width;
elessair 0:f269e3021894 1026 }
elessair 0:f269e3021894 1027
elessair 0:f269e3021894 1028 static void serial_rx_buffer_set(serial_t *obj, void *rx, size_t length, uint8_t width)
elessair 0:f269e3021894 1029 {
elessair 0:f269e3021894 1030 obj->rx_buff.buffer = rx;
elessair 0:f269e3021894 1031 obj->rx_buff.length = length;
elessair 0:f269e3021894 1032 obj->rx_buff.pos = 0;
elessair 0:f269e3021894 1033 obj->rx_buff.width = width;
elessair 0:f269e3021894 1034 }
elessair 0:f269e3021894 1035
elessair 0:f269e3021894 1036 static void serial_tx_enable_interrupt(serial_t *obj, uint32_t handler, uint8_t enable)
elessair 0:f269e3021894 1037 {
elessair 0:f269e3021894 1038 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
elessair 0:f269e3021894 1039 MBED_ASSERT(modinit != NULL);
elessair 0:f269e3021894 1040 MBED_ASSERT(modinit->modname == obj->serial.uart);
elessair 0:f269e3021894 1041
elessair 0:f269e3021894 1042 // Necessary for both interrupt way and DMA way
elessair 0:f269e3021894 1043 ((struct nu_uart_var *) modinit->var)->obj = obj;
elessair 0:f269e3021894 1044 // With our own async vector, tx/rx handlers can be different.
elessair 0:f269e3021894 1045 obj->serial.vec = ((struct nu_uart_var *) modinit->var)->vec_async;
elessair 0:f269e3021894 1046 obj->serial.irq_handler_tx_async = (void (*)(void)) handler;
elessair 0:f269e3021894 1047 serial_irq_set(obj, TxIrq, enable);
elessair 0:f269e3021894 1048 }
elessair 0:f269e3021894 1049
elessair 0:f269e3021894 1050 static void serial_rx_enable_interrupt(serial_t *obj, uint32_t handler, uint8_t enable)
elessair 0:f269e3021894 1051 {
elessair 0:f269e3021894 1052 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
elessair 0:f269e3021894 1053 MBED_ASSERT(modinit != NULL);
elessair 0:f269e3021894 1054 MBED_ASSERT(modinit->modname == obj->serial.uart);
elessair 0:f269e3021894 1055
elessair 0:f269e3021894 1056 // Necessary for both interrupt way and DMA way
elessair 0:f269e3021894 1057 ((struct nu_uart_var *) modinit->var)->obj = obj;
elessair 0:f269e3021894 1058 // With our own async vector, tx/rx handlers can be different.
elessair 0:f269e3021894 1059 obj->serial.vec = ((struct nu_uart_var *) modinit->var)->vec_async;
elessair 0:f269e3021894 1060 obj->serial.irq_handler_rx_async = (void (*) (void)) handler;
elessair 0:f269e3021894 1061 serial_irq_set(obj, RxIrq, enable);
elessair 0:f269e3021894 1062 }
elessair 0:f269e3021894 1063
elessair 0:f269e3021894 1064 static void serial_check_dma_usage(DMAUsage *dma_usage, int *dma_ch)
elessair 0:f269e3021894 1065 {
elessair 0:f269e3021894 1066 if (*dma_usage != DMA_USAGE_NEVER) {
elessair 0:f269e3021894 1067 if (*dma_ch == DMA_ERROR_OUT_OF_CHANNELS) {
elessair 0:f269e3021894 1068 *dma_ch = dma_channel_allocate(DMA_CAP_NONE);
elessair 0:f269e3021894 1069 }
elessair 0:f269e3021894 1070 if (*dma_ch == DMA_ERROR_OUT_OF_CHANNELS) {
elessair 0:f269e3021894 1071 *dma_usage = DMA_USAGE_NEVER;
elessair 0:f269e3021894 1072 }
elessair 0:f269e3021894 1073 }
elessair 0:f269e3021894 1074 else {
elessair 0:f269e3021894 1075 dma_channel_free(*dma_ch);
elessair 0:f269e3021894 1076 *dma_ch = DMA_ERROR_OUT_OF_CHANNELS;
elessair 0:f269e3021894 1077 }
elessair 0:f269e3021894 1078 }
elessair 0:f269e3021894 1079
elessair 0:f269e3021894 1080 static int serial_is_irq_en(serial_t *obj, SerialIrq irq)
elessair 0:f269e3021894 1081 {
elessair 0:f269e3021894 1082 int inten_msk = 0;
elessair 0:f269e3021894 1083
elessair 0:f269e3021894 1084 switch (irq) {
elessair 0:f269e3021894 1085 case RxIrq:
elessair 0:f269e3021894 1086 inten_msk = obj->serial.inten_msk & (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk);
elessair 0:f269e3021894 1087 break;
elessair 0:f269e3021894 1088 case TxIrq:
elessair 0:f269e3021894 1089 inten_msk = obj->serial.inten_msk & UART_INTEN_THREIEN_Msk;
elessair 0:f269e3021894 1090 break;
elessair 0:f269e3021894 1091 }
elessair 0:f269e3021894 1092
elessair 0:f269e3021894 1093 return !! inten_msk;
elessair 0:f269e3021894 1094 }
elessair 0:f269e3021894 1095
elessair 0:f269e3021894 1096 #endif // #if DEVICE_SERIAL_ASYNCH
elessair 0:f269e3021894 1097 #endif // #if DEVICE_SERIAL