Lee Kai Xuan / mbed-os

mbed-os

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targets/TARGET_Maxim/TARGET_MAX32600/sleep.c@0:f269e3021894, 2016-10-23 (annotated)

Committer:
elessair
Date:
Sun Oct 23 15:10:02 2016 +0000
Revision:
0:f269e3021894
Initial commit

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elessair 0:f269e3021894 1 /*******************************************************************************
elessair 0:f269e3021894 2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
elessair 0:f269e3021894 3 *
elessair 0:f269e3021894 4 * Permission is hereby granted, free of charge, to any person obtaining a
elessair 0:f269e3021894 5 * copy of this software and associated documentation files (the "Software"),
elessair 0:f269e3021894 6 * to deal in the Software without restriction, including without limitation
elessair 0:f269e3021894 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
elessair 0:f269e3021894 8 * and/or sell copies of the Software, and to permit persons to whom the
elessair 0:f269e3021894 9 * Software is furnished to do so, subject to the following conditions:
elessair 0:f269e3021894 10 *
elessair 0:f269e3021894 11 * The above copyright notice and this permission notice shall be included
elessair 0:f269e3021894 12 * in all copies or substantial portions of the Software.
elessair 0:f269e3021894 13 *
elessair 0:f269e3021894 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
elessair 0:f269e3021894 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
elessair 0:f269e3021894 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
elessair 0:f269e3021894 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
elessair 0:f269e3021894 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
elessair 0:f269e3021894 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
elessair 0:f269e3021894 20 * OTHER DEALINGS IN THE SOFTWARE.
elessair 0:f269e3021894 21 *
elessair 0:f269e3021894 22 * Except as contained in this notice, the name of Maxim Integrated
elessair 0:f269e3021894 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
elessair 0:f269e3021894 24 * Products, Inc. Branding Policy.
elessair 0:f269e3021894 25 *
elessair 0:f269e3021894 26 * The mere transfer of this software does not imply any licenses
elessair 0:f269e3021894 27 * of trade secrets, proprietary technology, copyrights, patents,
elessair 0:f269e3021894 28 * trademarks, maskwork rights, or any other form of intellectual
elessair 0:f269e3021894 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
elessair 0:f269e3021894 30 * ownership rights.
elessair 0:f269e3021894 31 *******************************************************************************
elessair 0:f269e3021894 32 */
elessair 0:f269e3021894 33
elessair 0:f269e3021894 34 #include "sleep_api.h"
elessair 0:f269e3021894 35 #include "cmsis.h"
elessair 0:f269e3021894 36 #include "pwrman_regs.h"
elessair 0:f269e3021894 37 #include "pwrseq_regs.h"
elessair 0:f269e3021894 38 #include "ioman_regs.h"
elessair 0:f269e3021894 39 #include "rtc_regs.h"
elessair 0:f269e3021894 40
elessair 0:f269e3021894 41 static mxc_uart_regs_t *stdio_uart = (mxc_uart_regs_t*)STDIO_UART;
elessair 0:f269e3021894 42
elessair 0:f269e3021894 43 // Normal wait mode
elessair 0:f269e3021894 44 void sleep(void)
elessair 0:f269e3021894 45 {
elessair 0:f269e3021894 46 // Normal sleep mode for ARM core
elessair 0:f269e3021894 47 SCB->SCR = 0;
elessair 0:f269e3021894 48
elessair 0:f269e3021894 49 __DSB();
elessair 0:f269e3021894 50 __WFI();
elessair 0:f269e3021894 51 }
elessair 0:f269e3021894 52
elessair 0:f269e3021894 53 // Work-around for issue of clearing power sequencer I/O flag
elessair 0:f269e3021894 54 static void clearAllGPIOWUD(void)
elessair 0:f269e3021894 55 {
elessair 0:f269e3021894 56 uint32_t wud_req0 = MXC_IOMAN->wud_req0;
elessair 0:f269e3021894 57 uint32_t wud_req1 = MXC_IOMAN->wud_req1;
elessair 0:f269e3021894 58
elessair 0:f269e3021894 59 // I/O must be a wakeup detect to clear
elessair 0:f269e3021894 60 MXC_IOMAN->wud_req0 = 0xffffffff;
elessair 0:f269e3021894 61 MXC_IOMAN->wud_req1 = 0xffffffff;
elessair 0:f269e3021894 62
elessair 0:f269e3021894 63 // Clear all WUDs
elessair 0:f269e3021894 64 MXC_PWRMAN->wud_ctrl = (MXC_E_PWRMAN_PAD_MODE_CLEAR_SET << MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS) | MXC_F_PWRMAN_WUD_CTRL_CLEAR_ALL;
elessair 0:f269e3021894 65 MXC_PWRMAN->wud_pulse0 = 1;
elessair 0:f269e3021894 66
elessair 0:f269e3021894 67 // Restore WUD requests
elessair 0:f269e3021894 68 MXC_IOMAN->wud_req0 = wud_req0;
elessair 0:f269e3021894 69 MXC_IOMAN->wud_req1 = wud_req1;
elessair 0:f269e3021894 70 }
elessair 0:f269e3021894 71
elessair 0:f269e3021894 72 // Low-power stop mode
elessair 0:f269e3021894 73 void deepsleep(void)
elessair 0:f269e3021894 74 {
elessair 0:f269e3021894 75 __disable_irq();
elessair 0:f269e3021894 76
elessair 0:f269e3021894 77 // Wait for all STDIO characters to be sent. The UART clock will stop.
elessair 0:f269e3021894 78 while (stdio_uart->status & MXC_F_UART_STATUS_TX_BUSY);
elessair 0:f269e3021894 79
elessair 0:f269e3021894 80 // Prepare for LP1
elessair 0:f269e3021894 81 uint32_t reg0 = MXC_PWRSEQ->reg0;
elessair 0:f269e3021894 82 reg0 &= ~MXC_F_PWRSEQ_REG0_PWR_SVM3EN_SLP; // disable VDD3 SVM during sleep mode
elessair 0:f269e3021894 83 reg0 &= ~MXC_F_PWRSEQ_REG0_PWR_SVM1EN_SLP; // disable VREG18 SVM during sleep mode
elessair 0:f269e3021894 84 if (reg0 & MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN) { // if real-time clock enabled during run
elessair 0:f269e3021894 85 reg0 |= MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP; // enable real-time clock during sleep mode
elessair 0:f269e3021894 86 } else {
elessair 0:f269e3021894 87 reg0 &= ~MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP; // disable real-time clock during sleep mode
elessair 0:f269e3021894 88 }
elessair 0:f269e3021894 89 reg0 |= MXC_F_PWRSEQ_REG0_PWR_CHZYEN_SLP; // enable CHZY regulator during sleep mode
elessair 0:f269e3021894 90 reg0 |= MXC_F_PWRSEQ_REG0_PWR_LP1; // go into LP1
elessair 0:f269e3021894 91 reg0 &= ~MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT; // clear first boot flag
elessair 0:f269e3021894 92 MXC_PWRSEQ->reg0 = reg0;
elessair 0:f269e3021894 93
elessair 0:f269e3021894 94 MXC_PWRSEQ->reg3 = (MXC_PWRSEQ->reg3 & ~MXC_F_PWRSEQ_REG3_PWR_ROSEL_QUICK) | (3 << MXC_F_PWRSEQ_REG3_PWR_ROSEL_QUICK_POS);
elessair 0:f269e3021894 95
elessair 0:f269e3021894 96 // Deep sleep for ARM core
elessair 0:f269e3021894 97 SCB->SCR = SCB_SCR_SLEEPDEEP_Msk;
elessair 0:f269e3021894 98
elessair 0:f269e3021894 99 // clear latches for wakeup detect
elessair 0:f269e3021894 100 MXC_PWRSEQ->flags = MXC_PWRSEQ->flags;
elessair 0:f269e3021894 101 if (MXC_PWRSEQ->flags & MXC_F_PWRSEQ_FLAGS_PWR_IO_WAKEUP) {
elessair 0:f269e3021894 102 // attempt work-around for I/O flag clearing issue
elessair 0:f269e3021894 103 clearAllGPIOWUD();
elessair 0:f269e3021894 104 MXC_PWRSEQ->flags = MXC_F_PWRSEQ_FLAGS_PWR_IO_WAKEUP;
elessair 0:f269e3021894 105 }
elessair 0:f269e3021894 106
elessair 0:f269e3021894 107 // Wait for pending RTC transaction
elessair 0:f269e3021894 108 while (MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING);
elessair 0:f269e3021894 109
elessair 0:f269e3021894 110 // Ensure that the event register is clear
elessair 0:f269e3021894 111 __SEV(); // set event
elessair 0:f269e3021894 112 __WFE(); // clear event
elessair 0:f269e3021894 113
elessair 0:f269e3021894 114 // Enter LP1
elessair 0:f269e3021894 115 __WFE();
elessair 0:f269e3021894 116 // Woke up from LP1
elessair 0:f269e3021894 117
elessair 0:f269e3021894 118 // The RTC timer does not update until the next tick
elessair 0:f269e3021894 119 uint32_t temp = MXC_RTCTMR->timer;
elessair 0:f269e3021894 120 while (MXC_RTCTMR->timer == temp);
elessair 0:f269e3021894 121
elessair 0:f269e3021894 122 __enable_irq();
elessair 0:f269e3021894 123 }