Lee Kai Xuan / mbed-os

mbed-os

Fork of mbed-os by erkin yucel

targets/TARGET_Freescale/TARGET_KLXX/rtc_api.c@0:f269e3021894, 2016-10-23 (annotated)

Committer:
elessair
Date:
Sun Oct 23 15:10:02 2016 +0000
Revision:
0:f269e3021894
Initial commit

Who changed what in which revision?

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elessair 0:f269e3021894 1 /* mbed Microcontroller Library
elessair 0:f269e3021894 2 * Copyright (c) 2006-2013 ARM Limited
elessair 0:f269e3021894 3 *
elessair 0:f269e3021894 4 * Licensed under the Apache License, Version 2.0 (the "License");
elessair 0:f269e3021894 5 * you may not use this file except in compliance with the License.
elessair 0:f269e3021894 6 * You may obtain a copy of the License at
elessair 0:f269e3021894 7 *
elessair 0:f269e3021894 8 * http://www.apache.org/licenses/LICENSE-2.0
elessair 0:f269e3021894 9 *
elessair 0:f269e3021894 10 * Unless required by applicable law or agreed to in writing, software
elessair 0:f269e3021894 11 * distributed under the License is distributed on an "AS IS" BASIS,
elessair 0:f269e3021894 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
elessair 0:f269e3021894 13 * See the License for the specific language governing permissions and
elessair 0:f269e3021894 14 * limitations under the License.
elessair 0:f269e3021894 15 */
elessair 0:f269e3021894 16
elessair 0:f269e3021894 17 #if DEVICE_RTC
elessair 0:f269e3021894 18
elessair 0:f269e3021894 19 #include "rtc_api.h"
elessair 0:f269e3021894 20 #include "PeripheralPins.h"
elessair 0:f269e3021894 21 #include "clk_freqs.h"
elessair 0:f269e3021894 22
elessair 0:f269e3021894 23 static void init(void) {
elessair 0:f269e3021894 24 // enable RTC clock
elessair 0:f269e3021894 25 SIM->SCGC6 |= SIM_SCGC6_RTC_MASK;
elessair 0:f269e3021894 26
elessair 0:f269e3021894 27 // select RTC clock source
elessair 0:f269e3021894 28 SIM->SOPT1 &= ~SIM_SOPT1_OSC32KSEL_MASK;
elessair 0:f269e3021894 29
elessair 0:f269e3021894 30 // Enable external crystal source if clock source is 32KHz
elessair 0:f269e3021894 31 if (extosc_frequency()==32768) {
elessair 0:f269e3021894 32 SIM->SOPT1 |= SIM_SOPT1_OSC32KSEL(OSC32KCLK);
elessair 0:f269e3021894 33 }
elessair 0:f269e3021894 34 else{
elessair 0:f269e3021894 35 // If main clock is NOT 32KHz crystal, use external 32KHz clock source defined in PeripheralPins.c
elessair 0:f269e3021894 36 SIM->SOPT1 |= SIM_SOPT1_OSC32KSEL(PinMap_RTC[0].peripheral);
elessair 0:f269e3021894 37 pinmap_pinout(PinMap_RTC[0].pin, PinMap_RTC); //Map RTC clk input (if not NC)
elessair 0:f269e3021894 38 }
elessair 0:f269e3021894 39 }
elessair 0:f269e3021894 40
elessair 0:f269e3021894 41 void rtc_init(void) {
elessair 0:f269e3021894 42 init();
elessair 0:f269e3021894 43
elessair 0:f269e3021894 44 // Configure the TSR. default value: 1
elessair 0:f269e3021894 45 RTC->TSR = 1;
elessair 0:f269e3021894 46
elessair 0:f269e3021894 47 // Configure Time Compensation Register to calibrate RTC accuracy
elessair 0:f269e3021894 48
elessair 0:f269e3021894 49 // dissable LRL lock
elessair 0:f269e3021894 50 RTC->LR &= ~RTC_LR_LRL_MASK;
elessair 0:f269e3021894 51 // RTC->TCR: RTC_TCR_CIR_MASK,RTC_TCR_CIR(x)=0,RTC_TCR_TCR(x)=0 Default no correction
elessair 0:f269e3021894 52 RTC->TCR = RTC_TCR_CIR(0) | RTC_TCR_TCR(0);
elessair 0:f269e3021894 53 /*
elessair 0:f269e3021894 54 RTC_TCR_CIR(x) sets the compensation interval in seconds from 1 to 256.
elessair 0:f269e3021894 55 0x05 will apply the compensation once every 4 seconds.
elessair 0:f269e3021894 56
elessair 0:f269e3021894 57 RTC_TCR_TCR(x) sets the Register Overflow
elessair 0:f269e3021894 58 0x80 Time Prescaler Register overflows every 32896 clock cycles. (+128)
elessair 0:f269e3021894 59 ... ... RTC runs slower
elessair 0:f269e3021894 60 0xFF Time Prescaler Register overflows every 32769 clock cycles.
elessair 0:f269e3021894 61 0x00 Time Prescaler Register overflows every 32768 clock cycles, Default.
elessair 0:f269e3021894 62 0x01 Time Prescaler Register overflows every 32767 clock cycles.
elessair 0:f269e3021894 63 ... ... RTC runs faster
elessair 0:f269e3021894 64 0x7F Time Prescaler Register overflows every 32641 clock cycles. (-128)
elessair 0:f269e3021894 65 */
elessair 0:f269e3021894 66 // enable TCL lock
elessair 0:f269e3021894 67 RTC->LR |= RTC_LR_TCL_MASK;
elessair 0:f269e3021894 68 // enable LRL lock
elessair 0:f269e3021894 69 RTC->LR |= RTC_LR_LRL_MASK;
elessair 0:f269e3021894 70
elessair 0:f269e3021894 71 // enable counter
elessair 0:f269e3021894 72 RTC->SR |= RTC_SR_TCE_MASK;
elessair 0:f269e3021894 73 }
elessair 0:f269e3021894 74
elessair 0:f269e3021894 75 void rtc_free(void) {
elessair 0:f269e3021894 76 // [TODO]
elessair 0:f269e3021894 77 }
elessair 0:f269e3021894 78
elessair 0:f269e3021894 79 /*
elessair 0:f269e3021894 80 * Little check routine to see if the RTC has been enabled
elessair 0:f269e3021894 81 * 0 = Disabled, 1 = Enabled
elessair 0:f269e3021894 82 */
elessair 0:f269e3021894 83 int rtc_isenabled(void) {
elessair 0:f269e3021894 84 // even if the RTC module is enabled,
elessair 0:f269e3021894 85 // as we use RTC_CLKIN and an external clock,
elessair 0:f269e3021894 86 // we need to reconfigure the pins. That is why we
elessair 0:f269e3021894 87 // call init() if the rtc is enabled
elessair 0:f269e3021894 88
elessair 0:f269e3021894 89 // if RTC not enabled return 0
elessair 0:f269e3021894 90 SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK;
elessair 0:f269e3021894 91 SIM->SCGC6 |= SIM_SCGC6_RTC_MASK;
elessair 0:f269e3021894 92 if ((RTC->SR & RTC_SR_TCE_MASK) == 0)
elessair 0:f269e3021894 93 return 0;
elessair 0:f269e3021894 94
elessair 0:f269e3021894 95 init();
elessair 0:f269e3021894 96 return 1;
elessair 0:f269e3021894 97 }
elessair 0:f269e3021894 98
elessair 0:f269e3021894 99 time_t rtc_read(void) {
elessair 0:f269e3021894 100 return RTC->TSR;
elessair 0:f269e3021894 101 }
elessair 0:f269e3021894 102
elessair 0:f269e3021894 103 void rtc_write(time_t t) {
elessair 0:f269e3021894 104 // disable counter
elessair 0:f269e3021894 105 RTC->SR &= ~RTC_SR_TCE_MASK;
elessair 0:f269e3021894 106
elessair 0:f269e3021894 107 // we do not write 0 into TSR
elessair 0:f269e3021894 108 // to avoid invalid time
elessair 0:f269e3021894 109 if (t == 0)
elessair 0:f269e3021894 110 t = 1;
elessair 0:f269e3021894 111
elessair 0:f269e3021894 112 // write seconds
elessair 0:f269e3021894 113 RTC->TSR = t;
elessair 0:f269e3021894 114
elessair 0:f269e3021894 115 // re-enable counter
elessair 0:f269e3021894 116 RTC->SR |= RTC_SR_TCE_MASK;
elessair 0:f269e3021894 117 }
elessair 0:f269e3021894 118
elessair 0:f269e3021894 119 #endif