Lee Kai Xuan / mbed-os

mbed-os

Fork of mbed-os by erkin yucel

targets/TARGET_Freescale/TARGET_K20XX/sleep.c@0:f269e3021894, 2016-10-23 (annotated)

Committer:
elessair
Date:
Sun Oct 23 15:10:02 2016 +0000
Revision:
0:f269e3021894
Initial commit

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elessair 0:f269e3021894 1 /* mbed Microcontroller Library
elessair 0:f269e3021894 2 * Copyright (c) 2006-2015 ARM Limited
elessair 0:f269e3021894 3 *
elessair 0:f269e3021894 4 * Licensed under the Apache License, Version 2.0 (the "License");
elessair 0:f269e3021894 5 * you may not use this file except in compliance with the License.
elessair 0:f269e3021894 6 * You may obtain a copy of the License at
elessair 0:f269e3021894 7 *
elessair 0:f269e3021894 8 * http://www.apache.org/licenses/LICENSE-2.0
elessair 0:f269e3021894 9 *
elessair 0:f269e3021894 10 * Unless required by applicable law or agreed to in writing, software
elessair 0:f269e3021894 11 * distributed under the License is distributed on an "AS IS" BASIS,
elessair 0:f269e3021894 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
elessair 0:f269e3021894 13 * See the License for the specific language governing permissions and
elessair 0:f269e3021894 14 * limitations under the License.
elessair 0:f269e3021894 15 */
elessair 0:f269e3021894 16 #include "sleep_api.h"
elessair 0:f269e3021894 17 #include "cmsis.h"
elessair 0:f269e3021894 18
elessair 0:f269e3021894 19 //Normal wait mode
elessair 0:f269e3021894 20 void sleep(void)
elessair 0:f269e3021894 21 {
elessair 0:f269e3021894 22 SMC->PMPROT = SMC_PMPROT_AVLLS_MASK | SMC_PMPROT_ALLS_MASK | SMC_PMPROT_AVLP_MASK;
elessair 0:f269e3021894 23
elessair 0:f269e3021894 24 //Normal sleep mode for ARM core:
elessair 0:f269e3021894 25 SCB->SCR = 0;
elessair 0:f269e3021894 26 __WFI();
elessair 0:f269e3021894 27 }
elessair 0:f269e3021894 28
elessair 0:f269e3021894 29 //Very low-power stop mode
elessair 0:f269e3021894 30 void deepsleep(void)
elessair 0:f269e3021894 31 {
elessair 0:f269e3021894 32 //Check if ADC is enabled and HS mode is set, if yes disable it (lowers power consumption by 60uA)
elessair 0:f269e3021894 33 uint8_t ADC_HSC = 0;
elessair 0:f269e3021894 34 if (SIM->SCGC6 & SIM_SCGC6_ADC0_MASK) {
elessair 0:f269e3021894 35 if (ADC0->CFG2 & ADC_CFG2_ADHSC_MASK) {
elessair 0:f269e3021894 36 ADC_HSC = 1;
elessair 0:f269e3021894 37 ADC0->CFG2 &= ~(ADC_CFG2_ADHSC_MASK);
elessair 0:f269e3021894 38 }
elessair 0:f269e3021894 39 }
elessair 0:f269e3021894 40
elessair 0:f269e3021894 41 //Check if PLL/FLL is enabled:
elessair 0:f269e3021894 42 uint32_t PLL_FLL_en = (MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(0);
elessair 0:f269e3021894 43
elessair 0:f269e3021894 44 SMC->PMPROT = SMC_PMPROT_AVLLS_MASK | SMC_PMPROT_ALLS_MASK | SMC_PMPROT_AVLP_MASK;
elessair 0:f269e3021894 45 SMC->PMCTRL = SMC_PMCTRL_STOPM(2);
elessair 0:f269e3021894 46
elessair 0:f269e3021894 47 //Deep sleep for ARM core:
elessair 0:f269e3021894 48 SCB->SCR = 1<<SCB_SCR_SLEEPDEEP_Pos;
elessair 0:f269e3021894 49
elessair 0:f269e3021894 50 __WFI();
elessair 0:f269e3021894 51 //Switch back to PLL as clock source if needed
elessair 0:f269e3021894 52 //The interrupt that woke up the device will run at reduced speed
elessair 0:f269e3021894 53 if (PLL_FLL_en) {
elessair 0:f269e3021894 54
elessair 0:f269e3021894 55 #if defined (TARGET_K20D50M)
elessair 0:f269e3021894 56 if (MCG->C6 & (1<<MCG_C6_PLLS_SHIFT) != 0) /* If PLL */
elessair 0:f269e3021894 57 while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U); /* Wait until locked */
elessair 0:f269e3021894 58 MCG->C1 &= ~MCG_C1_CLKS_MASK;
elessair 0:f269e3021894 59 #else
elessair 0:f269e3021894 60 // MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0
elessair 0:f269e3021894 61 MCG->C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(3) | MCG_C1_IRCLKEN_MASK;
elessair 0:f269e3021894 62 // MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0
elessair 0:f269e3021894 63 MCG->C6 = MCG_C6_VDIV0(0);
elessair 0:f269e3021894 64 while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { } // Check that the oscillator is running
elessair 0:f269e3021894 65 while((MCG->S & 0x0Cu) != 0x08u) { } // Wait until external reference clock is selected as MCG output
elessair 0:f269e3021894 66 // MCG->C5: PLLCLKEN=0,PLLSTEN=0,PRDIV0=3
elessair 0:f269e3021894 67 MCG->C5 = MCG_C5_PRDIV0(5);
elessair 0:f269e3021894 68 // MCG->C6: LOLIE=0,PLLS=1,CME=0,VDIV0=3
elessair 0:f269e3021894 69 MCG->C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV0(3);
elessair 0:f269e3021894 70 while((MCG->S & 0x0Cu) != 0x08u) { } // Wait until external reference clock is selected as MCG output
elessair 0:f269e3021894 71 while((MCG->S & MCG_S_PLLST_MASK) == 0u) { } // Wait until the source of the PLLS clock has switched to the PLL
elessair 0:f269e3021894 72 while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { } // Wait until locked
elessair 0:f269e3021894 73 // MCG->C1: CLKS=0,FRDIV=2,IREFS=0,IRCLKEN=1,IREFSTEN=0
elessair 0:f269e3021894 74 MCG->C1 = MCG_C1_FRDIV(2) | MCG_C1_IRCLKEN_MASK;;
elessair 0:f269e3021894 75 while((MCG->S & 0x0Cu) != 0x0Cu) { } // Wait until output of the PLL is selected
elessair 0:f269e3021894 76 while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { } // Wait until locked
elessair 0:f269e3021894 77 #endif
elessair 0:f269e3021894 78 }
elessair 0:f269e3021894 79
elessair 0:f269e3021894 80 if (ADC_HSC) {
elessair 0:f269e3021894 81 ADC0->CFG2 |= (ADC_CFG2_ADHSC_MASK);
elessair 0:f269e3021894 82 }
elessair 0:f269e3021894 83 }