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mbed-os

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cmsis/core_cmSimd.h@0:f269e3021894, 2016-10-23 (annotated)

Committer:
elessair
Date:
Sun Oct 23 15:10:02 2016 +0000
Revision:
0:f269e3021894
Initial commit

Who changed what in which revision?

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elessair 0:f269e3021894 1 /**************************************************************************//**
elessair 0:f269e3021894 2 * @file core_cmSimd.h
elessair 0:f269e3021894 3 * @brief CMSIS Cortex-M SIMD Header File
elessair 0:f269e3021894 4 * @version V4.10
elessair 0:f269e3021894 5 * @date 18. March 2015
elessair 0:f269e3021894 6 *
elessair 0:f269e3021894 7 * @note
elessair 0:f269e3021894 8 *
elessair 0:f269e3021894 9 ******************************************************************************/
elessair 0:f269e3021894 10 /* Copyright (c) 2009 - 2014 ARM LIMITED
elessair 0:f269e3021894 11
elessair 0:f269e3021894 12 All rights reserved.
elessair 0:f269e3021894 13 Redistribution and use in source and binary forms, with or without
elessair 0:f269e3021894 14 modification, are permitted provided that the following conditions are met:
elessair 0:f269e3021894 15 - Redistributions of source code must retain the above copyright
elessair 0:f269e3021894 16 notice, this list of conditions and the following disclaimer.
elessair 0:f269e3021894 17 - Redistributions in binary form must reproduce the above copyright
elessair 0:f269e3021894 18 notice, this list of conditions and the following disclaimer in the
elessair 0:f269e3021894 19 documentation and/or other materials provided with the distribution.
elessair 0:f269e3021894 20 - Neither the name of ARM nor the names of its contributors may be used
elessair 0:f269e3021894 21 to endorse or promote products derived from this software without
elessair 0:f269e3021894 22 specific prior written permission.
elessair 0:f269e3021894 23 *
elessair 0:f269e3021894 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
elessair 0:f269e3021894 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
elessair 0:f269e3021894 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
elessair 0:f269e3021894 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
elessair 0:f269e3021894 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
elessair 0:f269e3021894 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
elessair 0:f269e3021894 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
elessair 0:f269e3021894 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
elessair 0:f269e3021894 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
elessair 0:f269e3021894 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
elessair 0:f269e3021894 34 POSSIBILITY OF SUCH DAMAGE.
elessair 0:f269e3021894 35 ---------------------------------------------------------------------------*/
elessair 0:f269e3021894 36
elessair 0:f269e3021894 37
elessair 0:f269e3021894 38 #if defined ( __ICCARM__ )
elessair 0:f269e3021894 39 #pragma system_include /* treat file as system include file for MISRA check */
elessair 0:f269e3021894 40 #endif
elessair 0:f269e3021894 41
elessair 0:f269e3021894 42 #ifndef __CORE_CMSIMD_H
elessair 0:f269e3021894 43 #define __CORE_CMSIMD_H
elessair 0:f269e3021894 44
elessair 0:f269e3021894 45 #ifdef __cplusplus
elessair 0:f269e3021894 46 extern "C" {
elessair 0:f269e3021894 47 #endif
elessair 0:f269e3021894 48
elessair 0:f269e3021894 49
elessair 0:f269e3021894 50 /*******************************************************************************
elessair 0:f269e3021894 51 * Hardware Abstraction Layer
elessair 0:f269e3021894 52 ******************************************************************************/
elessair 0:f269e3021894 53
elessair 0:f269e3021894 54
elessair 0:f269e3021894 55 /* ################### Compiler specific Intrinsics ########################### */
elessair 0:f269e3021894 56 /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
elessair 0:f269e3021894 57 Access to dedicated SIMD instructions
elessair 0:f269e3021894 58 @{
elessair 0:f269e3021894 59 */
elessair 0:f269e3021894 60
elessair 0:f269e3021894 61 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
elessair 0:f269e3021894 62 /* ARM armcc specific functions */
elessair 0:f269e3021894 63 #define __SADD8 __sadd8
elessair 0:f269e3021894 64 #define __QADD8 __qadd8
elessair 0:f269e3021894 65 #define __SHADD8 __shadd8
elessair 0:f269e3021894 66 #define __UADD8 __uadd8
elessair 0:f269e3021894 67 #define __UQADD8 __uqadd8
elessair 0:f269e3021894 68 #define __UHADD8 __uhadd8
elessair 0:f269e3021894 69 #define __SSUB8 __ssub8
elessair 0:f269e3021894 70 #define __QSUB8 __qsub8
elessair 0:f269e3021894 71 #define __SHSUB8 __shsub8
elessair 0:f269e3021894 72 #define __USUB8 __usub8
elessair 0:f269e3021894 73 #define __UQSUB8 __uqsub8
elessair 0:f269e3021894 74 #define __UHSUB8 __uhsub8
elessair 0:f269e3021894 75 #define __SADD16 __sadd16
elessair 0:f269e3021894 76 #define __QADD16 __qadd16
elessair 0:f269e3021894 77 #define __SHADD16 __shadd16
elessair 0:f269e3021894 78 #define __UADD16 __uadd16
elessair 0:f269e3021894 79 #define __UQADD16 __uqadd16
elessair 0:f269e3021894 80 #define __UHADD16 __uhadd16
elessair 0:f269e3021894 81 #define __SSUB16 __ssub16
elessair 0:f269e3021894 82 #define __QSUB16 __qsub16
elessair 0:f269e3021894 83 #define __SHSUB16 __shsub16
elessair 0:f269e3021894 84 #define __USUB16 __usub16
elessair 0:f269e3021894 85 #define __UQSUB16 __uqsub16
elessair 0:f269e3021894 86 #define __UHSUB16 __uhsub16
elessair 0:f269e3021894 87 #define __SASX __sasx
elessair 0:f269e3021894 88 #define __QASX __qasx
elessair 0:f269e3021894 89 #define __SHASX __shasx
elessair 0:f269e3021894 90 #define __UASX __uasx
elessair 0:f269e3021894 91 #define __UQASX __uqasx
elessair 0:f269e3021894 92 #define __UHASX __uhasx
elessair 0:f269e3021894 93 #define __SSAX __ssax
elessair 0:f269e3021894 94 #define __QSAX __qsax
elessair 0:f269e3021894 95 #define __SHSAX __shsax
elessair 0:f269e3021894 96 #define __USAX __usax
elessair 0:f269e3021894 97 #define __UQSAX __uqsax
elessair 0:f269e3021894 98 #define __UHSAX __uhsax
elessair 0:f269e3021894 99 #define __USAD8 __usad8
elessair 0:f269e3021894 100 #define __USADA8 __usada8
elessair 0:f269e3021894 101 #define __SSAT16 __ssat16
elessair 0:f269e3021894 102 #define __USAT16 __usat16
elessair 0:f269e3021894 103 #define __UXTB16 __uxtb16
elessair 0:f269e3021894 104 #define __UXTAB16 __uxtab16
elessair 0:f269e3021894 105 #define __SXTB16 __sxtb16
elessair 0:f269e3021894 106 #define __SXTAB16 __sxtab16
elessair 0:f269e3021894 107 #define __SMUAD __smuad
elessair 0:f269e3021894 108 #define __SMUADX __smuadx
elessair 0:f269e3021894 109 #define __SMLAD __smlad
elessair 0:f269e3021894 110 #define __SMLADX __smladx
elessair 0:f269e3021894 111 #define __SMLALD __smlald
elessair 0:f269e3021894 112 #define __SMLALDX __smlaldx
elessair 0:f269e3021894 113 #define __SMUSD __smusd
elessair 0:f269e3021894 114 #define __SMUSDX __smusdx
elessair 0:f269e3021894 115 #define __SMLSD __smlsd
elessair 0:f269e3021894 116 #define __SMLSDX __smlsdx
elessair 0:f269e3021894 117 #define __SMLSLD __smlsld
elessair 0:f269e3021894 118 #define __SMLSLDX __smlsldx
elessair 0:f269e3021894 119 #define __SEL __sel
elessair 0:f269e3021894 120 #define __QADD __qadd
elessair 0:f269e3021894 121 #define __QSUB __qsub
elessair 0:f269e3021894 122
elessair 0:f269e3021894 123 #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
elessair 0:f269e3021894 124 ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
elessair 0:f269e3021894 125
elessair 0:f269e3021894 126 #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
elessair 0:f269e3021894 127 ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
elessair 0:f269e3021894 128
elessair 0:f269e3021894 129 #define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
elessair 0:f269e3021894 130 ((int64_t)(ARG3) << 32) ) >> 32))
elessair 0:f269e3021894 131
elessair 0:f269e3021894 132
elessair 0:f269e3021894 133 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
elessair 0:f269e3021894 134 /* GNU gcc specific functions */
elessair 0:f269e3021894 135 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 136 {
elessair 0:f269e3021894 137 uint32_t result;
elessair 0:f269e3021894 138
elessair 0:f269e3021894 139 __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 140 return(result);
elessair 0:f269e3021894 141 }
elessair 0:f269e3021894 142
elessair 0:f269e3021894 143 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 144 {
elessair 0:f269e3021894 145 uint32_t result;
elessair 0:f269e3021894 146
elessair 0:f269e3021894 147 __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 148 return(result);
elessair 0:f269e3021894 149 }
elessair 0:f269e3021894 150
elessair 0:f269e3021894 151 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 152 {
elessair 0:f269e3021894 153 uint32_t result;
elessair 0:f269e3021894 154
elessair 0:f269e3021894 155 __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 156 return(result);
elessair 0:f269e3021894 157 }
elessair 0:f269e3021894 158
elessair 0:f269e3021894 159 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 160 {
elessair 0:f269e3021894 161 uint32_t result;
elessair 0:f269e3021894 162
elessair 0:f269e3021894 163 __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 164 return(result);
elessair 0:f269e3021894 165 }
elessair 0:f269e3021894 166
elessair 0:f269e3021894 167 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 168 {
elessair 0:f269e3021894 169 uint32_t result;
elessair 0:f269e3021894 170
elessair 0:f269e3021894 171 __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 172 return(result);
elessair 0:f269e3021894 173 }
elessair 0:f269e3021894 174
elessair 0:f269e3021894 175 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 176 {
elessair 0:f269e3021894 177 uint32_t result;
elessair 0:f269e3021894 178
elessair 0:f269e3021894 179 __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 180 return(result);
elessair 0:f269e3021894 181 }
elessair 0:f269e3021894 182
elessair 0:f269e3021894 183
elessair 0:f269e3021894 184 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 185 {
elessair 0:f269e3021894 186 uint32_t result;
elessair 0:f269e3021894 187
elessair 0:f269e3021894 188 __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 189 return(result);
elessair 0:f269e3021894 190 }
elessair 0:f269e3021894 191
elessair 0:f269e3021894 192 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 193 {
elessair 0:f269e3021894 194 uint32_t result;
elessair 0:f269e3021894 195
elessair 0:f269e3021894 196 __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 197 return(result);
elessair 0:f269e3021894 198 }
elessair 0:f269e3021894 199
elessair 0:f269e3021894 200 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 201 {
elessair 0:f269e3021894 202 uint32_t result;
elessair 0:f269e3021894 203
elessair 0:f269e3021894 204 __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 205 return(result);
elessair 0:f269e3021894 206 }
elessair 0:f269e3021894 207
elessair 0:f269e3021894 208 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 209 {
elessair 0:f269e3021894 210 uint32_t result;
elessair 0:f269e3021894 211
elessair 0:f269e3021894 212 __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 213 return(result);
elessair 0:f269e3021894 214 }
elessair 0:f269e3021894 215
elessair 0:f269e3021894 216 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 217 {
elessair 0:f269e3021894 218 uint32_t result;
elessair 0:f269e3021894 219
elessair 0:f269e3021894 220 __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 221 return(result);
elessair 0:f269e3021894 222 }
elessair 0:f269e3021894 223
elessair 0:f269e3021894 224 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 225 {
elessair 0:f269e3021894 226 uint32_t result;
elessair 0:f269e3021894 227
elessair 0:f269e3021894 228 __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 229 return(result);
elessair 0:f269e3021894 230 }
elessair 0:f269e3021894 231
elessair 0:f269e3021894 232
elessair 0:f269e3021894 233 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 234 {
elessair 0:f269e3021894 235 uint32_t result;
elessair 0:f269e3021894 236
elessair 0:f269e3021894 237 __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 238 return(result);
elessair 0:f269e3021894 239 }
elessair 0:f269e3021894 240
elessair 0:f269e3021894 241 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 242 {
elessair 0:f269e3021894 243 uint32_t result;
elessair 0:f269e3021894 244
elessair 0:f269e3021894 245 __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 246 return(result);
elessair 0:f269e3021894 247 }
elessair 0:f269e3021894 248
elessair 0:f269e3021894 249 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 250 {
elessair 0:f269e3021894 251 uint32_t result;
elessair 0:f269e3021894 252
elessair 0:f269e3021894 253 __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 254 return(result);
elessair 0:f269e3021894 255 }
elessair 0:f269e3021894 256
elessair 0:f269e3021894 257 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 258 {
elessair 0:f269e3021894 259 uint32_t result;
elessair 0:f269e3021894 260
elessair 0:f269e3021894 261 __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 262 return(result);
elessair 0:f269e3021894 263 }
elessair 0:f269e3021894 264
elessair 0:f269e3021894 265 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 266 {
elessair 0:f269e3021894 267 uint32_t result;
elessair 0:f269e3021894 268
elessair 0:f269e3021894 269 __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 270 return(result);
elessair 0:f269e3021894 271 }
elessair 0:f269e3021894 272
elessair 0:f269e3021894 273 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 274 {
elessair 0:f269e3021894 275 uint32_t result;
elessair 0:f269e3021894 276
elessair 0:f269e3021894 277 __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 278 return(result);
elessair 0:f269e3021894 279 }
elessair 0:f269e3021894 280
elessair 0:f269e3021894 281 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 282 {
elessair 0:f269e3021894 283 uint32_t result;
elessair 0:f269e3021894 284
elessair 0:f269e3021894 285 __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 286 return(result);
elessair 0:f269e3021894 287 }
elessair 0:f269e3021894 288
elessair 0:f269e3021894 289 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 290 {
elessair 0:f269e3021894 291 uint32_t result;
elessair 0:f269e3021894 292
elessair 0:f269e3021894 293 __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 294 return(result);
elessair 0:f269e3021894 295 }
elessair 0:f269e3021894 296
elessair 0:f269e3021894 297 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 298 {
elessair 0:f269e3021894 299 uint32_t result;
elessair 0:f269e3021894 300
elessair 0:f269e3021894 301 __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 302 return(result);
elessair 0:f269e3021894 303 }
elessair 0:f269e3021894 304
elessair 0:f269e3021894 305 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 306 {
elessair 0:f269e3021894 307 uint32_t result;
elessair 0:f269e3021894 308
elessair 0:f269e3021894 309 __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 310 return(result);
elessair 0:f269e3021894 311 }
elessair 0:f269e3021894 312
elessair 0:f269e3021894 313 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 314 {
elessair 0:f269e3021894 315 uint32_t result;
elessair 0:f269e3021894 316
elessair 0:f269e3021894 317 __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 318 return(result);
elessair 0:f269e3021894 319 }
elessair 0:f269e3021894 320
elessair 0:f269e3021894 321 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 322 {
elessair 0:f269e3021894 323 uint32_t result;
elessair 0:f269e3021894 324
elessair 0:f269e3021894 325 __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 326 return(result);
elessair 0:f269e3021894 327 }
elessair 0:f269e3021894 328
elessair 0:f269e3021894 329 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 330 {
elessair 0:f269e3021894 331 uint32_t result;
elessair 0:f269e3021894 332
elessair 0:f269e3021894 333 __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 334 return(result);
elessair 0:f269e3021894 335 }
elessair 0:f269e3021894 336
elessair 0:f269e3021894 337 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 338 {
elessair 0:f269e3021894 339 uint32_t result;
elessair 0:f269e3021894 340
elessair 0:f269e3021894 341 __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 342 return(result);
elessair 0:f269e3021894 343 }
elessair 0:f269e3021894 344
elessair 0:f269e3021894 345 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 346 {
elessair 0:f269e3021894 347 uint32_t result;
elessair 0:f269e3021894 348
elessair 0:f269e3021894 349 __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 350 return(result);
elessair 0:f269e3021894 351 }
elessair 0:f269e3021894 352
elessair 0:f269e3021894 353 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 354 {
elessair 0:f269e3021894 355 uint32_t result;
elessair 0:f269e3021894 356
elessair 0:f269e3021894 357 __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 358 return(result);
elessair 0:f269e3021894 359 }
elessair 0:f269e3021894 360
elessair 0:f269e3021894 361 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 362 {
elessair 0:f269e3021894 363 uint32_t result;
elessair 0:f269e3021894 364
elessair 0:f269e3021894 365 __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 366 return(result);
elessair 0:f269e3021894 367 }
elessair 0:f269e3021894 368
elessair 0:f269e3021894 369 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 370 {
elessair 0:f269e3021894 371 uint32_t result;
elessair 0:f269e3021894 372
elessair 0:f269e3021894 373 __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 374 return(result);
elessair 0:f269e3021894 375 }
elessair 0:f269e3021894 376
elessair 0:f269e3021894 377 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 378 {
elessair 0:f269e3021894 379 uint32_t result;
elessair 0:f269e3021894 380
elessair 0:f269e3021894 381 __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 382 return(result);
elessair 0:f269e3021894 383 }
elessair 0:f269e3021894 384
elessair 0:f269e3021894 385 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 386 {
elessair 0:f269e3021894 387 uint32_t result;
elessair 0:f269e3021894 388
elessair 0:f269e3021894 389 __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 390 return(result);
elessair 0:f269e3021894 391 }
elessair 0:f269e3021894 392
elessair 0:f269e3021894 393 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 394 {
elessair 0:f269e3021894 395 uint32_t result;
elessair 0:f269e3021894 396
elessair 0:f269e3021894 397 __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 398 return(result);
elessair 0:f269e3021894 399 }
elessair 0:f269e3021894 400
elessair 0:f269e3021894 401 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 402 {
elessair 0:f269e3021894 403 uint32_t result;
elessair 0:f269e3021894 404
elessair 0:f269e3021894 405 __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 406 return(result);
elessair 0:f269e3021894 407 }
elessair 0:f269e3021894 408
elessair 0:f269e3021894 409 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 410 {
elessair 0:f269e3021894 411 uint32_t result;
elessair 0:f269e3021894 412
elessair 0:f269e3021894 413 __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 414 return(result);
elessair 0:f269e3021894 415 }
elessair 0:f269e3021894 416
elessair 0:f269e3021894 417 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 418 {
elessair 0:f269e3021894 419 uint32_t result;
elessair 0:f269e3021894 420
elessair 0:f269e3021894 421 __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 422 return(result);
elessair 0:f269e3021894 423 }
elessair 0:f269e3021894 424
elessair 0:f269e3021894 425 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 426 {
elessair 0:f269e3021894 427 uint32_t result;
elessair 0:f269e3021894 428
elessair 0:f269e3021894 429 __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 430 return(result);
elessair 0:f269e3021894 431 }
elessair 0:f269e3021894 432
elessair 0:f269e3021894 433 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
elessair 0:f269e3021894 434 {
elessair 0:f269e3021894 435 uint32_t result;
elessair 0:f269e3021894 436
elessair 0:f269e3021894 437 __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
elessair 0:f269e3021894 438 return(result);
elessair 0:f269e3021894 439 }
elessair 0:f269e3021894 440
elessair 0:f269e3021894 441 #define __SSAT16(ARG1,ARG2) \
elessair 0:f269e3021894 442 ({ \
elessair 0:f269e3021894 443 uint32_t __RES, __ARG1 = (ARG1); \
elessair 0:f269e3021894 444 __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
elessair 0:f269e3021894 445 __RES; \
elessair 0:f269e3021894 446 })
elessair 0:f269e3021894 447
elessair 0:f269e3021894 448 #define __USAT16(ARG1,ARG2) \
elessair 0:f269e3021894 449 ({ \
elessair 0:f269e3021894 450 uint32_t __RES, __ARG1 = (ARG1); \
elessair 0:f269e3021894 451 __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
elessair 0:f269e3021894 452 __RES; \
elessair 0:f269e3021894 453 })
elessair 0:f269e3021894 454
elessair 0:f269e3021894 455 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
elessair 0:f269e3021894 456 {
elessair 0:f269e3021894 457 uint32_t result;
elessair 0:f269e3021894 458
elessair 0:f269e3021894 459 __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
elessair 0:f269e3021894 460 return(result);
elessair 0:f269e3021894 461 }
elessair 0:f269e3021894 462
elessair 0:f269e3021894 463 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 464 {
elessair 0:f269e3021894 465 uint32_t result;
elessair 0:f269e3021894 466
elessair 0:f269e3021894 467 __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 468 return(result);
elessair 0:f269e3021894 469 }
elessair 0:f269e3021894 470
elessair 0:f269e3021894 471 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
elessair 0:f269e3021894 472 {
elessair 0:f269e3021894 473 uint32_t result;
elessair 0:f269e3021894 474
elessair 0:f269e3021894 475 __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
elessair 0:f269e3021894 476 return(result);
elessair 0:f269e3021894 477 }
elessair 0:f269e3021894 478
elessair 0:f269e3021894 479 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 480 {
elessair 0:f269e3021894 481 uint32_t result;
elessair 0:f269e3021894 482
elessair 0:f269e3021894 483 __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 484 return(result);
elessair 0:f269e3021894 485 }
elessair 0:f269e3021894 486
elessair 0:f269e3021894 487 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 488 {
elessair 0:f269e3021894 489 uint32_t result;
elessair 0:f269e3021894 490
elessair 0:f269e3021894 491 __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 492 return(result);
elessair 0:f269e3021894 493 }
elessair 0:f269e3021894 494
elessair 0:f269e3021894 495 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 496 {
elessair 0:f269e3021894 497 uint32_t result;
elessair 0:f269e3021894 498
elessair 0:f269e3021894 499 __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 500 return(result);
elessair 0:f269e3021894 501 }
elessair 0:f269e3021894 502
elessair 0:f269e3021894 503 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
elessair 0:f269e3021894 504 {
elessair 0:f269e3021894 505 uint32_t result;
elessair 0:f269e3021894 506
elessair 0:f269e3021894 507 __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
elessair 0:f269e3021894 508 return(result);
elessair 0:f269e3021894 509 }
elessair 0:f269e3021894 510
elessair 0:f269e3021894 511 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
elessair 0:f269e3021894 512 {
elessair 0:f269e3021894 513 uint32_t result;
elessair 0:f269e3021894 514
elessair 0:f269e3021894 515 __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
elessair 0:f269e3021894 516 return(result);
elessair 0:f269e3021894 517 }
elessair 0:f269e3021894 518
elessair 0:f269e3021894 519 __attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
elessair 0:f269e3021894 520 {
elessair 0:f269e3021894 521 union llreg_u{
elessair 0:f269e3021894 522 uint32_t w32[2];
elessair 0:f269e3021894 523 uint64_t w64;
elessair 0:f269e3021894 524 } llr;
elessair 0:f269e3021894 525 llr.w64 = acc;
elessair 0:f269e3021894 526
elessair 0:f269e3021894 527 #ifndef __ARMEB__ // Little endian
elessair 0:f269e3021894 528 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
elessair 0:f269e3021894 529 #else // Big endian
elessair 0:f269e3021894 530 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
elessair 0:f269e3021894 531 #endif
elessair 0:f269e3021894 532
elessair 0:f269e3021894 533 return(llr.w64);
elessair 0:f269e3021894 534 }
elessair 0:f269e3021894 535
elessair 0:f269e3021894 536 __attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
elessair 0:f269e3021894 537 {
elessair 0:f269e3021894 538 union llreg_u{
elessair 0:f269e3021894 539 uint32_t w32[2];
elessair 0:f269e3021894 540 uint64_t w64;
elessair 0:f269e3021894 541 } llr;
elessair 0:f269e3021894 542 llr.w64 = acc;
elessair 0:f269e3021894 543
elessair 0:f269e3021894 544 #ifndef __ARMEB__ // Little endian
elessair 0:f269e3021894 545 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
elessair 0:f269e3021894 546 #else // Big endian
elessair 0:f269e3021894 547 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
elessair 0:f269e3021894 548 #endif
elessair 0:f269e3021894 549
elessair 0:f269e3021894 550 return(llr.w64);
elessair 0:f269e3021894 551 }
elessair 0:f269e3021894 552
elessair 0:f269e3021894 553 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 554 {
elessair 0:f269e3021894 555 uint32_t result;
elessair 0:f269e3021894 556
elessair 0:f269e3021894 557 __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 558 return(result);
elessair 0:f269e3021894 559 }
elessair 0:f269e3021894 560
elessair 0:f269e3021894 561 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 562 {
elessair 0:f269e3021894 563 uint32_t result;
elessair 0:f269e3021894 564
elessair 0:f269e3021894 565 __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 566 return(result);
elessair 0:f269e3021894 567 }
elessair 0:f269e3021894 568
elessair 0:f269e3021894 569 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
elessair 0:f269e3021894 570 {
elessair 0:f269e3021894 571 uint32_t result;
elessair 0:f269e3021894 572
elessair 0:f269e3021894 573 __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
elessair 0:f269e3021894 574 return(result);
elessair 0:f269e3021894 575 }
elessair 0:f269e3021894 576
elessair 0:f269e3021894 577 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
elessair 0:f269e3021894 578 {
elessair 0:f269e3021894 579 uint32_t result;
elessair 0:f269e3021894 580
elessair 0:f269e3021894 581 __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
elessair 0:f269e3021894 582 return(result);
elessair 0:f269e3021894 583 }
elessair 0:f269e3021894 584
elessair 0:f269e3021894 585 __attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
elessair 0:f269e3021894 586 {
elessair 0:f269e3021894 587 union llreg_u{
elessair 0:f269e3021894 588 uint32_t w32[2];
elessair 0:f269e3021894 589 uint64_t w64;
elessair 0:f269e3021894 590 } llr;
elessair 0:f269e3021894 591 llr.w64 = acc;
elessair 0:f269e3021894 592
elessair 0:f269e3021894 593 #ifndef __ARMEB__ // Little endian
elessair 0:f269e3021894 594 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
elessair 0:f269e3021894 595 #else // Big endian
elessair 0:f269e3021894 596 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
elessair 0:f269e3021894 597 #endif
elessair 0:f269e3021894 598
elessair 0:f269e3021894 599 return(llr.w64);
elessair 0:f269e3021894 600 }
elessair 0:f269e3021894 601
elessair 0:f269e3021894 602 __attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
elessair 0:f269e3021894 603 {
elessair 0:f269e3021894 604 union llreg_u{
elessair 0:f269e3021894 605 uint32_t w32[2];
elessair 0:f269e3021894 606 uint64_t w64;
elessair 0:f269e3021894 607 } llr;
elessair 0:f269e3021894 608 llr.w64 = acc;
elessair 0:f269e3021894 609
elessair 0:f269e3021894 610 #ifndef __ARMEB__ // Little endian
elessair 0:f269e3021894 611 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
elessair 0:f269e3021894 612 #else // Big endian
elessair 0:f269e3021894 613 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
elessair 0:f269e3021894 614 #endif
elessair 0:f269e3021894 615
elessair 0:f269e3021894 616 return(llr.w64);
elessair 0:f269e3021894 617 }
elessair 0:f269e3021894 618
elessair 0:f269e3021894 619 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 620 {
elessair 0:f269e3021894 621 uint32_t result;
elessair 0:f269e3021894 622
elessair 0:f269e3021894 623 __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 624 return(result);
elessair 0:f269e3021894 625 }
elessair 0:f269e3021894 626
elessair 0:f269e3021894 627 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 628 {
elessair 0:f269e3021894 629 uint32_t result;
elessair 0:f269e3021894 630
elessair 0:f269e3021894 631 __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 632 return(result);
elessair 0:f269e3021894 633 }
elessair 0:f269e3021894 634
elessair 0:f269e3021894 635 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 636 {
elessair 0:f269e3021894 637 uint32_t result;
elessair 0:f269e3021894 638
elessair 0:f269e3021894 639 __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 640 return(result);
elessair 0:f269e3021894 641 }
elessair 0:f269e3021894 642
elessair 0:f269e3021894 643 #define __PKHBT(ARG1,ARG2,ARG3) \
elessair 0:f269e3021894 644 ({ \
elessair 0:f269e3021894 645 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
elessair 0:f269e3021894 646 __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
elessair 0:f269e3021894 647 __RES; \
elessair 0:f269e3021894 648 })
elessair 0:f269e3021894 649
elessair 0:f269e3021894 650 #define __PKHTB(ARG1,ARG2,ARG3) \
elessair 0:f269e3021894 651 ({ \
elessair 0:f269e3021894 652 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
elessair 0:f269e3021894 653 if (ARG3 == 0) \
elessair 0:f269e3021894 654 __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
elessair 0:f269e3021894 655 else \
elessair 0:f269e3021894 656 __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
elessair 0:f269e3021894 657 __RES; \
elessair 0:f269e3021894 658 })
elessair 0:f269e3021894 659
elessair 0:f269e3021894 660 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
elessair 0:f269e3021894 661 {
elessair 0:f269e3021894 662 int32_t result;
elessair 0:f269e3021894 663
elessair 0:f269e3021894 664 __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
elessair 0:f269e3021894 665 return(result);
elessair 0:f269e3021894 666 }
elessair 0:f269e3021894 667
elessair 0:f269e3021894 668
elessair 0:f269e3021894 669 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
elessair 0:f269e3021894 670 /* IAR iccarm specific functions */
elessair 0:f269e3021894 671 #include <cmsis_iar.h>
elessair 0:f269e3021894 672
elessair 0:f269e3021894 673
elessair 0:f269e3021894 674 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
elessair 0:f269e3021894 675 /* TI CCS specific functions */
elessair 0:f269e3021894 676 #include <cmsis_ccs.h>
elessair 0:f269e3021894 677
elessair 0:f269e3021894 678
elessair 0:f269e3021894 679 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
elessair 0:f269e3021894 680 /* TASKING carm specific functions */
elessair 0:f269e3021894 681 /* not yet supported */
elessair 0:f269e3021894 682
elessair 0:f269e3021894 683
elessair 0:f269e3021894 684 #elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
elessair 0:f269e3021894 685 /* Cosmic specific functions */
elessair 0:f269e3021894 686 #include <cmsis_csm.h>
elessair 0:f269e3021894 687
elessair 0:f269e3021894 688 #endif
elessair 0:f269e3021894 689
elessair 0:f269e3021894 690 /*@} end of group CMSIS_SIMD_intrinsics */
elessair 0:f269e3021894 691
elessair 0:f269e3021894 692
elessair 0:f269e3021894 693 #ifdef __cplusplus
elessair 0:f269e3021894 694 }
elessair 0:f269e3021894 695 #endif
elessair 0:f269e3021894 696
elessair 0:f269e3021894 697 #endif /* __CORE_CMSIMD_H */