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cmsis/core_cmFunc.h@0:f269e3021894, 2016-10-23 (annotated)

Committer:
elessair
Date:
Sun Oct 23 15:10:02 2016 +0000
Revision:
0:f269e3021894
Initial commit

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elessair 0:f269e3021894 1 /**************************************************************************//**
elessair 0:f269e3021894 2 * @file core_cmFunc.h
elessair 0:f269e3021894 3 * @brief CMSIS Cortex-M Core Function Access Header File
elessair 0:f269e3021894 4 * @version V4.10
elessair 0:f269e3021894 5 * @date 18. March 2015
elessair 0:f269e3021894 6 *
elessair 0:f269e3021894 7 * @note
elessair 0:f269e3021894 8 *
elessair 0:f269e3021894 9 ******************************************************************************/
elessair 0:f269e3021894 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
elessair 0:f269e3021894 11
elessair 0:f269e3021894 12 All rights reserved.
elessair 0:f269e3021894 13 Redistribution and use in source and binary forms, with or without
elessair 0:f269e3021894 14 modification, are permitted provided that the following conditions are met:
elessair 0:f269e3021894 15 - Redistributions of source code must retain the above copyright
elessair 0:f269e3021894 16 notice, this list of conditions and the following disclaimer.
elessair 0:f269e3021894 17 - Redistributions in binary form must reproduce the above copyright
elessair 0:f269e3021894 18 notice, this list of conditions and the following disclaimer in the
elessair 0:f269e3021894 19 documentation and/or other materials provided with the distribution.
elessair 0:f269e3021894 20 - Neither the name of ARM nor the names of its contributors may be used
elessair 0:f269e3021894 21 to endorse or promote products derived from this software without
elessair 0:f269e3021894 22 specific prior written permission.
elessair 0:f269e3021894 23 *
elessair 0:f269e3021894 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
elessair 0:f269e3021894 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
elessair 0:f269e3021894 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
elessair 0:f269e3021894 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
elessair 0:f269e3021894 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
elessair 0:f269e3021894 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
elessair 0:f269e3021894 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
elessair 0:f269e3021894 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
elessair 0:f269e3021894 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
elessair 0:f269e3021894 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
elessair 0:f269e3021894 34 POSSIBILITY OF SUCH DAMAGE.
elessair 0:f269e3021894 35 ---------------------------------------------------------------------------*/
elessair 0:f269e3021894 36
elessair 0:f269e3021894 37
elessair 0:f269e3021894 38 #ifndef __CORE_CMFUNC_H
elessair 0:f269e3021894 39 #define __CORE_CMFUNC_H
elessair 0:f269e3021894 40
elessair 0:f269e3021894 41
elessair 0:f269e3021894 42 /* ########################### Core Function Access ########################### */
elessair 0:f269e3021894 43 /** \ingroup CMSIS_Core_FunctionInterface
elessair 0:f269e3021894 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
elessair 0:f269e3021894 45 @{
elessair 0:f269e3021894 46 */
elessair 0:f269e3021894 47
elessair 0:f269e3021894 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
elessair 0:f269e3021894 49 /* ARM armcc specific functions */
elessair 0:f269e3021894 50
elessair 0:f269e3021894 51 #if (__ARMCC_VERSION < 400677)
elessair 0:f269e3021894 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
elessair 0:f269e3021894 53 #endif
elessair 0:f269e3021894 54
elessair 0:f269e3021894 55 /* intrinsic void __enable_irq(); */
elessair 0:f269e3021894 56 /* intrinsic void __disable_irq(); */
elessair 0:f269e3021894 57
elessair 0:f269e3021894 58 /** \brief Get Control Register
elessair 0:f269e3021894 59
elessair 0:f269e3021894 60 This function returns the content of the Control Register.
elessair 0:f269e3021894 61
elessair 0:f269e3021894 62 \return Control Register value
elessair 0:f269e3021894 63 */
elessair 0:f269e3021894 64 __STATIC_INLINE uint32_t __get_CONTROL(void)
elessair 0:f269e3021894 65 {
elessair 0:f269e3021894 66 register uint32_t __regControl __ASM("control");
elessair 0:f269e3021894 67 return(__regControl);
elessair 0:f269e3021894 68 }
elessair 0:f269e3021894 69
elessair 0:f269e3021894 70
elessair 0:f269e3021894 71 /** \brief Set Control Register
elessair 0:f269e3021894 72
elessair 0:f269e3021894 73 This function writes the given value to the Control Register.
elessair 0:f269e3021894 74
elessair 0:f269e3021894 75 \param [in] control Control Register value to set
elessair 0:f269e3021894 76 */
elessair 0:f269e3021894 77 __STATIC_INLINE void __set_CONTROL(uint32_t control)
elessair 0:f269e3021894 78 {
elessair 0:f269e3021894 79 register uint32_t __regControl __ASM("control");
elessair 0:f269e3021894 80 __regControl = control;
elessair 0:f269e3021894 81 }
elessair 0:f269e3021894 82
elessair 0:f269e3021894 83
elessair 0:f269e3021894 84 /** \brief Get IPSR Register
elessair 0:f269e3021894 85
elessair 0:f269e3021894 86 This function returns the content of the IPSR Register.
elessair 0:f269e3021894 87
elessair 0:f269e3021894 88 \return IPSR Register value
elessair 0:f269e3021894 89 */
elessair 0:f269e3021894 90 __STATIC_INLINE uint32_t __get_IPSR(void)
elessair 0:f269e3021894 91 {
elessair 0:f269e3021894 92 register uint32_t __regIPSR __ASM("ipsr");
elessair 0:f269e3021894 93 return(__regIPSR);
elessair 0:f269e3021894 94 }
elessair 0:f269e3021894 95
elessair 0:f269e3021894 96
elessair 0:f269e3021894 97 /** \brief Get APSR Register
elessair 0:f269e3021894 98
elessair 0:f269e3021894 99 This function returns the content of the APSR Register.
elessair 0:f269e3021894 100
elessair 0:f269e3021894 101 \return APSR Register value
elessair 0:f269e3021894 102 */
elessair 0:f269e3021894 103 __STATIC_INLINE uint32_t __get_APSR(void)
elessair 0:f269e3021894 104 {
elessair 0:f269e3021894 105 register uint32_t __regAPSR __ASM("apsr");
elessair 0:f269e3021894 106 return(__regAPSR);
elessair 0:f269e3021894 107 }
elessair 0:f269e3021894 108
elessair 0:f269e3021894 109
elessair 0:f269e3021894 110 /** \brief Get xPSR Register
elessair 0:f269e3021894 111
elessair 0:f269e3021894 112 This function returns the content of the xPSR Register.
elessair 0:f269e3021894 113
elessair 0:f269e3021894 114 \return xPSR Register value
elessair 0:f269e3021894 115 */
elessair 0:f269e3021894 116 __STATIC_INLINE uint32_t __get_xPSR(void)
elessair 0:f269e3021894 117 {
elessair 0:f269e3021894 118 register uint32_t __regXPSR __ASM("xpsr");
elessair 0:f269e3021894 119 return(__regXPSR);
elessair 0:f269e3021894 120 }
elessair 0:f269e3021894 121
elessair 0:f269e3021894 122
elessair 0:f269e3021894 123 /** \brief Get Process Stack Pointer
elessair 0:f269e3021894 124
elessair 0:f269e3021894 125 This function returns the current value of the Process Stack Pointer (PSP).
elessair 0:f269e3021894 126
elessair 0:f269e3021894 127 \return PSP Register value
elessair 0:f269e3021894 128 */
elessair 0:f269e3021894 129 __STATIC_INLINE uint32_t __get_PSP(void)
elessair 0:f269e3021894 130 {
elessair 0:f269e3021894 131 register uint32_t __regProcessStackPointer __ASM("psp");
elessair 0:f269e3021894 132 return(__regProcessStackPointer);
elessair 0:f269e3021894 133 }
elessair 0:f269e3021894 134
elessair 0:f269e3021894 135
elessair 0:f269e3021894 136 /** \brief Set Process Stack Pointer
elessair 0:f269e3021894 137
elessair 0:f269e3021894 138 This function assigns the given value to the Process Stack Pointer (PSP).
elessair 0:f269e3021894 139
elessair 0:f269e3021894 140 \param [in] topOfProcStack Process Stack Pointer value to set
elessair 0:f269e3021894 141 */
elessair 0:f269e3021894 142 __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
elessair 0:f269e3021894 143 {
elessair 0:f269e3021894 144 register uint32_t __regProcessStackPointer __ASM("psp");
elessair 0:f269e3021894 145 __regProcessStackPointer = topOfProcStack;
elessair 0:f269e3021894 146 }
elessair 0:f269e3021894 147
elessair 0:f269e3021894 148
elessair 0:f269e3021894 149 /** \brief Get Main Stack Pointer
elessair 0:f269e3021894 150
elessair 0:f269e3021894 151 This function returns the current value of the Main Stack Pointer (MSP).
elessair 0:f269e3021894 152
elessair 0:f269e3021894 153 \return MSP Register value
elessair 0:f269e3021894 154 */
elessair 0:f269e3021894 155 __STATIC_INLINE uint32_t __get_MSP(void)
elessair 0:f269e3021894 156 {
elessair 0:f269e3021894 157 register uint32_t __regMainStackPointer __ASM("msp");
elessair 0:f269e3021894 158 return(__regMainStackPointer);
elessair 0:f269e3021894 159 }
elessair 0:f269e3021894 160
elessair 0:f269e3021894 161
elessair 0:f269e3021894 162 /** \brief Set Main Stack Pointer
elessair 0:f269e3021894 163
elessair 0:f269e3021894 164 This function assigns the given value to the Main Stack Pointer (MSP).
elessair 0:f269e3021894 165
elessair 0:f269e3021894 166 \param [in] topOfMainStack Main Stack Pointer value to set
elessair 0:f269e3021894 167 */
elessair 0:f269e3021894 168 __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
elessair 0:f269e3021894 169 {
elessair 0:f269e3021894 170 register uint32_t __regMainStackPointer __ASM("msp");
elessair 0:f269e3021894 171 __regMainStackPointer = topOfMainStack;
elessair 0:f269e3021894 172 }
elessair 0:f269e3021894 173
elessair 0:f269e3021894 174
elessair 0:f269e3021894 175 /** \brief Get Priority Mask
elessair 0:f269e3021894 176
elessair 0:f269e3021894 177 This function returns the current state of the priority mask bit from the Priority Mask Register.
elessair 0:f269e3021894 178
elessair 0:f269e3021894 179 \return Priority Mask value
elessair 0:f269e3021894 180 */
elessair 0:f269e3021894 181 __STATIC_INLINE uint32_t __get_PRIMASK(void)
elessair 0:f269e3021894 182 {
elessair 0:f269e3021894 183 register uint32_t __regPriMask __ASM("primask");
elessair 0:f269e3021894 184 return(__regPriMask);
elessair 0:f269e3021894 185 }
elessair 0:f269e3021894 186
elessair 0:f269e3021894 187
elessair 0:f269e3021894 188 /** \brief Set Priority Mask
elessair 0:f269e3021894 189
elessair 0:f269e3021894 190 This function assigns the given value to the Priority Mask Register.
elessair 0:f269e3021894 191
elessair 0:f269e3021894 192 \param [in] priMask Priority Mask
elessair 0:f269e3021894 193 */
elessair 0:f269e3021894 194 __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
elessair 0:f269e3021894 195 {
elessair 0:f269e3021894 196 register uint32_t __regPriMask __ASM("primask");
elessair 0:f269e3021894 197 __regPriMask = (priMask);
elessair 0:f269e3021894 198 }
elessair 0:f269e3021894 199
elessair 0:f269e3021894 200
elessair 0:f269e3021894 201 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
elessair 0:f269e3021894 202
elessair 0:f269e3021894 203 /** \brief Enable FIQ
elessair 0:f269e3021894 204
elessair 0:f269e3021894 205 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
elessair 0:f269e3021894 206 Can only be executed in Privileged modes.
elessair 0:f269e3021894 207 */
elessair 0:f269e3021894 208 #define __enable_fault_irq __enable_fiq
elessair 0:f269e3021894 209
elessair 0:f269e3021894 210
elessair 0:f269e3021894 211 /** \brief Disable FIQ
elessair 0:f269e3021894 212
elessair 0:f269e3021894 213 This function disables FIQ interrupts by setting the F-bit in the CPSR.
elessair 0:f269e3021894 214 Can only be executed in Privileged modes.
elessair 0:f269e3021894 215 */
elessair 0:f269e3021894 216 #define __disable_fault_irq __disable_fiq
elessair 0:f269e3021894 217
elessair 0:f269e3021894 218
elessair 0:f269e3021894 219 /** \brief Get Base Priority
elessair 0:f269e3021894 220
elessair 0:f269e3021894 221 This function returns the current value of the Base Priority register.
elessair 0:f269e3021894 222
elessair 0:f269e3021894 223 \return Base Priority register value
elessair 0:f269e3021894 224 */
elessair 0:f269e3021894 225 __STATIC_INLINE uint32_t __get_BASEPRI(void)
elessair 0:f269e3021894 226 {
elessair 0:f269e3021894 227 register uint32_t __regBasePri __ASM("basepri");
elessair 0:f269e3021894 228 return(__regBasePri);
elessair 0:f269e3021894 229 }
elessair 0:f269e3021894 230
elessair 0:f269e3021894 231
elessair 0:f269e3021894 232 /** \brief Set Base Priority
elessair 0:f269e3021894 233
elessair 0:f269e3021894 234 This function assigns the given value to the Base Priority register.
elessair 0:f269e3021894 235
elessair 0:f269e3021894 236 \param [in] basePri Base Priority value to set
elessair 0:f269e3021894 237 */
elessair 0:f269e3021894 238 __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
elessair 0:f269e3021894 239 {
elessair 0:f269e3021894 240 register uint32_t __regBasePri __ASM("basepri");
elessair 0:f269e3021894 241 __regBasePri = (basePri & 0xff);
elessair 0:f269e3021894 242 }
elessair 0:f269e3021894 243
elessair 0:f269e3021894 244
elessair 0:f269e3021894 245 /** \brief Set Base Priority with condition
elessair 0:f269e3021894 246
elessair 0:f269e3021894 247 This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
elessair 0:f269e3021894 248 or the new value increases the BASEPRI priority level.
elessair 0:f269e3021894 249
elessair 0:f269e3021894 250 \param [in] basePri Base Priority value to set
elessair 0:f269e3021894 251 */
elessair 0:f269e3021894 252 __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
elessair 0:f269e3021894 253 {
elessair 0:f269e3021894 254 register uint32_t __regBasePriMax __ASM("basepri_max");
elessair 0:f269e3021894 255 __regBasePriMax = (basePri & 0xff);
elessair 0:f269e3021894 256 }
elessair 0:f269e3021894 257
elessair 0:f269e3021894 258
elessair 0:f269e3021894 259 /** \brief Get Fault Mask
elessair 0:f269e3021894 260
elessair 0:f269e3021894 261 This function returns the current value of the Fault Mask register.
elessair 0:f269e3021894 262
elessair 0:f269e3021894 263 \return Fault Mask register value
elessair 0:f269e3021894 264 */
elessair 0:f269e3021894 265 __STATIC_INLINE uint32_t __get_FAULTMASK(void)
elessair 0:f269e3021894 266 {
elessair 0:f269e3021894 267 register uint32_t __regFaultMask __ASM("faultmask");
elessair 0:f269e3021894 268 return(__regFaultMask);
elessair 0:f269e3021894 269 }
elessair 0:f269e3021894 270
elessair 0:f269e3021894 271
elessair 0:f269e3021894 272 /** \brief Set Fault Mask
elessair 0:f269e3021894 273
elessair 0:f269e3021894 274 This function assigns the given value to the Fault Mask register.
elessair 0:f269e3021894 275
elessair 0:f269e3021894 276 \param [in] faultMask Fault Mask value to set
elessair 0:f269e3021894 277 */
elessair 0:f269e3021894 278 __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
elessair 0:f269e3021894 279 {
elessair 0:f269e3021894 280 register uint32_t __regFaultMask __ASM("faultmask");
elessair 0:f269e3021894 281 __regFaultMask = (faultMask & (uint32_t)1);
elessair 0:f269e3021894 282 }
elessair 0:f269e3021894 283
elessair 0:f269e3021894 284 #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
elessair 0:f269e3021894 285
elessair 0:f269e3021894 286
elessair 0:f269e3021894 287 #if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
elessair 0:f269e3021894 288
elessair 0:f269e3021894 289 /** \brief Get FPSCR
elessair 0:f269e3021894 290
elessair 0:f269e3021894 291 This function returns the current value of the Floating Point Status/Control register.
elessair 0:f269e3021894 292
elessair 0:f269e3021894 293 \return Floating Point Status/Control register value
elessair 0:f269e3021894 294 */
elessair 0:f269e3021894 295 __STATIC_INLINE uint32_t __get_FPSCR(void)
elessair 0:f269e3021894 296 {
elessair 0:f269e3021894 297 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
elessair 0:f269e3021894 298 register uint32_t __regfpscr __ASM("fpscr");
elessair 0:f269e3021894 299 return(__regfpscr);
elessair 0:f269e3021894 300 #else
elessair 0:f269e3021894 301 return(0);
elessair 0:f269e3021894 302 #endif
elessair 0:f269e3021894 303 }
elessair 0:f269e3021894 304
elessair 0:f269e3021894 305
elessair 0:f269e3021894 306 /** \brief Set FPSCR
elessair 0:f269e3021894 307
elessair 0:f269e3021894 308 This function assigns the given value to the Floating Point Status/Control register.
elessair 0:f269e3021894 309
elessair 0:f269e3021894 310 \param [in] fpscr Floating Point Status/Control value to set
elessair 0:f269e3021894 311 */
elessair 0:f269e3021894 312 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
elessair 0:f269e3021894 313 {
elessair 0:f269e3021894 314 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
elessair 0:f269e3021894 315 register uint32_t __regfpscr __ASM("fpscr");
elessair 0:f269e3021894 316 __regfpscr = (fpscr);
elessair 0:f269e3021894 317 #endif
elessair 0:f269e3021894 318 }
elessair 0:f269e3021894 319
elessair 0:f269e3021894 320 #endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
elessair 0:f269e3021894 321
elessair 0:f269e3021894 322
elessair 0:f269e3021894 323 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
elessair 0:f269e3021894 324 /* GNU gcc specific functions */
elessair 0:f269e3021894 325
elessair 0:f269e3021894 326 /** \brief Enable IRQ Interrupts
elessair 0:f269e3021894 327
elessair 0:f269e3021894 328 This function enables IRQ interrupts by clearing the I-bit in the CPSR.
elessair 0:f269e3021894 329 Can only be executed in Privileged modes.
elessair 0:f269e3021894 330 */
elessair 0:f269e3021894 331 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
elessair 0:f269e3021894 332 {
elessair 0:f269e3021894 333 __ASM volatile ("cpsie i" : : : "memory");
elessair 0:f269e3021894 334 }
elessair 0:f269e3021894 335
elessair 0:f269e3021894 336
elessair 0:f269e3021894 337 /** \brief Disable IRQ Interrupts
elessair 0:f269e3021894 338
elessair 0:f269e3021894 339 This function disables IRQ interrupts by setting the I-bit in the CPSR.
elessair 0:f269e3021894 340 Can only be executed in Privileged modes.
elessair 0:f269e3021894 341 */
elessair 0:f269e3021894 342 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
elessair 0:f269e3021894 343 {
elessair 0:f269e3021894 344 __ASM volatile ("cpsid i" : : : "memory");
elessair 0:f269e3021894 345 }
elessair 0:f269e3021894 346
elessair 0:f269e3021894 347
elessair 0:f269e3021894 348 /** \brief Get Control Register
elessair 0:f269e3021894 349
elessair 0:f269e3021894 350 This function returns the content of the Control Register.
elessair 0:f269e3021894 351
elessair 0:f269e3021894 352 \return Control Register value
elessair 0:f269e3021894 353 */
elessair 0:f269e3021894 354 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
elessair 0:f269e3021894 355 {
elessair 0:f269e3021894 356 uint32_t result;
elessair 0:f269e3021894 357
elessair 0:f269e3021894 358 __ASM volatile ("MRS %0, control" : "=r" (result) );
elessair 0:f269e3021894 359 return(result);
elessair 0:f269e3021894 360 }
elessair 0:f269e3021894 361
elessair 0:f269e3021894 362
elessair 0:f269e3021894 363 /** \brief Set Control Register
elessair 0:f269e3021894 364
elessair 0:f269e3021894 365 This function writes the given value to the Control Register.
elessair 0:f269e3021894 366
elessair 0:f269e3021894 367 \param [in] control Control Register value to set
elessair 0:f269e3021894 368 */
elessair 0:f269e3021894 369 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
elessair 0:f269e3021894 370 {
elessair 0:f269e3021894 371 __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
elessair 0:f269e3021894 372 }
elessair 0:f269e3021894 373
elessair 0:f269e3021894 374
elessair 0:f269e3021894 375 /** \brief Get IPSR Register
elessair 0:f269e3021894 376
elessair 0:f269e3021894 377 This function returns the content of the IPSR Register.
elessair 0:f269e3021894 378
elessair 0:f269e3021894 379 \return IPSR Register value
elessair 0:f269e3021894 380 */
elessair 0:f269e3021894 381 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
elessair 0:f269e3021894 382 {
elessair 0:f269e3021894 383 uint32_t result;
elessair 0:f269e3021894 384
elessair 0:f269e3021894 385 __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
elessair 0:f269e3021894 386 return(result);
elessair 0:f269e3021894 387 }
elessair 0:f269e3021894 388
elessair 0:f269e3021894 389
elessair 0:f269e3021894 390 /** \brief Get APSR Register
elessair 0:f269e3021894 391
elessair 0:f269e3021894 392 This function returns the content of the APSR Register.
elessair 0:f269e3021894 393
elessair 0:f269e3021894 394 \return APSR Register value
elessair 0:f269e3021894 395 */
elessair 0:f269e3021894 396 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
elessair 0:f269e3021894 397 {
elessair 0:f269e3021894 398 uint32_t result;
elessair 0:f269e3021894 399
elessair 0:f269e3021894 400 __ASM volatile ("MRS %0, apsr" : "=r" (result) );
elessair 0:f269e3021894 401 return(result);
elessair 0:f269e3021894 402 }
elessair 0:f269e3021894 403
elessair 0:f269e3021894 404
elessair 0:f269e3021894 405 /** \brief Get xPSR Register
elessair 0:f269e3021894 406
elessair 0:f269e3021894 407 This function returns the content of the xPSR Register.
elessair 0:f269e3021894 408
elessair 0:f269e3021894 409 \return xPSR Register value
elessair 0:f269e3021894 410 */
elessair 0:f269e3021894 411 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
elessair 0:f269e3021894 412 {
elessair 0:f269e3021894 413 uint32_t result;
elessair 0:f269e3021894 414
elessair 0:f269e3021894 415 __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
elessair 0:f269e3021894 416 return(result);
elessair 0:f269e3021894 417 }
elessair 0:f269e3021894 418
elessair 0:f269e3021894 419
elessair 0:f269e3021894 420 /** \brief Get Process Stack Pointer
elessair 0:f269e3021894 421
elessair 0:f269e3021894 422 This function returns the current value of the Process Stack Pointer (PSP).
elessair 0:f269e3021894 423
elessair 0:f269e3021894 424 \return PSP Register value
elessair 0:f269e3021894 425 */
elessair 0:f269e3021894 426 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
elessair 0:f269e3021894 427 {
elessair 0:f269e3021894 428 register uint32_t result;
elessair 0:f269e3021894 429
elessair 0:f269e3021894 430 __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
elessair 0:f269e3021894 431 return(result);
elessair 0:f269e3021894 432 }
elessair 0:f269e3021894 433
elessair 0:f269e3021894 434
elessair 0:f269e3021894 435 /** \brief Set Process Stack Pointer
elessair 0:f269e3021894 436
elessair 0:f269e3021894 437 This function assigns the given value to the Process Stack Pointer (PSP).
elessair 0:f269e3021894 438
elessair 0:f269e3021894 439 \param [in] topOfProcStack Process Stack Pointer value to set
elessair 0:f269e3021894 440 */
elessair 0:f269e3021894 441 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
elessair 0:f269e3021894 442 {
elessair 0:f269e3021894 443 __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
elessair 0:f269e3021894 444 }
elessair 0:f269e3021894 445
elessair 0:f269e3021894 446
elessair 0:f269e3021894 447 /** \brief Get Main Stack Pointer
elessair 0:f269e3021894 448
elessair 0:f269e3021894 449 This function returns the current value of the Main Stack Pointer (MSP).
elessair 0:f269e3021894 450
elessair 0:f269e3021894 451 \return MSP Register value
elessair 0:f269e3021894 452 */
elessair 0:f269e3021894 453 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
elessair 0:f269e3021894 454 {
elessair 0:f269e3021894 455 register uint32_t result;
elessair 0:f269e3021894 456
elessair 0:f269e3021894 457 __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
elessair 0:f269e3021894 458 return(result);
elessair 0:f269e3021894 459 }
elessair 0:f269e3021894 460
elessair 0:f269e3021894 461
elessair 0:f269e3021894 462 /** \brief Set Main Stack Pointer
elessair 0:f269e3021894 463
elessair 0:f269e3021894 464 This function assigns the given value to the Main Stack Pointer (MSP).
elessair 0:f269e3021894 465
elessair 0:f269e3021894 466 \param [in] topOfMainStack Main Stack Pointer value to set
elessair 0:f269e3021894 467 */
elessair 0:f269e3021894 468 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
elessair 0:f269e3021894 469 {
elessair 0:f269e3021894 470 __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
elessair 0:f269e3021894 471 }
elessair 0:f269e3021894 472
elessair 0:f269e3021894 473
elessair 0:f269e3021894 474 /** \brief Get Priority Mask
elessair 0:f269e3021894 475
elessair 0:f269e3021894 476 This function returns the current state of the priority mask bit from the Priority Mask Register.
elessair 0:f269e3021894 477
elessair 0:f269e3021894 478 \return Priority Mask value
elessair 0:f269e3021894 479 */
elessair 0:f269e3021894 480 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
elessair 0:f269e3021894 481 {
elessair 0:f269e3021894 482 uint32_t result;
elessair 0:f269e3021894 483
elessair 0:f269e3021894 484 __ASM volatile ("MRS %0, primask" : "=r" (result) );
elessair 0:f269e3021894 485 return(result);
elessair 0:f269e3021894 486 }
elessair 0:f269e3021894 487
elessair 0:f269e3021894 488
elessair 0:f269e3021894 489 /** \brief Set Priority Mask
elessair 0:f269e3021894 490
elessair 0:f269e3021894 491 This function assigns the given value to the Priority Mask Register.
elessair 0:f269e3021894 492
elessair 0:f269e3021894 493 \param [in] priMask Priority Mask
elessair 0:f269e3021894 494 */
elessair 0:f269e3021894 495 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
elessair 0:f269e3021894 496 {
elessair 0:f269e3021894 497 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
elessair 0:f269e3021894 498 }
elessair 0:f269e3021894 499
elessair 0:f269e3021894 500
elessair 0:f269e3021894 501 #if (__CORTEX_M >= 0x03)
elessair 0:f269e3021894 502
elessair 0:f269e3021894 503 /** \brief Enable FIQ
elessair 0:f269e3021894 504
elessair 0:f269e3021894 505 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
elessair 0:f269e3021894 506 Can only be executed in Privileged modes.
elessair 0:f269e3021894 507 */
elessair 0:f269e3021894 508 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
elessair 0:f269e3021894 509 {
elessair 0:f269e3021894 510 __ASM volatile ("cpsie f" : : : "memory");
elessair 0:f269e3021894 511 }
elessair 0:f269e3021894 512
elessair 0:f269e3021894 513
elessair 0:f269e3021894 514 /** \brief Disable FIQ
elessair 0:f269e3021894 515
elessair 0:f269e3021894 516 This function disables FIQ interrupts by setting the F-bit in the CPSR.
elessair 0:f269e3021894 517 Can only be executed in Privileged modes.
elessair 0:f269e3021894 518 */
elessair 0:f269e3021894 519 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
elessair 0:f269e3021894 520 {
elessair 0:f269e3021894 521 __ASM volatile ("cpsid f" : : : "memory");
elessair 0:f269e3021894 522 }
elessair 0:f269e3021894 523
elessair 0:f269e3021894 524
elessair 0:f269e3021894 525 /** \brief Get Base Priority
elessair 0:f269e3021894 526
elessair 0:f269e3021894 527 This function returns the current value of the Base Priority register.
elessair 0:f269e3021894 528
elessair 0:f269e3021894 529 \return Base Priority register value
elessair 0:f269e3021894 530 */
elessair 0:f269e3021894 531 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
elessair 0:f269e3021894 532 {
elessair 0:f269e3021894 533 uint32_t result;
elessair 0:f269e3021894 534
elessair 0:f269e3021894 535 __ASM volatile ("MRS %0, basepri" : "=r" (result) );
elessair 0:f269e3021894 536 return(result);
elessair 0:f269e3021894 537 }
elessair 0:f269e3021894 538
elessair 0:f269e3021894 539
elessair 0:f269e3021894 540 /** \brief Set Base Priority
elessair 0:f269e3021894 541
elessair 0:f269e3021894 542 This function assigns the given value to the Base Priority register.
elessair 0:f269e3021894 543
elessair 0:f269e3021894 544 \param [in] basePri Base Priority value to set
elessair 0:f269e3021894 545 */
elessair 0:f269e3021894 546 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
elessair 0:f269e3021894 547 {
elessair 0:f269e3021894 548 __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
elessair 0:f269e3021894 549 }
elessair 0:f269e3021894 550
elessair 0:f269e3021894 551
elessair 0:f269e3021894 552 /** \brief Set Base Priority with condition
elessair 0:f269e3021894 553
elessair 0:f269e3021894 554 This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
elessair 0:f269e3021894 555 or the new value increases the BASEPRI priority level.
elessair 0:f269e3021894 556
elessair 0:f269e3021894 557 \param [in] basePri Base Priority value to set
elessair 0:f269e3021894 558 */
elessair 0:f269e3021894 559 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)
elessair 0:f269e3021894 560 {
elessair 0:f269e3021894 561 __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");
elessair 0:f269e3021894 562 }
elessair 0:f269e3021894 563
elessair 0:f269e3021894 564
elessair 0:f269e3021894 565 /** \brief Get Fault Mask
elessair 0:f269e3021894 566
elessair 0:f269e3021894 567 This function returns the current value of the Fault Mask register.
elessair 0:f269e3021894 568
elessair 0:f269e3021894 569 \return Fault Mask register value
elessair 0:f269e3021894 570 */
elessair 0:f269e3021894 571 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
elessair 0:f269e3021894 572 {
elessair 0:f269e3021894 573 uint32_t result;
elessair 0:f269e3021894 574
elessair 0:f269e3021894 575 __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
elessair 0:f269e3021894 576 return(result);
elessair 0:f269e3021894 577 }
elessair 0:f269e3021894 578
elessair 0:f269e3021894 579
elessair 0:f269e3021894 580 /** \brief Set Fault Mask
elessair 0:f269e3021894 581
elessair 0:f269e3021894 582 This function assigns the given value to the Fault Mask register.
elessair 0:f269e3021894 583
elessair 0:f269e3021894 584 \param [in] faultMask Fault Mask value to set
elessair 0:f269e3021894 585 */
elessair 0:f269e3021894 586 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
elessair 0:f269e3021894 587 {
elessair 0:f269e3021894 588 __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
elessair 0:f269e3021894 589 }
elessair 0:f269e3021894 590
elessair 0:f269e3021894 591 #endif /* (__CORTEX_M >= 0x03) */
elessair 0:f269e3021894 592
elessair 0:f269e3021894 593
elessair 0:f269e3021894 594 #if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
elessair 0:f269e3021894 595
elessair 0:f269e3021894 596 /** \brief Get FPSCR
elessair 0:f269e3021894 597
elessair 0:f269e3021894 598 This function returns the current value of the Floating Point Status/Control register.
elessair 0:f269e3021894 599
elessair 0:f269e3021894 600 \return Floating Point Status/Control register value
elessair 0:f269e3021894 601 */
elessair 0:f269e3021894 602 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
elessair 0:f269e3021894 603 {
elessair 0:f269e3021894 604 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
elessair 0:f269e3021894 605 uint32_t result;
elessair 0:f269e3021894 606
elessair 0:f269e3021894 607 /* Empty asm statement works as a scheduling barrier */
elessair 0:f269e3021894 608 __ASM volatile ("");
elessair 0:f269e3021894 609 __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
elessair 0:f269e3021894 610 __ASM volatile ("");
elessair 0:f269e3021894 611 return(result);
elessair 0:f269e3021894 612 #else
elessair 0:f269e3021894 613 return(0);
elessair 0:f269e3021894 614 #endif
elessair 0:f269e3021894 615 }
elessair 0:f269e3021894 616
elessair 0:f269e3021894 617
elessair 0:f269e3021894 618 /** \brief Set FPSCR
elessair 0:f269e3021894 619
elessair 0:f269e3021894 620 This function assigns the given value to the Floating Point Status/Control register.
elessair 0:f269e3021894 621
elessair 0:f269e3021894 622 \param [in] fpscr Floating Point Status/Control value to set
elessair 0:f269e3021894 623 */
elessair 0:f269e3021894 624 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
elessair 0:f269e3021894 625 {
elessair 0:f269e3021894 626 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
elessair 0:f269e3021894 627 /* Empty asm statement works as a scheduling barrier */
elessair 0:f269e3021894 628 __ASM volatile ("");
elessair 0:f269e3021894 629 __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
elessair 0:f269e3021894 630 __ASM volatile ("");
elessair 0:f269e3021894 631 #endif
elessair 0:f269e3021894 632 }
elessair 0:f269e3021894 633
elessair 0:f269e3021894 634 #endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
elessair 0:f269e3021894 635
elessair 0:f269e3021894 636
elessair 0:f269e3021894 637 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
elessair 0:f269e3021894 638 /* IAR iccarm specific functions */
elessair 0:f269e3021894 639 #include <cmsis_iar.h>
elessair 0:f269e3021894 640
elessair 0:f269e3021894 641
elessair 0:f269e3021894 642 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
elessair 0:f269e3021894 643 /* TI CCS specific functions */
elessair 0:f269e3021894 644 #include <cmsis_ccs.h>
elessair 0:f269e3021894 645
elessair 0:f269e3021894 646
elessair 0:f269e3021894 647 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
elessair 0:f269e3021894 648 /* TASKING carm specific functions */
elessair 0:f269e3021894 649 /*
elessair 0:f269e3021894 650 * The CMSIS functions have been implemented as intrinsics in the compiler.
elessair 0:f269e3021894 651 * Please use "carm -?i" to get an up to date list of all intrinsics,
elessair 0:f269e3021894 652 * Including the CMSIS ones.
elessair 0:f269e3021894 653 */
elessair 0:f269e3021894 654
elessair 0:f269e3021894 655
elessair 0:f269e3021894 656 #elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
elessair 0:f269e3021894 657 /* Cosmic specific functions */
elessair 0:f269e3021894 658 #include <cmsis_csm.h>
elessair 0:f269e3021894 659
elessair 0:f269e3021894 660 #endif
elessair 0:f269e3021894 661
elessair 0:f269e3021894 662 /*@} end of CMSIS_Core_RegAccFunctions */
elessair 0:f269e3021894 663
elessair 0:f269e3021894 664 #endif /* __CORE_CMFUNC_H */