Lee Kai Xuan / mbed-os

mbed-os

Fork of mbed-os by erkin yucel

targets/TARGET_ONSEMI/TARGET_NCS36510/wdt_map.h@1:3deb71413561, 2017-07-20 (annotated)

Committer:
xuaner
Date:
Thu Jul 20 14:26:57 2017 +0000
Revision:
1:3deb71413561
Parent:
0:f269e3021894 
mbed_os

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elessair 0:f269e3021894 1 /**
elessair 0:f269e3021894 2 ******************************************************************************
elessair 0:f269e3021894 3 * @file wdt_map.h
elessair 0:f269e3021894 4 * @brief WDT HW register map
elessair 0:f269e3021894 5 * @internal
elessair 0:f269e3021894 6 * @author ON Semiconductor
elessair 0:f269e3021894 7 * $Rev: 3283 $
elessair 0:f269e3021894 8 * $Date: 2015-02-26 18:52:22 +0530 (Thu, 26 Feb 2015) $
elessair 0:f269e3021894 9 ******************************************************************************
elessair 0:f269e3021894 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
elessair 0:f269e3021894 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
elessair 0:f269e3021894 12 * under limited terms and conditions. The terms and conditions pertaining to the software
elessair 0:f269e3021894 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
elessair 0:f269e3021894 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
elessair 0:f269e3021894 15 * if applicable the software license agreement. Do not use this software and/or
elessair 0:f269e3021894 16 * documentation unless you have carefully read and you agree to the limited terms and
elessair 0:f269e3021894 17 * conditions. By using this software and/or documentation, you agree to the limited
elessair 0:f269e3021894 18 * terms and conditions.
elessair 0:f269e3021894 19 *
elessair 0:f269e3021894 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
elessair 0:f269e3021894 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
elessair 0:f269e3021894 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
elessair 0:f269e3021894 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
elessair 0:f269e3021894 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
elessair 0:f269e3021894 25 * @endinternal
elessair 0:f269e3021894 26 *
elessair 0:f269e3021894 27 * @ingroup wdt
elessair 0:f269e3021894 28 *
elessair 0:f269e3021894 29 * @details
elessair 0:f269e3021894 30 * <p>
elessair 0:f269e3021894 31 * Watchdog Timer HW register map description
elessair 0:f269e3021894 32 * </p>
elessair 0:f269e3021894 33 *
elessair 0:f269e3021894 34 */
elessair 0:f269e3021894 35
elessair 0:f269e3021894 36 #if defined ( __CC_ARM )
elessair 0:f269e3021894 37 #pragma anon_unions
elessair 0:f269e3021894 38 #endif
elessair 0:f269e3021894 39
elessair 0:f269e3021894 40 #ifndef WDT_MAP_H_
elessair 0:f269e3021894 41 #define WDT_MAP_H_
elessair 0:f269e3021894 42
elessair 0:f269e3021894 43 #include "architecture.h"
elessair 0:f269e3021894 44
elessair 0:f269e3021894 45 #ifdef REVB
elessair 0:f269e3021894 46 /** Watch Dog Timer Control HW Structure Overlay */
elessair 0:f269e3021894 47 typedef struct {
elessair 0:f269e3021894 48 __IO uint32_t LOAD; /**< Watchdog load value */
elessair 0:f269e3021894 49 __I uint32_t VALUE; /**< Watchdog current value */
elessair 0:f269e3021894 50 union {
elessair 0:f269e3021894 51 struct {
elessair 0:f269e3021894 52 __IO uint32_t INT_EN :1; /**< interrupt event : 0 = disable counter and interrupt , 1 = enable counter and interrupt */
elessair 0:f269e3021894 53 __IO uint32_t RESET_EN :1; /**< Watchdog reset output : 0 = disable 1 = enable */
elessair 0:f269e3021894 54 __IO uint32_t PAD :30; /**< Reserved, read undefined, must read as zeros. */
elessair 0:f269e3021894 55 } BITS;
elessair 0:f269e3021894 56 __IO uint32_t WORD;
elessair 0:f269e3021894 57 } CONTROL;
elessair 0:f269e3021894 58 __IO uint32_t INT_CLEAR; /**< Watchdog interrupt clear */
elessair 0:f269e3021894 59 __I uint32_t RAW_INT_STAT; /**< Raw interrupt status from the counter */
elessair 0:f269e3021894 60 __I uint32_t MASKED_INT_STAT; /**< Enabled interrupt status from the counter */
elessair 0:f269e3021894 61 union {
elessair 0:f269e3021894 62 struct {
elessair 0:f269e3021894 63 __IO uint32_t WRITE_EN :1; /**< write access to all other registers : 0 = enabled(default) , 1 = disabled */
elessair 0:f269e3021894 64 __IO uint32_t REG_WRITE_EN :31; /**< Enable write access to all other registers by writing 0x1ACCE551. Disable it by writing any other value.*/
elessair 0:f269e3021894 65 } BITS;
elessair 0:f269e3021894 66 __IO uint32_t WORD;
elessair 0:f269e3021894 67 } LOCK;
elessair 0:f269e3021894 68 __I uint32_t TEST_CTRL; /**< Integration Test Mode : 0 = disable , 1 = Enable */
elessair 0:f269e3021894 69 union {
elessair 0:f269e3021894 70 struct {
elessair 0:f269e3021894 71 __IO uint32_t VAL_INT :1; /**< Value output on WDOGINT when in Integration Test Mode */
elessair 0:f269e3021894 72 __IO uint32_t VAL_RES :1; /**< Value output on WDOGRES when in Integration Test Mode */
elessair 0:f269e3021894 73 __IO uint32_t PAD:30; /**< Reserved, read undefined, must read as zeros.*/
elessair 0:f269e3021894 74 } BITS;
elessair 0:f269e3021894 75 __IO uint32_t WORD;
elessair 0:f269e3021894 76 } TEST_OUT;
elessair 0:f269e3021894 77 union {
elessair 0:f269e3021894 78 struct {
elessair 0:f269e3021894 79 __IO uint32_t PART_0 :8; /**< These bits read back as 0x05 */
elessair 0:f269e3021894 80 __IO uint32_t PAD :24; /**< Reserved, read undefined, must read as zeros.*/
elessair 0:f269e3021894 81 } BITS;
elessair 0:f269e3021894 82 __IO uint32_t WORD;
elessair 0:f269e3021894 83 } PID_REG0;
elessair 0:f269e3021894 84 union {
elessair 0:f269e3021894 85 struct {
elessair 0:f269e3021894 86 __IO uint32_t PART_1 :4; /**< These bits read back as 0x08 */
elessair 0:f269e3021894 87 __IO uint32_t DESIGNER_0 :4; /**< These bits read back as 0x01 */
elessair 0:f269e3021894 88 __IO uint32_t PAD :24; /**< Reserved, read undefined, must read as zeros.*/
elessair 0:f269e3021894 89 } BITS;
elessair 0:f269e3021894 90 __IO uint32_t WORD;
elessair 0:f269e3021894 91 } PID_REG1;
elessair 0:f269e3021894 92 union {
elessair 0:f269e3021894 93 struct {
elessair 0:f269e3021894 94 __IO uint32_t DESIGNER_1 :4; /**< These bits read back as 0x4 */
elessair 0:f269e3021894 95 __IO uint32_t REVISION :4; /**< These bits read back as 0x0*/
elessair 0:f269e3021894 96 __IO uint32_t PAD :24; /**< Reserved, read undefined, must read as zeros.*/
elessair 0:f269e3021894 97 } BITS;
elessair 0:f269e3021894 98 __IO uint32_t WORD;
elessair 0:f269e3021894 99 } PID_REG2;
elessair 0:f269e3021894 100 union {
elessair 0:f269e3021894 101 struct {
elessair 0:f269e3021894 102 __IO uint32_t CONFIG :8; /**< These bits read back as 0x00 */
elessair 0:f269e3021894 103 __IO uint32_t PAD :24; /**< Reserved, read undefined, must read as zeros.*/
elessair 0:f269e3021894 104 } BITS;
elessair 0:f269e3021894 105 __IO uint32_t WORD;
elessair 0:f269e3021894 106 } PID_REG3;
elessair 0:f269e3021894 107 union {
elessair 0:f269e3021894 108 struct {
elessair 0:f269e3021894 109 __IO uint32_t ID0 :8; /**< These bits read back as 0x0D */
elessair 0:f269e3021894 110 __IO uint32_t PAD :24; /**< Reserved, read undefined, must read as zeros.*/
elessair 0:f269e3021894 111 } BITS;
elessair 0:f269e3021894 112 __IO uint32_t WORD;
elessair 0:f269e3021894 113 } PCELL_ID0;
elessair 0:f269e3021894 114 union {
elessair 0:f269e3021894 115 struct {
elessair 0:f269e3021894 116 __IO uint32_t ID :8; /**< These bits read back as 0xF0*/
elessair 0:f269e3021894 117 __IO uint32_t PAD :24; /**< Reserved, read undefined, must read as zeros.*/
elessair 0:f269e3021894 118 } BITS;
elessair 0:f269e3021894 119 __IO uint32_t WORD;
elessair 0:f269e3021894 120 } PCELL_ID1;
elessair 0:f269e3021894 121 union {
elessair 0:f269e3021894 122 struct {
elessair 0:f269e3021894 123 __IO uint32_t ID :8; /**< These bits read back as 0x05*/
elessair 0:f269e3021894 124 __IO uint32_t PAD :24; /**< Reserved, read undefined, must read as zeros.*/
elessair 0:f269e3021894 125 } BITS;
elessair 0:f269e3021894 126 __IO uint32_t WORD;
elessair 0:f269e3021894 127 } PCELL_ID2;
elessair 0:f269e3021894 128 union {
elessair 0:f269e3021894 129 struct {
elessair 0:f269e3021894 130 __IO uint32_t ID :8; /**< These bits read back as 0xB1*/
elessair 0:f269e3021894 131 __IO uint32_t PAD :24; /**< Reserved, read undefined, must read as zeros.*/
elessair 0:f269e3021894 132 } BITS;
elessair 0:f269e3021894 133 __IO uint32_t WORD;
elessair 0:f269e3021894 134 } PCELL_ID3;
elessair 0:f269e3021894 135 } WdtReg_t, *WdtReg_pt;
elessair 0:f269e3021894 136 #endif /* REVB */
elessair 0:f269e3021894 137
elessair 0:f269e3021894 138 #ifdef REVD
elessair 0:f269e3021894 139 typedef struct {
elessair 0:f269e3021894 140 __IO uint32_t LOAD; /**< 0x4000A000 Contains the value from which the counter is decremented. When this register is written to the count is immediately restarted from the new value. The minimum valid value is 1. */
elessair 0:f269e3021894 141 __I uint32_t CURRENT_VALUE; /**< 0x4000A004 Gives the current value of the decrementing counter */
elessair 0:f269e3021894 142 union {
elessair 0:f269e3021894 143 struct {
elessair 0:f269e3021894 144 __IO uint32_t WDT_EN :1; /**< Watchdog enable, 0 – Watchdog disabled, 1 – Watchdog enabled */
elessair 0:f269e3021894 145 } BITS;
elessair 0:f269e3021894 146 __IO uint32_t WORD;
elessair 0:f269e3021894 147 } CONTROL; /* 0x4000A008 */
elessair 0:f269e3021894 148 __O uint32_t KICK; /**< 0x4000A00C A write of any value to this register reloads the value register from the load register */
elessair 0:f269e3021894 149 __O uint32_t LOCK; /**< 0x4000A010 Use of this register causes write-access to all other registers to be disabled. This is to prevent rogue software from disabling the watchdog functionality. Writing a value of 0x1ACCE551 enables write access to all other registers. Writing any other value disables write access. A read from this register only returns the bottom bit…, 0 – Write access is enabled, 1 – Write access is disabled */
elessair 0:f269e3021894 150 union {
elessair 0:f269e3021894 151 struct {
elessair 0:f269e3021894 152 __I uint32_t WRITE_BUSY_ANY :1; /**< Busy writing any register */
elessair 0:f269e3021894 153 __I uint32_t WRITE_BUSY_LOAD :1; /**< Busy writing the load register */
elessair 0:f269e3021894 154 __I uint32_t WRITE_BUSY_CONTROL :1; /**< Busy writing the control enable register */
elessair 0:f269e3021894 155 __IO uint32_t WRITE_ERROR :1; /**< Error bit. Set when write occurs before previous write completes (busy) */
elessair 0:f269e3021894 156 } BITS;
elessair 0:f269e3021894 157 __IO uint32_t WORD;
elessair 0:f269e3021894 158 } STATUS; /* 0x4000A014 */
elessair 0:f269e3021894 159 } WdtReg_t, *WdtReg_pt;
elessair 0:f269e3021894 160 #endif /* REVD */
elessair 0:f269e3021894 161 #endif /* WDT_MAP_H_ */