Lee Kai Xuan / mbed-os

mbed-os

Fork of mbed-os by erkin yucel

targets/TARGET_ONSEMI/TARGET_NCS36510/pmu_map.h@1:3deb71413561, 2017-07-20 (annotated)

Committer:
xuaner
Date:
Thu Jul 20 14:26:57 2017 +0000
Revision:
1:3deb71413561
Parent:
0:f269e3021894 
mbed_os

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elessair 0:f269e3021894 1 /**
elessair 0:f269e3021894 2 ******************************************************************************
elessair 0:f269e3021894 3 * @file pmu_map.h
elessair 0:f269e3021894 4 * @brief PMU hw module register map
elessair 0:f269e3021894 5 * @internal
elessair 0:f269e3021894 6 * @author ON Semiconductor
elessair 0:f269e3021894 7 * $Rev: 3372 $
elessair 0:f269e3021894 8 * $Date: 2015-04-22 12:18:18 +0530 (Wed, 22 Apr 2015) $
elessair 0:f269e3021894 9 ******************************************************************************
elessair 0:f269e3021894 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
elessair 0:f269e3021894 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
elessair 0:f269e3021894 12 * under limited terms and conditions. The terms and conditions pertaining to the software
elessair 0:f269e3021894 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
elessair 0:f269e3021894 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
elessair 0:f269e3021894 15 * if applicable the software license agreement. Do not use this software and/or
elessair 0:f269e3021894 16 * documentation unless you have carefully read and you agree to the limited terms and
elessair 0:f269e3021894 17 * conditions. By using this software and/or documentation, you agree to the limited
elessair 0:f269e3021894 18 * terms and conditions.
elessair 0:f269e3021894 19 *
elessair 0:f269e3021894 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
elessair 0:f269e3021894 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
elessair 0:f269e3021894 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
elessair 0:f269e3021894 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
elessair 0:f269e3021894 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
elessair 0:f269e3021894 25 * @endinternal
elessair 0:f269e3021894 26 *
elessair 0:f269e3021894 27 * @ingroup pmu
elessair 0:f269e3021894 28 *
elessair 0:f269e3021894 29 * @details
elessair 0:f269e3021894 30 */
elessair 0:f269e3021894 31
elessair 0:f269e3021894 32 #ifndef PMU_MAP_H_
elessair 0:f269e3021894 33 #define PMU_MAP_H_
elessair 0:f269e3021894 34
elessair 0:f269e3021894 35 /*************************************************************************************************
elessair 0:f269e3021894 36 * *
elessair 0:f269e3021894 37 * Header files *
elessair 0:f269e3021894 38 * *
elessair 0:f269e3021894 39 *************************************************************************************************/
elessair 0:f269e3021894 40
elessair 0:f269e3021894 41 #include "architecture.h"
elessair 0:f269e3021894 42
elessair 0:f269e3021894 43 /**************************************************************************************************
elessair 0:f269e3021894 44 * *
elessair 0:f269e3021894 45 * Type definitions *
elessair 0:f269e3021894 46 * *
elessair 0:f269e3021894 47 **************************************************************************************************/
elessair 0:f269e3021894 48
elessair 0:f269e3021894 49 /** PMU control
elessair 0:f269e3021894 50 * The Power Management Unit (PMU) is used to control the differing power modes.
elessair 0:f269e3021894 51 */
elessair 0:f269e3021894 52 typedef struct {
elessair 0:f269e3021894 53 union {
elessair 0:f269e3021894 54 struct {
elessair 0:f269e3021894 55 __IO uint32_t ENCOMA :1; /**< 0- Sleep or SleepDeep depending on System Control Register (see WFI and WFE instructions), 1 – Coma */
elessair 0:f269e3021894 56 __IO uint32_t SRAMA :1; /**< SRAMA Powered in Coma Modes: 0 – SRAM Powered, 1 – SRAM Un-Powered */
elessair 0:f269e3021894 57 __IO uint32_t SRAMB :1; /**< SRAMB Powered in Coma Modes: 0 – SRAM Powered, 1 – SRAM Un-Powered */
elessair 0:f269e3021894 58 __IO uint32_t EXT32K :1; /**< External 32.768kHz Enable: 0 – Disabled (off), 1 – Enabled (on), Hardware guarantees that this oscillator cannot be powered if the internal 32kHz oscillator is already powered down. Hardware insures that one of the 32kHz oscillators is running. */
elessair 0:f269e3021894 59 __IO uint32_t INT32K :1; /**< Internal 32kHz Enable: 0 – Enabled (on), 1 – Disabled (Off), Hardware guarantees that this oscillator cannot be powered down if the external 32.768kHz oscillator is already powered down. Hardware insures that one of the 32kHz oscillators is running. */
elessair 0:f269e3021894 60 __IO uint32_t INT32M :1; /**< Internal 32MHz Enable: 0 – Enabled (on), 1 – Disabled (off), This bit will automatically get cleared when exiting Coma, or SleepDeep modes of operation. This bit should be set by software after switching over to the external 32MHz oscillator using the Oscillator Select bit in the Clock Control register */
elessair 0:f269e3021894 61 __IO uint32_t C1V1:1; /**< Coma mode 1V1 regulator setting: 0 - Linear regulator, 1 - switching regulator */
elessair 0:f269e3021894 62 __IO uint32_t N1V1:1; /**< Regular mode (Run sleep and deepsleep) 1V1 regulator mode: 0 - Linear regulator, 1 - switching regulator */
elessair 0:f269e3021894 63 __IO uint32_t DBGPOW :1; /**< Debugger Power Behavior: 0 – Normal power behavior when the debugger is present, 1 – When debugger is present the ASIC can only enter SleepDeep mode and FVDDH and FVDDL always remain powered. The 32MHz oscillators can never be powered down in this mode either. */
elessair 0:f269e3021894 64 __IO uint32_t UVIC:1; /**< Under voltage indicator control: 0 - disabled, 1 - enabled */
elessair 0:f269e3021894 65 __IO uint32_t UVII:1; /**< Under voltage indicator input: 0 - 1V1 regulator, 1 - FVDDH regulator */
elessair 0:f269e3021894 66 __IO uint32_t UVIR:1; /**< Under voltage indicator reset: 0 - do not reset, 1 - reset */
elessair 0:f269e3021894 67 } BITS;
elessair 0:f269e3021894 68 __IO uint32_t WORD;
elessair 0:f269e3021894 69 } CONTROL; /* 0x4001D000 */
elessair 0:f269e3021894 70 union {
elessair 0:f269e3021894 71 struct {
elessair 0:f269e3021894 72 __I uint32_t BATTDET:1; /**< Detected battery: 0 - 1V, 1 - 3V */
elessair 0:f269e3021894 73 __I uint32_t UVIC:1; /**< Under voltage status: 0 - normal, 1 - low */
elessair 0:f269e3021894 74
elessair 0:f269e3021894 75 } BITS;
elessair 0:f269e3021894 76 __IO uint32_t WORD;
elessair 0:f269e3021894 77 } STATUS; /* 0x4001D004 */
elessair 0:f269e3021894 78
elessair 0:f269e3021894 79 __IO uint32_t PLACEHOLDER; /* 0x4001D008 */
elessair 0:f269e3021894 80 __IO uint32_t FVDD_TSTARTUP; /**< Regulator start time. */ /* 0x4001D00C */
elessair 0:f269e3021894 81 __IO uint32_t PLACEHOLDER1; /* 0x4001D010 */
elessair 0:f269e3021894 82 __IO uint32_t FVDD_TSETTLE; /**< Regulator settle time. */ /* 0x4001D014 */
elessair 0:f269e3021894 83 union {
elessair 0:f269e3021894 84 struct {
elessair 0:f269e3021894 85 __IO uint32_t TH:6; /**< Threshold */
elessair 0:f269e3021894 86 __I uint32_t PAD:2;
elessair 0:f269e3021894 87 __I uint32_t UVIVAL:6; /**< UVI value */
elessair 0:f269e3021894 88 } BITS;
elessair 0:f269e3021894 89 __IO uint32_t WORD;
elessair 0:f269e3021894 90 } UVI_TBASE; /* 0x4001D018 */
elessair 0:f269e3021894 91 __IO uint32_t SRAM_TRIM; /* 0x4001D01C */
elessair 0:f269e3021894 92
elessair 0:f269e3021894 93 } PmuReg_t, *PmuReg_pt;
elessair 0:f269e3021894 94
elessair 0:f269e3021894 95 #endif /* PMU_MAP_H_ */