Lee Kai Xuan / mbed-os

mbed-os

Fork of mbed-os by erkin yucel

targets/TARGET_NUVOTON/TARGET_NUC472/i2c_api.c@1:3deb71413561, 2017-07-20 (annotated)

Committer:
xuaner
Date:
Thu Jul 20 14:26:57 2017 +0000
Revision:
1:3deb71413561
Parent:
0:f269e3021894 
mbed_os

Who changed what in which revision?

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elessair 0:f269e3021894 1 /* mbed Microcontroller Library
elessair 0:f269e3021894 2 * Copyright (c) 2015-2016 Nuvoton
elessair 0:f269e3021894 3 *
elessair 0:f269e3021894 4 * Licensed under the Apache License, Version 2.0 (the "License");
elessair 0:f269e3021894 5 * you may not use this file except in compliance with the License.
elessair 0:f269e3021894 6 * You may obtain a copy of the License at
elessair 0:f269e3021894 7 *
elessair 0:f269e3021894 8 * http://www.apache.org/licenses/LICENSE-2.0
elessair 0:f269e3021894 9 *
elessair 0:f269e3021894 10 * Unless required by applicable law or agreed to in writing, software
elessair 0:f269e3021894 11 * distributed under the License is distributed on an "AS IS" BASIS,
elessair 0:f269e3021894 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
elessair 0:f269e3021894 13 * See the License for the specific language governing permissions and
elessair 0:f269e3021894 14 * limitations under the License.
elessair 0:f269e3021894 15 */
elessair 0:f269e3021894 16
elessair 0:f269e3021894 17 #include "i2c_api.h"
elessair 0:f269e3021894 18
elessair 0:f269e3021894 19 #if DEVICE_I2C
elessair 0:f269e3021894 20
elessair 0:f269e3021894 21 #include "cmsis.h"
elessair 0:f269e3021894 22 #include "pinmap.h"
elessair 0:f269e3021894 23 #include "PeripheralPins.h"
elessair 0:f269e3021894 24 #include "nu_modutil.h"
elessair 0:f269e3021894 25 #include "nu_miscutil.h"
elessair 0:f269e3021894 26 #include "nu_bitutil.h"
elessair 0:f269e3021894 27 #include "critical.h"
elessair 0:f269e3021894 28
elessair 0:f269e3021894 29 #define NU_I2C_DEBUG 0
elessair 0:f269e3021894 30
elessair 0:f269e3021894 31 #if NU_I2C_DEBUG
elessair 0:f269e3021894 32 struct i2c_s MY_I2C;
elessair 0:f269e3021894 33 struct i2c_s MY_I2C_2;
elessair 0:f269e3021894 34 char MY_I2C_STATUS[64];
elessair 0:f269e3021894 35 int MY_I2C_STATUS_POS = 0;
elessair 0:f269e3021894 36 uint32_t MY_I2C_TIMEOUT;
elessair 0:f269e3021894 37 uint32_t MY_I2C_ELAPSED;
elessair 0:f269e3021894 38 uint32_t MY_I2C_T1;
elessair 0:f269e3021894 39 uint32_t MY_I2C_T2;
elessair 0:f269e3021894 40 #endif
elessair 0:f269e3021894 41
elessair 0:f269e3021894 42 struct nu_i2c_var {
elessair 0:f269e3021894 43 i2c_t * obj;
elessair 0:f269e3021894 44 void (*vec)(void);
elessair 0:f269e3021894 45 };
elessair 0:f269e3021894 46
elessair 0:f269e3021894 47 static void i2c0_vec(void);
elessair 0:f269e3021894 48 static void i2c1_vec(void);
elessair 0:f269e3021894 49 static void i2c2_vec(void);
elessair 0:f269e3021894 50 static void i2c3_vec(void);
elessair 0:f269e3021894 51 static void i2c4_vec(void);
elessair 0:f269e3021894 52 static void i2c_irq(i2c_t *obj);
elessair 0:f269e3021894 53 static void i2c_fsm_reset(i2c_t *obj, uint32_t i2c_ctl);
elessair 0:f269e3021894 54
elessair 0:f269e3021894 55 static struct nu_i2c_var i2c0_var = {
elessair 0:f269e3021894 56 .obj = NULL,
elessair 0:f269e3021894 57 .vec = i2c0_vec,
elessair 0:f269e3021894 58 };
elessair 0:f269e3021894 59 static struct nu_i2c_var i2c1_var = {
elessair 0:f269e3021894 60 .obj = NULL,
elessair 0:f269e3021894 61 .vec = i2c1_vec,
elessair 0:f269e3021894 62 };
elessair 0:f269e3021894 63 static struct nu_i2c_var i2c2_var = {
elessair 0:f269e3021894 64 .obj = NULL,
elessair 0:f269e3021894 65 .vec = i2c2_vec,
elessair 0:f269e3021894 66 };
elessair 0:f269e3021894 67 static struct nu_i2c_var i2c3_var = {
elessair 0:f269e3021894 68 .obj = NULL,
elessair 0:f269e3021894 69 .vec = i2c3_vec,
elessair 0:f269e3021894 70 };
elessair 0:f269e3021894 71 static struct nu_i2c_var i2c4_var = {
elessair 0:f269e3021894 72 .obj = NULL,
elessair 0:f269e3021894 73 .vec = i2c4_vec,
elessair 0:f269e3021894 74 };
elessair 0:f269e3021894 75
elessair 0:f269e3021894 76 static uint32_t i2c_modinit_mask = 0;
elessair 0:f269e3021894 77
elessair 0:f269e3021894 78 static const struct nu_modinit_s i2c_modinit_tab[] = {
elessair 0:f269e3021894 79 {I2C_0, I2C0_MODULE, 0, 0, I2C0_RST, I2C0_IRQn, &i2c0_var},
elessair 0:f269e3021894 80 {I2C_1, I2C1_MODULE, 0, 0, I2C1_RST, I2C1_IRQn, &i2c1_var},
elessair 0:f269e3021894 81 {I2C_2, I2C2_MODULE, 0, 0, I2C2_RST, I2C2_IRQn, &i2c2_var},
elessair 0:f269e3021894 82 {I2C_3, I2C3_MODULE, 0, 0, I2C3_RST, I2C3_IRQn, &i2c3_var},
elessair 0:f269e3021894 83 {I2C_4, I2C4_MODULE, 0, 0, I2C4_RST, I2C4_IRQn, &i2c4_var},
elessair 0:f269e3021894 84
elessair 0:f269e3021894 85 {NC, 0, 0, 0, 0, (IRQn_Type) 0, NULL}
elessair 0:f269e3021894 86 };
elessair 0:f269e3021894 87
elessair 0:f269e3021894 88 static int i2c_do_tran(i2c_t *obj, char *buf, int length, int read, int naklastdata);
elessair 0:f269e3021894 89 static int i2c_do_write(i2c_t *obj, char data, int naklastdata);
elessair 0:f269e3021894 90 static int i2c_do_read(i2c_t *obj, char *data, int naklastdata);
elessair 0:f269e3021894 91 static int i2c_do_trsn(i2c_t *obj, uint32_t i2c_ctl, int sync);
elessair 0:f269e3021894 92 #define NU_I2C_TIMEOUT_STAT_INT 500000
elessair 0:f269e3021894 93 #define NU_I2C_TIMEOUT_STOP 500000
elessair 0:f269e3021894 94 static int i2c_poll_status_timeout(i2c_t *obj, int (*is_status)(i2c_t *obj), uint32_t timeout);
elessair 0:f269e3021894 95 static int i2c_poll_tran_heatbeat_timeout(i2c_t *obj, uint32_t timeout);
elessair 0:f269e3021894 96 //static int i2c_is_stat_int(i2c_t *obj);
elessair 0:f269e3021894 97 //static int i2c_is_stop_det(i2c_t *obj);
elessair 0:f269e3021894 98 static int i2c_is_trsn_done(i2c_t *obj);
elessair 0:f269e3021894 99 static int i2c_is_tran_started(i2c_t *obj);
elessair 0:f269e3021894 100 static int i2c_addr2data(int address, int read);
elessair 0:f269e3021894 101 #if DEVICE_I2CSLAVE
elessair 0:f269e3021894 102 // Convert mbed address to BSP address.
elessair 0:f269e3021894 103 static int i2c_addr2bspaddr(int address);
elessair 0:f269e3021894 104 #endif // #if DEVICE_I2CSLAVE
elessair 0:f269e3021894 105 static void i2c_enable_int(i2c_t *obj);
elessair 0:f269e3021894 106 static void i2c_disable_int(i2c_t *obj);
elessair 0:f269e3021894 107 static int i2c_set_int(i2c_t *obj, int inten);
elessair 0:f269e3021894 108
elessair 0:f269e3021894 109 #if DEVICE_I2C_ASYNCH
elessair 0:f269e3021894 110 static void i2c_buffer_set(i2c_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length);
elessair 0:f269e3021894 111 static void i2c_enable_vector_interrupt(i2c_t *obj, uint32_t handler, int enable);
elessair 0:f269e3021894 112 static void i2c_rollback_vector_interrupt(i2c_t *obj);
elessair 0:f269e3021894 113 #endif
elessair 0:f269e3021894 114
elessair 0:f269e3021894 115 #define TRANCTRL_STARTED (1)
elessair 0:f269e3021894 116 #define TRANCTRL_NAKLASTDATA (1 << 1)
elessair 0:f269e3021894 117
elessair 0:f269e3021894 118 uint32_t us_ticker_read(void);
elessair 0:f269e3021894 119
elessair 0:f269e3021894 120 void i2c_init(i2c_t *obj, PinName sda, PinName scl)
elessair 0:f269e3021894 121 {
elessair 0:f269e3021894 122 uint32_t i2c_sda = pinmap_peripheral(sda, PinMap_I2C_SDA);
elessair 0:f269e3021894 123 uint32_t i2c_scl = pinmap_peripheral(scl, PinMap_I2C_SCL);
elessair 0:f269e3021894 124 obj->i2c.i2c = (I2CName) pinmap_merge(i2c_sda, i2c_scl);
elessair 0:f269e3021894 125 MBED_ASSERT((int)obj->i2c.i2c != NC);
elessair 0:f269e3021894 126
elessair 0:f269e3021894 127 const struct nu_modinit_s *modinit = get_modinit(obj->i2c.i2c, i2c_modinit_tab);
elessair 0:f269e3021894 128 MBED_ASSERT(modinit != NULL);
elessair 0:f269e3021894 129 MBED_ASSERT(modinit->modname == obj->i2c.i2c);
elessair 0:f269e3021894 130
elessair 0:f269e3021894 131 // Reset this module
elessair 0:f269e3021894 132 SYS_ResetModule(modinit->rsetidx);
elessair 0:f269e3021894 133
elessair 0:f269e3021894 134 // Enable IP clock
elessair 0:f269e3021894 135 CLK_EnableModuleClock(modinit->clkidx);
elessair 0:f269e3021894 136
elessair 0:f269e3021894 137 pinmap_pinout(sda, PinMap_I2C_SDA);
elessair 0:f269e3021894 138 pinmap_pinout(scl, PinMap_I2C_SCL);
elessair 0:f269e3021894 139
elessair 0:f269e3021894 140 #if DEVICE_I2C_ASYNCH
elessair 0:f269e3021894 141 obj->i2c.dma_usage = DMA_USAGE_NEVER;
elessair 0:f269e3021894 142 obj->i2c.event = 0;
elessair 0:f269e3021894 143 obj->i2c.stop = 0;
elessair 0:f269e3021894 144 obj->i2c.address = 0;
elessair 0:f269e3021894 145 #endif
elessair 0:f269e3021894 146
elessair 0:f269e3021894 147 // NOTE: Setting I2C bus clock to 100 KHz is required. See I2C::I2C in common/I2C.cpp.
elessair 0:f269e3021894 148 I2C_Open((I2C_T *) NU_MODBASE(obj->i2c.i2c), 100000);
elessair 0:f269e3021894 149 // NOTE: INTEN bit and FSM control bits (STA, STO, SI, AA) are packed in one register CTL. We cannot control interrupt through
elessair 0:f269e3021894 150 // INTEN bit without impacting FSM control bits. Use NVIC_EnableIRQ/NVIC_DisableIRQ instead for interrupt control.
elessair 0:f269e3021894 151 I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
elessair 0:f269e3021894 152 i2c_base->CTL |= (I2C_CTL_INTEN_Msk | I2C_CTL_I2CEN_Msk);
elessair 0:f269e3021894 153
elessair 0:f269e3021894 154 // Enable sync-moce vector interrupt.
elessair 0:f269e3021894 155 struct nu_i2c_var *var = (struct nu_i2c_var *) modinit->var;
elessair 0:f269e3021894 156 var->obj = obj;
elessair 0:f269e3021894 157 obj->i2c.tran_ctrl = 0;
elessair 0:f269e3021894 158 obj->i2c.stop = 0;
elessair 0:f269e3021894 159 i2c_enable_vector_interrupt(obj, (uint32_t) var->vec, 1);
elessair 0:f269e3021894 160
elessair 0:f269e3021894 161 // Mark this module to be inited.
elessair 0:f269e3021894 162 int i = modinit - i2c_modinit_tab;
elessair 0:f269e3021894 163 i2c_modinit_mask |= 1 << i;
elessair 0:f269e3021894 164 }
elessair 0:f269e3021894 165
elessair 0:f269e3021894 166 int i2c_start(i2c_t *obj)
elessair 0:f269e3021894 167 {
elessair 0:f269e3021894 168 return i2c_do_trsn(obj, I2C_CTL_STA_Msk | I2C_CTL_SI_Msk, 1);
elessair 0:f269e3021894 169 }
elessair 0:f269e3021894 170
elessair 0:f269e3021894 171 int i2c_stop(i2c_t *obj)
elessair 0:f269e3021894 172 {
elessair 0:f269e3021894 173 return i2c_do_trsn(obj, I2C_CTL_STO_Msk | I2C_CTL_SI_Msk, 1);
elessair 0:f269e3021894 174 }
elessair 0:f269e3021894 175
elessair 0:f269e3021894 176 void i2c_frequency(i2c_t *obj, int hz)
elessair 0:f269e3021894 177 {
elessair 0:f269e3021894 178 I2C_SetBusClockFreq((I2C_T *) NU_MODBASE(obj->i2c.i2c), hz);
elessair 0:f269e3021894 179 }
elessair 0:f269e3021894 180
elessair 0:f269e3021894 181 int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
elessair 0:f269e3021894 182 {
elessair 0:f269e3021894 183 if (i2c_start(obj)) {
elessair 0:f269e3021894 184 i2c_stop(obj);
elessair 0:f269e3021894 185 return I2C_ERROR_BUS_BUSY;
elessair 0:f269e3021894 186 }
elessair 0:f269e3021894 187
elessair 0:f269e3021894 188 if (i2c_do_write(obj, i2c_addr2data(address, 1), 0)) {
elessair 0:f269e3021894 189 i2c_stop(obj);
elessair 0:f269e3021894 190 return I2C_ERROR_NO_SLAVE;
elessair 0:f269e3021894 191 }
elessair 0:f269e3021894 192
elessair 0:f269e3021894 193 // Read in bytes
elessair 0:f269e3021894 194 length = i2c_do_tran(obj, data, length, 1, 1);
elessair 0:f269e3021894 195
elessair 0:f269e3021894 196 // If not repeated start, send stop.
elessair 0:f269e3021894 197 if (stop) {
elessair 0:f269e3021894 198 i2c_stop(obj);
elessair 0:f269e3021894 199 }
elessair 0:f269e3021894 200
elessair 0:f269e3021894 201 return length;
elessair 0:f269e3021894 202 }
elessair 0:f269e3021894 203
elessair 0:f269e3021894 204 int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
elessair 0:f269e3021894 205 {
elessair 0:f269e3021894 206 if (i2c_start(obj)) {
elessair 0:f269e3021894 207 i2c_stop(obj);
elessair 0:f269e3021894 208 return I2C_ERROR_BUS_BUSY;
elessair 0:f269e3021894 209 }
elessair 0:f269e3021894 210
elessair 0:f269e3021894 211 if (i2c_do_write(obj, i2c_addr2data(address, 0), 0)) {
elessair 0:f269e3021894 212 i2c_stop(obj);
elessair 0:f269e3021894 213 return I2C_ERROR_NO_SLAVE;
elessair 0:f269e3021894 214 }
elessair 0:f269e3021894 215
elessair 0:f269e3021894 216 // Write out bytes
elessair 0:f269e3021894 217 length = i2c_do_tran(obj, (char *) data, length, 0, 1);
elessair 0:f269e3021894 218
elessair 0:f269e3021894 219 if (stop) {
elessair 0:f269e3021894 220 i2c_stop(obj);
elessair 0:f269e3021894 221 }
elessair 0:f269e3021894 222
elessair 0:f269e3021894 223 return length;
elessair 0:f269e3021894 224 }
elessair 0:f269e3021894 225
elessair 0:f269e3021894 226 void i2c_reset(i2c_t *obj)
elessair 0:f269e3021894 227 {
elessair 0:f269e3021894 228 i2c_stop(obj);
elessair 0:f269e3021894 229 }
elessair 0:f269e3021894 230
elessair 0:f269e3021894 231 int i2c_byte_read(i2c_t *obj, int last)
elessair 0:f269e3021894 232 {
elessair 0:f269e3021894 233 char data = 0;
elessair 0:f269e3021894 234
elessair 0:f269e3021894 235 i2c_do_read(obj, &data, last);
elessair 0:f269e3021894 236 return data;
elessair 0:f269e3021894 237 }
elessair 0:f269e3021894 238
elessair 0:f269e3021894 239 int i2c_byte_write(i2c_t *obj, int data)
elessair 0:f269e3021894 240 {
elessair 0:f269e3021894 241 return i2c_do_write(obj, (data & 0xFF), 0);
elessair 0:f269e3021894 242 }
elessair 0:f269e3021894 243
elessair 0:f269e3021894 244 #if DEVICE_I2CSLAVE
elessair 0:f269e3021894 245
elessair 0:f269e3021894 246 // See I2CSlave.h
elessair 0:f269e3021894 247 #define NoData 0 // the slave has not been addressed
elessair 0:f269e3021894 248 #define ReadAddressed 1 // the master has requested a read from this slave (slave = transmitter)
elessair 0:f269e3021894 249 #define WriteGeneral 2 // the master is writing to all slave
elessair 0:f269e3021894 250 #define WriteAddressed 3 // the master is writing to this slave (slave = receiver)
elessair 0:f269e3021894 251
elessair 0:f269e3021894 252 void i2c_slave_mode(i2c_t *obj, int enable_slave)
elessair 0:f269e3021894 253 {
elessair 0:f269e3021894 254 I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
elessair 0:f269e3021894 255
elessair 0:f269e3021894 256 i2c_disable_int(obj);
elessair 0:f269e3021894 257
elessair 0:f269e3021894 258 obj->i2c.slaveaddr_state = NoData;
elessair 0:f269e3021894 259
elessair 0:f269e3021894 260 // Switch to not addressed mode
elessair 0:f269e3021894 261 I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_SI_Msk | I2C_CTL_AA_Msk);
elessair 0:f269e3021894 262
elessair 0:f269e3021894 263 i2c_enable_int(obj);
elessair 0:f269e3021894 264 }
elessair 0:f269e3021894 265
elessair 0:f269e3021894 266 int i2c_slave_receive(i2c_t *obj)
elessair 0:f269e3021894 267 {
elessair 0:f269e3021894 268 int slaveaddr_state;
elessair 0:f269e3021894 269
elessair 0:f269e3021894 270 i2c_disable_int(obj);
elessair 0:f269e3021894 271 slaveaddr_state = obj->i2c.slaveaddr_state;
elessair 0:f269e3021894 272 i2c_enable_int(obj);
elessair 0:f269e3021894 273
elessair 0:f269e3021894 274 return slaveaddr_state;
elessair 0:f269e3021894 275 }
elessair 0:f269e3021894 276
elessair 0:f269e3021894 277 int i2c_slave_read(i2c_t *obj, char *data, int length)
elessair 0:f269e3021894 278 {
elessair 0:f269e3021894 279 return i2c_do_tran(obj, data, length, 1, 1);
elessair 0:f269e3021894 280 }
elessair 0:f269e3021894 281
elessair 0:f269e3021894 282 int i2c_slave_write(i2c_t *obj, const char *data, int length)
elessair 0:f269e3021894 283 {
elessair 0:f269e3021894 284 return i2c_do_tran(obj, (char *) data, length, 0, 1);
elessair 0:f269e3021894 285 }
elessair 0:f269e3021894 286
elessair 0:f269e3021894 287 void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask)
elessair 0:f269e3021894 288 {
elessair 0:f269e3021894 289 I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
elessair 0:f269e3021894 290
elessair 0:f269e3021894 291 i2c_disable_int(obj);
elessair 0:f269e3021894 292
elessair 0:f269e3021894 293 I2C_SetSlaveAddr(i2c_base, 0, i2c_addr2bspaddr(address), I2C_GCMODE_ENABLE);
elessair 0:f269e3021894 294
elessair 0:f269e3021894 295 i2c_enable_int(obj);
elessair 0:f269e3021894 296 }
elessair 0:f269e3021894 297
elessair 0:f269e3021894 298 static int i2c_addr2bspaddr(int address)
elessair 0:f269e3021894 299 {
elessair 0:f269e3021894 300 return (address >> 1);
elessair 0:f269e3021894 301 }
elessair 0:f269e3021894 302
elessair 0:f269e3021894 303 #endif // #if DEVICE_I2CSLAVE
elessair 0:f269e3021894 304
elessair 0:f269e3021894 305 static void i2c_enable_int(i2c_t *obj)
elessair 0:f269e3021894 306 {
elessair 0:f269e3021894 307 const struct nu_modinit_s *modinit = get_modinit(obj->i2c.i2c, i2c_modinit_tab);
elessair 0:f269e3021894 308
elessair 0:f269e3021894 309 core_util_critical_section_enter();
elessair 0:f269e3021894 310
elessair 0:f269e3021894 311 // Enable I2C interrupt
elessair 0:f269e3021894 312 NVIC_EnableIRQ(modinit->irq_n);
elessair 0:f269e3021894 313 obj->i2c.inten = 1;
elessair 0:f269e3021894 314
elessair 0:f269e3021894 315 core_util_critical_section_exit();
elessair 0:f269e3021894 316 }
elessair 0:f269e3021894 317
elessair 0:f269e3021894 318 static void i2c_disable_int(i2c_t *obj)
elessair 0:f269e3021894 319 {
elessair 0:f269e3021894 320 const struct nu_modinit_s *modinit = get_modinit(obj->i2c.i2c, i2c_modinit_tab);
elessair 0:f269e3021894 321
elessair 0:f269e3021894 322 core_util_critical_section_enter();
elessair 0:f269e3021894 323
elessair 0:f269e3021894 324 // Disable I2C interrupt
elessair 0:f269e3021894 325 NVIC_DisableIRQ(modinit->irq_n);
elessair 0:f269e3021894 326 obj->i2c.inten = 0;
elessair 0:f269e3021894 327
elessair 0:f269e3021894 328 core_util_critical_section_exit();
elessair 0:f269e3021894 329 }
elessair 0:f269e3021894 330
elessair 0:f269e3021894 331 static int i2c_set_int(i2c_t *obj, int inten)
elessair 0:f269e3021894 332 {
elessair 0:f269e3021894 333 int inten_back;
elessair 0:f269e3021894 334
elessair 0:f269e3021894 335 core_util_critical_section_enter();
elessair 0:f269e3021894 336
elessair 0:f269e3021894 337 inten_back = obj->i2c.inten;
elessair 0:f269e3021894 338
elessair 0:f269e3021894 339 core_util_critical_section_exit();
elessair 0:f269e3021894 340
elessair 0:f269e3021894 341 if (inten) {
elessair 0:f269e3021894 342 i2c_enable_int(obj);
elessair 0:f269e3021894 343 }
elessair 0:f269e3021894 344 else {
elessair 0:f269e3021894 345 i2c_disable_int(obj);
elessair 0:f269e3021894 346 }
elessair 0:f269e3021894 347
elessair 0:f269e3021894 348 return inten_back;
elessair 0:f269e3021894 349 }
elessair 0:f269e3021894 350
elessair 0:f269e3021894 351 int i2c_allow_powerdown(void)
elessair 0:f269e3021894 352 {
elessair 0:f269e3021894 353 uint32_t modinit_mask = i2c_modinit_mask;
elessair 0:f269e3021894 354 while (modinit_mask) {
elessair 0:f269e3021894 355 int i2c_idx = nu_ctz(modinit_mask);
elessair 0:f269e3021894 356 const struct nu_modinit_s *modinit = i2c_modinit_tab + i2c_idx;
elessair 0:f269e3021894 357 struct nu_i2c_var *var = (struct nu_i2c_var *) modinit->var;
elessair 0:f269e3021894 358 if (var->obj) {
elessair 0:f269e3021894 359 // Disallow entering power-down mode if I2C transfer is enabled.
elessair 0:f269e3021894 360 if (i2c_active(var->obj)) {
elessair 0:f269e3021894 361 return 0;
elessair 0:f269e3021894 362 }
elessair 0:f269e3021894 363 }
elessair 0:f269e3021894 364 modinit_mask &= ~(1 << i2c_idx);
elessair 0:f269e3021894 365 }
elessair 0:f269e3021894 366
elessair 0:f269e3021894 367 return 1;
elessair 0:f269e3021894 368 }
elessair 0:f269e3021894 369
elessair 0:f269e3021894 370 static int i2c_do_tran(i2c_t *obj, char *buf, int length, int read, int naklastdata)
elessair 0:f269e3021894 371 {
elessair 0:f269e3021894 372 int tran_len = 0;
elessair 0:f269e3021894 373
elessair 0:f269e3021894 374 i2c_disable_int(obj);
elessair 0:f269e3021894 375 obj->i2c.tran_ctrl = naklastdata ? (TRANCTRL_STARTED | TRANCTRL_NAKLASTDATA) : TRANCTRL_STARTED;
elessair 0:f269e3021894 376 obj->i2c.tran_beg = buf;
elessair 0:f269e3021894 377 obj->i2c.tran_pos = buf;
elessair 0:f269e3021894 378 obj->i2c.tran_end = buf + length;
elessair 0:f269e3021894 379 i2c_enable_int(obj);
elessair 0:f269e3021894 380
elessair 0:f269e3021894 381 if (i2c_poll_tran_heatbeat_timeout(obj, NU_I2C_TIMEOUT_STAT_INT)) {
elessair 0:f269e3021894 382 #if NU_I2C_DEBUG
elessair 0:f269e3021894 383 MY_I2C_2 = obj->i2c;
elessair 0:f269e3021894 384 while (1);
elessair 0:f269e3021894 385 #endif
elessair 0:f269e3021894 386 }
elessair 0:f269e3021894 387 else {
elessair 0:f269e3021894 388 i2c_disable_int(obj);
elessair 0:f269e3021894 389 obj->i2c.tran_ctrl = 0;
elessair 0:f269e3021894 390 tran_len = obj->i2c.tran_pos - obj->i2c.tran_beg;
elessair 0:f269e3021894 391 obj->i2c.tran_beg = NULL;
elessair 0:f269e3021894 392 obj->i2c.tran_pos = NULL;
elessair 0:f269e3021894 393 obj->i2c.tran_end = NULL;
elessair 0:f269e3021894 394 i2c_enable_int(obj);
elessair 0:f269e3021894 395 }
elessair 0:f269e3021894 396
elessair 0:f269e3021894 397 return tran_len;
elessair 0:f269e3021894 398 }
elessair 0:f269e3021894 399
elessair 0:f269e3021894 400 static int i2c_do_write(i2c_t *obj, char data, int naklastdata)
elessair 0:f269e3021894 401 {
elessair 0:f269e3021894 402 char data_[1];
elessair 0:f269e3021894 403 data_[0] = data;
elessair 0:f269e3021894 404 return i2c_do_tran(obj, data_, 1, 0, naklastdata) == 1 ? 0 : I2C_ERROR_BUS_BUSY;
elessair 0:f269e3021894 405 }
elessair 0:f269e3021894 406
elessair 0:f269e3021894 407 static int i2c_do_read(i2c_t *obj, char *data, int naklastdata)
elessair 0:f269e3021894 408 {
elessair 0:f269e3021894 409 return i2c_do_tran(obj, data, 1, 1, naklastdata) == 1 ? 0 : I2C_ERROR_BUS_BUSY;
elessair 0:f269e3021894 410 }
elessair 0:f269e3021894 411
elessair 0:f269e3021894 412 static int i2c_do_trsn(i2c_t *obj, uint32_t i2c_ctl, int sync)
elessair 0:f269e3021894 413 {
elessair 0:f269e3021894 414 I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
elessair 0:f269e3021894 415 int err = 0;
elessair 0:f269e3021894 416
elessair 0:f269e3021894 417 i2c_disable_int(obj);
elessair 0:f269e3021894 418
elessair 0:f269e3021894 419 if (i2c_poll_status_timeout(obj, i2c_is_trsn_done, NU_I2C_TIMEOUT_STAT_INT)) {
elessair 0:f269e3021894 420 err = I2C_ERROR_BUS_BUSY;
elessair 0:f269e3021894 421 #if NU_I2C_DEBUG
elessair 0:f269e3021894 422 MY_I2C_2 = obj->i2c;
elessair 0:f269e3021894 423 while (1);
elessair 0:f269e3021894 424 #endif
elessair 0:f269e3021894 425 }
elessair 0:f269e3021894 426 else {
elessair 0:f269e3021894 427 #if 1
elessair 0:f269e3021894 428 // NOTE: Avoid duplicate Start/Stop. Otherwise, we may meet strange error.
elessair 0:f269e3021894 429 uint32_t status = I2C_GET_STATUS(i2c_base);
elessair 0:f269e3021894 430
elessair 0:f269e3021894 431 switch (status) {
elessair 0:f269e3021894 432 case 0x08: // Start
elessair 0:f269e3021894 433 case 0x10: // Master Repeat Start
elessair 0:f269e3021894 434 if (i2c_ctl & I2C_CTL_STA_Msk) {
elessair 0:f269e3021894 435 return 0;
elessair 0:f269e3021894 436 }
elessair 0:f269e3021894 437 else {
elessair 0:f269e3021894 438 break;
elessair 0:f269e3021894 439 }
elessair 0:f269e3021894 440 case 0xF8: // Bus Released
elessair 0:f269e3021894 441 if (i2c_ctl & (I2C_CTL_STA_Msk | I2C_CTL_STO_Msk) == I2C_CTL_STO_Msk) {
elessair 0:f269e3021894 442 return 0;
elessair 0:f269e3021894 443 }
elessair 0:f269e3021894 444 else {
elessair 0:f269e3021894 445 break;
elessair 0:f269e3021894 446 }
elessair 0:f269e3021894 447 }
elessair 0:f269e3021894 448 #endif
elessair 0:f269e3021894 449 I2C_SET_CONTROL_REG(i2c_base, i2c_ctl);
elessair 0:f269e3021894 450 if (sync && i2c_poll_status_timeout(obj, i2c_is_trsn_done, NU_I2C_TIMEOUT_STAT_INT)) {
elessair 0:f269e3021894 451 err = I2C_ERROR_BUS_BUSY;
elessair 0:f269e3021894 452 #if NU_I2C_DEBUG
elessair 0:f269e3021894 453 MY_I2C_2 = obj->i2c;
elessair 0:f269e3021894 454 while (1);
elessair 0:f269e3021894 455 #endif
elessair 0:f269e3021894 456 }
elessair 0:f269e3021894 457 }
elessair 0:f269e3021894 458
elessair 0:f269e3021894 459 i2c_enable_int(obj);
elessair 0:f269e3021894 460
elessair 0:f269e3021894 461 return err;
elessair 0:f269e3021894 462 }
elessair 0:f269e3021894 463
elessair 0:f269e3021894 464 static int i2c_poll_status_timeout(i2c_t *obj, int (*is_status)(i2c_t *obj), uint32_t timeout)
elessair 0:f269e3021894 465 {
elessair 0:f269e3021894 466 uint32_t t1, t2, elapsed = 0;
elessair 0:f269e3021894 467 int status_assert = 0;
elessair 0:f269e3021894 468
elessair 0:f269e3021894 469 t1 = us_ticker_read();
elessair 0:f269e3021894 470 while (1) {
elessair 0:f269e3021894 471 status_assert = is_status(obj);
elessair 0:f269e3021894 472 if (status_assert) {
elessair 0:f269e3021894 473 break;
elessair 0:f269e3021894 474 }
elessair 0:f269e3021894 475
elessair 0:f269e3021894 476 t2 = us_ticker_read();
elessair 0:f269e3021894 477 elapsed = (t2 > t1) ? (t2 - t1) : ((uint64_t) t2 + 0xFFFFFFFF - t1 + 1);
elessair 0:f269e3021894 478 if (elapsed >= timeout) {
elessair 0:f269e3021894 479 #if NU_I2C_DEBUG
elessair 0:f269e3021894 480 MY_I2C_T1 = t1;
elessair 0:f269e3021894 481 MY_I2C_T2 = t2;
elessair 0:f269e3021894 482 MY_I2C_ELAPSED = elapsed;
elessair 0:f269e3021894 483 MY_I2C_TIMEOUT = timeout;
elessair 0:f269e3021894 484 MY_I2C_2 = obj->i2c;
elessair 0:f269e3021894 485 while (1);
elessair 0:f269e3021894 486 #endif
elessair 0:f269e3021894 487 break;
elessair 0:f269e3021894 488 }
elessair 0:f269e3021894 489 }
elessair 0:f269e3021894 490
elessair 0:f269e3021894 491 return (elapsed >= timeout);
elessair 0:f269e3021894 492 }
elessair 0:f269e3021894 493
elessair 0:f269e3021894 494 static int i2c_poll_tran_heatbeat_timeout(i2c_t *obj, uint32_t timeout)
elessair 0:f269e3021894 495 {
elessair 0:f269e3021894 496 uint32_t t1, t2, elapsed = 0;
elessair 0:f269e3021894 497 int tran_started;
elessair 0:f269e3021894 498 char *tran_pos = NULL;
elessair 0:f269e3021894 499 char *tran_pos2 = NULL;
elessair 0:f269e3021894 500
elessair 0:f269e3021894 501 i2c_disable_int(obj);
elessair 0:f269e3021894 502 tran_pos = obj->i2c.tran_pos;
elessair 0:f269e3021894 503 i2c_enable_int(obj);
elessair 0:f269e3021894 504 t1 = us_ticker_read();
elessair 0:f269e3021894 505 while (1) {
elessair 0:f269e3021894 506 i2c_disable_int(obj);
elessair 0:f269e3021894 507 tran_started = i2c_is_tran_started(obj);
elessair 0:f269e3021894 508 i2c_enable_int(obj);
elessair 0:f269e3021894 509 if (! tran_started) { // Transfer completed or stopped
elessair 0:f269e3021894 510 break;
elessair 0:f269e3021894 511 }
elessair 0:f269e3021894 512
elessair 0:f269e3021894 513 i2c_disable_int(obj);
elessair 0:f269e3021894 514 tran_pos2 = obj->i2c.tran_pos;
elessair 0:f269e3021894 515 i2c_enable_int(obj);
elessair 0:f269e3021894 516 t2 = us_ticker_read();
elessair 0:f269e3021894 517 if (tran_pos2 != tran_pos) { // Transfer on-going
elessair 0:f269e3021894 518 t1 = t2;
elessair 0:f269e3021894 519 tran_pos = tran_pos2;
elessair 0:f269e3021894 520 continue;
elessair 0:f269e3021894 521 }
elessair 0:f269e3021894 522
elessair 0:f269e3021894 523 elapsed = (t2 > t1) ? (t2 - t1) : ((uint64_t) t2 + 0xFFFFFFFF - t1 + 1);
elessair 0:f269e3021894 524 if (elapsed >= timeout) { // Transfer idle
elessair 0:f269e3021894 525 #if NU_I2C_DEBUG
elessair 0:f269e3021894 526 MY_I2C = obj->i2c;
elessair 0:f269e3021894 527 MY_I2C_T1 = t1;
elessair 0:f269e3021894 528 MY_I2C_T2 = t2;
elessair 0:f269e3021894 529 MY_I2C_ELAPSED = elapsed;
elessair 0:f269e3021894 530 MY_I2C_TIMEOUT = timeout;
elessair 0:f269e3021894 531 MY_I2C_2 = obj->i2c;
elessair 0:f269e3021894 532 while (1);
elessair 0:f269e3021894 533 #endif
elessair 0:f269e3021894 534 break;
elessair 0:f269e3021894 535 }
elessair 0:f269e3021894 536 }
elessair 0:f269e3021894 537
elessair 0:f269e3021894 538 return (elapsed >= timeout);
elessair 0:f269e3021894 539 }
elessair 0:f269e3021894 540
elessair 0:f269e3021894 541 #if 0
elessair 0:f269e3021894 542 static int i2c_is_stat_int(i2c_t *obj)
elessair 0:f269e3021894 543 {
elessair 0:f269e3021894 544 I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
elessair 0:f269e3021894 545
elessair 0:f269e3021894 546 return !! (i2c_base->CTL & I2C_CTL_SI_Msk);
elessair 0:f269e3021894 547 }
elessair 0:f269e3021894 548
elessair 0:f269e3021894 549
elessair 0:f269e3021894 550 static int i2c_is_stop_det(i2c_t *obj)
elessair 0:f269e3021894 551 {
elessair 0:f269e3021894 552 I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
elessair 0:f269e3021894 553
elessair 0:f269e3021894 554 return ! (i2c_base->CTL & I2C_CTL_STO_Msk);
elessair 0:f269e3021894 555 }
elessair 0:f269e3021894 556 #endif
elessair 0:f269e3021894 557
elessair 0:f269e3021894 558 static int i2c_is_trsn_done(i2c_t *obj)
elessair 0:f269e3021894 559 {
elessair 0:f269e3021894 560 I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
elessair 0:f269e3021894 561 int i2c_int;
elessair 0:f269e3021894 562 uint32_t status;
elessair 0:f269e3021894 563 int inten_back;
elessair 0:f269e3021894 564
elessair 0:f269e3021894 565 inten_back = i2c_set_int(obj, 0);
elessair 0:f269e3021894 566 i2c_int = !! (i2c_base->CTL & I2C_CTL_SI_Msk);
elessair 0:f269e3021894 567 status = I2C_GET_STATUS(i2c_base);
elessair 0:f269e3021894 568 i2c_set_int(obj, inten_back);
elessair 0:f269e3021894 569
elessair 0:f269e3021894 570 return (i2c_int || status == 0xF8);
elessair 0:f269e3021894 571 }
elessair 0:f269e3021894 572
elessair 0:f269e3021894 573 static int i2c_is_tran_started(i2c_t *obj)
elessair 0:f269e3021894 574 {
elessair 0:f269e3021894 575 int started;
elessair 0:f269e3021894 576 int inten_back;
elessair 0:f269e3021894 577
elessair 0:f269e3021894 578 inten_back = i2c_set_int(obj, 0);
elessair 0:f269e3021894 579 started = !! (obj->i2c.tran_ctrl & TRANCTRL_STARTED);
elessair 0:f269e3021894 580 i2c_set_int(obj, inten_back);
elessair 0:f269e3021894 581
elessair 0:f269e3021894 582 return started;
elessair 0:f269e3021894 583 }
elessair 0:f269e3021894 584
elessair 0:f269e3021894 585 static int i2c_addr2data(int address, int read)
elessair 0:f269e3021894 586 {
elessair 0:f269e3021894 587 return read ? (address | 1) : (address & 0xFE);
elessair 0:f269e3021894 588 }
elessair 0:f269e3021894 589
elessair 0:f269e3021894 590 static void i2c0_vec(void)
elessair 0:f269e3021894 591 {
elessair 0:f269e3021894 592 i2c_irq(i2c0_var.obj);
elessair 0:f269e3021894 593 }
elessair 0:f269e3021894 594 static void i2c1_vec(void)
elessair 0:f269e3021894 595 {
elessair 0:f269e3021894 596 i2c_irq(i2c1_var.obj);
elessair 0:f269e3021894 597 }
elessair 0:f269e3021894 598 static void i2c2_vec(void)
elessair 0:f269e3021894 599 {
elessair 0:f269e3021894 600 i2c_irq(i2c2_var.obj);
elessair 0:f269e3021894 601 }
elessair 0:f269e3021894 602 static void i2c3_vec(void)
elessair 0:f269e3021894 603 {
elessair 0:f269e3021894 604 i2c_irq(i2c3_var.obj);
elessair 0:f269e3021894 605 }
elessair 0:f269e3021894 606 static void i2c4_vec(void)
elessair 0:f269e3021894 607 {
elessair 0:f269e3021894 608 i2c_irq(i2c4_var.obj);
elessair 0:f269e3021894 609 }
elessair 0:f269e3021894 610
elessair 0:f269e3021894 611 static void i2c_irq(i2c_t *obj)
elessair 0:f269e3021894 612 {
elessair 0:f269e3021894 613 I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
elessair 0:f269e3021894 614 uint32_t status;
elessair 0:f269e3021894 615
elessair 0:f269e3021894 616 if (I2C_GET_TIMEOUT_FLAG(i2c_base)) {
elessair 0:f269e3021894 617 I2C_ClearTimeoutFlag(i2c_base);
elessair 0:f269e3021894 618 return;
elessair 0:f269e3021894 619 }
elessair 0:f269e3021894 620
elessair 0:f269e3021894 621 status = I2C_GET_STATUS(i2c_base);
elessair 0:f269e3021894 622 #if NU_I2C_DEBUG
elessair 0:f269e3021894 623 if (MY_I2C_STATUS_POS < (sizeof (MY_I2C_STATUS) / sizeof (MY_I2C_STATUS[0]))) {
elessair 0:f269e3021894 624 MY_I2C_STATUS[MY_I2C_STATUS_POS ++] = status;
elessair 0:f269e3021894 625 }
elessair 0:f269e3021894 626 else {
elessair 0:f269e3021894 627 memset(MY_I2C_STATUS, 0x00, sizeof (MY_I2C_STATUS));
elessair 0:f269e3021894 628 MY_I2C_STATUS_POS = 0;
elessair 0:f269e3021894 629 }
elessair 0:f269e3021894 630 #endif
elessair 0:f269e3021894 631
elessair 0:f269e3021894 632 switch (status) {
elessair 0:f269e3021894 633 // Master Transmit
elessair 0:f269e3021894 634 case 0x28: // Master Transmit Data ACK
elessair 0:f269e3021894 635 case 0x18: // Master Transmit Address ACK
elessair 0:f269e3021894 636 case 0x08: // Start
elessair 0:f269e3021894 637 case 0x10: // Master Repeat Start
elessair 0:f269e3021894 638 if ((obj->i2c.tran_ctrl & TRANCTRL_STARTED) && obj->i2c.tran_pos) {
elessair 0:f269e3021894 639 if (obj->i2c.tran_pos < obj->i2c.tran_end) {
elessair 0:f269e3021894 640 I2C_SET_DATA(i2c_base, *obj->i2c.tran_pos ++);
elessair 0:f269e3021894 641 I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_SI_Msk | I2C_CTL_AA_Msk);
elessair 0:f269e3021894 642 }
elessair 0:f269e3021894 643 else {
elessair 0:f269e3021894 644 if (status == 0x18) {
elessair 0:f269e3021894 645 obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED;
elessair 0:f269e3021894 646 i2c_disable_int(obj);
elessair 0:f269e3021894 647 break;
elessair 0:f269e3021894 648 }
elessair 0:f269e3021894 649 // Go Master Repeat Start
elessair 0:f269e3021894 650 i2c_fsm_reset(obj, I2C_CTL_STA_Msk | I2C_CTL_SI_Msk);
elessair 0:f269e3021894 651 }
elessair 0:f269e3021894 652 }
elessair 0:f269e3021894 653 else {
elessair 0:f269e3021894 654 i2c_disable_int(obj);
elessair 0:f269e3021894 655 }
elessair 0:f269e3021894 656 break;
elessair 0:f269e3021894 657 case 0x30: // Master Transmit Data NACK
elessair 0:f269e3021894 658 case 0x20: // Master Transmit Address NACK
elessair 0:f269e3021894 659 // Go Master Repeat Start
elessair 0:f269e3021894 660 i2c_fsm_reset(obj, I2C_CTL_STA_Msk | I2C_CTL_SI_Msk);
elessair 0:f269e3021894 661 break;
elessair 0:f269e3021894 662 case 0x38: // Master Arbitration Lost
elessair 0:f269e3021894 663 i2c_fsm_reset(obj, I2C_CTL_SI_Msk | I2C_CTL_AA_Msk);
elessair 0:f269e3021894 664 break;
elessair 0:f269e3021894 665
elessair 0:f269e3021894 666 case 0x48: // Master Receive Address NACK
elessair 0:f269e3021894 667 // Go Master Stop.
elessair 0:f269e3021894 668 // Go Master Repeat Start
elessair 0:f269e3021894 669 i2c_fsm_reset(obj, I2C_CTL_STA_Msk | I2C_CTL_SI_Msk);
elessair 0:f269e3021894 670 break;
elessair 0:f269e3021894 671 case 0x40: // Master Receive Address ACK
elessair 0:f269e3021894 672 case 0x50: // Master Receive Data ACK
elessair 0:f269e3021894 673 case 0x58: // Master Receive Data NACK
elessair 0:f269e3021894 674 if ((obj->i2c.tran_ctrl & TRANCTRL_STARTED) && obj->i2c.tran_pos) {
elessair 0:f269e3021894 675 if (obj->i2c.tran_pos < obj->i2c.tran_end) {
elessair 0:f269e3021894 676 if (status == 0x50 || status == 0x58) {
elessair 0:f269e3021894 677 *obj->i2c.tran_pos ++ = I2C_GET_DATA(i2c_base);
elessair 0:f269e3021894 678 }
elessair 0:f269e3021894 679
elessair 0:f269e3021894 680 if (status == 0x58) {
elessair 0:f269e3021894 681 #if NU_I2C_DEBUG
elessair 0:f269e3021894 682 if (obj->i2c.tran_pos != obj->i2c.tran_end) {
elessair 0:f269e3021894 683 MY_I2C = obj->i2c;
elessair 0:f269e3021894 684 while (1);
elessair 0:f269e3021894 685 }
elessair 0:f269e3021894 686 #endif
elessair 0:f269e3021894 687 // Go Master Repeat Start
elessair 0:f269e3021894 688 i2c_fsm_reset(obj, I2C_CTL_STA_Msk | I2C_CTL_SI_Msk);
elessair 0:f269e3021894 689 }
elessair 0:f269e3021894 690 else {
elessair 0:f269e3021894 691 uint32_t i2c_ctl = I2C_CTL_SI_Msk | I2C_CTL_AA_Msk;
elessair 0:f269e3021894 692 if ((obj->i2c.tran_end - obj->i2c.tran_pos) == 1 &&
elessair 0:f269e3021894 693 obj->i2c.tran_ctrl & TRANCTRL_NAKLASTDATA) {
elessair 0:f269e3021894 694 // Last data
elessair 0:f269e3021894 695 i2c_ctl &= ~I2C_CTL_AA_Msk;
elessair 0:f269e3021894 696 }
elessair 0:f269e3021894 697 I2C_SET_CONTROL_REG(i2c_base, i2c_ctl);
elessair 0:f269e3021894 698 }
elessair 0:f269e3021894 699 }
elessair 0:f269e3021894 700 else {
elessair 0:f269e3021894 701 obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED;
elessair 0:f269e3021894 702 i2c_disable_int(obj);
elessair 0:f269e3021894 703 break;
elessair 0:f269e3021894 704 }
elessair 0:f269e3021894 705 }
elessair 0:f269e3021894 706 else {
elessair 0:f269e3021894 707 i2c_disable_int(obj);
elessair 0:f269e3021894 708 }
elessair 0:f269e3021894 709 break;
elessair 0:f269e3021894 710
elessair 0:f269e3021894 711 //case 0x00: // Bus error
elessair 0:f269e3021894 712
elessair 0:f269e3021894 713 // Slave Transmit
elessair 0:f269e3021894 714 case 0xB8: // Slave Transmit Data ACK
elessair 0:f269e3021894 715 case 0xA8: // Slave Transmit Address ACK
elessair 0:f269e3021894 716 case 0xB0: // Slave Transmit Arbitration Lost
elessair 0:f269e3021894 717 if ((obj->i2c.tran_ctrl & TRANCTRL_STARTED) && obj->i2c.tran_pos) {
elessair 0:f269e3021894 718 if (obj->i2c.tran_pos < obj->i2c.tran_end) {
elessair 0:f269e3021894 719 uint32_t i2c_ctl = I2C_CTL_SI_Msk | I2C_CTL_AA_Msk;
elessair 0:f269e3021894 720
elessair 0:f269e3021894 721 I2C_SET_DATA(i2c_base, *obj->i2c.tran_pos ++);
elessair 0:f269e3021894 722 if (obj->i2c.tran_pos == obj->i2c.tran_end &&
elessair 0:f269e3021894 723 obj->i2c.tran_ctrl & TRANCTRL_NAKLASTDATA) {
elessair 0:f269e3021894 724 // Last data
elessair 0:f269e3021894 725 i2c_ctl &= ~I2C_CTL_AA_Msk;
elessair 0:f269e3021894 726 }
elessair 0:f269e3021894 727 I2C_SET_CONTROL_REG(i2c_base, i2c_ctl);
elessair 0:f269e3021894 728 }
elessair 0:f269e3021894 729 else {
elessair 0:f269e3021894 730 obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED;
elessair 0:f269e3021894 731 i2c_disable_int(obj);
elessair 0:f269e3021894 732 break;
elessair 0:f269e3021894 733 }
elessair 0:f269e3021894 734 }
elessair 0:f269e3021894 735 else {
elessair 0:f269e3021894 736 i2c_disable_int(obj);
elessair 0:f269e3021894 737 }
elessair 0:f269e3021894 738 obj->i2c.slaveaddr_state = ReadAddressed;
elessair 0:f269e3021894 739 break;
elessair 0:f269e3021894 740 //case 0xA0: // Slave Transmit Repeat Start or Stop
elessair 0:f269e3021894 741 case 0xC0: // Slave Transmit Data NACK
elessair 0:f269e3021894 742 case 0xC8: // Slave Transmit Last Data ACK
elessair 0:f269e3021894 743 obj->i2c.slaveaddr_state = NoData;
elessair 0:f269e3021894 744 i2c_fsm_reset(obj, I2C_CTL_SI_Msk | I2C_CTL_AA_Msk);
elessair 0:f269e3021894 745 break;
elessair 0:f269e3021894 746
elessair 0:f269e3021894 747 // Slave Receive
elessair 0:f269e3021894 748 case 0x80: // Slave Receive Data ACK
elessair 0:f269e3021894 749 case 0x88: // Slave Receive Data NACK
elessair 0:f269e3021894 750 case 0x60: // Slave Receive Address ACK
elessair 0:f269e3021894 751 case 0x68: // Slave Receive Arbitration Lost
elessair 0:f269e3021894 752 obj->i2c.slaveaddr_state = WriteAddressed;
elessair 0:f269e3021894 753 if ((obj->i2c.tran_ctrl & TRANCTRL_STARTED) && obj->i2c.tran_pos) {
elessair 0:f269e3021894 754 if (obj->i2c.tran_pos < obj->i2c.tran_end) {
elessair 0:f269e3021894 755 if (status == 0x80 || status == 0x88) {
elessair 0:f269e3021894 756 *obj->i2c.tran_pos ++ = I2C_GET_DATA(i2c_base);
elessair 0:f269e3021894 757 }
elessair 0:f269e3021894 758
elessair 0:f269e3021894 759 if (status == 0x88) {
elessair 0:f269e3021894 760 #if NU_I2C_DEBUG
elessair 0:f269e3021894 761 if (obj->i2c.tran_pos != obj->i2c.tran_end) {
elessair 0:f269e3021894 762 MY_I2C = obj->i2c;
elessair 0:f269e3021894 763 while (1);
elessair 0:f269e3021894 764 }
elessair 0:f269e3021894 765 #endif
elessair 0:f269e3021894 766 obj->i2c.slaveaddr_state = NoData;
elessair 0:f269e3021894 767 i2c_fsm_reset(obj, I2C_CTL_SI_Msk | I2C_CTL_AA_Msk);
elessair 0:f269e3021894 768 }
elessair 0:f269e3021894 769 else {
elessair 0:f269e3021894 770 uint32_t i2c_ctl = I2C_CTL_SI_Msk | I2C_CTL_AA_Msk;
elessair 0:f269e3021894 771 if ((obj->i2c.tran_end - obj->i2c.tran_pos) == 1 &&
elessair 0:f269e3021894 772 obj->i2c.tran_ctrl & TRANCTRL_NAKLASTDATA) {
elessair 0:f269e3021894 773 // Last data
elessair 0:f269e3021894 774 i2c_ctl &= ~I2C_CTL_AA_Msk;
elessair 0:f269e3021894 775 }
elessair 0:f269e3021894 776 I2C_SET_CONTROL_REG(i2c_base, i2c_ctl);
elessair 0:f269e3021894 777 }
elessair 0:f269e3021894 778 }
elessair 0:f269e3021894 779 else {
elessair 0:f269e3021894 780 obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED;
elessair 0:f269e3021894 781 i2c_disable_int(obj);
elessair 0:f269e3021894 782 break;
elessair 0:f269e3021894 783 }
elessair 0:f269e3021894 784 }
elessair 0:f269e3021894 785 else {
elessair 0:f269e3021894 786 i2c_disable_int(obj);
elessair 0:f269e3021894 787 }
elessair 0:f269e3021894 788 break;
elessair 0:f269e3021894 789 //case 0xA0: // Slave Receive Repeat Start or Stop
elessair 0:f269e3021894 790
elessair 0:f269e3021894 791 // GC mode
elessair 0:f269e3021894 792 //case 0xA0: // GC mode Repeat Start or Stop
elessair 0:f269e3021894 793 case 0x90: // GC mode Data ACK
elessair 0:f269e3021894 794 case 0x98: // GC mode Data NACK
elessair 0:f269e3021894 795 case 0x70: // GC mode Address ACK
elessair 0:f269e3021894 796 case 0x78: // GC mode Arbitration Lost
elessair 0:f269e3021894 797 obj->i2c.slaveaddr_state = WriteAddressed;
elessair 0:f269e3021894 798 if ((obj->i2c.tran_ctrl & TRANCTRL_STARTED) && obj->i2c.tran_pos) {
elessair 0:f269e3021894 799 if (obj->i2c.tran_pos < obj->i2c.tran_end) {
elessair 0:f269e3021894 800 if (status == 0x90 || status == 0x98) {
elessair 0:f269e3021894 801 *obj->i2c.tran_pos ++ = I2C_GET_DATA(i2c_base);
elessair 0:f269e3021894 802 }
elessair 0:f269e3021894 803
elessair 0:f269e3021894 804 if (status == 0x98) {
elessair 0:f269e3021894 805 #if NU_I2C_DEBUG
elessair 0:f269e3021894 806 if (obj->i2c.tran_pos != obj->i2c.tran_end) {
elessair 0:f269e3021894 807 MY_I2C = obj->i2c;
elessair 0:f269e3021894 808 while (1);
elessair 0:f269e3021894 809 }
elessair 0:f269e3021894 810 #endif
elessair 0:f269e3021894 811 obj->i2c.slaveaddr_state = NoData;
elessair 0:f269e3021894 812 i2c_fsm_reset(obj, I2C_CTL_SI_Msk | I2C_CTL_AA_Msk);
elessair 0:f269e3021894 813 }
elessair 0:f269e3021894 814 else {
elessair 0:f269e3021894 815 uint32_t i2c_ctl = I2C_CTL_SI_Msk | I2C_CTL_AA_Msk;
elessair 0:f269e3021894 816 if ((obj->i2c.tran_end - obj->i2c.tran_pos) == 1 &&
elessair 0:f269e3021894 817 obj->i2c.tran_ctrl & TRANCTRL_NAKLASTDATA) {
elessair 0:f269e3021894 818 // Last data
elessair 0:f269e3021894 819 i2c_ctl &= ~I2C_CTL_AA_Msk;
elessair 0:f269e3021894 820 }
elessair 0:f269e3021894 821 I2C_SET_CONTROL_REG(i2c_base, i2c_ctl);
elessair 0:f269e3021894 822 }
elessair 0:f269e3021894 823 }
elessair 0:f269e3021894 824 else {
elessair 0:f269e3021894 825 obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED;
elessair 0:f269e3021894 826 i2c_disable_int(obj);
elessair 0:f269e3021894 827 break;
elessair 0:f269e3021894 828 }
elessair 0:f269e3021894 829 }
elessair 0:f269e3021894 830 else {
elessair 0:f269e3021894 831 i2c_disable_int(obj);
elessair 0:f269e3021894 832 }
elessair 0:f269e3021894 833 break;
elessair 0:f269e3021894 834
elessair 0:f269e3021894 835 case 0xF8: // Bus Released
elessair 0:f269e3021894 836 break;
elessair 0:f269e3021894 837
elessair 0:f269e3021894 838 default:
elessair 0:f269e3021894 839 i2c_fsm_reset(obj, I2C_CTL_SI_Msk | I2C_CTL_AA_Msk);
elessair 0:f269e3021894 840 }
elessair 0:f269e3021894 841 }
elessair 0:f269e3021894 842
elessair 0:f269e3021894 843 static void i2c_fsm_reset(i2c_t *obj, uint32_t i2c_ctl)
elessair 0:f269e3021894 844 {
elessair 0:f269e3021894 845 I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
elessair 0:f269e3021894 846
elessair 0:f269e3021894 847 obj->i2c.stop = 0;
elessair 0:f269e3021894 848
elessair 0:f269e3021894 849 obj->i2c.tran_ctrl = 0;
elessair 0:f269e3021894 850
elessair 0:f269e3021894 851 I2C_SET_CONTROL_REG(i2c_base, i2c_ctl);
elessair 0:f269e3021894 852 obj->i2c.slaveaddr_state = NoData;
elessair 0:f269e3021894 853 }
elessair 0:f269e3021894 854
elessair 0:f269e3021894 855
elessair 0:f269e3021894 856 #if DEVICE_I2C_ASYNCH
elessair 0:f269e3021894 857
elessair 0:f269e3021894 858 void i2c_transfer_asynch(i2c_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint32_t address, uint32_t stop, uint32_t handler, uint32_t event, DMAUsage hint)
elessair 0:f269e3021894 859 {
elessair 0:f269e3021894 860 // NOTE: NUC472 I2C only supports 7-bit slave address. The mbed I2C address passed in is shifted left by 1 bit (7-bit addr << 1).
elessair 0:f269e3021894 861 MBED_ASSERT((address & 0xFFFFFF00) == 0);
elessair 0:f269e3021894 862
elessair 0:f269e3021894 863 // NOTE: First transmit and then receive.
elessair 0:f269e3021894 864
elessair 0:f269e3021894 865 (void) hint;
elessair 0:f269e3021894 866 obj->i2c.dma_usage = DMA_USAGE_NEVER;
elessair 0:f269e3021894 867 obj->i2c.stop = stop;
elessair 0:f269e3021894 868 obj->i2c.address = address;
elessair 0:f269e3021894 869 obj->i2c.event = event;
elessair 0:f269e3021894 870 i2c_buffer_set(obj, tx, tx_length, rx, rx_length);
elessair 0:f269e3021894 871
elessair 0:f269e3021894 872 //I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
elessair 0:f269e3021894 873
elessair 0:f269e3021894 874 i2c_enable_vector_interrupt(obj, handler, 1);
elessair 0:f269e3021894 875 i2c_start(obj);
elessair 0:f269e3021894 876 }
elessair 0:f269e3021894 877
elessair 0:f269e3021894 878 uint32_t i2c_irq_handler_asynch(i2c_t *obj)
elessair 0:f269e3021894 879 {
elessair 0:f269e3021894 880 int event = 0;
elessair 0:f269e3021894 881
elessair 0:f269e3021894 882 I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
elessair 0:f269e3021894 883 uint32_t status = I2C_GET_STATUS(i2c_base);
elessair 0:f269e3021894 884 switch (status) {
elessair 0:f269e3021894 885 case 0x08: // Start
elessair 0:f269e3021894 886 case 0x10: {// Master Repeat Start
elessair 0:f269e3021894 887 if (obj->tx_buff.buffer && obj->tx_buff.pos < obj->tx_buff.length) {
elessair 0:f269e3021894 888 I2C_SET_DATA(i2c_base, (i2c_addr2data(obj->i2c.address, 0)));
elessair 0:f269e3021894 889 I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_SI_Msk);
elessair 0:f269e3021894 890 }
elessair 0:f269e3021894 891 else if (obj->rx_buff.buffer && obj->rx_buff.pos < obj->rx_buff.length) {
elessair 0:f269e3021894 892 I2C_SET_DATA(i2c_base, (i2c_addr2data(obj->i2c.address, 1)));
elessair 0:f269e3021894 893 I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_SI_Msk);
elessair 0:f269e3021894 894 }
elessair 0:f269e3021894 895 else {
elessair 0:f269e3021894 896 event = I2C_EVENT_TRANSFER_COMPLETE;
elessair 0:f269e3021894 897 if (obj->i2c.stop) {
elessair 0:f269e3021894 898 I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_STO_Msk | I2C_CTL_SI_Msk);
elessair 0:f269e3021894 899 }
elessair 0:f269e3021894 900 }
elessair 0:f269e3021894 901 break;
elessair 0:f269e3021894 902 }
elessair 0:f269e3021894 903
elessair 0:f269e3021894 904 case 0x18: // Master Transmit Address ACK
elessair 0:f269e3021894 905 case 0x28: // Master Transmit Data ACK
elessair 0:f269e3021894 906 if (obj->tx_buff.buffer && obj->tx_buff.pos < obj->tx_buff.length) {
elessair 0:f269e3021894 907 uint8_t *tx = (uint8_t *)obj->tx_buff.buffer;
elessair 0:f269e3021894 908 I2C_SET_DATA(i2c_base, tx[obj->tx_buff.pos ++]);
elessair 0:f269e3021894 909 I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_SI_Msk);
elessair 0:f269e3021894 910 }
elessair 0:f269e3021894 911 else if (obj->rx_buff.buffer && obj->rx_buff.pos < obj->rx_buff.length) {
elessair 0:f269e3021894 912 I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_STA_Msk | I2C_CTL_SI_Msk);
elessair 0:f269e3021894 913 }
elessair 0:f269e3021894 914 else {
elessair 0:f269e3021894 915 event = I2C_EVENT_TRANSFER_COMPLETE;
elessair 0:f269e3021894 916 if (obj->i2c.stop) {
elessair 0:f269e3021894 917 I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_STO_Msk | I2C_CTL_SI_Msk);
elessair 0:f269e3021894 918 }
elessair 0:f269e3021894 919 }
elessair 0:f269e3021894 920 break;
elessair 0:f269e3021894 921
elessair 0:f269e3021894 922 case 0x20: // Master Transmit Address NACK
elessair 0:f269e3021894 923 event = I2C_EVENT_ERROR_NO_SLAVE;
elessair 0:f269e3021894 924 if (obj->i2c.stop) {
elessair 0:f269e3021894 925 I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_STO_Msk | I2C_CTL_SI_Msk);
elessair 0:f269e3021894 926 }
elessair 0:f269e3021894 927 break;
elessair 0:f269e3021894 928
elessair 0:f269e3021894 929 case 0x30: // Master Transmit Data NACK
elessair 0:f269e3021894 930 if (obj->tx_buff.buffer && obj->tx_buff.pos < obj->tx_buff.length) {
elessair 0:f269e3021894 931 event = I2C_EVENT_TRANSFER_EARLY_NACK;
elessair 0:f269e3021894 932 I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_STO_Msk | I2C_CTL_SI_Msk);
elessair 0:f269e3021894 933 }
elessair 0:f269e3021894 934 else if (obj->rx_buff.buffer && obj->rx_buff.pos < obj->rx_buff.length) {
elessair 0:f269e3021894 935 I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_STA_Msk | I2C_CTL_SI_Msk);
elessair 0:f269e3021894 936 }
elessair 0:f269e3021894 937 else {
elessair 0:f269e3021894 938 event = I2C_EVENT_TRANSFER_COMPLETE;
elessair 0:f269e3021894 939 if (obj->i2c.stop) {
elessair 0:f269e3021894 940 I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_STO_Msk | I2C_CTL_SI_Msk);
elessair 0:f269e3021894 941 }
elessair 0:f269e3021894 942 }
elessair 0:f269e3021894 943 break;
elessair 0:f269e3021894 944
elessair 0:f269e3021894 945 case 0x38: // Master Arbitration Lost
elessair 0:f269e3021894 946 I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_SI_Msk); // Enter not addressed SLV mode
elessair 0:f269e3021894 947 event = I2C_EVENT_ERROR;
elessair 0:f269e3021894 948 break;
elessair 0:f269e3021894 949
elessair 0:f269e3021894 950 case 0x50: // Master Receive Data ACK
elessair 0:f269e3021894 951 if (obj->rx_buff.buffer && obj->rx_buff.pos < obj->rx_buff.length) {
elessair 0:f269e3021894 952 uint8_t *rx = (uint8_t *) obj->rx_buff.buffer;
elessair 0:f269e3021894 953 rx[obj->rx_buff.pos ++] = I2C_GET_DATA(((I2C_T *) NU_MODBASE(obj->i2c.i2c)));
elessair 0:f269e3021894 954 }
elessair 0:f269e3021894 955 case 0x40: // Master Receive Address ACK
elessair 0:f269e3021894 956 I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_SI_Msk | ((obj->rx_buff.pos != obj->rx_buff.length - 1) ? I2C_CTL_AA_Msk : 0));
elessair 0:f269e3021894 957 break;
elessair 0:f269e3021894 958
elessair 0:f269e3021894 959 case 0x48: // Master Receive Address NACK
elessair 0:f269e3021894 960 event = I2C_EVENT_ERROR_NO_SLAVE;
elessair 0:f269e3021894 961 if (obj->i2c.stop) {
elessair 0:f269e3021894 962 I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_STO_Msk | I2C_CTL_SI_Msk);
elessair 0:f269e3021894 963 }
elessair 0:f269e3021894 964 break;
elessair 0:f269e3021894 965
elessair 0:f269e3021894 966 case 0x58: // Master Receive Data NACK
elessair 0:f269e3021894 967 if (obj->rx_buff.buffer && obj->rx_buff.pos < obj->rx_buff.length) {
elessair 0:f269e3021894 968 uint8_t *rx = (uint8_t *) obj->rx_buff.buffer;
elessair 0:f269e3021894 969 rx[obj->rx_buff.pos ++] = I2C_GET_DATA(((I2C_T *) NU_MODBASE(obj->i2c.i2c)));
elessair 0:f269e3021894 970 }
elessair 0:f269e3021894 971 I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_STA_Msk | I2C_CTL_SI_Msk);
elessair 0:f269e3021894 972 break;
elessair 0:f269e3021894 973
elessair 0:f269e3021894 974 case 0x00: // Bus error
elessair 0:f269e3021894 975 event = I2C_EVENT_ERROR;
elessair 0:f269e3021894 976 i2c_reset(obj);
elessair 0:f269e3021894 977 break;
elessair 0:f269e3021894 978
elessair 0:f269e3021894 979 default:
elessair 0:f269e3021894 980 event = I2C_EVENT_ERROR;
elessair 0:f269e3021894 981 if (obj->i2c.stop) {
elessair 0:f269e3021894 982 I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_STO_Msk | I2C_CTL_SI_Msk);
elessair 0:f269e3021894 983 }
elessair 0:f269e3021894 984 }
elessair 0:f269e3021894 985
elessair 0:f269e3021894 986 if (event) {
elessair 0:f269e3021894 987 i2c_rollback_vector_interrupt(obj);
elessair 0:f269e3021894 988 }
elessair 0:f269e3021894 989
elessair 0:f269e3021894 990 return (event & obj->i2c.event);
elessair 0:f269e3021894 991 }
elessair 0:f269e3021894 992
elessair 0:f269e3021894 993 uint8_t i2c_active(i2c_t *obj)
elessair 0:f269e3021894 994 {
elessair 0:f269e3021894 995 const struct nu_modinit_s *modinit = get_modinit(obj->i2c.i2c, i2c_modinit_tab);
elessair 0:f269e3021894 996 MBED_ASSERT(modinit != NULL);
elessair 0:f269e3021894 997 MBED_ASSERT(modinit->modname == obj->i2c.i2c);
elessair 0:f269e3021894 998
elessair 0:f269e3021894 999 // Vector will be changed for async transfer. Use it to judge if async transfer is on-going.
elessair 0:f269e3021894 1000 uint32_t vec = NVIC_GetVector(modinit->irq_n);
elessair 0:f269e3021894 1001 struct nu_i2c_var *var = (struct nu_i2c_var *) modinit->var;
elessair 0:f269e3021894 1002 return (vec && vec != (uint32_t) var->vec);
elessair 0:f269e3021894 1003 }
elessair 0:f269e3021894 1004
elessair 0:f269e3021894 1005 void i2c_abort_asynch(i2c_t *obj)
elessair 0:f269e3021894 1006 {
elessair 0:f269e3021894 1007 i2c_rollback_vector_interrupt(obj);
elessair 0:f269e3021894 1008 i2c_stop(obj);
elessair 0:f269e3021894 1009 }
elessair 0:f269e3021894 1010
elessair 0:f269e3021894 1011 static void i2c_buffer_set(i2c_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length)
elessair 0:f269e3021894 1012 {
elessair 0:f269e3021894 1013 obj->tx_buff.buffer = (void *) tx;
elessair 0:f269e3021894 1014 obj->tx_buff.length = tx_length;
elessair 0:f269e3021894 1015 obj->tx_buff.pos = 0;
elessair 0:f269e3021894 1016 obj->rx_buff.buffer = rx;
elessair 0:f269e3021894 1017 obj->rx_buff.length = rx_length;
elessair 0:f269e3021894 1018 obj->rx_buff.pos = 0;
elessair 0:f269e3021894 1019 }
elessair 0:f269e3021894 1020
elessair 0:f269e3021894 1021 static void i2c_enable_vector_interrupt(i2c_t *obj, uint32_t handler, int enable)
elessair 0:f269e3021894 1022 {
elessair 0:f269e3021894 1023 const struct nu_modinit_s *modinit = get_modinit(obj->i2c.i2c, i2c_modinit_tab);
elessair 0:f269e3021894 1024 MBED_ASSERT(modinit != NULL);
elessair 0:f269e3021894 1025 MBED_ASSERT(modinit->modname == obj->i2c.i2c);
elessair 0:f269e3021894 1026
elessair 0:f269e3021894 1027 if (enable) {
elessair 0:f269e3021894 1028 NVIC_SetVector(modinit->irq_n, handler);
elessair 0:f269e3021894 1029 i2c_enable_int(obj);
elessair 0:f269e3021894 1030 }
elessair 0:f269e3021894 1031 else {
elessair 0:f269e3021894 1032 i2c_disable_int(obj);
elessair 0:f269e3021894 1033 }
elessair 0:f269e3021894 1034 }
elessair 0:f269e3021894 1035
elessair 0:f269e3021894 1036 static void i2c_rollback_vector_interrupt(i2c_t *obj)
elessair 0:f269e3021894 1037 {
elessair 0:f269e3021894 1038 const struct nu_modinit_s *modinit = get_modinit(obj->i2c.i2c, i2c_modinit_tab);
elessair 0:f269e3021894 1039 MBED_ASSERT(modinit != NULL);
elessair 0:f269e3021894 1040 MBED_ASSERT(modinit->modname == obj->i2c.i2c);
elessair 0:f269e3021894 1041
elessair 0:f269e3021894 1042 struct nu_i2c_var *var = (struct nu_i2c_var *) modinit->var;
elessair 0:f269e3021894 1043 i2c_enable_vector_interrupt(obj, (uint32_t) var->vec, 1);
elessair 0:f269e3021894 1044 }
elessair 0:f269e3021894 1045
elessair 0:f269e3021894 1046 #endif
elessair 0:f269e3021894 1047
elessair 0:f269e3021894 1048 #endif