Lee Kai Xuan / mbed-os

mbed-os

Fork of mbed-os by erkin yucel

targets/TARGET_Maxim/TARGET_MAX32600/i2c_api.c@1:3deb71413561, 2017-07-20 (annotated)

Committer:
xuaner
Date:
Thu Jul 20 14:26:57 2017 +0000
Revision:
1:3deb71413561
Parent:
0:f269e3021894 
mbed_os

Who changed what in which revision?

UserRevisionLine numberNew contents of line
elessair 0:f269e3021894 1 /*******************************************************************************
elessair 0:f269e3021894 2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
elessair 0:f269e3021894 3 *
elessair 0:f269e3021894 4 * Permission is hereby granted, free of charge, to any person obtaining a
elessair 0:f269e3021894 5 * copy of this software and associated documentation files (the "Software"),
elessair 0:f269e3021894 6 * to deal in the Software without restriction, including without limitation
elessair 0:f269e3021894 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
elessair 0:f269e3021894 8 * and/or sell copies of the Software, and to permit persons to whom the
elessair 0:f269e3021894 9 * Software is furnished to do so, subject to the following conditions:
elessair 0:f269e3021894 10 *
elessair 0:f269e3021894 11 * The above copyright notice and this permission notice shall be included
elessair 0:f269e3021894 12 * in all copies or substantial portions of the Software.
elessair 0:f269e3021894 13 *
elessair 0:f269e3021894 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
elessair 0:f269e3021894 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
elessair 0:f269e3021894 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
elessair 0:f269e3021894 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
elessair 0:f269e3021894 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
elessair 0:f269e3021894 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
elessair 0:f269e3021894 20 * OTHER DEALINGS IN THE SOFTWARE.
elessair 0:f269e3021894 21 *
elessair 0:f269e3021894 22 * Except as contained in this notice, the name of Maxim Integrated
elessair 0:f269e3021894 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
elessair 0:f269e3021894 24 * Products, Inc. Branding Policy.
elessair 0:f269e3021894 25 *
elessair 0:f269e3021894 26 * The mere transfer of this software does not imply any licenses
elessair 0:f269e3021894 27 * of trade secrets, proprietary technology, copyrights, patents,
elessair 0:f269e3021894 28 * trademarks, maskwork rights, or any other form of intellectual
elessair 0:f269e3021894 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
elessair 0:f269e3021894 30 * ownership rights.
elessair 0:f269e3021894 31 *******************************************************************************
elessair 0:f269e3021894 32 */
elessair 0:f269e3021894 33
elessair 0:f269e3021894 34 #include "mbed_assert.h"
elessair 0:f269e3021894 35 #include "i2c_api.h"
elessair 0:f269e3021894 36 #include "cmsis.h"
elessair 0:f269e3021894 37 #include "i2cm_regs.h"
elessair 0:f269e3021894 38 #include "clkman_regs.h"
elessair 0:f269e3021894 39 #include "ioman_regs.h"
elessair 0:f269e3021894 40 #include "PeripheralPins.h"
elessair 0:f269e3021894 41
elessair 0:f269e3021894 42 #define I2C_SLAVE_ADDR_READ_BIT 0x0001
elessair 0:f269e3021894 43
elessair 0:f269e3021894 44 #ifndef MXC_I2CM_TX_TIMEOUT
elessair 0:f269e3021894 45 #define MXC_I2CM_TX_TIMEOUT 0x5000
elessair 0:f269e3021894 46 #endif
elessair 0:f269e3021894 47
elessair 0:f269e3021894 48 #ifndef MXC_I2CM_RX_TIMEOUT
elessair 0:f269e3021894 49 #define MXC_I2CM_RX_TIMEOUT 0x5000
elessair 0:f269e3021894 50 #endif
elessair 0:f269e3021894 51
elessair 0:f269e3021894 52 typedef enum {
elessair 0:f269e3021894 53 /** 100KHz */
elessair 0:f269e3021894 54 MXC_E_I2CM_SPEED_100KHZ = 0,
elessair 0:f269e3021894 55 /** 400KHz */
elessair 0:f269e3021894 56 MXC_E_I2CM_SPEED_400KHZ,
elessair 0:f269e3021894 57 /** 1MHz */
elessair 0:f269e3021894 58 MXC_E_I2CM_SPEED_1MHZ
elessair 0:f269e3021894 59 } i2cm_speed_t;
elessair 0:f269e3021894 60
elessair 0:f269e3021894 61 /* Clock divider lookup table */
elessair 0:f269e3021894 62 static const uint32_t clk_div_table[3][8] = {
elessair 0:f269e3021894 63 /* MXC_E_I2CM_SPEED_100KHZ */
elessair 0:f269e3021894 64 {
elessair 0:f269e3021894 65 /* 0: */ 0, /* not supported */
elessair 0:f269e3021894 66 /* 1: 6MHz */ (( 3 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | ( 7 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | ( 36 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)),
elessair 0:f269e3021894 67 /* 2: 8MHz */ (( 4 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | (10 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | ( 48 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)),
elessair 0:f269e3021894 68 /* 3: 12MHz */ (( 6 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | (17 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | ( 72 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)),
elessair 0:f269e3021894 69 /* 4: 16MHz */ (( 8 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | (24 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | ( 96 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)),
elessair 0:f269e3021894 70 /* 5: */ 0, /* not supported */
elessair 0:f269e3021894 71 /* 6: */ 0, /* not supported */
elessair 0:f269e3021894 72 /* 7: 24MHz */ ((12 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | (38 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | (144 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)),
elessair 0:f269e3021894 73 },
elessair 0:f269e3021894 74 /* MXC_E_I2CM_SPEED_400KHZ */
elessair 0:f269e3021894 75 {
elessair 0:f269e3021894 76 /* 0: */ 0, /* not supported */
elessair 0:f269e3021894 77 /* 1: */ 0, /* not supported */
elessair 0:f269e3021894 78 /* 2: */ 0, /* not supported */
elessair 0:f269e3021894 79 /* 3: 12MHz */ ((2 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | (1 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | (18 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)),
elessair 0:f269e3021894 80 /* 4: 16MHz */ ((2 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | (2 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | (24 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)),
elessair 0:f269e3021894 81 /* 5: */ 0, /* not supported */
elessair 0:f269e3021894 82 /* 6: */ 0, /* not supported */
elessair 0:f269e3021894 83 /* 7: 24MHz */ ((3 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | (5 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | (36 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)),
elessair 0:f269e3021894 84 },
elessair 0:f269e3021894 85 /* MXC_E_I2CM_SPEED_1MHZ */
elessair 0:f269e3021894 86 {
elessair 0:f269e3021894 87 /* 0: */ 0, /* not supported */
elessair 0:f269e3021894 88 /* 1: */ 0, /* not supported */
elessair 0:f269e3021894 89 /* 2: */ 0, /* not supported */
elessair 0:f269e3021894 90 /* 3: */ 0, /* not supported */
elessair 0:f269e3021894 91 /* 4: */ 0, /* not supported */
elessair 0:f269e3021894 92 /* 5: */ 0, /* not supported */
elessair 0:f269e3021894 93 /* 6: */ 0, /* not supported */
elessair 0:f269e3021894 94 /* 7: 24MHz */ ((1 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | (0 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | (14 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)),
elessair 0:f269e3021894 95 },
elessair 0:f269e3021894 96 };
elessair 0:f269e3021894 97
elessair 0:f269e3021894 98 void i2c_init(i2c_t *obj, PinName sda, PinName scl)
elessair 0:f269e3021894 99 {
elessair 0:f269e3021894 100 // determine the I2C to use
elessair 0:f269e3021894 101 I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
elessair 0:f269e3021894 102 I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
elessair 0:f269e3021894 103 mxc_i2cm_regs_t *i2c = (mxc_i2cm_regs_t*)pinmap_merge(i2c_sda, i2c_scl);
elessair 0:f269e3021894 104 MBED_ASSERT((int)i2c != NC);
elessair 0:f269e3021894 105
elessair 0:f269e3021894 106 obj->i2c = i2c;
elessair 0:f269e3021894 107 obj->txfifo = (uint16_t*)MXC_I2CM_GET_BASE_TX_FIFO(MXC_I2CM_BASE_TO_INSTANCE(i2c));
elessair 0:f269e3021894 108 obj->rxfifo = (uint16_t*)MXC_I2CM_GET_BASE_RX_FIFO(MXC_I2CM_BASE_TO_INSTANCE(i2c));
elessair 0:f269e3021894 109 obj->start_pending = 0;
elessair 0:f269e3021894 110 obj->stop_pending = 0;
elessair 0:f269e3021894 111
elessair 0:f269e3021894 112 // configure the pins
elessair 0:f269e3021894 113 pinmap_pinout(sda, PinMap_I2C_SDA);
elessair 0:f269e3021894 114 pinmap_pinout(scl, PinMap_I2C_SCL);
elessair 0:f269e3021894 115
elessair 0:f269e3021894 116 // enable the clock
elessair 0:f269e3021894 117 MXC_CLKMAN->clk_ctrl_6_i2cm = MXC_E_CLKMAN_CLK_SCALE_ENABLED;
elessair 0:f269e3021894 118
elessair 0:f269e3021894 119 // reset module
elessair 0:f269e3021894 120 i2c->ctrl = MXC_F_I2CM_CTRL_MSTR_RESET_EN;
elessair 0:f269e3021894 121 i2c->ctrl = 0;
elessair 0:f269e3021894 122
elessair 0:f269e3021894 123 // set default frequency at 100k
elessair 0:f269e3021894 124 i2c_frequency(obj, 100000);
elessair 0:f269e3021894 125
elessair 0:f269e3021894 126 // set timeout to 255 ms and turn on the auto-stop option
elessair 0:f269e3021894 127 i2c->timeout = (0xFF << MXC_F_I2CM_TIMEOUT_TX_TIMEOUT_POS) | MXC_F_I2CM_TIMEOUT_AUTO_STOP_EN;
elessair 0:f269e3021894 128
elessair 0:f269e3021894 129 // enable tx_fifo and rx_fifo
elessair 0:f269e3021894 130 i2c->ctrl |= (MXC_F_I2CM_CTRL_TX_FIFO_EN | MXC_F_I2CM_CTRL_RX_FIFO_EN);
elessair 0:f269e3021894 131 }
elessair 0:f269e3021894 132
elessair 0:f269e3021894 133 void i2c_frequency(i2c_t *obj, int hz)
elessair 0:f269e3021894 134 {
elessair 0:f269e3021894 135 // compute clock array index
elessair 0:f269e3021894 136 int clki = ((SystemCoreClock + 1500000) / 3000000) - 1;
elessair 0:f269e3021894 137
elessair 0:f269e3021894 138 // get clock divider settings from lookup table
elessair 0:f269e3021894 139 if ((hz < 400000) && (clk_div_table[MXC_E_I2CM_SPEED_100KHZ][clki] > 0)) {
elessair 0:f269e3021894 140 obj->i2c->fs_clk_div = clk_div_table[MXC_E_I2CM_SPEED_100KHZ][clki];
elessair 0:f269e3021894 141 } else if ((hz < 1000000) && (clk_div_table[MXC_E_I2CM_SPEED_400KHZ][clki] > 0)) {
elessair 0:f269e3021894 142 obj->i2c->fs_clk_div = clk_div_table[MXC_E_I2CM_SPEED_400KHZ][clki];
elessair 0:f269e3021894 143 } else if ((hz >= 1000000) && (clk_div_table[MXC_E_I2CM_SPEED_1MHZ][clki] > 0)) {
elessair 0:f269e3021894 144 obj->i2c->hs_clk_div = clk_div_table[MXC_E_I2CM_SPEED_1MHZ][clki];
elessair 0:f269e3021894 145 }
elessair 0:f269e3021894 146 }
elessair 0:f269e3021894 147
elessair 0:f269e3021894 148 static int write_tx_fifo(i2c_t *obj, const uint16_t data)
elessair 0:f269e3021894 149 {
elessair 0:f269e3021894 150 int timeout = MXC_I2CM_TX_TIMEOUT;
elessair 0:f269e3021894 151
elessair 0:f269e3021894 152 while (*obj->txfifo) {
elessair 0:f269e3021894 153 uint32_t intfl = obj->i2c->intfl;
elessair 0:f269e3021894 154 if (intfl & MXC_F_I2CM_INTFL_TX_NACKED) {
elessair 0:f269e3021894 155 return I2C_ERROR_NO_SLAVE;
elessair 0:f269e3021894 156 }
elessair 0:f269e3021894 157 if (!timeout || (intfl & (MXC_F_I2CM_INTFL_TX_TIMEOUT | MXC_F_I2CM_INTFL_TX_LOST_ARBITR))) {
elessair 0:f269e3021894 158 return I2C_ERROR_BUS_BUSY;
elessair 0:f269e3021894 159 }
elessair 0:f269e3021894 160 timeout--;
elessair 0:f269e3021894 161 }
elessair 0:f269e3021894 162 *obj->txfifo = data;
elessair 0:f269e3021894 163
elessair 0:f269e3021894 164 return 0;
elessair 0:f269e3021894 165 }
elessair 0:f269e3021894 166
elessair 0:f269e3021894 167 static int wait_tx_in_progress(i2c_t *obj)
elessair 0:f269e3021894 168 {
elessair 0:f269e3021894 169 int timeout = MXC_I2CM_TX_TIMEOUT;
elessair 0:f269e3021894 170
elessair 0:f269e3021894 171 while ((obj->i2c->trans & MXC_F_I2CM_TRANS_TX_IN_PROGRESS) && --timeout);
elessair 0:f269e3021894 172
elessair 0:f269e3021894 173 uint32_t intfl = obj->i2c->intfl;
elessair 0:f269e3021894 174
elessair 0:f269e3021894 175 if (intfl & MXC_F_I2CM_INTFL_TX_NACKED) {
elessair 0:f269e3021894 176 i2c_reset(obj);
elessair 0:f269e3021894 177 return I2C_ERROR_NO_SLAVE;
elessair 0:f269e3021894 178 }
elessair 0:f269e3021894 179
elessair 0:f269e3021894 180 if (!timeout || (intfl & (MXC_F_I2CM_INTFL_TX_TIMEOUT | MXC_F_I2CM_INTFL_TX_LOST_ARBITR))) {
elessair 0:f269e3021894 181 i2c_reset(obj);
elessair 0:f269e3021894 182 return I2C_ERROR_BUS_BUSY;
elessair 0:f269e3021894 183 }
elessair 0:f269e3021894 184
elessair 0:f269e3021894 185 return 0;
elessair 0:f269e3021894 186 }
elessair 0:f269e3021894 187
elessair 0:f269e3021894 188 int i2c_start(i2c_t *obj)
elessair 0:f269e3021894 189 {
elessair 0:f269e3021894 190 obj->start_pending = 1;
elessair 0:f269e3021894 191 return 0;
elessair 0:f269e3021894 192 }
elessair 0:f269e3021894 193
elessair 0:f269e3021894 194 int i2c_stop(i2c_t *obj)
elessair 0:f269e3021894 195 {
elessair 0:f269e3021894 196 obj->start_pending = 0;
elessair 0:f269e3021894 197 write_tx_fifo(obj, MXC_S_I2CM_TRANS_TAG_STOP);
elessair 0:f269e3021894 198
elessair 0:f269e3021894 199 return wait_tx_in_progress(obj);
elessair 0:f269e3021894 200 }
elessair 0:f269e3021894 201
elessair 0:f269e3021894 202 void i2c_reset(i2c_t *obj)
elessair 0:f269e3021894 203 {
elessair 0:f269e3021894 204 obj->i2c->ctrl = MXC_F_I2CM_CTRL_MSTR_RESET_EN;
elessair 0:f269e3021894 205 obj->i2c->intfl = 0x3FF; // clear all interrupts
elessair 0:f269e3021894 206 obj->i2c->ctrl = MXC_F_I2CM_CTRL_TX_FIFO_EN | MXC_F_I2CM_CTRL_RX_FIFO_EN;
elessair 0:f269e3021894 207 obj->start_pending = 0;
elessair 0:f269e3021894 208 }
elessair 0:f269e3021894 209
elessair 0:f269e3021894 210 int i2c_byte_write(i2c_t *obj, int data)
elessair 0:f269e3021894 211 {
elessair 0:f269e3021894 212 int err;
elessair 0:f269e3021894 213
elessair 0:f269e3021894 214 // clear all interrupts
elessair 0:f269e3021894 215 obj->i2c->intfl = 0x3FF;
elessair 0:f269e3021894 216
elessair 0:f269e3021894 217 if (obj->start_pending) {
elessair 0:f269e3021894 218 obj->start_pending = 0;
elessair 0:f269e3021894 219 data = (data & 0xFF) | MXC_S_I2CM_TRANS_TAG_START;
elessair 0:f269e3021894 220 } else {
elessair 0:f269e3021894 221 data = (data & 0xFF) | MXC_S_I2CM_TRANS_TAG_TXDATA_ACK;
elessair 0:f269e3021894 222 }
elessair 0:f269e3021894 223
elessair 0:f269e3021894 224 if ((err = write_tx_fifo(obj, data)) != 0) {
elessair 0:f269e3021894 225 return err;
elessair 0:f269e3021894 226 }
elessair 0:f269e3021894 227
elessair 0:f269e3021894 228 obj->i2c->trans |= MXC_F_I2CM_TRANS_TX_START;
elessair 0:f269e3021894 229
elessair 0:f269e3021894 230 // Wait for the FIFO to be empty
elessair 0:f269e3021894 231 while (!(obj->i2c->intfl & MXC_F_I2CM_INTFL_TX_FIFO_EMPTY));
elessair 0:f269e3021894 232
elessair 0:f269e3021894 233 if (obj->i2c->intfl & MXC_F_I2CM_INTFL_TX_NACKED) {
elessair 0:f269e3021894 234 i2c_reset(obj);
elessair 0:f269e3021894 235 return 0;
elessair 0:f269e3021894 236 }
elessair 0:f269e3021894 237
elessair 0:f269e3021894 238 if (obj->i2c->intfl & (MXC_F_I2CM_INTFL_TX_TIMEOUT | MXC_F_I2CM_INTFL_TX_LOST_ARBITR)) {
elessair 0:f269e3021894 239 i2c_reset(obj);
elessair 0:f269e3021894 240 return 2;
elessair 0:f269e3021894 241 }
elessair 0:f269e3021894 242
elessair 0:f269e3021894 243 return 1;
elessair 0:f269e3021894 244 }
elessair 0:f269e3021894 245
elessair 0:f269e3021894 246 int i2c_byte_read(i2c_t *obj, int last)
elessair 0:f269e3021894 247 {
elessair 0:f269e3021894 248 uint16_t fifo_value;
elessair 0:f269e3021894 249 int err;
elessair 0:f269e3021894 250
elessair 0:f269e3021894 251 // clear all interrupts
elessair 0:f269e3021894 252 obj->i2c->intfl = 0x3FF;
elessair 0:f269e3021894 253
elessair 0:f269e3021894 254 if (last) {
elessair 0:f269e3021894 255 fifo_value = MXC_S_I2CM_TRANS_TAG_RXDATA_NACK;
elessair 0:f269e3021894 256 } else {
elessair 0:f269e3021894 257 fifo_value = MXC_S_I2CM_TRANS_TAG_RXDATA_COUNT;
elessair 0:f269e3021894 258 }
elessair 0:f269e3021894 259
elessair 0:f269e3021894 260 if ((err = write_tx_fifo(obj, fifo_value)) != 0) {
elessair 0:f269e3021894 261 i2c_reset(obj);
elessair 0:f269e3021894 262 return err;
elessair 0:f269e3021894 263 }
elessair 0:f269e3021894 264
elessair 0:f269e3021894 265 obj->i2c->trans |= MXC_F_I2CM_TRANS_TX_START;
elessair 0:f269e3021894 266
elessair 0:f269e3021894 267 int timeout = MXC_I2CM_RX_TIMEOUT;
elessair 0:f269e3021894 268 while (!(obj->i2c->intfl & MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY) &&
elessair 0:f269e3021894 269 (!(obj->i2c->bb & MXC_F_I2CM_BB_RX_FIFO_CNT))) {
elessair 0:f269e3021894 270 if ((--timeout < 0) || (obj->i2c->trans & (MXC_F_I2CM_TRANS_TX_TIMEOUT |
elessair 0:f269e3021894 271 MXC_F_I2CM_TRANS_TX_LOST_ARBITR | MXC_F_I2CM_TRANS_TX_NACKED))) {
elessair 0:f269e3021894 272 break;
elessair 0:f269e3021894 273 }
elessair 0:f269e3021894 274 }
elessair 0:f269e3021894 275
elessair 0:f269e3021894 276 if (obj->i2c->intfl & MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY) {
elessair 0:f269e3021894 277 obj->i2c->intfl = MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY;
elessair 0:f269e3021894 278 return *obj->rxfifo;
elessair 0:f269e3021894 279 }
elessair 0:f269e3021894 280
elessair 0:f269e3021894 281 i2c_reset(obj);
elessair 0:f269e3021894 282
elessair 0:f269e3021894 283 return -1;
elessair 0:f269e3021894 284 }
elessair 0:f269e3021894 285
elessair 0:f269e3021894 286 int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
elessair 0:f269e3021894 287 {
elessair 0:f269e3021894 288 int err, retval = 0;
elessair 0:f269e3021894 289 int i;
elessair 0:f269e3021894 290
elessair 0:f269e3021894 291 if (!(obj->stop_pending) && (obj->i2c->trans & MXC_F_I2CM_TRANS_TX_IN_PROGRESS)) {
elessair 0:f269e3021894 292 return 0;
elessair 0:f269e3021894 293 }
elessair 0:f269e3021894 294
elessair 0:f269e3021894 295 // clear all interrupts
elessair 0:f269e3021894 296 obj->i2c->intfl = 0x3FF;
elessair 0:f269e3021894 297
elessair 0:f269e3021894 298 // write the address to the fifo
elessair 0:f269e3021894 299 if ((err = write_tx_fifo(obj, (MXC_S_I2CM_TRANS_TAG_START | address))) != 0) { // start + addr (write)
elessair 0:f269e3021894 300 i2c_reset(obj);
elessair 0:f269e3021894 301 return err;
elessair 0:f269e3021894 302 }
elessair 0:f269e3021894 303 obj->start_pending = 0;
elessair 0:f269e3021894 304
elessair 0:f269e3021894 305 // start the transaction
elessair 0:f269e3021894 306 obj->i2c->trans |= MXC_F_I2CM_TRANS_TX_START;
elessair 0:f269e3021894 307
elessair 0:f269e3021894 308 // load as much of the cmd into the FIFO as possible
elessair 0:f269e3021894 309 for (i = 0; i < length; i++) {
elessair 0:f269e3021894 310 if ((err = write_tx_fifo(obj, (MXC_S_I2CM_TRANS_TAG_TXDATA_ACK | data[i]))) != 0) { // cmd (expect ACK)
elessair 0:f269e3021894 311 retval = (retval ? retval : err);
elessair 0:f269e3021894 312 break;
elessair 0:f269e3021894 313 }
elessair 0:f269e3021894 314 }
elessair 0:f269e3021894 315
elessair 0:f269e3021894 316 if (stop) {
elessair 0:f269e3021894 317 obj->stop_pending = 0;
elessair 0:f269e3021894 318 if ((err = write_tx_fifo(obj, MXC_S_I2CM_TRANS_TAG_STOP)) != 0) { // stop condition
elessair 0:f269e3021894 319 retval = (retval ? retval : err);
elessair 0:f269e3021894 320 }
elessair 0:f269e3021894 321
elessair 0:f269e3021894 322 if ((err = wait_tx_in_progress(obj)) != 0) {
elessair 0:f269e3021894 323 retval = (retval ? retval : err);
elessair 0:f269e3021894 324 }
elessair 0:f269e3021894 325 } else {
elessair 0:f269e3021894 326 obj->stop_pending = 1;
elessair 0:f269e3021894 327 int timeout = MXC_I2CM_TX_TIMEOUT;
elessair 0:f269e3021894 328 // Wait for TX fifo to be empty
elessair 0:f269e3021894 329 while (!(obj->i2c->intfl & MXC_F_I2CM_INTFL_TX_FIFO_EMPTY) && timeout--);
elessair 0:f269e3021894 330 }
elessair 0:f269e3021894 331
elessair 0:f269e3021894 332 if (retval == 0) {
elessair 0:f269e3021894 333 return length;
elessair 0:f269e3021894 334 }
elessair 0:f269e3021894 335
elessair 0:f269e3021894 336 i2c_reset(obj);
elessair 0:f269e3021894 337
elessair 0:f269e3021894 338 return retval;
elessair 0:f269e3021894 339 }
elessair 0:f269e3021894 340
elessair 0:f269e3021894 341 int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
elessair 0:f269e3021894 342 {
elessair 0:f269e3021894 343 int err, retval = 0;
elessair 0:f269e3021894 344 int i = length;
elessair 0:f269e3021894 345 int timeout;
elessair 0:f269e3021894 346
elessair 0:f269e3021894 347 if (!(obj->stop_pending) && (obj->i2c->trans & MXC_F_I2CM_TRANS_TX_IN_PROGRESS)) {
elessair 0:f269e3021894 348 return 0;
elessair 0:f269e3021894 349 }
elessair 0:f269e3021894 350
elessair 0:f269e3021894 351 // clear all interrupts
elessair 0:f269e3021894 352 obj->i2c->intfl = 0x3FF;
elessair 0:f269e3021894 353
elessair 0:f269e3021894 354 // start + addr (read)
elessair 0:f269e3021894 355 if ((retval = write_tx_fifo(obj, (MXC_S_I2CM_TRANS_TAG_START | address | I2C_SLAVE_ADDR_READ_BIT))) != 0) {
elessair 0:f269e3021894 356 goto read_done;
elessair 0:f269e3021894 357 }
elessair 0:f269e3021894 358 obj->start_pending = 0;
elessair 0:f269e3021894 359
elessair 0:f269e3021894 360 while (i > 256) {
elessair 0:f269e3021894 361 if ((retval = write_tx_fifo(obj, (MXC_S_I2CM_TRANS_TAG_RXDATA_COUNT | 255))) != 0) {
elessair 0:f269e3021894 362 goto read_done;
elessair 0:f269e3021894 363 }
elessair 0:f269e3021894 364 i -= 256;
elessair 0:f269e3021894 365 }
elessair 0:f269e3021894 366
elessair 0:f269e3021894 367 if (i > 1) {
elessair 0:f269e3021894 368 if ((retval = write_tx_fifo(obj, (MXC_S_I2CM_TRANS_TAG_RXDATA_COUNT | (i - 2)))) != 0) {
elessair 0:f269e3021894 369 goto read_done;
elessair 0:f269e3021894 370 }
elessair 0:f269e3021894 371 }
elessair 0:f269e3021894 372
elessair 0:f269e3021894 373 // start the transaction
elessair 0:f269e3021894 374 obj->i2c->trans |= MXC_F_I2CM_TRANS_TX_START;
elessair 0:f269e3021894 375
elessair 0:f269e3021894 376 if ((retval = write_tx_fifo(obj, MXC_S_I2CM_TRANS_TAG_RXDATA_NACK)) != 0) { // NACK last data byte
elessair 0:f269e3021894 377 goto read_done;
elessair 0:f269e3021894 378 }
elessair 0:f269e3021894 379
elessair 0:f269e3021894 380 if (stop) {
elessair 0:f269e3021894 381 if ((retval = write_tx_fifo(obj, MXC_S_I2CM_TRANS_TAG_STOP)) != 0) { // stop condition
elessair 0:f269e3021894 382 goto read_done;
elessair 0:f269e3021894 383 }
elessair 0:f269e3021894 384 }
elessair 0:f269e3021894 385
elessair 0:f269e3021894 386 timeout = MXC_I2CM_RX_TIMEOUT;
elessair 0:f269e3021894 387 i = 0;
elessair 0:f269e3021894 388 while (i < length) {
elessair 0:f269e3021894 389 while (!(obj->i2c->intfl & MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY) &&
elessair 0:f269e3021894 390 (!(obj->i2c->bb & MXC_F_I2CM_BB_RX_FIFO_CNT))) {
elessair 0:f269e3021894 391 if ((--timeout < 0) || (obj->i2c->trans & (MXC_F_I2CM_TRANS_TX_TIMEOUT |
elessair 0:f269e3021894 392 MXC_F_I2CM_TRANS_TX_LOST_ARBITR | MXC_F_I2CM_TRANS_TX_NACKED))) {
elessair 0:f269e3021894 393 retval = -3;
elessair 0:f269e3021894 394 goto read_done;
elessair 0:f269e3021894 395 }
elessair 0:f269e3021894 396 }
elessair 0:f269e3021894 397
elessair 0:f269e3021894 398 timeout = MXC_I2CM_RX_TIMEOUT;
elessair 0:f269e3021894 399
elessair 0:f269e3021894 400 obj->i2c->intfl = MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY;
elessair 0:f269e3021894 401
elessair 0:f269e3021894 402 uint16_t temp = *obj->rxfifo;
elessair 0:f269e3021894 403
elessair 0:f269e3021894 404 if (temp & MXC_S_I2CM_RSTLS_TAG_EMPTY) {
elessair 0:f269e3021894 405 continue;
elessair 0:f269e3021894 406 }
elessair 0:f269e3021894 407 data[i++] = (uint8_t) temp;
elessair 0:f269e3021894 408 }
elessair 0:f269e3021894 409
elessair 0:f269e3021894 410 read_done:
elessair 0:f269e3021894 411
elessair 0:f269e3021894 412 if (stop) {
elessair 0:f269e3021894 413 obj->stop_pending = 0;
elessair 0:f269e3021894 414 if ((err = wait_tx_in_progress(obj)) != 0) {
elessair 0:f269e3021894 415 retval = (retval ? retval : err);
elessair 0:f269e3021894 416 }
elessair 0:f269e3021894 417 } else {
elessair 0:f269e3021894 418 obj->stop_pending = 1;
elessair 0:f269e3021894 419 }
elessair 0:f269e3021894 420
elessair 0:f269e3021894 421 if (retval == 0) {
elessair 0:f269e3021894 422 return length;
elessair 0:f269e3021894 423 }
elessair 0:f269e3021894 424
elessair 0:f269e3021894 425 i2c_reset(obj);
elessair 0:f269e3021894 426
elessair 0:f269e3021894 427 return retval;
elessair 0:f269e3021894 428 }