Lee Kai Xuan / mbed-os

mbed-os

Fork of mbed-os by erkin yucel

targets/TARGET_Freescale/TARGET_KLXX/clk_freqs.h@1:3deb71413561, 2017-07-20 (annotated)

Committer:
xuaner
Date:
Thu Jul 20 14:26:57 2017 +0000
Revision:
1:3deb71413561
Parent:
0:f269e3021894 
mbed_os

Who changed what in which revision?

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elessair 0:f269e3021894 1 /* mbed Microcontroller Library
elessair 0:f269e3021894 2 * Copyright (c) 2006-2013 ARM Limited
elessair 0:f269e3021894 3 *
elessair 0:f269e3021894 4 * Licensed under the Apache License, Version 2.0 (the "License");
elessair 0:f269e3021894 5 * you may not use this file except in compliance with the License.
elessair 0:f269e3021894 6 * You may obtain a copy of the License at
elessair 0:f269e3021894 7 *
elessair 0:f269e3021894 8 * http://www.apache.org/licenses/LICENSE-2.0
elessair 0:f269e3021894 9 *
elessair 0:f269e3021894 10 * Unless required by applicable law or agreed to in writing, software
elessair 0:f269e3021894 11 * distributed under the License is distributed on an "AS IS" BASIS,
elessair 0:f269e3021894 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
elessair 0:f269e3021894 13 * See the License for the specific language governing permissions and
elessair 0:f269e3021894 14 * limitations under the License.
elessair 0:f269e3021894 15 */
elessair 0:f269e3021894 16 #ifndef MBED_CLK_FREQS_H
elessair 0:f269e3021894 17 #define MBED_CLK_FREQS_H
elessair 0:f269e3021894 18
elessair 0:f269e3021894 19 #ifdef __cplusplus
elessair 0:f269e3021894 20 extern "C" {
elessair 0:f269e3021894 21 #endif
elessair 0:f269e3021894 22
elessair 0:f269e3021894 23 #include "PeripheralPins.h"
elessair 0:f269e3021894 24
elessair 0:f269e3021894 25 //Get the peripheral bus clock frequency
elessair 0:f269e3021894 26 static inline uint32_t bus_frequency(void) {
elessair 0:f269e3021894 27 return (SystemCoreClock / (((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV4_MASK) >> SIM_CLKDIV1_OUTDIV4_SHIFT) + 1));
elessair 0:f269e3021894 28 }
elessair 0:f269e3021894 29
elessair 0:f269e3021894 30 #if defined(TARGET_KL43Z)
elessair 0:f269e3021894 31
elessair 0:f269e3021894 32 static inline uint32_t extosc_frequency(void) {
elessair 0:f269e3021894 33 return CPU_XTAL_CLK_HZ;
elessair 0:f269e3021894 34 }
elessair 0:f269e3021894 35
elessair 0:f269e3021894 36 static inline uint32_t fastirc_frequency(void) {
elessair 0:f269e3021894 37 return CPU_INT_FAST_CLK_HZ;
elessair 0:f269e3021894 38 }
elessair 0:f269e3021894 39
elessair 0:f269e3021894 40 static inline uint32_t mcgirc_frequency(void) {
elessair 0:f269e3021894 41 uint32_t mcgirc_clock = 0;
elessair 0:f269e3021894 42
elessair 0:f269e3021894 43 if (MCG->C1 & MCG_C1_IREFSTEN_MASK) {
elessair 0:f269e3021894 44 mcgirc_clock = (MCG->C2 & MCG_C2_IRCS_MASK) ? 8000000u : 2000000u;
elessair 0:f269e3021894 45 mcgirc_clock /= 1u + ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT);
elessair 0:f269e3021894 46 mcgirc_clock /= 1u + (MCG->MC & MCG_MC_LIRC_DIV2_MASK);
elessair 0:f269e3021894 47 }
elessair 0:f269e3021894 48
elessair 0:f269e3021894 49 return mcgirc_clock;
elessair 0:f269e3021894 50 }
elessair 0:f269e3021894 51
elessair 0:f269e3021894 52 #else
elessair 0:f269e3021894 53
elessair 0:f269e3021894 54 //Get external oscillator (crystal) frequency
elessair 0:f269e3021894 55 static uint32_t extosc_frequency(void) {
elessair 0:f269e3021894 56 uint32_t MCGClock = SystemCoreClock * (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT));
elessair 0:f269e3021894 57
elessair 0:f269e3021894 58 if ((MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(2)) //MCG clock = external reference clock
elessair 0:f269e3021894 59 return MCGClock;
elessair 0:f269e3021894 60
elessair 0:f269e3021894 61 uint32_t divider, multiplier;
elessair 0:f269e3021894 62 #ifdef MCG_C5_PLLCLKEN0_MASK //PLL available
elessair 0:f269e3021894 63 if ((MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(0)) { //PLL/FLL is selected
elessair 0:f269e3021894 64 if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) { //FLL is selected
elessair 0:f269e3021894 65 #endif
elessair 0:f269e3021894 66 if ((MCG->S & MCG_S_IREFST_MASK) == 0x0u) { //FLL uses external reference
elessair 0:f269e3021894 67 divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
elessair 0:f269e3021894 68 if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u)
elessair 0:f269e3021894 69 divider <<= 5u;
elessair 0:f269e3021894 70 /* Select correct multiplier to calculate the MCG output clock */
elessair 0:f269e3021894 71 switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
elessair 0:f269e3021894 72 case 0x0u:
elessair 0:f269e3021894 73 multiplier = 640u;
elessair 0:f269e3021894 74 break;
elessair 0:f269e3021894 75 case 0x20u:
elessair 0:f269e3021894 76 multiplier = 1280u;
elessair 0:f269e3021894 77 break;
elessair 0:f269e3021894 78 case 0x40u:
elessair 0:f269e3021894 79 multiplier = 1920u;
elessair 0:f269e3021894 80 break;
elessair 0:f269e3021894 81 case 0x60u:
elessair 0:f269e3021894 82 multiplier = 2560u;
elessair 0:f269e3021894 83 break;
elessair 0:f269e3021894 84 case 0x80u:
elessair 0:f269e3021894 85 multiplier = 732u;
elessair 0:f269e3021894 86 break;
elessair 0:f269e3021894 87 case 0xA0u:
elessair 0:f269e3021894 88 multiplier = 1464u;
elessair 0:f269e3021894 89 break;
elessair 0:f269e3021894 90 case 0xC0u:
elessair 0:f269e3021894 91 multiplier = 2197u;
elessair 0:f269e3021894 92 break;
elessair 0:f269e3021894 93 case 0xE0u:
elessair 0:f269e3021894 94 default:
elessair 0:f269e3021894 95 multiplier = 2929u;
elessair 0:f269e3021894 96 break;
elessair 0:f269e3021894 97 }
elessair 0:f269e3021894 98
elessair 0:f269e3021894 99 return MCGClock * divider / multiplier;
elessair 0:f269e3021894 100 }
elessair 0:f269e3021894 101 #ifdef MCG_C5_PLLCLKEN0_MASK
elessair 0:f269e3021894 102 } else { //PLL is selected
elessair 0:f269e3021894 103 divider = (1u + (MCG->C5 & MCG_C5_PRDIV0_MASK));
elessair 0:f269e3021894 104 multiplier = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 24u);
elessair 0:f269e3021894 105 return MCGClock * divider / multiplier;
elessair 0:f269e3021894 106 }
elessair 0:f269e3021894 107 }
elessair 0:f269e3021894 108 #endif
elessair 0:f269e3021894 109
elessair 0:f269e3021894 110 //In all other cases either there is no crystal or we cannot determine it
elessair 0:f269e3021894 111 //For example when the FLL is running on the internal reference, and there is also an
elessair 0:f269e3021894 112 //external crystal. However these are unlikely situations
elessair 0:f269e3021894 113 return 0;
elessair 0:f269e3021894 114 }
elessair 0:f269e3021894 115
elessair 0:f269e3021894 116 //Get MCG PLL/2 or FLL frequency, depending on which one is active, sets PLLFLLSEL bit
elessair 0:f269e3021894 117 static uint32_t mcgpllfll_frequency(void) {
elessair 0:f269e3021894 118 if ((MCG->C1 & MCG_C1_CLKS_MASK) != MCG_C1_CLKS(0)) //PLL/FLL is not selected
elessair 0:f269e3021894 119 return 0;
elessair 0:f269e3021894 120
elessair 0:f269e3021894 121 uint32_t MCGClock = SystemCoreClock * (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT));
elessair 0:f269e3021894 122 #ifdef MCG_C5_PLLCLKEN0_MASK
elessair 0:f269e3021894 123 if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) { //FLL is selected
elessair 0:f269e3021894 124 SIM->SOPT2 &= ~SIM_SOPT2_PLLFLLSEL_MASK; //MCG peripheral clock is FLL output
elessair 0:f269e3021894 125 #endif
elessair 0:f269e3021894 126 return MCGClock;
elessair 0:f269e3021894 127 #ifdef MCG_C5_PLLCLKEN0_MASK
elessair 0:f269e3021894 128 } else { //PLL is selected
elessair 0:f269e3021894 129 SIM->SOPT2 |= SIM_SOPT2_PLLFLLSEL_MASK; //MCG peripheral clock is PLL output
elessair 0:f269e3021894 130 return (MCGClock >> 1);
elessair 0:f269e3021894 131 }
elessair 0:f269e3021894 132 #endif
elessair 0:f269e3021894 133
elessair 0:f269e3021894 134 //It is possible the SystemCoreClock isn't running on the PLL, and the PLL is still active
elessair 0:f269e3021894 135 //for the peripherals, this is however an unlikely setup
elessair 0:f269e3021894 136 }
elessair 0:f269e3021894 137
elessair 0:f269e3021894 138 #endif
elessair 0:f269e3021894 139
elessair 0:f269e3021894 140 #ifdef __cplusplus
elessair 0:f269e3021894 141 }
elessair 0:f269e3021894 142 #endif
elessair 0:f269e3021894 143
elessair 0:f269e3021894 144 #endif