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mbed-os

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cmsis/core_cm4_simd.h@1:3deb71413561, 2017-07-20 (annotated)

Committer:
xuaner
Date:
Thu Jul 20 14:26:57 2017 +0000
Revision:
1:3deb71413561
Parent:
0:f269e3021894 
mbed_os

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elessair 0:f269e3021894 1 /**************************************************************************//**
elessair 0:f269e3021894 2 * @file core_cm4_simd.h
elessair 0:f269e3021894 3 * @brief CMSIS Cortex-M4 SIMD Header File
elessair 0:f269e3021894 4 * @version V3.20
elessair 0:f269e3021894 5 * @date 25. February 2013
elessair 0:f269e3021894 6 *
elessair 0:f269e3021894 7 * @note
elessair 0:f269e3021894 8 *
elessair 0:f269e3021894 9 ******************************************************************************/
elessair 0:f269e3021894 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
elessair 0:f269e3021894 11
elessair 0:f269e3021894 12 All rights reserved.
elessair 0:f269e3021894 13 Redistribution and use in source and binary forms, with or without
elessair 0:f269e3021894 14 modification, are permitted provided that the following conditions are met:
elessair 0:f269e3021894 15 - Redistributions of source code must retain the above copyright
elessair 0:f269e3021894 16 notice, this list of conditions and the following disclaimer.
elessair 0:f269e3021894 17 - Redistributions in binary form must reproduce the above copyright
elessair 0:f269e3021894 18 notice, this list of conditions and the following disclaimer in the
elessair 0:f269e3021894 19 documentation and/or other materials provided with the distribution.
elessair 0:f269e3021894 20 - Neither the name of ARM nor the names of its contributors may be used
elessair 0:f269e3021894 21 to endorse or promote products derived from this software without
elessair 0:f269e3021894 22 specific prior written permission.
elessair 0:f269e3021894 23 *
elessair 0:f269e3021894 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
elessair 0:f269e3021894 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
elessair 0:f269e3021894 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
elessair 0:f269e3021894 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
elessair 0:f269e3021894 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
elessair 0:f269e3021894 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
elessair 0:f269e3021894 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
elessair 0:f269e3021894 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
elessair 0:f269e3021894 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
elessair 0:f269e3021894 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
elessair 0:f269e3021894 34 POSSIBILITY OF SUCH DAMAGE.
elessair 0:f269e3021894 35 ---------------------------------------------------------------------------*/
elessair 0:f269e3021894 36
elessair 0:f269e3021894 37
elessair 0:f269e3021894 38 #ifdef __cplusplus
elessair 0:f269e3021894 39 extern "C" {
elessair 0:f269e3021894 40 #endif
elessair 0:f269e3021894 41
elessair 0:f269e3021894 42 #ifndef __CORE_CM4_SIMD_H
elessair 0:f269e3021894 43 #define __CORE_CM4_SIMD_H
elessair 0:f269e3021894 44
elessair 0:f269e3021894 45
elessair 0:f269e3021894 46 /*******************************************************************************
elessair 0:f269e3021894 47 * Hardware Abstraction Layer
elessair 0:f269e3021894 48 ******************************************************************************/
elessair 0:f269e3021894 49
elessair 0:f269e3021894 50
elessair 0:f269e3021894 51 /* ################### Compiler specific Intrinsics ########################### */
elessair 0:f269e3021894 52 /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
elessair 0:f269e3021894 53 Access to dedicated SIMD instructions
elessair 0:f269e3021894 54 @{
elessair 0:f269e3021894 55 */
elessair 0:f269e3021894 56
elessair 0:f269e3021894 57 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
elessair 0:f269e3021894 58 /* ARM armcc specific functions */
elessair 0:f269e3021894 59
elessair 0:f269e3021894 60 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
elessair 0:f269e3021894 61 #define __SADD8 __sadd8
elessair 0:f269e3021894 62 #define __QADD8 __qadd8
elessair 0:f269e3021894 63 #define __SHADD8 __shadd8
elessair 0:f269e3021894 64 #define __UADD8 __uadd8
elessair 0:f269e3021894 65 #define __UQADD8 __uqadd8
elessair 0:f269e3021894 66 #define __UHADD8 __uhadd8
elessair 0:f269e3021894 67 #define __SSUB8 __ssub8
elessair 0:f269e3021894 68 #define __QSUB8 __qsub8
elessair 0:f269e3021894 69 #define __SHSUB8 __shsub8
elessair 0:f269e3021894 70 #define __USUB8 __usub8
elessair 0:f269e3021894 71 #define __UQSUB8 __uqsub8
elessair 0:f269e3021894 72 #define __UHSUB8 __uhsub8
elessair 0:f269e3021894 73 #define __SADD16 __sadd16
elessair 0:f269e3021894 74 #define __QADD16 __qadd16
elessair 0:f269e3021894 75 #define __SHADD16 __shadd16
elessair 0:f269e3021894 76 #define __UADD16 __uadd16
elessair 0:f269e3021894 77 #define __UQADD16 __uqadd16
elessair 0:f269e3021894 78 #define __UHADD16 __uhadd16
elessair 0:f269e3021894 79 #define __SSUB16 __ssub16
elessair 0:f269e3021894 80 #define __QSUB16 __qsub16
elessair 0:f269e3021894 81 #define __SHSUB16 __shsub16
elessair 0:f269e3021894 82 #define __USUB16 __usub16
elessair 0:f269e3021894 83 #define __UQSUB16 __uqsub16
elessair 0:f269e3021894 84 #define __UHSUB16 __uhsub16
elessair 0:f269e3021894 85 #define __SASX __sasx
elessair 0:f269e3021894 86 #define __QASX __qasx
elessair 0:f269e3021894 87 #define __SHASX __shasx
elessair 0:f269e3021894 88 #define __UASX __uasx
elessair 0:f269e3021894 89 #define __UQASX __uqasx
elessair 0:f269e3021894 90 #define __UHASX __uhasx
elessair 0:f269e3021894 91 #define __SSAX __ssax
elessair 0:f269e3021894 92 #define __QSAX __qsax
elessair 0:f269e3021894 93 #define __SHSAX __shsax
elessair 0:f269e3021894 94 #define __USAX __usax
elessair 0:f269e3021894 95 #define __UQSAX __uqsax
elessair 0:f269e3021894 96 #define __UHSAX __uhsax
elessair 0:f269e3021894 97 #define __USAD8 __usad8
elessair 0:f269e3021894 98 #define __USADA8 __usada8
elessair 0:f269e3021894 99 #define __SSAT16 __ssat16
elessair 0:f269e3021894 100 #define __USAT16 __usat16
elessair 0:f269e3021894 101 #define __UXTB16 __uxtb16
elessair 0:f269e3021894 102 #define __UXTAB16 __uxtab16
elessair 0:f269e3021894 103 #define __SXTB16 __sxtb16
elessair 0:f269e3021894 104 #define __SXTAB16 __sxtab16
elessair 0:f269e3021894 105 #define __SMUAD __smuad
elessair 0:f269e3021894 106 #define __SMUADX __smuadx
elessair 0:f269e3021894 107 #define __SMLAD __smlad
elessair 0:f269e3021894 108 #define __SMLADX __smladx
elessair 0:f269e3021894 109 #define __SMLALD __smlald
elessair 0:f269e3021894 110 #define __SMLALDX __smlaldx
elessair 0:f269e3021894 111 #define __SMUSD __smusd
elessair 0:f269e3021894 112 #define __SMUSDX __smusdx
elessair 0:f269e3021894 113 #define __SMLSD __smlsd
elessair 0:f269e3021894 114 #define __SMLSDX __smlsdx
elessair 0:f269e3021894 115 #define __SMLSLD __smlsld
elessair 0:f269e3021894 116 #define __SMLSLDX __smlsldx
elessair 0:f269e3021894 117 #define __SEL __sel
elessair 0:f269e3021894 118 #define __QADD __qadd
elessair 0:f269e3021894 119 #define __QSUB __qsub
elessair 0:f269e3021894 120
elessair 0:f269e3021894 121 #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
elessair 0:f269e3021894 122 ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
elessair 0:f269e3021894 123
elessair 0:f269e3021894 124 #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
elessair 0:f269e3021894 125 ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
elessair 0:f269e3021894 126
elessair 0:f269e3021894 127 #define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
elessair 0:f269e3021894 128 ((int64_t)(ARG3) << 32) ) >> 32))
elessair 0:f269e3021894 129
elessair 0:f269e3021894 130 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
elessair 0:f269e3021894 131
elessair 0:f269e3021894 132
elessair 0:f269e3021894 133
elessair 0:f269e3021894 134 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
elessair 0:f269e3021894 135 /* IAR iccarm specific functions */
elessair 0:f269e3021894 136
elessair 0:f269e3021894 137 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
elessair 0:f269e3021894 138 #include <cmsis_iar.h>
elessair 0:f269e3021894 139
elessair 0:f269e3021894 140 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
elessair 0:f269e3021894 141
elessair 0:f269e3021894 142
elessair 0:f269e3021894 143
elessair 0:f269e3021894 144 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
elessair 0:f269e3021894 145 /* TI CCS specific functions */
elessair 0:f269e3021894 146
elessair 0:f269e3021894 147 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
elessair 0:f269e3021894 148 #include <cmsis_ccs.h>
elessair 0:f269e3021894 149
elessair 0:f269e3021894 150 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
elessair 0:f269e3021894 151
elessair 0:f269e3021894 152
elessair 0:f269e3021894 153
elessair 0:f269e3021894 154 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
elessair 0:f269e3021894 155 /* GNU gcc specific functions */
elessair 0:f269e3021894 156
elessair 0:f269e3021894 157 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
elessair 0:f269e3021894 158 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 159 {
elessair 0:f269e3021894 160 uint32_t result;
elessair 0:f269e3021894 161
elessair 0:f269e3021894 162 __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 163 return(result);
elessair 0:f269e3021894 164 }
elessair 0:f269e3021894 165
elessair 0:f269e3021894 166 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 167 {
elessair 0:f269e3021894 168 uint32_t result;
elessair 0:f269e3021894 169
elessair 0:f269e3021894 170 __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 171 return(result);
elessair 0:f269e3021894 172 }
elessair 0:f269e3021894 173
elessair 0:f269e3021894 174 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 175 {
elessair 0:f269e3021894 176 uint32_t result;
elessair 0:f269e3021894 177
elessair 0:f269e3021894 178 __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 179 return(result);
elessair 0:f269e3021894 180 }
elessair 0:f269e3021894 181
elessair 0:f269e3021894 182 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 183 {
elessair 0:f269e3021894 184 uint32_t result;
elessair 0:f269e3021894 185
elessair 0:f269e3021894 186 __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 187 return(result);
elessair 0:f269e3021894 188 }
elessair 0:f269e3021894 189
elessair 0:f269e3021894 190 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 191 {
elessair 0:f269e3021894 192 uint32_t result;
elessair 0:f269e3021894 193
elessair 0:f269e3021894 194 __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 195 return(result);
elessair 0:f269e3021894 196 }
elessair 0:f269e3021894 197
elessair 0:f269e3021894 198 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 199 {
elessair 0:f269e3021894 200 uint32_t result;
elessair 0:f269e3021894 201
elessair 0:f269e3021894 202 __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 203 return(result);
elessair 0:f269e3021894 204 }
elessair 0:f269e3021894 205
elessair 0:f269e3021894 206
elessair 0:f269e3021894 207 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 208 {
elessair 0:f269e3021894 209 uint32_t result;
elessair 0:f269e3021894 210
elessair 0:f269e3021894 211 __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 212 return(result);
elessair 0:f269e3021894 213 }
elessair 0:f269e3021894 214
elessair 0:f269e3021894 215 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 216 {
elessair 0:f269e3021894 217 uint32_t result;
elessair 0:f269e3021894 218
elessair 0:f269e3021894 219 __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 220 return(result);
elessair 0:f269e3021894 221 }
elessair 0:f269e3021894 222
elessair 0:f269e3021894 223 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 224 {
elessair 0:f269e3021894 225 uint32_t result;
elessair 0:f269e3021894 226
elessair 0:f269e3021894 227 __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 228 return(result);
elessair 0:f269e3021894 229 }
elessair 0:f269e3021894 230
elessair 0:f269e3021894 231 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 232 {
elessair 0:f269e3021894 233 uint32_t result;
elessair 0:f269e3021894 234
elessair 0:f269e3021894 235 __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 236 return(result);
elessair 0:f269e3021894 237 }
elessair 0:f269e3021894 238
elessair 0:f269e3021894 239 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 240 {
elessair 0:f269e3021894 241 uint32_t result;
elessair 0:f269e3021894 242
elessair 0:f269e3021894 243 __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 244 return(result);
elessair 0:f269e3021894 245 }
elessair 0:f269e3021894 246
elessair 0:f269e3021894 247 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 248 {
elessair 0:f269e3021894 249 uint32_t result;
elessair 0:f269e3021894 250
elessair 0:f269e3021894 251 __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 252 return(result);
elessair 0:f269e3021894 253 }
elessair 0:f269e3021894 254
elessair 0:f269e3021894 255
elessair 0:f269e3021894 256 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 257 {
elessair 0:f269e3021894 258 uint32_t result;
elessair 0:f269e3021894 259
elessair 0:f269e3021894 260 __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 261 return(result);
elessair 0:f269e3021894 262 }
elessair 0:f269e3021894 263
elessair 0:f269e3021894 264 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 265 {
elessair 0:f269e3021894 266 uint32_t result;
elessair 0:f269e3021894 267
elessair 0:f269e3021894 268 __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 269 return(result);
elessair 0:f269e3021894 270 }
elessair 0:f269e3021894 271
elessair 0:f269e3021894 272 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 273 {
elessair 0:f269e3021894 274 uint32_t result;
elessair 0:f269e3021894 275
elessair 0:f269e3021894 276 __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 277 return(result);
elessair 0:f269e3021894 278 }
elessair 0:f269e3021894 279
elessair 0:f269e3021894 280 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 281 {
elessair 0:f269e3021894 282 uint32_t result;
elessair 0:f269e3021894 283
elessair 0:f269e3021894 284 __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 285 return(result);
elessair 0:f269e3021894 286 }
elessair 0:f269e3021894 287
elessair 0:f269e3021894 288 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 289 {
elessair 0:f269e3021894 290 uint32_t result;
elessair 0:f269e3021894 291
elessair 0:f269e3021894 292 __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 293 return(result);
elessair 0:f269e3021894 294 }
elessair 0:f269e3021894 295
elessair 0:f269e3021894 296 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 297 {
elessair 0:f269e3021894 298 uint32_t result;
elessair 0:f269e3021894 299
elessair 0:f269e3021894 300 __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 301 return(result);
elessair 0:f269e3021894 302 }
elessair 0:f269e3021894 303
elessair 0:f269e3021894 304 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 305 {
elessair 0:f269e3021894 306 uint32_t result;
elessair 0:f269e3021894 307
elessair 0:f269e3021894 308 __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 309 return(result);
elessair 0:f269e3021894 310 }
elessair 0:f269e3021894 311
elessair 0:f269e3021894 312 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 313 {
elessair 0:f269e3021894 314 uint32_t result;
elessair 0:f269e3021894 315
elessair 0:f269e3021894 316 __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 317 return(result);
elessair 0:f269e3021894 318 }
elessair 0:f269e3021894 319
elessair 0:f269e3021894 320 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 321 {
elessair 0:f269e3021894 322 uint32_t result;
elessair 0:f269e3021894 323
elessair 0:f269e3021894 324 __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 325 return(result);
elessair 0:f269e3021894 326 }
elessair 0:f269e3021894 327
elessair 0:f269e3021894 328 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 329 {
elessair 0:f269e3021894 330 uint32_t result;
elessair 0:f269e3021894 331
elessair 0:f269e3021894 332 __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 333 return(result);
elessair 0:f269e3021894 334 }
elessair 0:f269e3021894 335
elessair 0:f269e3021894 336 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 337 {
elessair 0:f269e3021894 338 uint32_t result;
elessair 0:f269e3021894 339
elessair 0:f269e3021894 340 __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 341 return(result);
elessair 0:f269e3021894 342 }
elessair 0:f269e3021894 343
elessair 0:f269e3021894 344 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 345 {
elessair 0:f269e3021894 346 uint32_t result;
elessair 0:f269e3021894 347
elessair 0:f269e3021894 348 __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 349 return(result);
elessair 0:f269e3021894 350 }
elessair 0:f269e3021894 351
elessair 0:f269e3021894 352 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 353 {
elessair 0:f269e3021894 354 uint32_t result;
elessair 0:f269e3021894 355
elessair 0:f269e3021894 356 __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 357 return(result);
elessair 0:f269e3021894 358 }
elessair 0:f269e3021894 359
elessair 0:f269e3021894 360 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 361 {
elessair 0:f269e3021894 362 uint32_t result;
elessair 0:f269e3021894 363
elessair 0:f269e3021894 364 __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 365 return(result);
elessair 0:f269e3021894 366 }
elessair 0:f269e3021894 367
elessair 0:f269e3021894 368 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 369 {
elessair 0:f269e3021894 370 uint32_t result;
elessair 0:f269e3021894 371
elessair 0:f269e3021894 372 __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 373 return(result);
elessair 0:f269e3021894 374 }
elessair 0:f269e3021894 375
elessair 0:f269e3021894 376 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 377 {
elessair 0:f269e3021894 378 uint32_t result;
elessair 0:f269e3021894 379
elessair 0:f269e3021894 380 __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 381 return(result);
elessair 0:f269e3021894 382 }
elessair 0:f269e3021894 383
elessair 0:f269e3021894 384 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 385 {
elessair 0:f269e3021894 386 uint32_t result;
elessair 0:f269e3021894 387
elessair 0:f269e3021894 388 __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 389 return(result);
elessair 0:f269e3021894 390 }
elessair 0:f269e3021894 391
elessair 0:f269e3021894 392 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 393 {
elessair 0:f269e3021894 394 uint32_t result;
elessair 0:f269e3021894 395
elessair 0:f269e3021894 396 __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 397 return(result);
elessair 0:f269e3021894 398 }
elessair 0:f269e3021894 399
elessair 0:f269e3021894 400 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 401 {
elessair 0:f269e3021894 402 uint32_t result;
elessair 0:f269e3021894 403
elessair 0:f269e3021894 404 __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 405 return(result);
elessair 0:f269e3021894 406 }
elessair 0:f269e3021894 407
elessair 0:f269e3021894 408 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 409 {
elessair 0:f269e3021894 410 uint32_t result;
elessair 0:f269e3021894 411
elessair 0:f269e3021894 412 __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 413 return(result);
elessair 0:f269e3021894 414 }
elessair 0:f269e3021894 415
elessair 0:f269e3021894 416 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 417 {
elessair 0:f269e3021894 418 uint32_t result;
elessair 0:f269e3021894 419
elessair 0:f269e3021894 420 __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 421 return(result);
elessair 0:f269e3021894 422 }
elessair 0:f269e3021894 423
elessair 0:f269e3021894 424 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 425 {
elessair 0:f269e3021894 426 uint32_t result;
elessair 0:f269e3021894 427
elessair 0:f269e3021894 428 __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 429 return(result);
elessair 0:f269e3021894 430 }
elessair 0:f269e3021894 431
elessair 0:f269e3021894 432 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 433 {
elessair 0:f269e3021894 434 uint32_t result;
elessair 0:f269e3021894 435
elessair 0:f269e3021894 436 __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 437 return(result);
elessair 0:f269e3021894 438 }
elessair 0:f269e3021894 439
elessair 0:f269e3021894 440 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 441 {
elessair 0:f269e3021894 442 uint32_t result;
elessair 0:f269e3021894 443
elessair 0:f269e3021894 444 __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 445 return(result);
elessair 0:f269e3021894 446 }
elessair 0:f269e3021894 447
elessair 0:f269e3021894 448 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 449 {
elessair 0:f269e3021894 450 uint32_t result;
elessair 0:f269e3021894 451
elessair 0:f269e3021894 452 __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 453 return(result);
elessair 0:f269e3021894 454 }
elessair 0:f269e3021894 455
elessair 0:f269e3021894 456 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
elessair 0:f269e3021894 457 {
elessair 0:f269e3021894 458 uint32_t result;
elessair 0:f269e3021894 459
elessair 0:f269e3021894 460 __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
elessair 0:f269e3021894 461 return(result);
elessair 0:f269e3021894 462 }
elessair 0:f269e3021894 463
elessair 0:f269e3021894 464 #define __SSAT16(ARG1,ARG2) \
elessair 0:f269e3021894 465 ({ \
elessair 0:f269e3021894 466 uint32_t __RES, __ARG1 = (ARG1); \
elessair 0:f269e3021894 467 __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
elessair 0:f269e3021894 468 __RES; \
elessair 0:f269e3021894 469 })
elessair 0:f269e3021894 470
elessair 0:f269e3021894 471 #define __USAT16(ARG1,ARG2) \
elessair 0:f269e3021894 472 ({ \
elessair 0:f269e3021894 473 uint32_t __RES, __ARG1 = (ARG1); \
elessair 0:f269e3021894 474 __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
elessair 0:f269e3021894 475 __RES; \
elessair 0:f269e3021894 476 })
elessair 0:f269e3021894 477
elessair 0:f269e3021894 478 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
elessair 0:f269e3021894 479 {
elessair 0:f269e3021894 480 uint32_t result;
elessair 0:f269e3021894 481
elessair 0:f269e3021894 482 __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
elessair 0:f269e3021894 483 return(result);
elessair 0:f269e3021894 484 }
elessair 0:f269e3021894 485
elessair 0:f269e3021894 486 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 487 {
elessair 0:f269e3021894 488 uint32_t result;
elessair 0:f269e3021894 489
elessair 0:f269e3021894 490 __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 491 return(result);
elessair 0:f269e3021894 492 }
elessair 0:f269e3021894 493
elessair 0:f269e3021894 494 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
elessair 0:f269e3021894 495 {
elessair 0:f269e3021894 496 uint32_t result;
elessair 0:f269e3021894 497
elessair 0:f269e3021894 498 __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
elessair 0:f269e3021894 499 return(result);
elessair 0:f269e3021894 500 }
elessair 0:f269e3021894 501
elessair 0:f269e3021894 502 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 503 {
elessair 0:f269e3021894 504 uint32_t result;
elessair 0:f269e3021894 505
elessair 0:f269e3021894 506 __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 507 return(result);
elessair 0:f269e3021894 508 }
elessair 0:f269e3021894 509
elessair 0:f269e3021894 510 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 511 {
elessair 0:f269e3021894 512 uint32_t result;
elessair 0:f269e3021894 513
elessair 0:f269e3021894 514 __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 515 return(result);
elessair 0:f269e3021894 516 }
elessair 0:f269e3021894 517
elessair 0:f269e3021894 518 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 519 {
elessair 0:f269e3021894 520 uint32_t result;
elessair 0:f269e3021894 521
elessair 0:f269e3021894 522 __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 523 return(result);
elessair 0:f269e3021894 524 }
elessair 0:f269e3021894 525
elessair 0:f269e3021894 526 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
elessair 0:f269e3021894 527 {
elessair 0:f269e3021894 528 uint32_t result;
elessair 0:f269e3021894 529
elessair 0:f269e3021894 530 __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
elessair 0:f269e3021894 531 return(result);
elessair 0:f269e3021894 532 }
elessair 0:f269e3021894 533
elessair 0:f269e3021894 534 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
elessair 0:f269e3021894 535 {
elessair 0:f269e3021894 536 uint32_t result;
elessair 0:f269e3021894 537
elessair 0:f269e3021894 538 __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
elessair 0:f269e3021894 539 return(result);
elessair 0:f269e3021894 540 }
elessair 0:f269e3021894 541
elessair 0:f269e3021894 542 #define __SMLALD(ARG1,ARG2,ARG3) \
elessair 0:f269e3021894 543 ({ \
elessair 0:f269e3021894 544 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
elessair 0:f269e3021894 545 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
elessair 0:f269e3021894 546 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
elessair 0:f269e3021894 547 })
elessair 0:f269e3021894 548
elessair 0:f269e3021894 549 #define __SMLALDX(ARG1,ARG2,ARG3) \
elessair 0:f269e3021894 550 ({ \
elessair 0:f269e3021894 551 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
elessair 0:f269e3021894 552 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
elessair 0:f269e3021894 553 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
elessair 0:f269e3021894 554 })
elessair 0:f269e3021894 555
elessair 0:f269e3021894 556 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 557 {
elessair 0:f269e3021894 558 uint32_t result;
elessair 0:f269e3021894 559
elessair 0:f269e3021894 560 __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 561 return(result);
elessair 0:f269e3021894 562 }
elessair 0:f269e3021894 563
elessair 0:f269e3021894 564 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 565 {
elessair 0:f269e3021894 566 uint32_t result;
elessair 0:f269e3021894 567
elessair 0:f269e3021894 568 __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 569 return(result);
elessair 0:f269e3021894 570 }
elessair 0:f269e3021894 571
elessair 0:f269e3021894 572 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
elessair 0:f269e3021894 573 {
elessair 0:f269e3021894 574 uint32_t result;
elessair 0:f269e3021894 575
elessair 0:f269e3021894 576 __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
elessair 0:f269e3021894 577 return(result);
elessair 0:f269e3021894 578 }
elessair 0:f269e3021894 579
elessair 0:f269e3021894 580 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
elessair 0:f269e3021894 581 {
elessair 0:f269e3021894 582 uint32_t result;
elessair 0:f269e3021894 583
elessair 0:f269e3021894 584 __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
elessair 0:f269e3021894 585 return(result);
elessair 0:f269e3021894 586 }
elessair 0:f269e3021894 587
elessair 0:f269e3021894 588 #define __SMLSLD(ARG1,ARG2,ARG3) \
elessair 0:f269e3021894 589 ({ \
elessair 0:f269e3021894 590 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
elessair 0:f269e3021894 591 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
elessair 0:f269e3021894 592 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
elessair 0:f269e3021894 593 })
elessair 0:f269e3021894 594
elessair 0:f269e3021894 595 #define __SMLSLDX(ARG1,ARG2,ARG3) \
elessair 0:f269e3021894 596 ({ \
elessair 0:f269e3021894 597 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
elessair 0:f269e3021894 598 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
elessair 0:f269e3021894 599 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
elessair 0:f269e3021894 600 })
elessair 0:f269e3021894 601
elessair 0:f269e3021894 602 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 603 {
elessair 0:f269e3021894 604 uint32_t result;
elessair 0:f269e3021894 605
elessair 0:f269e3021894 606 __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 607 return(result);
elessair 0:f269e3021894 608 }
elessair 0:f269e3021894 609
elessair 0:f269e3021894 610 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 611 {
elessair 0:f269e3021894 612 uint32_t result;
elessair 0:f269e3021894 613
elessair 0:f269e3021894 614 __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 615 return(result);
elessair 0:f269e3021894 616 }
elessair 0:f269e3021894 617
elessair 0:f269e3021894 618 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 619 {
elessair 0:f269e3021894 620 uint32_t result;
elessair 0:f269e3021894 621
elessair 0:f269e3021894 622 __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
elessair 0:f269e3021894 623 return(result);
elessair 0:f269e3021894 624 }
elessair 0:f269e3021894 625
elessair 0:f269e3021894 626 #define __PKHBT(ARG1,ARG2,ARG3) \
elessair 0:f269e3021894 627 ({ \
elessair 0:f269e3021894 628 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
elessair 0:f269e3021894 629 __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
elessair 0:f269e3021894 630 __RES; \
elessair 0:f269e3021894 631 })
elessair 0:f269e3021894 632
elessair 0:f269e3021894 633 #define __PKHTB(ARG1,ARG2,ARG3) \
elessair 0:f269e3021894 634 ({ \
elessair 0:f269e3021894 635 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
elessair 0:f269e3021894 636 if (ARG3 == 0) \
elessair 0:f269e3021894 637 __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
elessair 0:f269e3021894 638 else \
elessair 0:f269e3021894 639 __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
elessair 0:f269e3021894 640 __RES; \
elessair 0:f269e3021894 641 })
elessair 0:f269e3021894 642
elessair 0:f269e3021894 643 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
elessair 0:f269e3021894 644 {
elessair 0:f269e3021894 645 int32_t result;
elessair 0:f269e3021894 646
elessair 0:f269e3021894 647 __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
elessair 0:f269e3021894 648 return(result);
elessair 0:f269e3021894 649 }
elessair 0:f269e3021894 650
elessair 0:f269e3021894 651 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
elessair 0:f269e3021894 652
elessair 0:f269e3021894 653
elessair 0:f269e3021894 654
elessair 0:f269e3021894 655 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
elessair 0:f269e3021894 656 /* TASKING carm specific functions */
elessair 0:f269e3021894 657
elessair 0:f269e3021894 658
elessair 0:f269e3021894 659 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
elessair 0:f269e3021894 660 /* not yet supported */
elessair 0:f269e3021894 661 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
elessair 0:f269e3021894 662
elessair 0:f269e3021894 663
elessair 0:f269e3021894 664 #endif
elessair 0:f269e3021894 665
elessair 0:f269e3021894 666 /*@} end of group CMSIS_SIMD_intrinsics */
elessair 0:f269e3021894 667
elessair 0:f269e3021894 668
elessair 0:f269e3021894 669 #endif /* __CORE_CM4_SIMD_H */
elessair 0:f269e3021894 670
elessair 0:f269e3021894 671 #ifdef __cplusplus
elessair 0:f269e3021894 672 }
elessair 0:f269e3021894 673 #endif