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cmsis/core_cm4.h@1:3deb71413561, 2017-07-20 (annotated)

Committer:
xuaner
Date:
Thu Jul 20 14:26:57 2017 +0000
Revision:
1:3deb71413561
Parent:
0:f269e3021894 
mbed_os

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elessair 0:f269e3021894 1 /**************************************************************************//**
elessair 0:f269e3021894 2 * @file core_cm4.h
elessair 0:f269e3021894 3 * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
elessair 0:f269e3021894 4 * @version V4.10
elessair 0:f269e3021894 5 * @date 18. March 2015
elessair 0:f269e3021894 6 *
elessair 0:f269e3021894 7 * @note
elessair 0:f269e3021894 8 *
elessair 0:f269e3021894 9 ******************************************************************************/
elessair 0:f269e3021894 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
elessair 0:f269e3021894 11
elessair 0:f269e3021894 12 All rights reserved.
elessair 0:f269e3021894 13 Redistribution and use in source and binary forms, with or without
elessair 0:f269e3021894 14 modification, are permitted provided that the following conditions are met:
elessair 0:f269e3021894 15 - Redistributions of source code must retain the above copyright
elessair 0:f269e3021894 16 notice, this list of conditions and the following disclaimer.
elessair 0:f269e3021894 17 - Redistributions in binary form must reproduce the above copyright
elessair 0:f269e3021894 18 notice, this list of conditions and the following disclaimer in the
elessair 0:f269e3021894 19 documentation and/or other materials provided with the distribution.
elessair 0:f269e3021894 20 - Neither the name of ARM nor the names of its contributors may be used
elessair 0:f269e3021894 21 to endorse or promote products derived from this software without
elessair 0:f269e3021894 22 specific prior written permission.
elessair 0:f269e3021894 23 *
elessair 0:f269e3021894 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
elessair 0:f269e3021894 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
elessair 0:f269e3021894 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
elessair 0:f269e3021894 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
elessair 0:f269e3021894 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
elessair 0:f269e3021894 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
elessair 0:f269e3021894 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
elessair 0:f269e3021894 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
elessair 0:f269e3021894 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
elessair 0:f269e3021894 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
elessair 0:f269e3021894 34 POSSIBILITY OF SUCH DAMAGE.
elessair 0:f269e3021894 35 ---------------------------------------------------------------------------*/
elessair 0:f269e3021894 36
elessair 0:f269e3021894 37
elessair 0:f269e3021894 38 #if defined ( __ICCARM__ )
elessair 0:f269e3021894 39 #pragma system_include /* treat file as system include file for MISRA check */
elessair 0:f269e3021894 40 #endif
elessair 0:f269e3021894 41
elessair 0:f269e3021894 42 #ifndef __CORE_CM4_H_GENERIC
elessair 0:f269e3021894 43 #define __CORE_CM4_H_GENERIC
elessair 0:f269e3021894 44
elessair 0:f269e3021894 45 #ifdef __cplusplus
elessair 0:f269e3021894 46 extern "C" {
elessair 0:f269e3021894 47 #endif
elessair 0:f269e3021894 48
elessair 0:f269e3021894 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
elessair 0:f269e3021894 50 CMSIS violates the following MISRA-C:2004 rules:
elessair 0:f269e3021894 51
elessair 0:f269e3021894 52 \li Required Rule 8.5, object/function definition in header file.<br>
elessair 0:f269e3021894 53 Function definitions in header files are used to allow 'inlining'.
elessair 0:f269e3021894 54
elessair 0:f269e3021894 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
elessair 0:f269e3021894 56 Unions are used for effective representation of core registers.
elessair 0:f269e3021894 57
elessair 0:f269e3021894 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
elessair 0:f269e3021894 59 Function-like macros are used to allow more efficient code.
elessair 0:f269e3021894 60 */
elessair 0:f269e3021894 61
elessair 0:f269e3021894 62
elessair 0:f269e3021894 63 /*******************************************************************************
elessair 0:f269e3021894 64 * CMSIS definitions
elessair 0:f269e3021894 65 ******************************************************************************/
elessair 0:f269e3021894 66 /** \ingroup Cortex_M4
elessair 0:f269e3021894 67 @{
elessair 0:f269e3021894 68 */
elessair 0:f269e3021894 69
elessair 0:f269e3021894 70 /* CMSIS CM4 definitions */
elessair 0:f269e3021894 71 #define __CM4_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
elessair 0:f269e3021894 72 #define __CM4_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
elessair 0:f269e3021894 73 #define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \
elessair 0:f269e3021894 74 __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
elessair 0:f269e3021894 75
elessair 0:f269e3021894 76 #define __CORTEX_M (0x04) /*!< Cortex-M Core */
elessair 0:f269e3021894 77
elessair 0:f269e3021894 78
elessair 0:f269e3021894 79 #if defined ( __CC_ARM )
elessair 0:f269e3021894 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
elessair 0:f269e3021894 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
elessair 0:f269e3021894 82 #define __STATIC_INLINE static __inline
elessair 0:f269e3021894 83
elessair 0:f269e3021894 84 #elif defined ( __GNUC__ )
elessair 0:f269e3021894 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
elessair 0:f269e3021894 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
elessair 0:f269e3021894 87 #define __STATIC_INLINE static inline
elessair 0:f269e3021894 88
elessair 0:f269e3021894 89 #elif defined ( __ICCARM__ )
elessair 0:f269e3021894 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
elessair 0:f269e3021894 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
elessair 0:f269e3021894 92 #define __STATIC_INLINE static inline
elessair 0:f269e3021894 93
elessair 0:f269e3021894 94 #elif defined ( __TMS470__ )
elessair 0:f269e3021894 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
elessair 0:f269e3021894 96 #define __STATIC_INLINE static inline
elessair 0:f269e3021894 97
elessair 0:f269e3021894 98 #elif defined ( __TASKING__ )
elessair 0:f269e3021894 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
elessair 0:f269e3021894 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
elessair 0:f269e3021894 101 #define __STATIC_INLINE static inline
elessair 0:f269e3021894 102
elessair 0:f269e3021894 103 #elif defined ( __CSMC__ )
elessair 0:f269e3021894 104 #define __packed
elessair 0:f269e3021894 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
elessair 0:f269e3021894 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
elessair 0:f269e3021894 107 #define __STATIC_INLINE static inline
elessair 0:f269e3021894 108
elessair 0:f269e3021894 109 #endif
elessair 0:f269e3021894 110
elessair 0:f269e3021894 111 /** __FPU_USED indicates whether an FPU is used or not.
elessair 0:f269e3021894 112 For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
elessair 0:f269e3021894 113 */
elessair 0:f269e3021894 114 #if defined ( __CC_ARM )
elessair 0:f269e3021894 115 #if defined __TARGET_FPU_VFP
elessair 0:f269e3021894 116 #if (__FPU_PRESENT == 1)
elessair 0:f269e3021894 117 #define __FPU_USED 1
elessair 0:f269e3021894 118 #else
elessair 0:f269e3021894 119 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
elessair 0:f269e3021894 120 #define __FPU_USED 0
elessair 0:f269e3021894 121 #endif
elessair 0:f269e3021894 122 #else
elessair 0:f269e3021894 123 #define __FPU_USED 0
elessair 0:f269e3021894 124 #endif
elessair 0:f269e3021894 125
elessair 0:f269e3021894 126 #elif defined ( __GNUC__ )
elessair 0:f269e3021894 127 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
elessair 0:f269e3021894 128 #if (__FPU_PRESENT == 1)
elessair 0:f269e3021894 129 #define __FPU_USED 1
elessair 0:f269e3021894 130 #else
elessair 0:f269e3021894 131 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
elessair 0:f269e3021894 132 #define __FPU_USED 0
elessair 0:f269e3021894 133 #endif
elessair 0:f269e3021894 134 #else
elessair 0:f269e3021894 135 #define __FPU_USED 0
elessair 0:f269e3021894 136 #endif
elessair 0:f269e3021894 137
elessair 0:f269e3021894 138 #elif defined ( __ICCARM__ )
elessair 0:f269e3021894 139 #if defined __ARMVFP__
elessair 0:f269e3021894 140 #if (__FPU_PRESENT == 1)
elessair 0:f269e3021894 141 #define __FPU_USED 1
elessair 0:f269e3021894 142 #else
elessair 0:f269e3021894 143 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
elessair 0:f269e3021894 144 #define __FPU_USED 0
elessair 0:f269e3021894 145 #endif
elessair 0:f269e3021894 146 #else
elessair 0:f269e3021894 147 #define __FPU_USED 0
elessair 0:f269e3021894 148 #endif
elessair 0:f269e3021894 149
elessair 0:f269e3021894 150 #elif defined ( __TMS470__ )
elessair 0:f269e3021894 151 #if defined __TI_VFP_SUPPORT__
elessair 0:f269e3021894 152 #if (__FPU_PRESENT == 1)
elessair 0:f269e3021894 153 #define __FPU_USED 1
elessair 0:f269e3021894 154 #else
elessair 0:f269e3021894 155 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
elessair 0:f269e3021894 156 #define __FPU_USED 0
elessair 0:f269e3021894 157 #endif
elessair 0:f269e3021894 158 #else
elessair 0:f269e3021894 159 #define __FPU_USED 0
elessair 0:f269e3021894 160 #endif
elessair 0:f269e3021894 161
elessair 0:f269e3021894 162 #elif defined ( __TASKING__ )
elessair 0:f269e3021894 163 #if defined __FPU_VFP__
elessair 0:f269e3021894 164 #if (__FPU_PRESENT == 1)
elessair 0:f269e3021894 165 #define __FPU_USED 1
elessair 0:f269e3021894 166 #else
elessair 0:f269e3021894 167 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
elessair 0:f269e3021894 168 #define __FPU_USED 0
elessair 0:f269e3021894 169 #endif
elessair 0:f269e3021894 170 #else
elessair 0:f269e3021894 171 #define __FPU_USED 0
elessair 0:f269e3021894 172 #endif
elessair 0:f269e3021894 173
elessair 0:f269e3021894 174 #elif defined ( __CSMC__ ) /* Cosmic */
elessair 0:f269e3021894 175 #if ( __CSMC__ & 0x400) // FPU present for parser
elessair 0:f269e3021894 176 #if (__FPU_PRESENT == 1)
elessair 0:f269e3021894 177 #define __FPU_USED 1
elessair 0:f269e3021894 178 #else
elessair 0:f269e3021894 179 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
elessair 0:f269e3021894 180 #define __FPU_USED 0
elessair 0:f269e3021894 181 #endif
elessair 0:f269e3021894 182 #else
elessair 0:f269e3021894 183 #define __FPU_USED 0
elessair 0:f269e3021894 184 #endif
elessair 0:f269e3021894 185 #endif
elessair 0:f269e3021894 186
elessair 0:f269e3021894 187 #include <stdint.h> /* standard types definitions */
elessair 0:f269e3021894 188 #include <core_cmInstr.h> /* Core Instruction Access */
elessair 0:f269e3021894 189 #include <core_cmFunc.h> /* Core Function Access */
elessair 0:f269e3021894 190 #include <core_cmSimd.h> /* Compiler specific SIMD Intrinsics */
elessair 0:f269e3021894 191
elessair 0:f269e3021894 192 #ifdef __cplusplus
elessair 0:f269e3021894 193 }
elessair 0:f269e3021894 194 #endif
elessair 0:f269e3021894 195
elessair 0:f269e3021894 196 #endif /* __CORE_CM4_H_GENERIC */
elessair 0:f269e3021894 197
elessair 0:f269e3021894 198 #ifndef __CMSIS_GENERIC
elessair 0:f269e3021894 199
elessair 0:f269e3021894 200 #ifndef __CORE_CM4_H_DEPENDANT
elessair 0:f269e3021894 201 #define __CORE_CM4_H_DEPENDANT
elessair 0:f269e3021894 202
elessair 0:f269e3021894 203 #ifdef __cplusplus
elessair 0:f269e3021894 204 extern "C" {
elessair 0:f269e3021894 205 #endif
elessair 0:f269e3021894 206
elessair 0:f269e3021894 207 /* check device defines and use defaults */
elessair 0:f269e3021894 208 #if defined __CHECK_DEVICE_DEFINES
elessair 0:f269e3021894 209 #ifndef __CM4_REV
elessair 0:f269e3021894 210 #define __CM4_REV 0x0000
elessair 0:f269e3021894 211 #warning "__CM4_REV not defined in device header file; using default!"
elessair 0:f269e3021894 212 #endif
elessair 0:f269e3021894 213
elessair 0:f269e3021894 214 #ifndef __FPU_PRESENT
elessair 0:f269e3021894 215 #define __FPU_PRESENT 0
elessair 0:f269e3021894 216 #warning "__FPU_PRESENT not defined in device header file; using default!"
elessair 0:f269e3021894 217 #endif
elessair 0:f269e3021894 218
elessair 0:f269e3021894 219 #ifndef __MPU_PRESENT
elessair 0:f269e3021894 220 #define __MPU_PRESENT 0
elessair 0:f269e3021894 221 #warning "__MPU_PRESENT not defined in device header file; using default!"
elessair 0:f269e3021894 222 #endif
elessair 0:f269e3021894 223
elessair 0:f269e3021894 224 #ifndef __NVIC_PRIO_BITS
elessair 0:f269e3021894 225 #define __NVIC_PRIO_BITS 4
elessair 0:f269e3021894 226 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
elessair 0:f269e3021894 227 #endif
elessair 0:f269e3021894 228
elessair 0:f269e3021894 229 #ifndef __Vendor_SysTickConfig
elessair 0:f269e3021894 230 #define __Vendor_SysTickConfig 0
elessair 0:f269e3021894 231 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
elessair 0:f269e3021894 232 #endif
elessair 0:f269e3021894 233 #endif
elessair 0:f269e3021894 234
elessair 0:f269e3021894 235 /* IO definitions (access restrictions to peripheral registers) */
elessair 0:f269e3021894 236 /**
elessair 0:f269e3021894 237 \defgroup CMSIS_glob_defs CMSIS Global Defines
elessair 0:f269e3021894 238
elessair 0:f269e3021894 239 <strong>IO Type Qualifiers</strong> are used
elessair 0:f269e3021894 240 \li to specify the access to peripheral variables.
elessair 0:f269e3021894 241 \li for automatic generation of peripheral register debug information.
elessair 0:f269e3021894 242 */
elessair 0:f269e3021894 243 #ifdef __cplusplus
elessair 0:f269e3021894 244 #define __I volatile /*!< Defines 'read only' permissions */
elessair 0:f269e3021894 245 #else
elessair 0:f269e3021894 246 #define __I volatile const /*!< Defines 'read only' permissions */
elessair 0:f269e3021894 247 #endif
elessair 0:f269e3021894 248 #define __O volatile /*!< Defines 'write only' permissions */
elessair 0:f269e3021894 249 #define __IO volatile /*!< Defines 'read / write' permissions */
elessair 0:f269e3021894 250
elessair 0:f269e3021894 251 /*@} end of group Cortex_M4 */
elessair 0:f269e3021894 252
elessair 0:f269e3021894 253
elessair 0:f269e3021894 254
elessair 0:f269e3021894 255 /*******************************************************************************
elessair 0:f269e3021894 256 * Register Abstraction
elessair 0:f269e3021894 257 Core Register contain:
elessair 0:f269e3021894 258 - Core Register
elessair 0:f269e3021894 259 - Core NVIC Register
elessair 0:f269e3021894 260 - Core SCB Register
elessair 0:f269e3021894 261 - Core SysTick Register
elessair 0:f269e3021894 262 - Core Debug Register
elessair 0:f269e3021894 263 - Core MPU Register
elessair 0:f269e3021894 264 - Core FPU Register
elessair 0:f269e3021894 265 ******************************************************************************/
elessair 0:f269e3021894 266 /** \defgroup CMSIS_core_register Defines and Type Definitions
elessair 0:f269e3021894 267 \brief Type definitions and defines for Cortex-M processor based devices.
elessair 0:f269e3021894 268 */
elessair 0:f269e3021894 269
elessair 0:f269e3021894 270 /** \ingroup CMSIS_core_register
elessair 0:f269e3021894 271 \defgroup CMSIS_CORE Status and Control Registers
elessair 0:f269e3021894 272 \brief Core Register type definitions.
elessair 0:f269e3021894 273 @{
elessair 0:f269e3021894 274 */
elessair 0:f269e3021894 275
elessair 0:f269e3021894 276 /** \brief Union type to access the Application Program Status Register (APSR).
elessair 0:f269e3021894 277 */
elessair 0:f269e3021894 278 typedef union
elessair 0:f269e3021894 279 {
elessair 0:f269e3021894 280 struct
elessair 0:f269e3021894 281 {
elessair 0:f269e3021894 282 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
elessair 0:f269e3021894 283 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
elessair 0:f269e3021894 284 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
elessair 0:f269e3021894 285 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
elessair 0:f269e3021894 286 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
elessair 0:f269e3021894 287 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
elessair 0:f269e3021894 288 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
elessair 0:f269e3021894 289 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
elessair 0:f269e3021894 290 } b; /*!< Structure used for bit access */
elessair 0:f269e3021894 291 uint32_t w; /*!< Type used for word access */
elessair 0:f269e3021894 292 } APSR_Type;
elessair 0:f269e3021894 293
elessair 0:f269e3021894 294 /* APSR Register Definitions */
elessair 0:f269e3021894 295 #define APSR_N_Pos 31 /*!< APSR: N Position */
elessair 0:f269e3021894 296 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
elessair 0:f269e3021894 297
elessair 0:f269e3021894 298 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
elessair 0:f269e3021894 299 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
elessair 0:f269e3021894 300
elessair 0:f269e3021894 301 #define APSR_C_Pos 29 /*!< APSR: C Position */
elessair 0:f269e3021894 302 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
elessair 0:f269e3021894 303
elessair 0:f269e3021894 304 #define APSR_V_Pos 28 /*!< APSR: V Position */
elessair 0:f269e3021894 305 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
elessair 0:f269e3021894 306
elessair 0:f269e3021894 307 #define APSR_Q_Pos 27 /*!< APSR: Q Position */
elessair 0:f269e3021894 308 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
elessair 0:f269e3021894 309
elessair 0:f269e3021894 310 #define APSR_GE_Pos 16 /*!< APSR: GE Position */
elessair 0:f269e3021894 311 #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
elessair 0:f269e3021894 312
elessair 0:f269e3021894 313
elessair 0:f269e3021894 314 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
elessair 0:f269e3021894 315 */
elessair 0:f269e3021894 316 typedef union
elessair 0:f269e3021894 317 {
elessair 0:f269e3021894 318 struct
elessair 0:f269e3021894 319 {
elessair 0:f269e3021894 320 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
elessair 0:f269e3021894 321 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
elessair 0:f269e3021894 322 } b; /*!< Structure used for bit access */
elessair 0:f269e3021894 323 uint32_t w; /*!< Type used for word access */
elessair 0:f269e3021894 324 } IPSR_Type;
elessair 0:f269e3021894 325
elessair 0:f269e3021894 326 /* IPSR Register Definitions */
elessair 0:f269e3021894 327 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
elessair 0:f269e3021894 328 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
elessair 0:f269e3021894 329
elessair 0:f269e3021894 330
elessair 0:f269e3021894 331 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
elessair 0:f269e3021894 332 */
elessair 0:f269e3021894 333 typedef union
elessair 0:f269e3021894 334 {
elessair 0:f269e3021894 335 struct
elessair 0:f269e3021894 336 {
elessair 0:f269e3021894 337 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
elessair 0:f269e3021894 338 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
elessair 0:f269e3021894 339 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
elessair 0:f269e3021894 340 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
elessair 0:f269e3021894 341 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
elessair 0:f269e3021894 342 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
elessair 0:f269e3021894 343 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
elessair 0:f269e3021894 344 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
elessair 0:f269e3021894 345 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
elessair 0:f269e3021894 346 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
elessair 0:f269e3021894 347 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
elessair 0:f269e3021894 348 } b; /*!< Structure used for bit access */
elessair 0:f269e3021894 349 uint32_t w; /*!< Type used for word access */
elessair 0:f269e3021894 350 } xPSR_Type;
elessair 0:f269e3021894 351
elessair 0:f269e3021894 352 /* xPSR Register Definitions */
elessair 0:f269e3021894 353 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
elessair 0:f269e3021894 354 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
elessair 0:f269e3021894 355
elessair 0:f269e3021894 356 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
elessair 0:f269e3021894 357 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
elessair 0:f269e3021894 358
elessair 0:f269e3021894 359 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
elessair 0:f269e3021894 360 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
elessair 0:f269e3021894 361
elessair 0:f269e3021894 362 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
elessair 0:f269e3021894 363 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
elessair 0:f269e3021894 364
elessair 0:f269e3021894 365 #define xPSR_Q_Pos 27 /*!< xPSR: Q Position */
elessair 0:f269e3021894 366 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
elessair 0:f269e3021894 367
elessair 0:f269e3021894 368 #define xPSR_IT_Pos 25 /*!< xPSR: IT Position */
elessair 0:f269e3021894 369 #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
elessair 0:f269e3021894 370
elessair 0:f269e3021894 371 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
elessair 0:f269e3021894 372 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
elessair 0:f269e3021894 373
elessair 0:f269e3021894 374 #define xPSR_GE_Pos 16 /*!< xPSR: GE Position */
elessair 0:f269e3021894 375 #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
elessair 0:f269e3021894 376
elessair 0:f269e3021894 377 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
elessair 0:f269e3021894 378 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
elessair 0:f269e3021894 379
elessair 0:f269e3021894 380
elessair 0:f269e3021894 381 /** \brief Union type to access the Control Registers (CONTROL).
elessair 0:f269e3021894 382 */
elessair 0:f269e3021894 383 typedef union
elessair 0:f269e3021894 384 {
elessair 0:f269e3021894 385 struct
elessair 0:f269e3021894 386 {
elessair 0:f269e3021894 387 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
elessair 0:f269e3021894 388 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
elessair 0:f269e3021894 389 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
elessair 0:f269e3021894 390 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
elessair 0:f269e3021894 391 } b; /*!< Structure used for bit access */
elessair 0:f269e3021894 392 uint32_t w; /*!< Type used for word access */
elessair 0:f269e3021894 393 } CONTROL_Type;
elessair 0:f269e3021894 394
elessair 0:f269e3021894 395 /* CONTROL Register Definitions */
elessair 0:f269e3021894 396 #define CONTROL_FPCA_Pos 2 /*!< CONTROL: FPCA Position */
elessair 0:f269e3021894 397 #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
elessair 0:f269e3021894 398
elessair 0:f269e3021894 399 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
elessair 0:f269e3021894 400 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
elessair 0:f269e3021894 401
elessair 0:f269e3021894 402 #define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
elessair 0:f269e3021894 403 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
elessair 0:f269e3021894 404
elessair 0:f269e3021894 405 /*@} end of group CMSIS_CORE */
elessair 0:f269e3021894 406
elessair 0:f269e3021894 407
elessair 0:f269e3021894 408 /** \ingroup CMSIS_core_register
elessair 0:f269e3021894 409 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
elessair 0:f269e3021894 410 \brief Type definitions for the NVIC Registers
elessair 0:f269e3021894 411 @{
elessair 0:f269e3021894 412 */
elessair 0:f269e3021894 413
elessair 0:f269e3021894 414 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
elessair 0:f269e3021894 415 */
elessair 0:f269e3021894 416 typedef struct
elessair 0:f269e3021894 417 {
elessair 0:f269e3021894 418 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
elessair 0:f269e3021894 419 uint32_t RESERVED0[24];
elessair 0:f269e3021894 420 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
elessair 0:f269e3021894 421 uint32_t RSERVED1[24];
elessair 0:f269e3021894 422 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
elessair 0:f269e3021894 423 uint32_t RESERVED2[24];
elessair 0:f269e3021894 424 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
elessair 0:f269e3021894 425 uint32_t RESERVED3[24];
elessair 0:f269e3021894 426 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
elessair 0:f269e3021894 427 uint32_t RESERVED4[56];
elessair 0:f269e3021894 428 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
elessair 0:f269e3021894 429 uint32_t RESERVED5[644];
elessair 0:f269e3021894 430 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
elessair 0:f269e3021894 431 } NVIC_Type;
elessair 0:f269e3021894 432
elessair 0:f269e3021894 433 /* Software Triggered Interrupt Register Definitions */
elessair 0:f269e3021894 434 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
elessair 0:f269e3021894 435 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
elessair 0:f269e3021894 436
elessair 0:f269e3021894 437 /*@} end of group CMSIS_NVIC */
elessair 0:f269e3021894 438
elessair 0:f269e3021894 439
elessair 0:f269e3021894 440 /** \ingroup CMSIS_core_register
elessair 0:f269e3021894 441 \defgroup CMSIS_SCB System Control Block (SCB)
elessair 0:f269e3021894 442 \brief Type definitions for the System Control Block Registers
elessair 0:f269e3021894 443 @{
elessair 0:f269e3021894 444 */
elessair 0:f269e3021894 445
elessair 0:f269e3021894 446 /** \brief Structure type to access the System Control Block (SCB).
elessair 0:f269e3021894 447 */
elessair 0:f269e3021894 448 typedef struct
elessair 0:f269e3021894 449 {
elessair 0:f269e3021894 450 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
elessair 0:f269e3021894 451 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
elessair 0:f269e3021894 452 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
elessair 0:f269e3021894 453 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
elessair 0:f269e3021894 454 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
elessair 0:f269e3021894 455 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
elessair 0:f269e3021894 456 __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
elessair 0:f269e3021894 457 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
elessair 0:f269e3021894 458 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
elessair 0:f269e3021894 459 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
elessair 0:f269e3021894 460 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
elessair 0:f269e3021894 461 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
elessair 0:f269e3021894 462 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
elessair 0:f269e3021894 463 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
elessair 0:f269e3021894 464 __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
elessair 0:f269e3021894 465 __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
elessair 0:f269e3021894 466 __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
elessair 0:f269e3021894 467 __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
elessair 0:f269e3021894 468 __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
elessair 0:f269e3021894 469 uint32_t RESERVED0[5];
elessair 0:f269e3021894 470 __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
elessair 0:f269e3021894 471 } SCB_Type;
elessair 0:f269e3021894 472
elessair 0:f269e3021894 473 /* SCB CPUID Register Definitions */
elessair 0:f269e3021894 474 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
elessair 0:f269e3021894 475 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
elessair 0:f269e3021894 476
elessair 0:f269e3021894 477 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
elessair 0:f269e3021894 478 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
elessair 0:f269e3021894 479
elessair 0:f269e3021894 480 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
elessair 0:f269e3021894 481 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
elessair 0:f269e3021894 482
elessair 0:f269e3021894 483 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
elessair 0:f269e3021894 484 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
elessair 0:f269e3021894 485
elessair 0:f269e3021894 486 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
elessair 0:f269e3021894 487 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
elessair 0:f269e3021894 488
elessair 0:f269e3021894 489 /* SCB Interrupt Control State Register Definitions */
elessair 0:f269e3021894 490 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
elessair 0:f269e3021894 491 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
elessair 0:f269e3021894 492
elessair 0:f269e3021894 493 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
elessair 0:f269e3021894 494 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
elessair 0:f269e3021894 495
elessair 0:f269e3021894 496 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
elessair 0:f269e3021894 497 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
elessair 0:f269e3021894 498
elessair 0:f269e3021894 499 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
elessair 0:f269e3021894 500 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
elessair 0:f269e3021894 501
elessair 0:f269e3021894 502 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
elessair 0:f269e3021894 503 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
elessair 0:f269e3021894 504
elessair 0:f269e3021894 505 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
elessair 0:f269e3021894 506 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
elessair 0:f269e3021894 507
elessair 0:f269e3021894 508 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
elessair 0:f269e3021894 509 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
elessair 0:f269e3021894 510
elessair 0:f269e3021894 511 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
elessair 0:f269e3021894 512 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
elessair 0:f269e3021894 513
elessair 0:f269e3021894 514 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
elessair 0:f269e3021894 515 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
elessair 0:f269e3021894 516
elessair 0:f269e3021894 517 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
elessair 0:f269e3021894 518 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
elessair 0:f269e3021894 519
elessair 0:f269e3021894 520 /* SCB Vector Table Offset Register Definitions */
elessair 0:f269e3021894 521 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
elessair 0:f269e3021894 522 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
elessair 0:f269e3021894 523
elessair 0:f269e3021894 524 /* SCB Application Interrupt and Reset Control Register Definitions */
elessair 0:f269e3021894 525 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
elessair 0:f269e3021894 526 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
elessair 0:f269e3021894 527
elessair 0:f269e3021894 528 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
elessair 0:f269e3021894 529 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
elessair 0:f269e3021894 530
elessair 0:f269e3021894 531 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
elessair 0:f269e3021894 532 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
elessair 0:f269e3021894 533
elessair 0:f269e3021894 534 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
elessair 0:f269e3021894 535 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
elessair 0:f269e3021894 536
elessair 0:f269e3021894 537 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
elessair 0:f269e3021894 538 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
elessair 0:f269e3021894 539
elessair 0:f269e3021894 540 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
elessair 0:f269e3021894 541 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
elessair 0:f269e3021894 542
elessair 0:f269e3021894 543 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
elessair 0:f269e3021894 544 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
elessair 0:f269e3021894 545
elessair 0:f269e3021894 546 /* SCB System Control Register Definitions */
elessair 0:f269e3021894 547 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
elessair 0:f269e3021894 548 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
elessair 0:f269e3021894 549
elessair 0:f269e3021894 550 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
elessair 0:f269e3021894 551 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
elessair 0:f269e3021894 552
elessair 0:f269e3021894 553 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
elessair 0:f269e3021894 554 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
elessair 0:f269e3021894 555
elessair 0:f269e3021894 556 /* SCB Configuration Control Register Definitions */
elessair 0:f269e3021894 557 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
elessair 0:f269e3021894 558 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
elessair 0:f269e3021894 559
elessair 0:f269e3021894 560 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
elessair 0:f269e3021894 561 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
elessair 0:f269e3021894 562
elessair 0:f269e3021894 563 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
elessair 0:f269e3021894 564 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
elessair 0:f269e3021894 565
elessair 0:f269e3021894 566 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
elessair 0:f269e3021894 567 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
elessair 0:f269e3021894 568
elessair 0:f269e3021894 569 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
elessair 0:f269e3021894 570 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
elessair 0:f269e3021894 571
elessair 0:f269e3021894 572 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
elessair 0:f269e3021894 573 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
elessair 0:f269e3021894 574
elessair 0:f269e3021894 575 /* SCB System Handler Control and State Register Definitions */
elessair 0:f269e3021894 576 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
elessair 0:f269e3021894 577 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
elessair 0:f269e3021894 578
elessair 0:f269e3021894 579 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
elessair 0:f269e3021894 580 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
elessair 0:f269e3021894 581
elessair 0:f269e3021894 582 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
elessair 0:f269e3021894 583 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
elessair 0:f269e3021894 584
elessair 0:f269e3021894 585 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
elessair 0:f269e3021894 586 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
elessair 0:f269e3021894 587
elessair 0:f269e3021894 588 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
elessair 0:f269e3021894 589 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
elessair 0:f269e3021894 590
elessair 0:f269e3021894 591 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
elessair 0:f269e3021894 592 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
elessair 0:f269e3021894 593
elessair 0:f269e3021894 594 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
elessair 0:f269e3021894 595 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
elessair 0:f269e3021894 596
elessair 0:f269e3021894 597 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
elessair 0:f269e3021894 598 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
elessair 0:f269e3021894 599
elessair 0:f269e3021894 600 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
elessair 0:f269e3021894 601 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
elessair 0:f269e3021894 602
elessair 0:f269e3021894 603 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
elessair 0:f269e3021894 604 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
elessair 0:f269e3021894 605
elessair 0:f269e3021894 606 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
elessair 0:f269e3021894 607 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
elessair 0:f269e3021894 608
elessair 0:f269e3021894 609 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
elessair 0:f269e3021894 610 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
elessair 0:f269e3021894 611
elessair 0:f269e3021894 612 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
elessair 0:f269e3021894 613 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
elessair 0:f269e3021894 614
elessair 0:f269e3021894 615 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
elessair 0:f269e3021894 616 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
elessair 0:f269e3021894 617
elessair 0:f269e3021894 618 /* SCB Configurable Fault Status Registers Definitions */
elessair 0:f269e3021894 619 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
elessair 0:f269e3021894 620 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
elessair 0:f269e3021894 621
elessair 0:f269e3021894 622 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
elessair 0:f269e3021894 623 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
elessair 0:f269e3021894 624
elessair 0:f269e3021894 625 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
elessair 0:f269e3021894 626 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
elessair 0:f269e3021894 627
elessair 0:f269e3021894 628 /* SCB Hard Fault Status Registers Definitions */
elessair 0:f269e3021894 629 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
elessair 0:f269e3021894 630 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
elessair 0:f269e3021894 631
elessair 0:f269e3021894 632 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
elessair 0:f269e3021894 633 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
elessair 0:f269e3021894 634
elessair 0:f269e3021894 635 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
elessair 0:f269e3021894 636 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
elessair 0:f269e3021894 637
elessair 0:f269e3021894 638 /* SCB Debug Fault Status Register Definitions */
elessair 0:f269e3021894 639 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
elessair 0:f269e3021894 640 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
elessair 0:f269e3021894 641
elessair 0:f269e3021894 642 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
elessair 0:f269e3021894 643 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
elessair 0:f269e3021894 644
elessair 0:f269e3021894 645 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
elessair 0:f269e3021894 646 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
elessair 0:f269e3021894 647
elessair 0:f269e3021894 648 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
elessair 0:f269e3021894 649 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
elessair 0:f269e3021894 650
elessair 0:f269e3021894 651 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
elessair 0:f269e3021894 652 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
elessair 0:f269e3021894 653
elessair 0:f269e3021894 654 /*@} end of group CMSIS_SCB */
elessair 0:f269e3021894 655
elessair 0:f269e3021894 656
elessair 0:f269e3021894 657 /** \ingroup CMSIS_core_register
elessair 0:f269e3021894 658 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
elessair 0:f269e3021894 659 \brief Type definitions for the System Control and ID Register not in the SCB
elessair 0:f269e3021894 660 @{
elessair 0:f269e3021894 661 */
elessair 0:f269e3021894 662
elessair 0:f269e3021894 663 /** \brief Structure type to access the System Control and ID Register not in the SCB.
elessair 0:f269e3021894 664 */
elessair 0:f269e3021894 665 typedef struct
elessair 0:f269e3021894 666 {
elessair 0:f269e3021894 667 uint32_t RESERVED0[1];
elessair 0:f269e3021894 668 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
elessair 0:f269e3021894 669 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
elessair 0:f269e3021894 670 } SCnSCB_Type;
elessair 0:f269e3021894 671
elessair 0:f269e3021894 672 /* Interrupt Controller Type Register Definitions */
elessair 0:f269e3021894 673 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
elessair 0:f269e3021894 674 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
elessair 0:f269e3021894 675
elessair 0:f269e3021894 676 /* Auxiliary Control Register Definitions */
elessair 0:f269e3021894 677 #define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */
elessair 0:f269e3021894 678 #define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
elessair 0:f269e3021894 679
elessair 0:f269e3021894 680 #define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */
elessair 0:f269e3021894 681 #define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
elessair 0:f269e3021894 682
elessair 0:f269e3021894 683 #define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
elessair 0:f269e3021894 684 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
elessair 0:f269e3021894 685
elessair 0:f269e3021894 686 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
elessair 0:f269e3021894 687 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
elessair 0:f269e3021894 688
elessair 0:f269e3021894 689 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
elessair 0:f269e3021894 690 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
elessair 0:f269e3021894 691
elessair 0:f269e3021894 692 /*@} end of group CMSIS_SCnotSCB */
elessair 0:f269e3021894 693
elessair 0:f269e3021894 694
elessair 0:f269e3021894 695 /** \ingroup CMSIS_core_register
elessair 0:f269e3021894 696 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
elessair 0:f269e3021894 697 \brief Type definitions for the System Timer Registers.
elessair 0:f269e3021894 698 @{
elessair 0:f269e3021894 699 */
elessair 0:f269e3021894 700
elessair 0:f269e3021894 701 /** \brief Structure type to access the System Timer (SysTick).
elessair 0:f269e3021894 702 */
elessair 0:f269e3021894 703 typedef struct
elessair 0:f269e3021894 704 {
elessair 0:f269e3021894 705 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
elessair 0:f269e3021894 706 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
elessair 0:f269e3021894 707 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
elessair 0:f269e3021894 708 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
elessair 0:f269e3021894 709 } SysTick_Type;
elessair 0:f269e3021894 710
elessair 0:f269e3021894 711 /* SysTick Control / Status Register Definitions */
elessair 0:f269e3021894 712 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
elessair 0:f269e3021894 713 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
elessair 0:f269e3021894 714
elessair 0:f269e3021894 715 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
elessair 0:f269e3021894 716 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
elessair 0:f269e3021894 717
elessair 0:f269e3021894 718 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
elessair 0:f269e3021894 719 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
elessair 0:f269e3021894 720
elessair 0:f269e3021894 721 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
elessair 0:f269e3021894 722 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
elessair 0:f269e3021894 723
elessair 0:f269e3021894 724 /* SysTick Reload Register Definitions */
elessair 0:f269e3021894 725 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
elessair 0:f269e3021894 726 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
elessair 0:f269e3021894 727
elessair 0:f269e3021894 728 /* SysTick Current Register Definitions */
elessair 0:f269e3021894 729 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
elessair 0:f269e3021894 730 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
elessair 0:f269e3021894 731
elessair 0:f269e3021894 732 /* SysTick Calibration Register Definitions */
elessair 0:f269e3021894 733 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
elessair 0:f269e3021894 734 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
elessair 0:f269e3021894 735
elessair 0:f269e3021894 736 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
elessair 0:f269e3021894 737 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
elessair 0:f269e3021894 738
elessair 0:f269e3021894 739 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
elessair 0:f269e3021894 740 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
elessair 0:f269e3021894 741
elessair 0:f269e3021894 742 /*@} end of group CMSIS_SysTick */
elessair 0:f269e3021894 743
elessair 0:f269e3021894 744
elessair 0:f269e3021894 745 /** \ingroup CMSIS_core_register
elessair 0:f269e3021894 746 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
elessair 0:f269e3021894 747 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
elessair 0:f269e3021894 748 @{
elessair 0:f269e3021894 749 */
elessair 0:f269e3021894 750
elessair 0:f269e3021894 751 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
elessair 0:f269e3021894 752 */
elessair 0:f269e3021894 753 typedef struct
elessair 0:f269e3021894 754 {
elessair 0:f269e3021894 755 __O union
elessair 0:f269e3021894 756 {
elessair 0:f269e3021894 757 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
elessair 0:f269e3021894 758 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
elessair 0:f269e3021894 759 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
elessair 0:f269e3021894 760 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
elessair 0:f269e3021894 761 uint32_t RESERVED0[864];
elessair 0:f269e3021894 762 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
elessair 0:f269e3021894 763 uint32_t RESERVED1[15];
elessair 0:f269e3021894 764 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
elessair 0:f269e3021894 765 uint32_t RESERVED2[15];
elessair 0:f269e3021894 766 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
elessair 0:f269e3021894 767 uint32_t RESERVED3[29];
elessair 0:f269e3021894 768 __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
elessair 0:f269e3021894 769 __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
elessair 0:f269e3021894 770 __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
elessair 0:f269e3021894 771 uint32_t RESERVED4[43];
elessair 0:f269e3021894 772 __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
elessair 0:f269e3021894 773 __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
elessair 0:f269e3021894 774 uint32_t RESERVED5[6];
elessair 0:f269e3021894 775 __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
elessair 0:f269e3021894 776 __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
elessair 0:f269e3021894 777 __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
elessair 0:f269e3021894 778 __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
elessair 0:f269e3021894 779 __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
elessair 0:f269e3021894 780 __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
elessair 0:f269e3021894 781 __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
elessair 0:f269e3021894 782 __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
elessair 0:f269e3021894 783 __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
elessair 0:f269e3021894 784 __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
elessair 0:f269e3021894 785 __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
elessair 0:f269e3021894 786 __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
elessair 0:f269e3021894 787 } ITM_Type;
elessair 0:f269e3021894 788
elessair 0:f269e3021894 789 /* ITM Trace Privilege Register Definitions */
elessair 0:f269e3021894 790 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
elessair 0:f269e3021894 791 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
elessair 0:f269e3021894 792
elessair 0:f269e3021894 793 /* ITM Trace Control Register Definitions */
elessair 0:f269e3021894 794 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
elessair 0:f269e3021894 795 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
elessair 0:f269e3021894 796
elessair 0:f269e3021894 797 #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
elessair 0:f269e3021894 798 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
elessair 0:f269e3021894 799
elessair 0:f269e3021894 800 #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
elessair 0:f269e3021894 801 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
elessair 0:f269e3021894 802
elessair 0:f269e3021894 803 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
elessair 0:f269e3021894 804 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
elessair 0:f269e3021894 805
elessair 0:f269e3021894 806 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
elessair 0:f269e3021894 807 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
elessair 0:f269e3021894 808
elessair 0:f269e3021894 809 #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
elessair 0:f269e3021894 810 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
elessair 0:f269e3021894 811
elessair 0:f269e3021894 812 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
elessair 0:f269e3021894 813 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
elessair 0:f269e3021894 814
elessair 0:f269e3021894 815 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
elessair 0:f269e3021894 816 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
elessair 0:f269e3021894 817
elessair 0:f269e3021894 818 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
elessair 0:f269e3021894 819 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
elessair 0:f269e3021894 820
elessair 0:f269e3021894 821 /* ITM Integration Write Register Definitions */
elessair 0:f269e3021894 822 #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
elessair 0:f269e3021894 823 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
elessair 0:f269e3021894 824
elessair 0:f269e3021894 825 /* ITM Integration Read Register Definitions */
elessair 0:f269e3021894 826 #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
elessair 0:f269e3021894 827 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
elessair 0:f269e3021894 828
elessair 0:f269e3021894 829 /* ITM Integration Mode Control Register Definitions */
elessair 0:f269e3021894 830 #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
elessair 0:f269e3021894 831 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
elessair 0:f269e3021894 832
elessair 0:f269e3021894 833 /* ITM Lock Status Register Definitions */
elessair 0:f269e3021894 834 #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
elessair 0:f269e3021894 835 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
elessair 0:f269e3021894 836
elessair 0:f269e3021894 837 #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
elessair 0:f269e3021894 838 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
elessair 0:f269e3021894 839
elessair 0:f269e3021894 840 #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
elessair 0:f269e3021894 841 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
elessair 0:f269e3021894 842
elessair 0:f269e3021894 843 /*@}*/ /* end of group CMSIS_ITM */
elessair 0:f269e3021894 844
elessair 0:f269e3021894 845
elessair 0:f269e3021894 846 /** \ingroup CMSIS_core_register
elessair 0:f269e3021894 847 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
elessair 0:f269e3021894 848 \brief Type definitions for the Data Watchpoint and Trace (DWT)
elessair 0:f269e3021894 849 @{
elessair 0:f269e3021894 850 */
elessair 0:f269e3021894 851
elessair 0:f269e3021894 852 /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
elessair 0:f269e3021894 853 */
elessair 0:f269e3021894 854 typedef struct
elessair 0:f269e3021894 855 {
elessair 0:f269e3021894 856 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
elessair 0:f269e3021894 857 __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
elessair 0:f269e3021894 858 __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
elessair 0:f269e3021894 859 __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
elessair 0:f269e3021894 860 __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
elessair 0:f269e3021894 861 __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
elessair 0:f269e3021894 862 __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
elessair 0:f269e3021894 863 __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
elessair 0:f269e3021894 864 __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
elessair 0:f269e3021894 865 __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
elessair 0:f269e3021894 866 __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
elessair 0:f269e3021894 867 uint32_t RESERVED0[1];
elessair 0:f269e3021894 868 __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
elessair 0:f269e3021894 869 __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
elessair 0:f269e3021894 870 __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
elessair 0:f269e3021894 871 uint32_t RESERVED1[1];
elessair 0:f269e3021894 872 __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
elessair 0:f269e3021894 873 __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
elessair 0:f269e3021894 874 __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
elessair 0:f269e3021894 875 uint32_t RESERVED2[1];
elessair 0:f269e3021894 876 __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
elessair 0:f269e3021894 877 __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
elessair 0:f269e3021894 878 __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
elessair 0:f269e3021894 879 } DWT_Type;
elessair 0:f269e3021894 880
elessair 0:f269e3021894 881 /* DWT Control Register Definitions */
elessair 0:f269e3021894 882 #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
elessair 0:f269e3021894 883 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
elessair 0:f269e3021894 884
elessair 0:f269e3021894 885 #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
elessair 0:f269e3021894 886 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
elessair 0:f269e3021894 887
elessair 0:f269e3021894 888 #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
elessair 0:f269e3021894 889 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
elessair 0:f269e3021894 890
elessair 0:f269e3021894 891 #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
elessair 0:f269e3021894 892 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
elessair 0:f269e3021894 893
elessair 0:f269e3021894 894 #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
elessair 0:f269e3021894 895 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
elessair 0:f269e3021894 896
elessair 0:f269e3021894 897 #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
elessair 0:f269e3021894 898 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
elessair 0:f269e3021894 899
elessair 0:f269e3021894 900 #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
elessair 0:f269e3021894 901 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
elessair 0:f269e3021894 902
elessair 0:f269e3021894 903 #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
elessair 0:f269e3021894 904 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
elessair 0:f269e3021894 905
elessair 0:f269e3021894 906 #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
elessair 0:f269e3021894 907 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
elessair 0:f269e3021894 908
elessair 0:f269e3021894 909 #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
elessair 0:f269e3021894 910 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
elessair 0:f269e3021894 911
elessair 0:f269e3021894 912 #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
elessair 0:f269e3021894 913 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
elessair 0:f269e3021894 914
elessair 0:f269e3021894 915 #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
elessair 0:f269e3021894 916 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
elessair 0:f269e3021894 917
elessair 0:f269e3021894 918 #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
elessair 0:f269e3021894 919 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
elessair 0:f269e3021894 920
elessair 0:f269e3021894 921 #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
elessair 0:f269e3021894 922 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
elessair 0:f269e3021894 923
elessair 0:f269e3021894 924 #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
elessair 0:f269e3021894 925 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
elessair 0:f269e3021894 926
elessair 0:f269e3021894 927 #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
elessair 0:f269e3021894 928 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
elessair 0:f269e3021894 929
elessair 0:f269e3021894 930 #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
elessair 0:f269e3021894 931 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
elessair 0:f269e3021894 932
elessair 0:f269e3021894 933 #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
elessair 0:f269e3021894 934 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
elessair 0:f269e3021894 935
elessair 0:f269e3021894 936 /* DWT CPI Count Register Definitions */
elessair 0:f269e3021894 937 #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
elessair 0:f269e3021894 938 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
elessair 0:f269e3021894 939
elessair 0:f269e3021894 940 /* DWT Exception Overhead Count Register Definitions */
elessair 0:f269e3021894 941 #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
elessair 0:f269e3021894 942 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
elessair 0:f269e3021894 943
elessair 0:f269e3021894 944 /* DWT Sleep Count Register Definitions */
elessair 0:f269e3021894 945 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
elessair 0:f269e3021894 946 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
elessair 0:f269e3021894 947
elessair 0:f269e3021894 948 /* DWT LSU Count Register Definitions */
elessair 0:f269e3021894 949 #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
elessair 0:f269e3021894 950 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
elessair 0:f269e3021894 951
elessair 0:f269e3021894 952 /* DWT Folded-instruction Count Register Definitions */
elessair 0:f269e3021894 953 #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
elessair 0:f269e3021894 954 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
elessair 0:f269e3021894 955
elessair 0:f269e3021894 956 /* DWT Comparator Mask Register Definitions */
elessair 0:f269e3021894 957 #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
elessair 0:f269e3021894 958 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
elessair 0:f269e3021894 959
elessair 0:f269e3021894 960 /* DWT Comparator Function Register Definitions */
elessair 0:f269e3021894 961 #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
elessair 0:f269e3021894 962 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
elessair 0:f269e3021894 963
elessair 0:f269e3021894 964 #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
elessair 0:f269e3021894 965 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
elessair 0:f269e3021894 966
elessair 0:f269e3021894 967 #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
elessair 0:f269e3021894 968 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
elessair 0:f269e3021894 969
elessair 0:f269e3021894 970 #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
elessair 0:f269e3021894 971 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
elessair 0:f269e3021894 972
elessair 0:f269e3021894 973 #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
elessair 0:f269e3021894 974 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
elessair 0:f269e3021894 975
elessair 0:f269e3021894 976 #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
elessair 0:f269e3021894 977 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
elessair 0:f269e3021894 978
elessair 0:f269e3021894 979 #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
elessair 0:f269e3021894 980 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
elessair 0:f269e3021894 981
elessair 0:f269e3021894 982 #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
elessair 0:f269e3021894 983 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
elessair 0:f269e3021894 984
elessair 0:f269e3021894 985 #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
elessair 0:f269e3021894 986 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
elessair 0:f269e3021894 987
elessair 0:f269e3021894 988 /*@}*/ /* end of group CMSIS_DWT */
elessair 0:f269e3021894 989
elessair 0:f269e3021894 990
elessair 0:f269e3021894 991 /** \ingroup CMSIS_core_register
elessair 0:f269e3021894 992 \defgroup CMSIS_TPI Trace Port Interface (TPI)
elessair 0:f269e3021894 993 \brief Type definitions for the Trace Port Interface (TPI)
elessair 0:f269e3021894 994 @{
elessair 0:f269e3021894 995 */
elessair 0:f269e3021894 996
elessair 0:f269e3021894 997 /** \brief Structure type to access the Trace Port Interface Register (TPI).
elessair 0:f269e3021894 998 */
elessair 0:f269e3021894 999 typedef struct
elessair 0:f269e3021894 1000 {
elessair 0:f269e3021894 1001 __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
elessair 0:f269e3021894 1002 __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
elessair 0:f269e3021894 1003 uint32_t RESERVED0[2];
elessair 0:f269e3021894 1004 __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
elessair 0:f269e3021894 1005 uint32_t RESERVED1[55];
elessair 0:f269e3021894 1006 __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
elessair 0:f269e3021894 1007 uint32_t RESERVED2[131];
elessair 0:f269e3021894 1008 __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
elessair 0:f269e3021894 1009 __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
elessair 0:f269e3021894 1010 __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
elessair 0:f269e3021894 1011 uint32_t RESERVED3[759];
elessair 0:f269e3021894 1012 __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
elessair 0:f269e3021894 1013 __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
elessair 0:f269e3021894 1014 __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
elessair 0:f269e3021894 1015 uint32_t RESERVED4[1];
elessair 0:f269e3021894 1016 __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
elessair 0:f269e3021894 1017 __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
elessair 0:f269e3021894 1018 __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
elessair 0:f269e3021894 1019 uint32_t RESERVED5[39];
elessair 0:f269e3021894 1020 __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
elessair 0:f269e3021894 1021 __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
elessair 0:f269e3021894 1022 uint32_t RESERVED7[8];
elessair 0:f269e3021894 1023 __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
elessair 0:f269e3021894 1024 __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
elessair 0:f269e3021894 1025 } TPI_Type;
elessair 0:f269e3021894 1026
elessair 0:f269e3021894 1027 /* TPI Asynchronous Clock Prescaler Register Definitions */
elessair 0:f269e3021894 1028 #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
elessair 0:f269e3021894 1029 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
elessair 0:f269e3021894 1030
elessair 0:f269e3021894 1031 /* TPI Selected Pin Protocol Register Definitions */
elessair 0:f269e3021894 1032 #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
elessair 0:f269e3021894 1033 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
elessair 0:f269e3021894 1034
elessair 0:f269e3021894 1035 /* TPI Formatter and Flush Status Register Definitions */
elessair 0:f269e3021894 1036 #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
elessair 0:f269e3021894 1037 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
elessair 0:f269e3021894 1038
elessair 0:f269e3021894 1039 #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
elessair 0:f269e3021894 1040 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
elessair 0:f269e3021894 1041
elessair 0:f269e3021894 1042 #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
elessair 0:f269e3021894 1043 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
elessair 0:f269e3021894 1044
elessair 0:f269e3021894 1045 #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
elessair 0:f269e3021894 1046 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
elessair 0:f269e3021894 1047
elessair 0:f269e3021894 1048 /* TPI Formatter and Flush Control Register Definitions */
elessair 0:f269e3021894 1049 #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
elessair 0:f269e3021894 1050 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
elessair 0:f269e3021894 1051
elessair 0:f269e3021894 1052 #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
elessair 0:f269e3021894 1053 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
elessair 0:f269e3021894 1054
elessair 0:f269e3021894 1055 /* TPI TRIGGER Register Definitions */
elessair 0:f269e3021894 1056 #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
elessair 0:f269e3021894 1057 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
elessair 0:f269e3021894 1058
elessair 0:f269e3021894 1059 /* TPI Integration ETM Data Register Definitions (FIFO0) */
elessair 0:f269e3021894 1060 #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
elessair 0:f269e3021894 1061 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
elessair 0:f269e3021894 1062
elessair 0:f269e3021894 1063 #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
elessair 0:f269e3021894 1064 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
elessair 0:f269e3021894 1065
elessair 0:f269e3021894 1066 #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
elessair 0:f269e3021894 1067 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
elessair 0:f269e3021894 1068
elessair 0:f269e3021894 1069 #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
elessair 0:f269e3021894 1070 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
elessair 0:f269e3021894 1071
elessair 0:f269e3021894 1072 #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
elessair 0:f269e3021894 1073 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
elessair 0:f269e3021894 1074
elessair 0:f269e3021894 1075 #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
elessair 0:f269e3021894 1076 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
elessair 0:f269e3021894 1077
elessair 0:f269e3021894 1078 #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
elessair 0:f269e3021894 1079 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
elessair 0:f269e3021894 1080
elessair 0:f269e3021894 1081 /* TPI ITATBCTR2 Register Definitions */
elessair 0:f269e3021894 1082 #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
elessair 0:f269e3021894 1083 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
elessair 0:f269e3021894 1084
elessair 0:f269e3021894 1085 /* TPI Integration ITM Data Register Definitions (FIFO1) */
elessair 0:f269e3021894 1086 #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
elessair 0:f269e3021894 1087 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
elessair 0:f269e3021894 1088
elessair 0:f269e3021894 1089 #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
elessair 0:f269e3021894 1090 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
elessair 0:f269e3021894 1091
elessair 0:f269e3021894 1092 #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
elessair 0:f269e3021894 1093 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
elessair 0:f269e3021894 1094
elessair 0:f269e3021894 1095 #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
elessair 0:f269e3021894 1096 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
elessair 0:f269e3021894 1097
elessair 0:f269e3021894 1098 #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
elessair 0:f269e3021894 1099 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
elessair 0:f269e3021894 1100
elessair 0:f269e3021894 1101 #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
elessair 0:f269e3021894 1102 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
elessair 0:f269e3021894 1103
elessair 0:f269e3021894 1104 #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
elessair 0:f269e3021894 1105 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
elessair 0:f269e3021894 1106
elessair 0:f269e3021894 1107 /* TPI ITATBCTR0 Register Definitions */
elessair 0:f269e3021894 1108 #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
elessair 0:f269e3021894 1109 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
elessair 0:f269e3021894 1110
elessair 0:f269e3021894 1111 /* TPI Integration Mode Control Register Definitions */
elessair 0:f269e3021894 1112 #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
elessair 0:f269e3021894 1113 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
elessair 0:f269e3021894 1114
elessair 0:f269e3021894 1115 /* TPI DEVID Register Definitions */
elessair 0:f269e3021894 1116 #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
elessair 0:f269e3021894 1117 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
elessair 0:f269e3021894 1118
elessair 0:f269e3021894 1119 #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
elessair 0:f269e3021894 1120 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
elessair 0:f269e3021894 1121
elessair 0:f269e3021894 1122 #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
elessair 0:f269e3021894 1123 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
elessair 0:f269e3021894 1124
elessair 0:f269e3021894 1125 #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
elessair 0:f269e3021894 1126 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
elessair 0:f269e3021894 1127
elessair 0:f269e3021894 1128 #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
elessair 0:f269e3021894 1129 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
elessair 0:f269e3021894 1130
elessair 0:f269e3021894 1131 #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
elessair 0:f269e3021894 1132 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
elessair 0:f269e3021894 1133
elessair 0:f269e3021894 1134 /* TPI DEVTYPE Register Definitions */
elessair 0:f269e3021894 1135 #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
elessair 0:f269e3021894 1136 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
elessair 0:f269e3021894 1137
elessair 0:f269e3021894 1138 #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
elessair 0:f269e3021894 1139 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
elessair 0:f269e3021894 1140
elessair 0:f269e3021894 1141 /*@}*/ /* end of group CMSIS_TPI */
elessair 0:f269e3021894 1142
elessair 0:f269e3021894 1143
elessair 0:f269e3021894 1144 #if (__MPU_PRESENT == 1)
elessair 0:f269e3021894 1145 /** \ingroup CMSIS_core_register
elessair 0:f269e3021894 1146 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
elessair 0:f269e3021894 1147 \brief Type definitions for the Memory Protection Unit (MPU)
elessair 0:f269e3021894 1148 @{
elessair 0:f269e3021894 1149 */
elessair 0:f269e3021894 1150
elessair 0:f269e3021894 1151 /** \brief Structure type to access the Memory Protection Unit (MPU).
elessair 0:f269e3021894 1152 */
elessair 0:f269e3021894 1153 typedef struct
elessair 0:f269e3021894 1154 {
elessair 0:f269e3021894 1155 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
elessair 0:f269e3021894 1156 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
elessair 0:f269e3021894 1157 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
elessair 0:f269e3021894 1158 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
elessair 0:f269e3021894 1159 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
elessair 0:f269e3021894 1160 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
elessair 0:f269e3021894 1161 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
elessair 0:f269e3021894 1162 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
elessair 0:f269e3021894 1163 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
elessair 0:f269e3021894 1164 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
elessair 0:f269e3021894 1165 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
elessair 0:f269e3021894 1166 } MPU_Type;
elessair 0:f269e3021894 1167
elessair 0:f269e3021894 1168 /* MPU Type Register */
elessair 0:f269e3021894 1169 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
elessair 0:f269e3021894 1170 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
elessair 0:f269e3021894 1171
elessair 0:f269e3021894 1172 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
elessair 0:f269e3021894 1173 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
elessair 0:f269e3021894 1174
elessair 0:f269e3021894 1175 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
elessair 0:f269e3021894 1176 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
elessair 0:f269e3021894 1177
elessair 0:f269e3021894 1178 /* MPU Control Register */
elessair 0:f269e3021894 1179 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
elessair 0:f269e3021894 1180 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
elessair 0:f269e3021894 1181
elessair 0:f269e3021894 1182 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
elessair 0:f269e3021894 1183 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
elessair 0:f269e3021894 1184
elessair 0:f269e3021894 1185 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
elessair 0:f269e3021894 1186 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
elessair 0:f269e3021894 1187
elessair 0:f269e3021894 1188 /* MPU Region Number Register */
elessair 0:f269e3021894 1189 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
elessair 0:f269e3021894 1190 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
elessair 0:f269e3021894 1191
elessair 0:f269e3021894 1192 /* MPU Region Base Address Register */
elessair 0:f269e3021894 1193 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
elessair 0:f269e3021894 1194 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
elessair 0:f269e3021894 1195
elessair 0:f269e3021894 1196 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
elessair 0:f269e3021894 1197 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
elessair 0:f269e3021894 1198
elessair 0:f269e3021894 1199 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
elessair 0:f269e3021894 1200 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
elessair 0:f269e3021894 1201
elessair 0:f269e3021894 1202 /* MPU Region Attribute and Size Register */
elessair 0:f269e3021894 1203 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
elessair 0:f269e3021894 1204 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
elessair 0:f269e3021894 1205
elessair 0:f269e3021894 1206 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
elessair 0:f269e3021894 1207 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
elessair 0:f269e3021894 1208
elessair 0:f269e3021894 1209 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
elessair 0:f269e3021894 1210 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
elessair 0:f269e3021894 1211
elessair 0:f269e3021894 1212 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
elessair 0:f269e3021894 1213 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
elessair 0:f269e3021894 1214
elessair 0:f269e3021894 1215 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
elessair 0:f269e3021894 1216 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
elessair 0:f269e3021894 1217
elessair 0:f269e3021894 1218 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
elessair 0:f269e3021894 1219 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
elessair 0:f269e3021894 1220
elessair 0:f269e3021894 1221 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
elessair 0:f269e3021894 1222 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
elessair 0:f269e3021894 1223
elessair 0:f269e3021894 1224 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
elessair 0:f269e3021894 1225 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
elessair 0:f269e3021894 1226
elessair 0:f269e3021894 1227 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
elessair 0:f269e3021894 1228 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
elessair 0:f269e3021894 1229
elessair 0:f269e3021894 1230 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
elessair 0:f269e3021894 1231 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
elessair 0:f269e3021894 1232
elessair 0:f269e3021894 1233 /*@} end of group CMSIS_MPU */
elessair 0:f269e3021894 1234 #endif
elessair 0:f269e3021894 1235
elessair 0:f269e3021894 1236
elessair 0:f269e3021894 1237 #if (__FPU_PRESENT == 1)
elessair 0:f269e3021894 1238 /** \ingroup CMSIS_core_register
elessair 0:f269e3021894 1239 \defgroup CMSIS_FPU Floating Point Unit (FPU)
elessair 0:f269e3021894 1240 \brief Type definitions for the Floating Point Unit (FPU)
elessair 0:f269e3021894 1241 @{
elessair 0:f269e3021894 1242 */
elessair 0:f269e3021894 1243
elessair 0:f269e3021894 1244 /** \brief Structure type to access the Floating Point Unit (FPU).
elessair 0:f269e3021894 1245 */
elessair 0:f269e3021894 1246 typedef struct
elessair 0:f269e3021894 1247 {
elessair 0:f269e3021894 1248 uint32_t RESERVED0[1];
elessair 0:f269e3021894 1249 __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
elessair 0:f269e3021894 1250 __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
elessair 0:f269e3021894 1251 __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
elessair 0:f269e3021894 1252 __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
elessair 0:f269e3021894 1253 __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
elessair 0:f269e3021894 1254 } FPU_Type;
elessair 0:f269e3021894 1255
elessair 0:f269e3021894 1256 /* Floating-Point Context Control Register */
elessair 0:f269e3021894 1257 #define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */
elessair 0:f269e3021894 1258 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
elessair 0:f269e3021894 1259
elessair 0:f269e3021894 1260 #define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */
elessair 0:f269e3021894 1261 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
elessair 0:f269e3021894 1262
elessair 0:f269e3021894 1263 #define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */
elessair 0:f269e3021894 1264 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
elessair 0:f269e3021894 1265
elessair 0:f269e3021894 1266 #define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */
elessair 0:f269e3021894 1267 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
elessair 0:f269e3021894 1268
elessair 0:f269e3021894 1269 #define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */
elessair 0:f269e3021894 1270 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
elessair 0:f269e3021894 1271
elessair 0:f269e3021894 1272 #define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */
elessair 0:f269e3021894 1273 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
elessair 0:f269e3021894 1274
elessair 0:f269e3021894 1275 #define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */
elessair 0:f269e3021894 1276 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
elessair 0:f269e3021894 1277
elessair 0:f269e3021894 1278 #define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */
elessair 0:f269e3021894 1279 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
elessair 0:f269e3021894 1280
elessair 0:f269e3021894 1281 #define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */
elessair 0:f269e3021894 1282 #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
elessair 0:f269e3021894 1283
elessair 0:f269e3021894 1284 /* Floating-Point Context Address Register */
elessair 0:f269e3021894 1285 #define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */
elessair 0:f269e3021894 1286 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
elessair 0:f269e3021894 1287
elessair 0:f269e3021894 1288 /* Floating-Point Default Status Control Register */
elessair 0:f269e3021894 1289 #define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */
elessair 0:f269e3021894 1290 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
elessair 0:f269e3021894 1291
elessair 0:f269e3021894 1292 #define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */
elessair 0:f269e3021894 1293 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
elessair 0:f269e3021894 1294
elessair 0:f269e3021894 1295 #define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */
elessair 0:f269e3021894 1296 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
elessair 0:f269e3021894 1297
elessair 0:f269e3021894 1298 #define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */
elessair 0:f269e3021894 1299 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
elessair 0:f269e3021894 1300
elessair 0:f269e3021894 1301 /* Media and FP Feature Register 0 */
elessair 0:f269e3021894 1302 #define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */
elessair 0:f269e3021894 1303 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
elessair 0:f269e3021894 1304
elessair 0:f269e3021894 1305 #define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */
elessair 0:f269e3021894 1306 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
elessair 0:f269e3021894 1307
elessair 0:f269e3021894 1308 #define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */
elessair 0:f269e3021894 1309 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
elessair 0:f269e3021894 1310
elessair 0:f269e3021894 1311 #define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */
elessair 0:f269e3021894 1312 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
elessair 0:f269e3021894 1313
elessair 0:f269e3021894 1314 #define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */
elessair 0:f269e3021894 1315 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
elessair 0:f269e3021894 1316
elessair 0:f269e3021894 1317 #define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */
elessair 0:f269e3021894 1318 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
elessair 0:f269e3021894 1319
elessair 0:f269e3021894 1320 #define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */
elessair 0:f269e3021894 1321 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
elessair 0:f269e3021894 1322
elessair 0:f269e3021894 1323 #define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */
elessair 0:f269e3021894 1324 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
elessair 0:f269e3021894 1325
elessair 0:f269e3021894 1326 /* Media and FP Feature Register 1 */
elessair 0:f269e3021894 1327 #define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */
elessair 0:f269e3021894 1328 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
elessair 0:f269e3021894 1329
elessair 0:f269e3021894 1330 #define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */
elessair 0:f269e3021894 1331 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
elessair 0:f269e3021894 1332
elessair 0:f269e3021894 1333 #define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */
elessair 0:f269e3021894 1334 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
elessair 0:f269e3021894 1335
elessair 0:f269e3021894 1336 #define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */
elessair 0:f269e3021894 1337 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
elessair 0:f269e3021894 1338
elessair 0:f269e3021894 1339 /*@} end of group CMSIS_FPU */
elessair 0:f269e3021894 1340 #endif
elessair 0:f269e3021894 1341
elessair 0:f269e3021894 1342
elessair 0:f269e3021894 1343 /** \ingroup CMSIS_core_register
elessair 0:f269e3021894 1344 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
elessair 0:f269e3021894 1345 \brief Type definitions for the Core Debug Registers
elessair 0:f269e3021894 1346 @{
elessair 0:f269e3021894 1347 */
elessair 0:f269e3021894 1348
elessair 0:f269e3021894 1349 /** \brief Structure type to access the Core Debug Register (CoreDebug).
elessair 0:f269e3021894 1350 */
elessair 0:f269e3021894 1351 typedef struct
elessair 0:f269e3021894 1352 {
elessair 0:f269e3021894 1353 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
elessair 0:f269e3021894 1354 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
elessair 0:f269e3021894 1355 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
elessair 0:f269e3021894 1356 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
elessair 0:f269e3021894 1357 } CoreDebug_Type;
elessair 0:f269e3021894 1358
elessair 0:f269e3021894 1359 /* Debug Halting Control and Status Register */
elessair 0:f269e3021894 1360 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
elessair 0:f269e3021894 1361 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
elessair 0:f269e3021894 1362
elessair 0:f269e3021894 1363 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
elessair 0:f269e3021894 1364 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
elessair 0:f269e3021894 1365
elessair 0:f269e3021894 1366 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
elessair 0:f269e3021894 1367 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
elessair 0:f269e3021894 1368
elessair 0:f269e3021894 1369 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
elessair 0:f269e3021894 1370 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
elessair 0:f269e3021894 1371
elessair 0:f269e3021894 1372 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
elessair 0:f269e3021894 1373 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
elessair 0:f269e3021894 1374
elessair 0:f269e3021894 1375 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
elessair 0:f269e3021894 1376 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
elessair 0:f269e3021894 1377
elessair 0:f269e3021894 1378 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
elessair 0:f269e3021894 1379 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
elessair 0:f269e3021894 1380
elessair 0:f269e3021894 1381 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
elessair 0:f269e3021894 1382 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
elessair 0:f269e3021894 1383
elessair 0:f269e3021894 1384 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
elessair 0:f269e3021894 1385 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
elessair 0:f269e3021894 1386
elessair 0:f269e3021894 1387 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
elessair 0:f269e3021894 1388 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
elessair 0:f269e3021894 1389
elessair 0:f269e3021894 1390 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
elessair 0:f269e3021894 1391 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
elessair 0:f269e3021894 1392
elessair 0:f269e3021894 1393 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
elessair 0:f269e3021894 1394 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
elessair 0:f269e3021894 1395
elessair 0:f269e3021894 1396 /* Debug Core Register Selector Register */
elessair 0:f269e3021894 1397 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
elessair 0:f269e3021894 1398 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
elessair 0:f269e3021894 1399
elessair 0:f269e3021894 1400 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
elessair 0:f269e3021894 1401 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
elessair 0:f269e3021894 1402
elessair 0:f269e3021894 1403 /* Debug Exception and Monitor Control Register */
elessair 0:f269e3021894 1404 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
elessair 0:f269e3021894 1405 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
elessair 0:f269e3021894 1406
elessair 0:f269e3021894 1407 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
elessair 0:f269e3021894 1408 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
elessair 0:f269e3021894 1409
elessair 0:f269e3021894 1410 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
elessair 0:f269e3021894 1411 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
elessair 0:f269e3021894 1412
elessair 0:f269e3021894 1413 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
elessair 0:f269e3021894 1414 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
elessair 0:f269e3021894 1415
elessair 0:f269e3021894 1416 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
elessair 0:f269e3021894 1417 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
elessair 0:f269e3021894 1418
elessair 0:f269e3021894 1419 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
elessair 0:f269e3021894 1420 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
elessair 0:f269e3021894 1421
elessair 0:f269e3021894 1422 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
elessair 0:f269e3021894 1423 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
elessair 0:f269e3021894 1424
elessair 0:f269e3021894 1425 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
elessair 0:f269e3021894 1426 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
elessair 0:f269e3021894 1427
elessair 0:f269e3021894 1428 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
elessair 0:f269e3021894 1429 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
elessair 0:f269e3021894 1430
elessair 0:f269e3021894 1431 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
elessair 0:f269e3021894 1432 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
elessair 0:f269e3021894 1433
elessair 0:f269e3021894 1434 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
elessair 0:f269e3021894 1435 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
elessair 0:f269e3021894 1436
elessair 0:f269e3021894 1437 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
elessair 0:f269e3021894 1438 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
elessair 0:f269e3021894 1439
elessair 0:f269e3021894 1440 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
elessair 0:f269e3021894 1441 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
elessair 0:f269e3021894 1442
elessair 0:f269e3021894 1443 /*@} end of group CMSIS_CoreDebug */
elessair 0:f269e3021894 1444
elessair 0:f269e3021894 1445
elessair 0:f269e3021894 1446 /** \ingroup CMSIS_core_register
elessair 0:f269e3021894 1447 \defgroup CMSIS_core_base Core Definitions
elessair 0:f269e3021894 1448 \brief Definitions for base addresses, unions, and structures.
elessair 0:f269e3021894 1449 @{
elessair 0:f269e3021894 1450 */
elessair 0:f269e3021894 1451
elessair 0:f269e3021894 1452 /* Memory mapping of Cortex-M4 Hardware */
elessair 0:f269e3021894 1453 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
elessair 0:f269e3021894 1454 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
elessair 0:f269e3021894 1455 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
elessair 0:f269e3021894 1456 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
elessair 0:f269e3021894 1457 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
elessair 0:f269e3021894 1458 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
elessair 0:f269e3021894 1459 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
elessair 0:f269e3021894 1460 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
elessair 0:f269e3021894 1461
elessair 0:f269e3021894 1462 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
elessair 0:f269e3021894 1463 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
elessair 0:f269e3021894 1464 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
elessair 0:f269e3021894 1465 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
elessair 0:f269e3021894 1466 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
elessair 0:f269e3021894 1467 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
elessair 0:f269e3021894 1468 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
elessair 0:f269e3021894 1469 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
elessair 0:f269e3021894 1470
elessair 0:f269e3021894 1471 #if (__MPU_PRESENT == 1)
elessair 0:f269e3021894 1472 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
elessair 0:f269e3021894 1473 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
elessair 0:f269e3021894 1474 #endif
elessair 0:f269e3021894 1475
elessair 0:f269e3021894 1476 #if (__FPU_PRESENT == 1)
elessair 0:f269e3021894 1477 #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
elessair 0:f269e3021894 1478 #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
elessair 0:f269e3021894 1479 #endif
elessair 0:f269e3021894 1480
elessair 0:f269e3021894 1481 /*@} */
elessair 0:f269e3021894 1482
elessair 0:f269e3021894 1483
elessair 0:f269e3021894 1484
elessair 0:f269e3021894 1485 /*******************************************************************************
elessair 0:f269e3021894 1486 * Hardware Abstraction Layer
elessair 0:f269e3021894 1487 Core Function Interface contains:
elessair 0:f269e3021894 1488 - Core NVIC Functions
elessair 0:f269e3021894 1489 - Core SysTick Functions
elessair 0:f269e3021894 1490 - Core Debug Functions
elessair 0:f269e3021894 1491 - Core Register Access Functions
elessair 0:f269e3021894 1492 ******************************************************************************/
elessair 0:f269e3021894 1493 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
elessair 0:f269e3021894 1494 */
elessair 0:f269e3021894 1495
elessair 0:f269e3021894 1496
elessair 0:f269e3021894 1497
elessair 0:f269e3021894 1498 /* ########################## NVIC functions #################################### */
elessair 0:f269e3021894 1499 /** \ingroup CMSIS_Core_FunctionInterface
elessair 0:f269e3021894 1500 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
elessair 0:f269e3021894 1501 \brief Functions that manage interrupts and exceptions via the NVIC.
elessair 0:f269e3021894 1502 @{
elessair 0:f269e3021894 1503 */
elessair 0:f269e3021894 1504
elessair 0:f269e3021894 1505 #ifdef CMSIS_NVIC_VIRTUAL
elessair 0:f269e3021894 1506 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
elessair 0:f269e3021894 1507 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
elessair 0:f269e3021894 1508 #endif
elessair 0:f269e3021894 1509 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
elessair 0:f269e3021894 1510 #else
elessair 0:f269e3021894 1511 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
elessair 0:f269e3021894 1512 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
elessair 0:f269e3021894 1513 #define NVIC_EnableIRQ __NVIC_EnableIRQ
elessair 0:f269e3021894 1514 #define NVIC_DisableIRQ __NVIC_DisableIRQ
elessair 0:f269e3021894 1515 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
elessair 0:f269e3021894 1516 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
elessair 0:f269e3021894 1517 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
elessair 0:f269e3021894 1518 #define NVIC_GetActive __NVIC_GetActive
elessair 0:f269e3021894 1519 #define NVIC_SetPriority __NVIC_SetPriority
elessair 0:f269e3021894 1520 #define NVIC_GetPriority __NVIC_GetPriority
elessair 0:f269e3021894 1521 #define NVIC_SystemReset __NVIC_SystemReset
elessair 0:f269e3021894 1522 #endif /* CMSIS_NVIC_VIRTUAL */
elessair 0:f269e3021894 1523
elessair 0:f269e3021894 1524 #ifdef CMSIS_VECTAB_VIRTUAL
elessair 0:f269e3021894 1525 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
elessair 0:f269e3021894 1526 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
elessair 0:f269e3021894 1527 #endif
elessair 0:f269e3021894 1528 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
elessair 0:f269e3021894 1529 #else
elessair 0:f269e3021894 1530 #define NVIC_SetVector __NVIC_SetVector
elessair 0:f269e3021894 1531 #define NVIC_GetVector __NVIC_GetVector
elessair 0:f269e3021894 1532 #endif /* CMSIS_VECTAB_VIRTUAL */
elessair 0:f269e3021894 1533
elessair 0:f269e3021894 1534
elessair 0:f269e3021894 1535 /** \brief Set Priority Grouping
elessair 0:f269e3021894 1536
elessair 0:f269e3021894 1537 The function sets the priority grouping field using the required unlock sequence.
elessair 0:f269e3021894 1538 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
elessair 0:f269e3021894 1539 Only values from 0..7 are used.
elessair 0:f269e3021894 1540 In case of a conflict between priority grouping and available
elessair 0:f269e3021894 1541 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
elessair 0:f269e3021894 1542
elessair 0:f269e3021894 1543 \param [in] PriorityGroup Priority grouping field.
elessair 0:f269e3021894 1544 */
elessair 0:f269e3021894 1545 __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
elessair 0:f269e3021894 1546 {
elessair 0:f269e3021894 1547 uint32_t reg_value;
elessair 0:f269e3021894 1548 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
elessair 0:f269e3021894 1549
elessair 0:f269e3021894 1550 reg_value = SCB->AIRCR; /* read old register configuration */
elessair 0:f269e3021894 1551 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
elessair 0:f269e3021894 1552 reg_value = (reg_value |
elessair 0:f269e3021894 1553 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
elessair 0:f269e3021894 1554 (PriorityGroupTmp << 8) ); /* Insert write key and priorty group */
elessair 0:f269e3021894 1555 SCB->AIRCR = reg_value;
elessair 0:f269e3021894 1556 }
elessair 0:f269e3021894 1557
elessair 0:f269e3021894 1558
elessair 0:f269e3021894 1559 /** \brief Get Priority Grouping
elessair 0:f269e3021894 1560
elessair 0:f269e3021894 1561 The function reads the priority grouping field from the NVIC Interrupt Controller.
elessair 0:f269e3021894 1562
elessair 0:f269e3021894 1563 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
elessair 0:f269e3021894 1564 */
elessair 0:f269e3021894 1565 __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
elessair 0:f269e3021894 1566 {
elessair 0:f269e3021894 1567 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
elessair 0:f269e3021894 1568 }
elessair 0:f269e3021894 1569
elessair 0:f269e3021894 1570
elessair 0:f269e3021894 1571 /** \brief Enable External Interrupt
elessair 0:f269e3021894 1572
elessair 0:f269e3021894 1573 The function enables a device-specific interrupt in the NVIC interrupt controller.
elessair 0:f269e3021894 1574
elessair 0:f269e3021894 1575 \param [in] IRQn External interrupt number. Value cannot be negative.
elessair 0:f269e3021894 1576 */
elessair 0:f269e3021894 1577 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
elessair 0:f269e3021894 1578 {
elessair 0:f269e3021894 1579 NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
elessair 0:f269e3021894 1580 }
elessair 0:f269e3021894 1581
elessair 0:f269e3021894 1582
elessair 0:f269e3021894 1583 /** \brief Disable External Interrupt
elessair 0:f269e3021894 1584
elessair 0:f269e3021894 1585 The function disables a device-specific interrupt in the NVIC interrupt controller.
elessair 0:f269e3021894 1586
elessair 0:f269e3021894 1587 \param [in] IRQn External interrupt number. Value cannot be negative.
elessair 0:f269e3021894 1588 */
elessair 0:f269e3021894 1589 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
elessair 0:f269e3021894 1590 {
elessair 0:f269e3021894 1591 NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
elessair 0:f269e3021894 1592 }
elessair 0:f269e3021894 1593
elessair 0:f269e3021894 1594
elessair 0:f269e3021894 1595 /** \brief Get Pending Interrupt
elessair 0:f269e3021894 1596
elessair 0:f269e3021894 1597 The function reads the pending register in the NVIC and returns the pending bit
elessair 0:f269e3021894 1598 for the specified interrupt.
elessair 0:f269e3021894 1599
elessair 0:f269e3021894 1600 \param [in] IRQn Interrupt number.
elessair 0:f269e3021894 1601
elessair 0:f269e3021894 1602 \return 0 Interrupt status is not pending.
elessair 0:f269e3021894 1603 \return 1 Interrupt status is pending.
elessair 0:f269e3021894 1604 */
elessair 0:f269e3021894 1605 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
elessair 0:f269e3021894 1606 {
elessair 0:f269e3021894 1607 return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
elessair 0:f269e3021894 1608 }
elessair 0:f269e3021894 1609
elessair 0:f269e3021894 1610
elessair 0:f269e3021894 1611 /** \brief Set Pending Interrupt
elessair 0:f269e3021894 1612
elessair 0:f269e3021894 1613 The function sets the pending bit of an external interrupt.
elessair 0:f269e3021894 1614
elessair 0:f269e3021894 1615 \param [in] IRQn Interrupt number. Value cannot be negative.
elessair 0:f269e3021894 1616 */
elessair 0:f269e3021894 1617 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
elessair 0:f269e3021894 1618 {
elessair 0:f269e3021894 1619 NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
elessair 0:f269e3021894 1620 }
elessair 0:f269e3021894 1621
elessair 0:f269e3021894 1622
elessair 0:f269e3021894 1623 /** \brief Clear Pending Interrupt
elessair 0:f269e3021894 1624
elessair 0:f269e3021894 1625 The function clears the pending bit of an external interrupt.
elessair 0:f269e3021894 1626
elessair 0:f269e3021894 1627 \param [in] IRQn External interrupt number. Value cannot be negative.
elessair 0:f269e3021894 1628 */
elessair 0:f269e3021894 1629 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
elessair 0:f269e3021894 1630 {
elessair 0:f269e3021894 1631 NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
elessair 0:f269e3021894 1632 }
elessair 0:f269e3021894 1633
elessair 0:f269e3021894 1634
elessair 0:f269e3021894 1635 /** \brief Get Active Interrupt
elessair 0:f269e3021894 1636
elessair 0:f269e3021894 1637 The function reads the active register in NVIC and returns the active bit.
elessair 0:f269e3021894 1638
elessair 0:f269e3021894 1639 \param [in] IRQn Interrupt number.
elessair 0:f269e3021894 1640
elessair 0:f269e3021894 1641 \return 0 Interrupt status is not active.
elessair 0:f269e3021894 1642 \return 1 Interrupt status is active.
elessair 0:f269e3021894 1643 */
elessair 0:f269e3021894 1644 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
elessair 0:f269e3021894 1645 {
elessair 0:f269e3021894 1646 return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
elessair 0:f269e3021894 1647 }
elessair 0:f269e3021894 1648
elessair 0:f269e3021894 1649
elessair 0:f269e3021894 1650 /** \brief Set Interrupt Priority
elessair 0:f269e3021894 1651
elessair 0:f269e3021894 1652 The function sets the priority of an interrupt.
elessair 0:f269e3021894 1653
elessair 0:f269e3021894 1654 \note The priority cannot be set for every core interrupt.
elessair 0:f269e3021894 1655
elessair 0:f269e3021894 1656 \param [in] IRQn Interrupt number.
elessair 0:f269e3021894 1657 \param [in] priority Priority to set.
elessair 0:f269e3021894 1658 */
elessair 0:f269e3021894 1659 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
elessair 0:f269e3021894 1660 {
elessair 0:f269e3021894 1661 if((int32_t)IRQn < 0) {
elessair 0:f269e3021894 1662 SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
elessair 0:f269e3021894 1663 }
elessair 0:f269e3021894 1664 else {
elessair 0:f269e3021894 1665 NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
elessair 0:f269e3021894 1666 }
elessair 0:f269e3021894 1667 }
elessair 0:f269e3021894 1668
elessair 0:f269e3021894 1669
elessair 0:f269e3021894 1670 /** \brief Get Interrupt Priority
elessair 0:f269e3021894 1671
elessair 0:f269e3021894 1672 The function reads the priority of an interrupt. The interrupt
elessair 0:f269e3021894 1673 number can be positive to specify an external (device specific)
elessair 0:f269e3021894 1674 interrupt, or negative to specify an internal (core) interrupt.
elessair 0:f269e3021894 1675
elessair 0:f269e3021894 1676
elessair 0:f269e3021894 1677 \param [in] IRQn Interrupt number.
elessair 0:f269e3021894 1678 \return Interrupt Priority. Value is aligned automatically to the implemented
elessair 0:f269e3021894 1679 priority bits of the microcontroller.
elessair 0:f269e3021894 1680 */
elessair 0:f269e3021894 1681 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
elessair 0:f269e3021894 1682 {
elessair 0:f269e3021894 1683
elessair 0:f269e3021894 1684 if((int32_t)IRQn < 0) {
elessair 0:f269e3021894 1685 return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
elessair 0:f269e3021894 1686 }
elessair 0:f269e3021894 1687 else {
elessair 0:f269e3021894 1688 return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));
elessair 0:f269e3021894 1689 }
elessair 0:f269e3021894 1690 }
elessair 0:f269e3021894 1691
elessair 0:f269e3021894 1692
elessair 0:f269e3021894 1693 /** \brief Encode Priority
elessair 0:f269e3021894 1694
elessair 0:f269e3021894 1695 The function encodes the priority for an interrupt with the given priority group,
elessair 0:f269e3021894 1696 preemptive priority value, and subpriority value.
elessair 0:f269e3021894 1697 In case of a conflict between priority grouping and available
elessair 0:f269e3021894 1698 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
elessair 0:f269e3021894 1699
elessair 0:f269e3021894 1700 \param [in] PriorityGroup Used priority group.
elessair 0:f269e3021894 1701 \param [in] PreemptPriority Preemptive priority value (starting from 0).
elessair 0:f269e3021894 1702 \param [in] SubPriority Subpriority value (starting from 0).
elessair 0:f269e3021894 1703 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
elessair 0:f269e3021894 1704 */
elessair 0:f269e3021894 1705 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
elessair 0:f269e3021894 1706 {
elessair 0:f269e3021894 1707 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
elessair 0:f269e3021894 1708 uint32_t PreemptPriorityBits;
elessair 0:f269e3021894 1709 uint32_t SubPriorityBits;
elessair 0:f269e3021894 1710
elessair 0:f269e3021894 1711 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
elessair 0:f269e3021894 1712 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
elessair 0:f269e3021894 1713
elessair 0:f269e3021894 1714 return (
elessair 0:f269e3021894 1715 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
elessair 0:f269e3021894 1716 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
elessair 0:f269e3021894 1717 );
elessair 0:f269e3021894 1718 }
elessair 0:f269e3021894 1719
elessair 0:f269e3021894 1720
elessair 0:f269e3021894 1721 /** \brief Decode Priority
elessair 0:f269e3021894 1722
elessair 0:f269e3021894 1723 The function decodes an interrupt priority value with a given priority group to
elessair 0:f269e3021894 1724 preemptive priority value and subpriority value.
elessair 0:f269e3021894 1725 In case of a conflict between priority grouping and available
elessair 0:f269e3021894 1726 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
elessair 0:f269e3021894 1727
elessair 0:f269e3021894 1728 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
elessair 0:f269e3021894 1729 \param [in] PriorityGroup Used priority group.
elessair 0:f269e3021894 1730 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
elessair 0:f269e3021894 1731 \param [out] pSubPriority Subpriority value (starting from 0).
elessair 0:f269e3021894 1732 */
elessair 0:f269e3021894 1733 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
elessair 0:f269e3021894 1734 {
elessair 0:f269e3021894 1735 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
elessair 0:f269e3021894 1736 uint32_t PreemptPriorityBits;
elessair 0:f269e3021894 1737 uint32_t SubPriorityBits;
elessair 0:f269e3021894 1738
elessair 0:f269e3021894 1739 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
elessair 0:f269e3021894 1740 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
elessair 0:f269e3021894 1741
elessair 0:f269e3021894 1742 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
elessair 0:f269e3021894 1743 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
elessair 0:f269e3021894 1744 }
elessair 0:f269e3021894 1745
elessair 0:f269e3021894 1746
elessair 0:f269e3021894 1747 /** \brief System Reset
elessair 0:f269e3021894 1748
elessair 0:f269e3021894 1749 The function initiates a system reset request to reset the MCU.
elessair 0:f269e3021894 1750 */
elessair 0:f269e3021894 1751 __STATIC_INLINE void __NVIC_SystemReset(void)
elessair 0:f269e3021894 1752 {
elessair 0:f269e3021894 1753 __DSB(); /* Ensure all outstanding memory accesses included
elessair 0:f269e3021894 1754 buffered write are completed before reset */
elessair 0:f269e3021894 1755 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
elessair 0:f269e3021894 1756 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
elessair 0:f269e3021894 1757 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
elessair 0:f269e3021894 1758 __DSB(); /* Ensure completion of memory access */
elessair 0:f269e3021894 1759 while(1) { __NOP(); } /* wait until reset */
elessair 0:f269e3021894 1760 }
elessair 0:f269e3021894 1761
elessair 0:f269e3021894 1762 /*@} end of CMSIS_Core_NVICFunctions */
elessair 0:f269e3021894 1763
elessair 0:f269e3021894 1764
elessair 0:f269e3021894 1765
elessair 0:f269e3021894 1766 /* ################################## SysTick function ############################################ */
elessair 0:f269e3021894 1767 /** \ingroup CMSIS_Core_FunctionInterface
elessair 0:f269e3021894 1768 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
elessair 0:f269e3021894 1769 \brief Functions that configure the System.
elessair 0:f269e3021894 1770 @{
elessair 0:f269e3021894 1771 */
elessair 0:f269e3021894 1772
elessair 0:f269e3021894 1773 #if (__Vendor_SysTickConfig == 0)
elessair 0:f269e3021894 1774
elessair 0:f269e3021894 1775 /** \brief System Tick Configuration
elessair 0:f269e3021894 1776
elessair 0:f269e3021894 1777 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
elessair 0:f269e3021894 1778 Counter is in free running mode to generate periodic interrupts.
elessair 0:f269e3021894 1779
elessair 0:f269e3021894 1780 \param [in] ticks Number of ticks between two interrupts.
elessair 0:f269e3021894 1781
elessair 0:f269e3021894 1782 \return 0 Function succeeded.
elessair 0:f269e3021894 1783 \return 1 Function failed.
elessair 0:f269e3021894 1784
elessair 0:f269e3021894 1785 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
elessair 0:f269e3021894 1786 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
elessair 0:f269e3021894 1787 must contain a vendor-specific implementation of this function.
elessair 0:f269e3021894 1788
elessair 0:f269e3021894 1789 */
elessair 0:f269e3021894 1790 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
elessair 0:f269e3021894 1791 {
elessair 0:f269e3021894 1792 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
elessair 0:f269e3021894 1793
elessair 0:f269e3021894 1794 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
elessair 0:f269e3021894 1795 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
elessair 0:f269e3021894 1796 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
elessair 0:f269e3021894 1797 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
elessair 0:f269e3021894 1798 SysTick_CTRL_TICKINT_Msk |
elessair 0:f269e3021894 1799 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
elessair 0:f269e3021894 1800 return (0UL); /* Function successful */
elessair 0:f269e3021894 1801 }
elessair 0:f269e3021894 1802
elessair 0:f269e3021894 1803 #endif
elessair 0:f269e3021894 1804
elessair 0:f269e3021894 1805 /*@} end of CMSIS_Core_SysTickFunctions */
elessair 0:f269e3021894 1806
elessair 0:f269e3021894 1807
elessair 0:f269e3021894 1808
elessair 0:f269e3021894 1809 /* ##################################### Debug In/Output function ########################################### */
elessair 0:f269e3021894 1810 /** \ingroup CMSIS_Core_FunctionInterface
elessair 0:f269e3021894 1811 \defgroup CMSIS_core_DebugFunctions ITM Functions
elessair 0:f269e3021894 1812 \brief Functions that access the ITM debug interface.
elessair 0:f269e3021894 1813 @{
elessair 0:f269e3021894 1814 */
elessair 0:f269e3021894 1815
elessair 0:f269e3021894 1816 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
elessair 0:f269e3021894 1817 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
elessair 0:f269e3021894 1818
elessair 0:f269e3021894 1819
elessair 0:f269e3021894 1820 /** \brief ITM Send Character
elessair 0:f269e3021894 1821
elessair 0:f269e3021894 1822 The function transmits a character via the ITM channel 0, and
elessair 0:f269e3021894 1823 \li Just returns when no debugger is connected that has booked the output.
elessair 0:f269e3021894 1824 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
elessair 0:f269e3021894 1825
elessair 0:f269e3021894 1826 \param [in] ch Character to transmit.
elessair 0:f269e3021894 1827
elessair 0:f269e3021894 1828 \returns Character to transmit.
elessair 0:f269e3021894 1829 */
elessair 0:f269e3021894 1830 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
elessair 0:f269e3021894 1831 {
elessair 0:f269e3021894 1832 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
elessair 0:f269e3021894 1833 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
elessair 0:f269e3021894 1834 {
elessair 0:f269e3021894 1835 while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
elessair 0:f269e3021894 1836 ITM->PORT[0].u8 = (uint8_t)ch;
elessair 0:f269e3021894 1837 }
elessair 0:f269e3021894 1838 return (ch);
elessair 0:f269e3021894 1839 }
elessair 0:f269e3021894 1840
elessair 0:f269e3021894 1841
elessair 0:f269e3021894 1842 /** \brief ITM Receive Character
elessair 0:f269e3021894 1843
elessair 0:f269e3021894 1844 The function inputs a character via the external variable \ref ITM_RxBuffer.
elessair 0:f269e3021894 1845
elessair 0:f269e3021894 1846 \return Received character.
elessair 0:f269e3021894 1847 \return -1 No character pending.
elessair 0:f269e3021894 1848 */
elessair 0:f269e3021894 1849 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
elessair 0:f269e3021894 1850 int32_t ch = -1; /* no character available */
elessair 0:f269e3021894 1851
elessair 0:f269e3021894 1852 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
elessair 0:f269e3021894 1853 ch = ITM_RxBuffer;
elessair 0:f269e3021894 1854 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
elessair 0:f269e3021894 1855 }
elessair 0:f269e3021894 1856
elessair 0:f269e3021894 1857 return (ch);
elessair 0:f269e3021894 1858 }
elessair 0:f269e3021894 1859
elessair 0:f269e3021894 1860
elessair 0:f269e3021894 1861 /** \brief ITM Check Character
elessair 0:f269e3021894 1862
elessair 0:f269e3021894 1863 The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
elessair 0:f269e3021894 1864
elessair 0:f269e3021894 1865 \return 0 No character available.
elessair 0:f269e3021894 1866 \return 1 Character available.
elessair 0:f269e3021894 1867 */
elessair 0:f269e3021894 1868 __STATIC_INLINE int32_t ITM_CheckChar (void) {
elessair 0:f269e3021894 1869
elessair 0:f269e3021894 1870 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
elessair 0:f269e3021894 1871 return (0); /* no character available */
elessair 0:f269e3021894 1872 } else {
elessair 0:f269e3021894 1873 return (1); /* character available */
elessair 0:f269e3021894 1874 }
elessair 0:f269e3021894 1875 }
elessair 0:f269e3021894 1876
elessair 0:f269e3021894 1877 /*@} end of CMSIS_core_DebugFunctions */
elessair 0:f269e3021894 1878
elessair 0:f269e3021894 1879
elessair 0:f269e3021894 1880
elessair 0:f269e3021894 1881
elessair 0:f269e3021894 1882 #ifdef __cplusplus
elessair 0:f269e3021894 1883 }
elessair 0:f269e3021894 1884 #endif
elessair 0:f269e3021894 1885
elessair 0:f269e3021894 1886 #endif /* __CORE_CM4_H_DEPENDANT */
elessair 0:f269e3021894 1887
elessair 0:f269e3021894 1888 #endif /* __CMSIS_GENERIC */