CMSIS_DSP_5 - The CMSIS DSP 5 library

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The CMSIS DSP 5 library

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headers/core_cm7.h@3:4098b9d3d571, 2018-06-21 (annotated)

Committer:: xorjoep
Date:: Thu Jun 21 11:56:27 2018 +0000
Revision:: 3:4098b9d3d571

headers is a folder not a library

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User	Revision	Line number	New contents of line
xorjoep	3:4098b9d3d571	1	/************************************************************************//
xorjoep	3:4098b9d3d571	2	* @file core_cm7.h
xorjoep	3:4098b9d3d571	3	* @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File
xorjoep	3:4098b9d3d571	4	* @version V5.0.8
xorjoep	3:4098b9d3d571	5	* @date 04. June 2018
xorjoep	3:4098b9d3d571	6	******************************************************************************/
xorjoep	3:4098b9d3d571	7	/*
xorjoep	3:4098b9d3d571	8	* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
xorjoep	3:4098b9d3d571	9	*
xorjoep	3:4098b9d3d571	10	* SPDX-License-Identifier: Apache-2.0
xorjoep	3:4098b9d3d571	11	*
xorjoep	3:4098b9d3d571	12	* Licensed under the Apache License, Version 2.0 (the License); you may
xorjoep	3:4098b9d3d571	13	* not use this file except in compliance with the License.
xorjoep	3:4098b9d3d571	14	* You may obtain a copy of the License at
xorjoep	3:4098b9d3d571	15	*
xorjoep	3:4098b9d3d571	16	* www.apache.org/licenses/LICENSE-2.0
xorjoep	3:4098b9d3d571	17	*
xorjoep	3:4098b9d3d571	18	* Unless required by applicable law or agreed to in writing, software
xorjoep	3:4098b9d3d571	19	* distributed under the License is distributed on an AS IS BASIS, WITHOUT
xorjoep	3:4098b9d3d571	20	* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
xorjoep	3:4098b9d3d571	21	* See the License for the specific language governing permissions and
xorjoep	3:4098b9d3d571	22	* limitations under the License.
xorjoep	3:4098b9d3d571	23	*/
xorjoep	3:4098b9d3d571	24
xorjoep	3:4098b9d3d571	25	#if defined ( __ICCARM__ )
xorjoep	3:4098b9d3d571	26	#pragma system_include /* treat file as system include file for MISRA check */
xorjoep	3:4098b9d3d571	27	#elif defined (__clang__)
xorjoep	3:4098b9d3d571	28	#pragma clang system_header /* treat file as system include file */
xorjoep	3:4098b9d3d571	29	#endif
xorjoep	3:4098b9d3d571	30
xorjoep	3:4098b9d3d571	31	#ifndef __CORE_CM7_H_GENERIC
xorjoep	3:4098b9d3d571	32	#define __CORE_CM7_H_GENERIC
xorjoep	3:4098b9d3d571	33
xorjoep	3:4098b9d3d571	34	#include <stdint.h>
xorjoep	3:4098b9d3d571	35
xorjoep	3:4098b9d3d571	36	#ifdef __cplusplus
xorjoep	3:4098b9d3d571	37	extern "C" {
xorjoep	3:4098b9d3d571	38	#endif
xorjoep	3:4098b9d3d571	39
xorjoep	3:4098b9d3d571	40	/**
xorjoep	3:4098b9d3d571	41	\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
xorjoep	3:4098b9d3d571	42	CMSIS violates the following MISRA-C:2004 rules:
xorjoep	3:4098b9d3d571	43
xorjoep	3:4098b9d3d571	44	\li Required Rule 8.5, object/function definition in header file.<br>
xorjoep	3:4098b9d3d571	45	Function definitions in header files are used to allow 'inlining'.
xorjoep	3:4098b9d3d571	46
xorjoep	3:4098b9d3d571	47	\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
xorjoep	3:4098b9d3d571	48	Unions are used for effective representation of core registers.
xorjoep	3:4098b9d3d571	49
xorjoep	3:4098b9d3d571	50	\li Advisory Rule 19.7, Function-like macro defined.<br>
xorjoep	3:4098b9d3d571	51	Function-like macros are used to allow more efficient code.
xorjoep	3:4098b9d3d571	52	*/
xorjoep	3:4098b9d3d571	53
xorjoep	3:4098b9d3d571	54
xorjoep	3:4098b9d3d571	55	/*******************************************************************************
xorjoep	3:4098b9d3d571	56	* CMSIS definitions
xorjoep	3:4098b9d3d571	57	******************************************************************************/
xorjoep	3:4098b9d3d571	58	/**
xorjoep	3:4098b9d3d571	59	\ingroup Cortex_M7
xorjoep	3:4098b9d3d571	60	@{
xorjoep	3:4098b9d3d571	61	*/
xorjoep	3:4098b9d3d571	62
xorjoep	3:4098b9d3d571	63	#include "cmsis_version.h"
xorjoep	3:4098b9d3d571	64
xorjoep	3:4098b9d3d571	65	/* CMSIS CM7 definitions */
xorjoep	3:4098b9d3d571	66	#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /!< \deprecated [31:16] CMSIS HAL main version /
xorjoep	3:4098b9d3d571	67	#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /!< \deprecated [15:0] CMSIS HAL sub version /
xorjoep	3:4098b9d3d571	68	#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) \| \
xorjoep	3:4098b9d3d571	69	__CM7_CMSIS_VERSION_SUB ) /!< \deprecated CMSIS HAL version number /
xorjoep	3:4098b9d3d571	70
xorjoep	3:4098b9d3d571	71	#define __CORTEX_M (7U) /!< Cortex-M Core /
xorjoep	3:4098b9d3d571	72
xorjoep	3:4098b9d3d571	73	/** __FPU_USED indicates whether an FPU is used or not.
xorjoep	3:4098b9d3d571	74	For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
xorjoep	3:4098b9d3d571	75	*/
xorjoep	3:4098b9d3d571	76	#if defined ( __CC_ARM )
xorjoep	3:4098b9d3d571	77	#if defined __TARGET_FPU_VFP
xorjoep	3:4098b9d3d571	78	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
xorjoep	3:4098b9d3d571	79	#define __FPU_USED 1U
xorjoep	3:4098b9d3d571	80	#else
xorjoep	3:4098b9d3d571	81	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
xorjoep	3:4098b9d3d571	82	#define __FPU_USED 0U
xorjoep	3:4098b9d3d571	83	#endif
xorjoep	3:4098b9d3d571	84	#else
xorjoep	3:4098b9d3d571	85	#define __FPU_USED 0U
xorjoep	3:4098b9d3d571	86	#endif
xorjoep	3:4098b9d3d571	87
xorjoep	3:4098b9d3d571	88	#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
xorjoep	3:4098b9d3d571	89	#if defined __ARM_PCS_VFP
xorjoep	3:4098b9d3d571	90	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
xorjoep	3:4098b9d3d571	91	#define __FPU_USED 1U
xorjoep	3:4098b9d3d571	92	#else
xorjoep	3:4098b9d3d571	93	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
xorjoep	3:4098b9d3d571	94	#define __FPU_USED 0U
xorjoep	3:4098b9d3d571	95	#endif
xorjoep	3:4098b9d3d571	96	#else
xorjoep	3:4098b9d3d571	97	#define __FPU_USED 0U
xorjoep	3:4098b9d3d571	98	#endif
xorjoep	3:4098b9d3d571	99
xorjoep	3:4098b9d3d571	100	#elif defined ( __GNUC__ )
xorjoep	3:4098b9d3d571	101	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
xorjoep	3:4098b9d3d571	102	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
xorjoep	3:4098b9d3d571	103	#define __FPU_USED 1U
xorjoep	3:4098b9d3d571	104	#else
xorjoep	3:4098b9d3d571	105	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
xorjoep	3:4098b9d3d571	106	#define __FPU_USED 0U
xorjoep	3:4098b9d3d571	107	#endif
xorjoep	3:4098b9d3d571	108	#else
xorjoep	3:4098b9d3d571	109	#define __FPU_USED 0U
xorjoep	3:4098b9d3d571	110	#endif
xorjoep	3:4098b9d3d571	111
xorjoep	3:4098b9d3d571	112	#elif defined ( __ICCARM__ )
xorjoep	3:4098b9d3d571	113	#if defined __ARMVFP__
xorjoep	3:4098b9d3d571	114	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
xorjoep	3:4098b9d3d571	115	#define __FPU_USED 1U
xorjoep	3:4098b9d3d571	116	#else
xorjoep	3:4098b9d3d571	117	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
xorjoep	3:4098b9d3d571	118	#define __FPU_USED 0U
xorjoep	3:4098b9d3d571	119	#endif
xorjoep	3:4098b9d3d571	120	#else
xorjoep	3:4098b9d3d571	121	#define __FPU_USED 0U
xorjoep	3:4098b9d3d571	122	#endif
xorjoep	3:4098b9d3d571	123
xorjoep	3:4098b9d3d571	124	#elif defined ( __TI_ARM__ )
xorjoep	3:4098b9d3d571	125	#if defined __TI_VFP_SUPPORT__
xorjoep	3:4098b9d3d571	126	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
xorjoep	3:4098b9d3d571	127	#define __FPU_USED 1U
xorjoep	3:4098b9d3d571	128	#else
xorjoep	3:4098b9d3d571	129	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
xorjoep	3:4098b9d3d571	130	#define __FPU_USED 0U
xorjoep	3:4098b9d3d571	131	#endif
xorjoep	3:4098b9d3d571	132	#else
xorjoep	3:4098b9d3d571	133	#define __FPU_USED 0U
xorjoep	3:4098b9d3d571	134	#endif
xorjoep	3:4098b9d3d571	135
xorjoep	3:4098b9d3d571	136	#elif defined ( __TASKING__ )
xorjoep	3:4098b9d3d571	137	#if defined __FPU_VFP__
xorjoep	3:4098b9d3d571	138	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
xorjoep	3:4098b9d3d571	139	#define __FPU_USED 1U
xorjoep	3:4098b9d3d571	140	#else
xorjoep	3:4098b9d3d571	141	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
xorjoep	3:4098b9d3d571	142	#define __FPU_USED 0U
xorjoep	3:4098b9d3d571	143	#endif
xorjoep	3:4098b9d3d571	144	#else
xorjoep	3:4098b9d3d571	145	#define __FPU_USED 0U
xorjoep	3:4098b9d3d571	146	#endif
xorjoep	3:4098b9d3d571	147
xorjoep	3:4098b9d3d571	148	#elif defined ( __CSMC__ )
xorjoep	3:4098b9d3d571	149	#if ( __CSMC__ & 0x400U)
xorjoep	3:4098b9d3d571	150	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
xorjoep	3:4098b9d3d571	151	#define __FPU_USED 1U
xorjoep	3:4098b9d3d571	152	#else
xorjoep	3:4098b9d3d571	153	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
xorjoep	3:4098b9d3d571	154	#define __FPU_USED 0U
xorjoep	3:4098b9d3d571	155	#endif
xorjoep	3:4098b9d3d571	156	#else
xorjoep	3:4098b9d3d571	157	#define __FPU_USED 0U
xorjoep	3:4098b9d3d571	158	#endif
xorjoep	3:4098b9d3d571	159
xorjoep	3:4098b9d3d571	160	#endif
xorjoep	3:4098b9d3d571	161
xorjoep	3:4098b9d3d571	162	#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
xorjoep	3:4098b9d3d571	163
xorjoep	3:4098b9d3d571	164
xorjoep	3:4098b9d3d571	165	#ifdef __cplusplus
xorjoep	3:4098b9d3d571	166	}
xorjoep	3:4098b9d3d571	167	#endif
xorjoep	3:4098b9d3d571	168
xorjoep	3:4098b9d3d571	169	#endif /* __CORE_CM7_H_GENERIC */
xorjoep	3:4098b9d3d571	170
xorjoep	3:4098b9d3d571	171	#ifndef __CMSIS_GENERIC
xorjoep	3:4098b9d3d571	172
xorjoep	3:4098b9d3d571	173	#ifndef __CORE_CM7_H_DEPENDANT
xorjoep	3:4098b9d3d571	174	#define __CORE_CM7_H_DEPENDANT
xorjoep	3:4098b9d3d571	175
xorjoep	3:4098b9d3d571	176	#ifdef __cplusplus
xorjoep	3:4098b9d3d571	177	extern "C" {
xorjoep	3:4098b9d3d571	178	#endif
xorjoep	3:4098b9d3d571	179
xorjoep	3:4098b9d3d571	180	/* check device defines and use defaults */
xorjoep	3:4098b9d3d571	181	#if defined __CHECK_DEVICE_DEFINES
xorjoep	3:4098b9d3d571	182	#ifndef __CM7_REV
xorjoep	3:4098b9d3d571	183	#define __CM7_REV 0x0000U
xorjoep	3:4098b9d3d571	184	#warning "__CM7_REV not defined in device header file; using default!"
xorjoep	3:4098b9d3d571	185	#endif
xorjoep	3:4098b9d3d571	186
xorjoep	3:4098b9d3d571	187	#ifndef __FPU_PRESENT
xorjoep	3:4098b9d3d571	188	#define __FPU_PRESENT 0U
xorjoep	3:4098b9d3d571	189	#warning "__FPU_PRESENT not defined in device header file; using default!"
xorjoep	3:4098b9d3d571	190	#endif
xorjoep	3:4098b9d3d571	191
xorjoep	3:4098b9d3d571	192	#ifndef __MPU_PRESENT
xorjoep	3:4098b9d3d571	193	#define __MPU_PRESENT 0U
xorjoep	3:4098b9d3d571	194	#warning "__MPU_PRESENT not defined in device header file; using default!"
xorjoep	3:4098b9d3d571	195	#endif
xorjoep	3:4098b9d3d571	196
xorjoep	3:4098b9d3d571	197	#ifndef __ICACHE_PRESENT
xorjoep	3:4098b9d3d571	198	#define __ICACHE_PRESENT 0U
xorjoep	3:4098b9d3d571	199	#warning "__ICACHE_PRESENT not defined in device header file; using default!"
xorjoep	3:4098b9d3d571	200	#endif
xorjoep	3:4098b9d3d571	201
xorjoep	3:4098b9d3d571	202	#ifndef __DCACHE_PRESENT
xorjoep	3:4098b9d3d571	203	#define __DCACHE_PRESENT 0U
xorjoep	3:4098b9d3d571	204	#warning "__DCACHE_PRESENT not defined in device header file; using default!"
xorjoep	3:4098b9d3d571	205	#endif
xorjoep	3:4098b9d3d571	206
xorjoep	3:4098b9d3d571	207	#ifndef __DTCM_PRESENT
xorjoep	3:4098b9d3d571	208	#define __DTCM_PRESENT 0U
xorjoep	3:4098b9d3d571	209	#warning "__DTCM_PRESENT not defined in device header file; using default!"
xorjoep	3:4098b9d3d571	210	#endif
xorjoep	3:4098b9d3d571	211
xorjoep	3:4098b9d3d571	212	#ifndef __NVIC_PRIO_BITS
xorjoep	3:4098b9d3d571	213	#define __NVIC_PRIO_BITS 3U
xorjoep	3:4098b9d3d571	214	#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
xorjoep	3:4098b9d3d571	215	#endif
xorjoep	3:4098b9d3d571	216
xorjoep	3:4098b9d3d571	217	#ifndef __Vendor_SysTickConfig
xorjoep	3:4098b9d3d571	218	#define __Vendor_SysTickConfig 0U
xorjoep	3:4098b9d3d571	219	#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
xorjoep	3:4098b9d3d571	220	#endif
xorjoep	3:4098b9d3d571	221	#endif
xorjoep	3:4098b9d3d571	222
xorjoep	3:4098b9d3d571	223	/* IO definitions (access restrictions to peripheral registers) */
xorjoep	3:4098b9d3d571	224	/**
xorjoep	3:4098b9d3d571	225	\defgroup CMSIS_glob_defs CMSIS Global Defines
xorjoep	3:4098b9d3d571	226
xorjoep	3:4098b9d3d571	227	<strong>IO Type Qualifiers</strong> are used
xorjoep	3:4098b9d3d571	228	\li to specify the access to peripheral variables.
xorjoep	3:4098b9d3d571	229	\li for automatic generation of peripheral register debug information.
xorjoep	3:4098b9d3d571	230	*/
xorjoep	3:4098b9d3d571	231	#ifdef __cplusplus
xorjoep	3:4098b9d3d571	232	#define __I volatile /!< Defines 'read only' permissions /
xorjoep	3:4098b9d3d571	233	#else
xorjoep	3:4098b9d3d571	234	#define __I volatile const /!< Defines 'read only' permissions /
xorjoep	3:4098b9d3d571	235	#endif
xorjoep	3:4098b9d3d571	236	#define __O volatile /!< Defines 'write only' permissions /
xorjoep	3:4098b9d3d571	237	#define __IO volatile /!< Defines 'read / write' permissions /
xorjoep	3:4098b9d3d571	238
xorjoep	3:4098b9d3d571	239	/* following defines should be used for structure members */
xorjoep	3:4098b9d3d571	240	#define __IM volatile const /! Defines 'read only' structure member permissions /
xorjoep	3:4098b9d3d571	241	#define __OM volatile /! Defines 'write only' structure member permissions /
xorjoep	3:4098b9d3d571	242	#define __IOM volatile /! Defines 'read / write' structure member permissions /
xorjoep	3:4098b9d3d571	243
xorjoep	3:4098b9d3d571	244	/@} end of group Cortex_M7 /
xorjoep	3:4098b9d3d571	245
xorjoep	3:4098b9d3d571	246
xorjoep	3:4098b9d3d571	247
xorjoep	3:4098b9d3d571	248	/*******************************************************************************
xorjoep	3:4098b9d3d571	249	* Register Abstraction
xorjoep	3:4098b9d3d571	250	Core Register contain:
xorjoep	3:4098b9d3d571	251	- Core Register
xorjoep	3:4098b9d3d571	252	- Core NVIC Register
xorjoep	3:4098b9d3d571	253	- Core SCB Register
xorjoep	3:4098b9d3d571	254	- Core SysTick Register
xorjoep	3:4098b9d3d571	255	- Core Debug Register
xorjoep	3:4098b9d3d571	256	- Core MPU Register
xorjoep	3:4098b9d3d571	257	- Core FPU Register
xorjoep	3:4098b9d3d571	258	******************************************************************************/
xorjoep	3:4098b9d3d571	259	/**
xorjoep	3:4098b9d3d571	260	\defgroup CMSIS_core_register Defines and Type Definitions
xorjoep	3:4098b9d3d571	261	\brief Type definitions and defines for Cortex-M processor based devices.
xorjoep	3:4098b9d3d571	262	*/
xorjoep	3:4098b9d3d571	263
xorjoep	3:4098b9d3d571	264	/**
xorjoep	3:4098b9d3d571	265	\ingroup CMSIS_core_register
xorjoep	3:4098b9d3d571	266	\defgroup CMSIS_CORE Status and Control Registers
xorjoep	3:4098b9d3d571	267	\brief Core Register type definitions.
xorjoep	3:4098b9d3d571	268	@{
xorjoep	3:4098b9d3d571	269	*/
xorjoep	3:4098b9d3d571	270
xorjoep	3:4098b9d3d571	271	/**
xorjoep	3:4098b9d3d571	272	\brief Union type to access the Application Program Status Register (APSR).
xorjoep	3:4098b9d3d571	273	*/
xorjoep	3:4098b9d3d571	274	typedef union
xorjoep	3:4098b9d3d571	275	{
xorjoep	3:4098b9d3d571	276	struct
xorjoep	3:4098b9d3d571	277	{
xorjoep	3:4098b9d3d571	278	uint32_t _reserved0:16; /!< bit: 0..15 Reserved /
xorjoep	3:4098b9d3d571	279	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
xorjoep	3:4098b9d3d571	280	uint32_t _reserved1:7; /!< bit: 20..26 Reserved /
xorjoep	3:4098b9d3d571	281	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
xorjoep	3:4098b9d3d571	282	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
xorjoep	3:4098b9d3d571	283	uint32_t C:1; /!< bit: 29 Carry condition code flag /
xorjoep	3:4098b9d3d571	284	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
xorjoep	3:4098b9d3d571	285	uint32_t N:1; /!< bit: 31 Negative condition code flag /
xorjoep	3:4098b9d3d571	286	} b; /!< Structure used for bit access /
xorjoep	3:4098b9d3d571	287	uint32_t w; /!< Type used for word access /
xorjoep	3:4098b9d3d571	288	} APSR_Type;
xorjoep	3:4098b9d3d571	289
xorjoep	3:4098b9d3d571	290	/* APSR Register Definitions */
xorjoep	3:4098b9d3d571	291	#define APSR_N_Pos 31U /!< APSR: N Position /
xorjoep	3:4098b9d3d571	292	#define APSR_N_Msk (1UL << APSR_N_Pos) /!< APSR: N Mask /
xorjoep	3:4098b9d3d571	293
xorjoep	3:4098b9d3d571	294	#define APSR_Z_Pos 30U /!< APSR: Z Position /
xorjoep	3:4098b9d3d571	295	#define APSR_Z_Msk (1UL << APSR_Z_Pos) /!< APSR: Z Mask /
xorjoep	3:4098b9d3d571	296
xorjoep	3:4098b9d3d571	297	#define APSR_C_Pos 29U /!< APSR: C Position /
xorjoep	3:4098b9d3d571	298	#define APSR_C_Msk (1UL << APSR_C_Pos) /!< APSR: C Mask /
xorjoep	3:4098b9d3d571	299
xorjoep	3:4098b9d3d571	300	#define APSR_V_Pos 28U /!< APSR: V Position /
xorjoep	3:4098b9d3d571	301	#define APSR_V_Msk (1UL << APSR_V_Pos) /!< APSR: V Mask /
xorjoep	3:4098b9d3d571	302
xorjoep	3:4098b9d3d571	303	#define APSR_Q_Pos 27U /!< APSR: Q Position /
xorjoep	3:4098b9d3d571	304	#define APSR_Q_Msk (1UL << APSR_Q_Pos) /!< APSR: Q Mask /
xorjoep	3:4098b9d3d571	305
xorjoep	3:4098b9d3d571	306	#define APSR_GE_Pos 16U /!< APSR: GE Position /
xorjoep	3:4098b9d3d571	307	#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /!< APSR: GE Mask /
xorjoep	3:4098b9d3d571	308
xorjoep	3:4098b9d3d571	309
xorjoep	3:4098b9d3d571	310	/**
xorjoep	3:4098b9d3d571	311	\brief Union type to access the Interrupt Program Status Register (IPSR).
xorjoep	3:4098b9d3d571	312	*/
xorjoep	3:4098b9d3d571	313	typedef union
xorjoep	3:4098b9d3d571	314	{
xorjoep	3:4098b9d3d571	315	struct
xorjoep	3:4098b9d3d571	316	{
xorjoep	3:4098b9d3d571	317	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
xorjoep	3:4098b9d3d571	318	uint32_t _reserved0:23; /!< bit: 9..31 Reserved /
xorjoep	3:4098b9d3d571	319	} b; /!< Structure used for bit access /
xorjoep	3:4098b9d3d571	320	uint32_t w; /!< Type used for word access /
xorjoep	3:4098b9d3d571	321	} IPSR_Type;
xorjoep	3:4098b9d3d571	322
xorjoep	3:4098b9d3d571	323	/* IPSR Register Definitions */
xorjoep	3:4098b9d3d571	324	#define IPSR_ISR_Pos 0U /!< IPSR: ISR Position /
xorjoep	3:4098b9d3d571	325	#define IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/) /!< IPSR: ISR Mask /
xorjoep	3:4098b9d3d571	326
xorjoep	3:4098b9d3d571	327
xorjoep	3:4098b9d3d571	328	/**
xorjoep	3:4098b9d3d571	329	\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
xorjoep	3:4098b9d3d571	330	*/
xorjoep	3:4098b9d3d571	331	typedef union
xorjoep	3:4098b9d3d571	332	{
xorjoep	3:4098b9d3d571	333	struct
xorjoep	3:4098b9d3d571	334	{
xorjoep	3:4098b9d3d571	335	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
xorjoep	3:4098b9d3d571	336	uint32_t _reserved0:1; /!< bit: 9 Reserved /
xorjoep	3:4098b9d3d571	337	uint32_t ICI_IT_1:6; /!< bit: 10..15 ICI/IT part 1 /
xorjoep	3:4098b9d3d571	338	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
xorjoep	3:4098b9d3d571	339	uint32_t _reserved1:4; /!< bit: 20..23 Reserved /
xorjoep	3:4098b9d3d571	340	uint32_t T:1; /!< bit: 24 Thumb bit /
xorjoep	3:4098b9d3d571	341	uint32_t ICI_IT_2:2; /!< bit: 25..26 ICI/IT part 2 /
xorjoep	3:4098b9d3d571	342	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
xorjoep	3:4098b9d3d571	343	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
xorjoep	3:4098b9d3d571	344	uint32_t C:1; /!< bit: 29 Carry condition code flag /
xorjoep	3:4098b9d3d571	345	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
xorjoep	3:4098b9d3d571	346	uint32_t N:1; /!< bit: 31 Negative condition code flag /
xorjoep	3:4098b9d3d571	347	} b; /!< Structure used for bit access /
xorjoep	3:4098b9d3d571	348	uint32_t w; /!< Type used for word access /
xorjoep	3:4098b9d3d571	349	} xPSR_Type;
xorjoep	3:4098b9d3d571	350
xorjoep	3:4098b9d3d571	351	/* xPSR Register Definitions */
xorjoep	3:4098b9d3d571	352	#define xPSR_N_Pos 31U /!< xPSR: N Position /
xorjoep	3:4098b9d3d571	353	#define xPSR_N_Msk (1UL << xPSR_N_Pos) /!< xPSR: N Mask /
xorjoep	3:4098b9d3d571	354
xorjoep	3:4098b9d3d571	355	#define xPSR_Z_Pos 30U /!< xPSR: Z Position /
xorjoep	3:4098b9d3d571	356	#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /!< xPSR: Z Mask /
xorjoep	3:4098b9d3d571	357
xorjoep	3:4098b9d3d571	358	#define xPSR_C_Pos 29U /!< xPSR: C Position /
xorjoep	3:4098b9d3d571	359	#define xPSR_C_Msk (1UL << xPSR_C_Pos) /!< xPSR: C Mask /
xorjoep	3:4098b9d3d571	360
xorjoep	3:4098b9d3d571	361	#define xPSR_V_Pos 28U /!< xPSR: V Position /
xorjoep	3:4098b9d3d571	362	#define xPSR_V_Msk (1UL << xPSR_V_Pos) /!< xPSR: V Mask /
xorjoep	3:4098b9d3d571	363
xorjoep	3:4098b9d3d571	364	#define xPSR_Q_Pos 27U /!< xPSR: Q Position /
xorjoep	3:4098b9d3d571	365	#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /!< xPSR: Q Mask /
xorjoep	3:4098b9d3d571	366
xorjoep	3:4098b9d3d571	367	#define xPSR_ICI_IT_2_Pos 25U /!< xPSR: ICI/IT part 2 Position /
xorjoep	3:4098b9d3d571	368	#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /!< xPSR: ICI/IT part 2 Mask /
xorjoep	3:4098b9d3d571	369
xorjoep	3:4098b9d3d571	370	#define xPSR_T_Pos 24U /!< xPSR: T Position /
xorjoep	3:4098b9d3d571	371	#define xPSR_T_Msk (1UL << xPSR_T_Pos) /!< xPSR: T Mask /
xorjoep	3:4098b9d3d571	372
xorjoep	3:4098b9d3d571	373	#define xPSR_GE_Pos 16U /!< xPSR: GE Position /
xorjoep	3:4098b9d3d571	374	#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /!< xPSR: GE Mask /
xorjoep	3:4098b9d3d571	375
xorjoep	3:4098b9d3d571	376	#define xPSR_ICI_IT_1_Pos 10U /!< xPSR: ICI/IT part 1 Position /
xorjoep	3:4098b9d3d571	377	#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /!< xPSR: ICI/IT part 1 Mask /
xorjoep	3:4098b9d3d571	378
xorjoep	3:4098b9d3d571	379	#define xPSR_ISR_Pos 0U /!< xPSR: ISR Position /
xorjoep	3:4098b9d3d571	380	#define xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/) /!< xPSR: ISR Mask /
xorjoep	3:4098b9d3d571	381
xorjoep	3:4098b9d3d571	382
xorjoep	3:4098b9d3d571	383	/**
xorjoep	3:4098b9d3d571	384	\brief Union type to access the Control Registers (CONTROL).
xorjoep	3:4098b9d3d571	385	*/
xorjoep	3:4098b9d3d571	386	typedef union
xorjoep	3:4098b9d3d571	387	{
xorjoep	3:4098b9d3d571	388	struct
xorjoep	3:4098b9d3d571	389	{
xorjoep	3:4098b9d3d571	390	uint32_t nPRIV:1; /!< bit: 0 Execution privilege in Thread mode /
xorjoep	3:4098b9d3d571	391	uint32_t SPSEL:1; /!< bit: 1 Stack to be used /
xorjoep	3:4098b9d3d571	392	uint32_t FPCA:1; /!< bit: 2 FP extension active flag /
xorjoep	3:4098b9d3d571	393	uint32_t _reserved0:29; /!< bit: 3..31 Reserved /
xorjoep	3:4098b9d3d571	394	} b; /!< Structure used for bit access /
xorjoep	3:4098b9d3d571	395	uint32_t w; /!< Type used for word access /
xorjoep	3:4098b9d3d571	396	} CONTROL_Type;
xorjoep	3:4098b9d3d571	397
xorjoep	3:4098b9d3d571	398	/* CONTROL Register Definitions */
xorjoep	3:4098b9d3d571	399	#define CONTROL_FPCA_Pos 2U /!< CONTROL: FPCA Position /
xorjoep	3:4098b9d3d571	400	#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /!< CONTROL: FPCA Mask /
xorjoep	3:4098b9d3d571	401
xorjoep	3:4098b9d3d571	402	#define CONTROL_SPSEL_Pos 1U /!< CONTROL: SPSEL Position /
xorjoep	3:4098b9d3d571	403	#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /!< CONTROL: SPSEL Mask /
xorjoep	3:4098b9d3d571	404
xorjoep	3:4098b9d3d571	405	#define CONTROL_nPRIV_Pos 0U /!< CONTROL: nPRIV Position /
xorjoep	3:4098b9d3d571	406	#define CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/) /!< CONTROL: nPRIV Mask /
xorjoep	3:4098b9d3d571	407
xorjoep	3:4098b9d3d571	408	/@} end of group CMSIS_CORE /
xorjoep	3:4098b9d3d571	409
xorjoep	3:4098b9d3d571	410
xorjoep	3:4098b9d3d571	411	/**
xorjoep	3:4098b9d3d571	412	\ingroup CMSIS_core_register
xorjoep	3:4098b9d3d571	413	\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
xorjoep	3:4098b9d3d571	414	\brief Type definitions for the NVIC Registers
xorjoep	3:4098b9d3d571	415	@{
xorjoep	3:4098b9d3d571	416	*/
xorjoep	3:4098b9d3d571	417
xorjoep	3:4098b9d3d571	418	/**
xorjoep	3:4098b9d3d571	419	\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
xorjoep	3:4098b9d3d571	420	*/
xorjoep	3:4098b9d3d571	421	typedef struct
xorjoep	3:4098b9d3d571	422	{
xorjoep	3:4098b9d3d571	423	__IOM uint32_t ISER[8U]; /!< Offset: 0x000 (R/W) Interrupt Set Enable Register /
xorjoep	3:4098b9d3d571	424	uint32_t RESERVED0[24U];
xorjoep	3:4098b9d3d571	425	__IOM uint32_t ICER[8U]; /!< Offset: 0x080 (R/W) Interrupt Clear Enable Register /
xorjoep	3:4098b9d3d571	426	uint32_t RSERVED1[24U];
xorjoep	3:4098b9d3d571	427	__IOM uint32_t ISPR[8U]; /!< Offset: 0x100 (R/W) Interrupt Set Pending Register /
xorjoep	3:4098b9d3d571	428	uint32_t RESERVED2[24U];
xorjoep	3:4098b9d3d571	429	__IOM uint32_t ICPR[8U]; /!< Offset: 0x180 (R/W) Interrupt Clear Pending Register /
xorjoep	3:4098b9d3d571	430	uint32_t RESERVED3[24U];
xorjoep	3:4098b9d3d571	431	__IOM uint32_t IABR[8U]; /!< Offset: 0x200 (R/W) Interrupt Active bit Register /
xorjoep	3:4098b9d3d571	432	uint32_t RESERVED4[56U];
xorjoep	3:4098b9d3d571	433	__IOM uint8_t IP[240U]; /!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) /
xorjoep	3:4098b9d3d571	434	uint32_t RESERVED5[644U];
xorjoep	3:4098b9d3d571	435	__OM uint32_t STIR; /!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register /
xorjoep	3:4098b9d3d571	436	} NVIC_Type;
xorjoep	3:4098b9d3d571	437
xorjoep	3:4098b9d3d571	438	/* Software Triggered Interrupt Register Definitions */
xorjoep	3:4098b9d3d571	439	#define NVIC_STIR_INTID_Pos 0U /!< STIR: INTLINESNUM Position /
xorjoep	3:4098b9d3d571	440	#define NVIC_STIR_INTID_Msk (0x1FFUL /<< NVIC_STIR_INTID_Pos/) /!< STIR: INTLINESNUM Mask /
xorjoep	3:4098b9d3d571	441
xorjoep	3:4098b9d3d571	442	/@} end of group CMSIS_NVIC /
xorjoep	3:4098b9d3d571	443
xorjoep	3:4098b9d3d571	444
xorjoep	3:4098b9d3d571	445	/**
xorjoep	3:4098b9d3d571	446	\ingroup CMSIS_core_register
xorjoep	3:4098b9d3d571	447	\defgroup CMSIS_SCB System Control Block (SCB)
xorjoep	3:4098b9d3d571	448	\brief Type definitions for the System Control Block Registers
xorjoep	3:4098b9d3d571	449	@{
xorjoep	3:4098b9d3d571	450	*/
xorjoep	3:4098b9d3d571	451
xorjoep	3:4098b9d3d571	452	/**
xorjoep	3:4098b9d3d571	453	\brief Structure type to access the System Control Block (SCB).
xorjoep	3:4098b9d3d571	454	*/
xorjoep	3:4098b9d3d571	455	typedef struct
xorjoep	3:4098b9d3d571	456	{
xorjoep	3:4098b9d3d571	457	__IM uint32_t CPUID; /!< Offset: 0x000 (R/ ) CPUID Base Register /
xorjoep	3:4098b9d3d571	458	__IOM uint32_t ICSR; /!< Offset: 0x004 (R/W) Interrupt Control and State Register /
xorjoep	3:4098b9d3d571	459	__IOM uint32_t VTOR; /!< Offset: 0x008 (R/W) Vector Table Offset Register /
xorjoep	3:4098b9d3d571	460	__IOM uint32_t AIRCR; /!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register /
xorjoep	3:4098b9d3d571	461	__IOM uint32_t SCR; /!< Offset: 0x010 (R/W) System Control Register /
xorjoep	3:4098b9d3d571	462	__IOM uint32_t CCR; /!< Offset: 0x014 (R/W) Configuration Control Register /
xorjoep	3:4098b9d3d571	463	__IOM uint8_t SHPR[12U]; /!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) /
xorjoep	3:4098b9d3d571	464	__IOM uint32_t SHCSR; /!< Offset: 0x024 (R/W) System Handler Control and State Register /
xorjoep	3:4098b9d3d571	465	__IOM uint32_t CFSR; /!< Offset: 0x028 (R/W) Configurable Fault Status Register /
xorjoep	3:4098b9d3d571	466	__IOM uint32_t HFSR; /!< Offset: 0x02C (R/W) HardFault Status Register /
xorjoep	3:4098b9d3d571	467	__IOM uint32_t DFSR; /!< Offset: 0x030 (R/W) Debug Fault Status Register /
xorjoep	3:4098b9d3d571	468	__IOM uint32_t MMFAR; /!< Offset: 0x034 (R/W) MemManage Fault Address Register /
xorjoep	3:4098b9d3d571	469	__IOM uint32_t BFAR; /!< Offset: 0x038 (R/W) BusFault Address Register /
xorjoep	3:4098b9d3d571	470	__IOM uint32_t AFSR; /!< Offset: 0x03C (R/W) Auxiliary Fault Status Register /
xorjoep	3:4098b9d3d571	471	__IM uint32_t ID_PFR[2U]; /!< Offset: 0x040 (R/ ) Processor Feature Register /
xorjoep	3:4098b9d3d571	472	__IM uint32_t ID_DFR; /!< Offset: 0x048 (R/ ) Debug Feature Register /
xorjoep	3:4098b9d3d571	473	__IM uint32_t ID_AFR; /!< Offset: 0x04C (R/ ) Auxiliary Feature Register /
xorjoep	3:4098b9d3d571	474	__IM uint32_t ID_MFR[4U]; /!< Offset: 0x050 (R/ ) Memory Model Feature Register /
xorjoep	3:4098b9d3d571	475	__IM uint32_t ID_ISAR[5U]; /!< Offset: 0x060 (R/ ) Instruction Set Attributes Register /
xorjoep	3:4098b9d3d571	476	uint32_t RESERVED0[1U];
xorjoep	3:4098b9d3d571	477	__IM uint32_t CLIDR; /!< Offset: 0x078 (R/ ) Cache Level ID register /
xorjoep	3:4098b9d3d571	478	__IM uint32_t CTR; /!< Offset: 0x07C (R/ ) Cache Type register /
xorjoep	3:4098b9d3d571	479	__IM uint32_t CCSIDR; /!< Offset: 0x080 (R/ ) Cache Size ID Register /
xorjoep	3:4098b9d3d571	480	__IOM uint32_t CSSELR; /!< Offset: 0x084 (R/W) Cache Size Selection Register /
xorjoep	3:4098b9d3d571	481	__IOM uint32_t CPACR; /!< Offset: 0x088 (R/W) Coprocessor Access Control Register /
xorjoep	3:4098b9d3d571	482	uint32_t RESERVED3[93U];
xorjoep	3:4098b9d3d571	483	__OM uint32_t STIR; /!< Offset: 0x200 ( /W) Software Triggered Interrupt Register /
xorjoep	3:4098b9d3d571	484	uint32_t RESERVED4[15U];
xorjoep	3:4098b9d3d571	485	__IM uint32_t MVFR0; /!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 /
xorjoep	3:4098b9d3d571	486	__IM uint32_t MVFR1; /!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 /
xorjoep	3:4098b9d3d571	487	__IM uint32_t MVFR2; /!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 /
xorjoep	3:4098b9d3d571	488	uint32_t RESERVED5[1U];
xorjoep	3:4098b9d3d571	489	__OM uint32_t ICIALLU; /!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU /
xorjoep	3:4098b9d3d571	490	uint32_t RESERVED6[1U];
xorjoep	3:4098b9d3d571	491	__OM uint32_t ICIMVAU; /!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU /
xorjoep	3:4098b9d3d571	492	__OM uint32_t DCIMVAC; /!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC /
xorjoep	3:4098b9d3d571	493	__OM uint32_t DCISW; /!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way /
xorjoep	3:4098b9d3d571	494	__OM uint32_t DCCMVAU; /!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU /
xorjoep	3:4098b9d3d571	495	__OM uint32_t DCCMVAC; /!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC /
xorjoep	3:4098b9d3d571	496	__OM uint32_t DCCSW; /!< Offset: 0x26C ( /W) D-Cache Clean by Set-way /
xorjoep	3:4098b9d3d571	497	__OM uint32_t DCCIMVAC; /!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC /
xorjoep	3:4098b9d3d571	498	__OM uint32_t DCCISW; /!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way /
xorjoep	3:4098b9d3d571	499	uint32_t RESERVED7[6U];
xorjoep	3:4098b9d3d571	500	__IOM uint32_t ITCMCR; /!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register /
xorjoep	3:4098b9d3d571	501	__IOM uint32_t DTCMCR; /!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers /
xorjoep	3:4098b9d3d571	502	__IOM uint32_t AHBPCR; /!< Offset: 0x298 (R/W) AHBP Control Register /
xorjoep	3:4098b9d3d571	503	__IOM uint32_t CACR; /!< Offset: 0x29C (R/W) L1 Cache Control Register /
xorjoep	3:4098b9d3d571	504	__IOM uint32_t AHBSCR; /!< Offset: 0x2A0 (R/W) AHB Slave Control Register /
xorjoep	3:4098b9d3d571	505	uint32_t RESERVED8[1U];
xorjoep	3:4098b9d3d571	506	__IOM uint32_t ABFSR; /!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register /
xorjoep	3:4098b9d3d571	507	} SCB_Type;
xorjoep	3:4098b9d3d571	508
xorjoep	3:4098b9d3d571	509	/* SCB CPUID Register Definitions */
xorjoep	3:4098b9d3d571	510	#define SCB_CPUID_IMPLEMENTER_Pos 24U /!< SCB CPUID: IMPLEMENTER Position /
xorjoep	3:4098b9d3d571	511	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
xorjoep	3:4098b9d3d571	512
xorjoep	3:4098b9d3d571	513	#define SCB_CPUID_VARIANT_Pos 20U /!< SCB CPUID: VARIANT Position /
xorjoep	3:4098b9d3d571	514	#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
xorjoep	3:4098b9d3d571	515
xorjoep	3:4098b9d3d571	516	#define SCB_CPUID_ARCHITECTURE_Pos 16U /!< SCB CPUID: ARCHITECTURE Position /
xorjoep	3:4098b9d3d571	517	#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /!< SCB CPUID: ARCHITECTURE Mask /
xorjoep	3:4098b9d3d571	518
xorjoep	3:4098b9d3d571	519	#define SCB_CPUID_PARTNO_Pos 4U /!< SCB CPUID: PARTNO Position /
xorjoep	3:4098b9d3d571	520	#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
xorjoep	3:4098b9d3d571	521
xorjoep	3:4098b9d3d571	522	#define SCB_CPUID_REVISION_Pos 0U /!< SCB CPUID: REVISION Position /
xorjoep	3:4098b9d3d571	523	#define SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/) /!< SCB CPUID: REVISION Mask /
xorjoep	3:4098b9d3d571	524
xorjoep	3:4098b9d3d571	525	/* SCB Interrupt Control State Register Definitions */
xorjoep	3:4098b9d3d571	526	#define SCB_ICSR_NMIPENDSET_Pos 31U /!< SCB ICSR: NMIPENDSET Position /
xorjoep	3:4098b9d3d571	527	#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /!< SCB ICSR: NMIPENDSET Mask /
xorjoep	3:4098b9d3d571	528
xorjoep	3:4098b9d3d571	529	#define SCB_ICSR_PENDSVSET_Pos 28U /!< SCB ICSR: PENDSVSET Position /
xorjoep	3:4098b9d3d571	530	#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
xorjoep	3:4098b9d3d571	531
xorjoep	3:4098b9d3d571	532	#define SCB_ICSR_PENDSVCLR_Pos 27U /!< SCB ICSR: PENDSVCLR Position /
xorjoep	3:4098b9d3d571	533	#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
xorjoep	3:4098b9d3d571	534
xorjoep	3:4098b9d3d571	535	#define SCB_ICSR_PENDSTSET_Pos 26U /!< SCB ICSR: PENDSTSET Position /
xorjoep	3:4098b9d3d571	536	#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
xorjoep	3:4098b9d3d571	537
xorjoep	3:4098b9d3d571	538	#define SCB_ICSR_PENDSTCLR_Pos 25U /!< SCB ICSR: PENDSTCLR Position /
xorjoep	3:4098b9d3d571	539	#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
xorjoep	3:4098b9d3d571	540
xorjoep	3:4098b9d3d571	541	#define SCB_ICSR_ISRPREEMPT_Pos 23U /!< SCB ICSR: ISRPREEMPT Position /
xorjoep	3:4098b9d3d571	542	#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
xorjoep	3:4098b9d3d571	543
xorjoep	3:4098b9d3d571	544	#define SCB_ICSR_ISRPENDING_Pos 22U /!< SCB ICSR: ISRPENDING Position /
xorjoep	3:4098b9d3d571	545	#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
xorjoep	3:4098b9d3d571	546
xorjoep	3:4098b9d3d571	547	#define SCB_ICSR_VECTPENDING_Pos 12U /!< SCB ICSR: VECTPENDING Position /
xorjoep	3:4098b9d3d571	548	#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
xorjoep	3:4098b9d3d571	549
xorjoep	3:4098b9d3d571	550	#define SCB_ICSR_RETTOBASE_Pos 11U /!< SCB ICSR: RETTOBASE Position /
xorjoep	3:4098b9d3d571	551	#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
xorjoep	3:4098b9d3d571	552
xorjoep	3:4098b9d3d571	553	#define SCB_ICSR_VECTACTIVE_Pos 0U /!< SCB ICSR: VECTACTIVE Position /
xorjoep	3:4098b9d3d571	554	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/) /!< SCB ICSR: VECTACTIVE Mask /
xorjoep	3:4098b9d3d571	555
xorjoep	3:4098b9d3d571	556	/* SCB Vector Table Offset Register Definitions */
xorjoep	3:4098b9d3d571	557	#define SCB_VTOR_TBLOFF_Pos 7U /!< SCB VTOR: TBLOFF Position /
xorjoep	3:4098b9d3d571	558	#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
xorjoep	3:4098b9d3d571	559
xorjoep	3:4098b9d3d571	560	/* SCB Application Interrupt and Reset Control Register Definitions */
xorjoep	3:4098b9d3d571	561	#define SCB_AIRCR_VECTKEY_Pos 16U /!< SCB AIRCR: VECTKEY Position /
xorjoep	3:4098b9d3d571	562	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
xorjoep	3:4098b9d3d571	563
xorjoep	3:4098b9d3d571	564	#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /!< SCB AIRCR: VECTKEYSTAT Position /
xorjoep	3:4098b9d3d571	565	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
xorjoep	3:4098b9d3d571	566
xorjoep	3:4098b9d3d571	567	#define SCB_AIRCR_ENDIANESS_Pos 15U /!< SCB AIRCR: ENDIANESS Position /
xorjoep	3:4098b9d3d571	568	#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
xorjoep	3:4098b9d3d571	569
xorjoep	3:4098b9d3d571	570	#define SCB_AIRCR_PRIGROUP_Pos 8U /!< SCB AIRCR: PRIGROUP Position /
xorjoep	3:4098b9d3d571	571	#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /!< SCB AIRCR: PRIGROUP Mask /
xorjoep	3:4098b9d3d571	572
xorjoep	3:4098b9d3d571	573	#define SCB_AIRCR_SYSRESETREQ_Pos 2U /!< SCB AIRCR: SYSRESETREQ Position /
xorjoep	3:4098b9d3d571	574	#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
xorjoep	3:4098b9d3d571	575
xorjoep	3:4098b9d3d571	576	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /!< SCB AIRCR: VECTCLRACTIVE Position /
xorjoep	3:4098b9d3d571	577	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
xorjoep	3:4098b9d3d571	578
xorjoep	3:4098b9d3d571	579	#define SCB_AIRCR_VECTRESET_Pos 0U /!< SCB AIRCR: VECTRESET Position /
xorjoep	3:4098b9d3d571	580	#define SCB_AIRCR_VECTRESET_Msk (1UL /<< SCB_AIRCR_VECTRESET_Pos/) /!< SCB AIRCR: VECTRESET Mask /
xorjoep	3:4098b9d3d571	581
xorjoep	3:4098b9d3d571	582	/* SCB System Control Register Definitions */
xorjoep	3:4098b9d3d571	583	#define SCB_SCR_SEVONPEND_Pos 4U /!< SCB SCR: SEVONPEND Position /
xorjoep	3:4098b9d3d571	584	#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
xorjoep	3:4098b9d3d571	585
xorjoep	3:4098b9d3d571	586	#define SCB_SCR_SLEEPDEEP_Pos 2U /!< SCB SCR: SLEEPDEEP Position /
xorjoep	3:4098b9d3d571	587	#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
xorjoep	3:4098b9d3d571	588
xorjoep	3:4098b9d3d571	589	#define SCB_SCR_SLEEPONEXIT_Pos 1U /!< SCB SCR: SLEEPONEXIT Position /
xorjoep	3:4098b9d3d571	590	#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
xorjoep	3:4098b9d3d571	591
xorjoep	3:4098b9d3d571	592	/* SCB Configuration Control Register Definitions */
xorjoep	3:4098b9d3d571	593	#define SCB_CCR_BP_Pos 18U /!< SCB CCR: Branch prediction enable bit Position /
xorjoep	3:4098b9d3d571	594	#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /!< SCB CCR: Branch prediction enable bit Mask /
xorjoep	3:4098b9d3d571	595
xorjoep	3:4098b9d3d571	596	#define SCB_CCR_IC_Pos 17U /!< SCB CCR: Instruction cache enable bit Position /
xorjoep	3:4098b9d3d571	597	#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /!< SCB CCR: Instruction cache enable bit Mask /
xorjoep	3:4098b9d3d571	598
xorjoep	3:4098b9d3d571	599	#define SCB_CCR_DC_Pos 16U /!< SCB CCR: Cache enable bit Position /
xorjoep	3:4098b9d3d571	600	#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /!< SCB CCR: Cache enable bit Mask /
xorjoep	3:4098b9d3d571	601
xorjoep	3:4098b9d3d571	602	#define SCB_CCR_STKALIGN_Pos 9U /!< SCB CCR: STKALIGN Position /
xorjoep	3:4098b9d3d571	603	#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /!< SCB CCR: STKALIGN Mask /
xorjoep	3:4098b9d3d571	604
xorjoep	3:4098b9d3d571	605	#define SCB_CCR_BFHFNMIGN_Pos 8U /!< SCB CCR: BFHFNMIGN Position /
xorjoep	3:4098b9d3d571	606	#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
xorjoep	3:4098b9d3d571	607
xorjoep	3:4098b9d3d571	608	#define SCB_CCR_DIV_0_TRP_Pos 4U /!< SCB CCR: DIV_0_TRP Position /
xorjoep	3:4098b9d3d571	609	#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
xorjoep	3:4098b9d3d571	610
xorjoep	3:4098b9d3d571	611	#define SCB_CCR_UNALIGN_TRP_Pos 3U /!< SCB CCR: UNALIGN_TRP Position /
xorjoep	3:4098b9d3d571	612	#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
xorjoep	3:4098b9d3d571	613
xorjoep	3:4098b9d3d571	614	#define SCB_CCR_USERSETMPEND_Pos 1U /!< SCB CCR: USERSETMPEND Position /
xorjoep	3:4098b9d3d571	615	#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
xorjoep	3:4098b9d3d571	616
xorjoep	3:4098b9d3d571	617	#define SCB_CCR_NONBASETHRDENA_Pos 0U /!< SCB CCR: NONBASETHRDENA Position /
xorjoep	3:4098b9d3d571	618	#define SCB_CCR_NONBASETHRDENA_Msk (1UL /<< SCB_CCR_NONBASETHRDENA_Pos/) /!< SCB CCR: NONBASETHRDENA Mask /
xorjoep	3:4098b9d3d571	619
xorjoep	3:4098b9d3d571	620	/* SCB System Handler Control and State Register Definitions */
xorjoep	3:4098b9d3d571	621	#define SCB_SHCSR_USGFAULTENA_Pos 18U /!< SCB SHCSR: USGFAULTENA Position /
xorjoep	3:4098b9d3d571	622	#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /!< SCB SHCSR: USGFAULTENA Mask /
xorjoep	3:4098b9d3d571	623
xorjoep	3:4098b9d3d571	624	#define SCB_SHCSR_BUSFAULTENA_Pos 17U /!< SCB SHCSR: BUSFAULTENA Position /
xorjoep	3:4098b9d3d571	625	#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /!< SCB SHCSR: BUSFAULTENA Mask /
xorjoep	3:4098b9d3d571	626
xorjoep	3:4098b9d3d571	627	#define SCB_SHCSR_MEMFAULTENA_Pos 16U /!< SCB SHCSR: MEMFAULTENA Position /
xorjoep	3:4098b9d3d571	628	#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /!< SCB SHCSR: MEMFAULTENA Mask /
xorjoep	3:4098b9d3d571	629
xorjoep	3:4098b9d3d571	630	#define SCB_SHCSR_SVCALLPENDED_Pos 15U /!< SCB SHCSR: SVCALLPENDED Position /
xorjoep	3:4098b9d3d571	631	#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
xorjoep	3:4098b9d3d571	632
xorjoep	3:4098b9d3d571	633	#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /!< SCB SHCSR: BUSFAULTPENDED Position /
xorjoep	3:4098b9d3d571	634	#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /!< SCB SHCSR: BUSFAULTPENDED Mask /
xorjoep	3:4098b9d3d571	635
xorjoep	3:4098b9d3d571	636	#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /!< SCB SHCSR: MEMFAULTPENDED Position /
xorjoep	3:4098b9d3d571	637	#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /!< SCB SHCSR: MEMFAULTPENDED Mask /
xorjoep	3:4098b9d3d571	638
xorjoep	3:4098b9d3d571	639	#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /!< SCB SHCSR: USGFAULTPENDED Position /
xorjoep	3:4098b9d3d571	640	#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /!< SCB SHCSR: USGFAULTPENDED Mask /
xorjoep	3:4098b9d3d571	641
xorjoep	3:4098b9d3d571	642	#define SCB_SHCSR_SYSTICKACT_Pos 11U /!< SCB SHCSR: SYSTICKACT Position /
xorjoep	3:4098b9d3d571	643	#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
xorjoep	3:4098b9d3d571	644
xorjoep	3:4098b9d3d571	645	#define SCB_SHCSR_PENDSVACT_Pos 10U /!< SCB SHCSR: PENDSVACT Position /
xorjoep	3:4098b9d3d571	646	#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
xorjoep	3:4098b9d3d571	647
xorjoep	3:4098b9d3d571	648	#define SCB_SHCSR_MONITORACT_Pos 8U /!< SCB SHCSR: MONITORACT Position /
xorjoep	3:4098b9d3d571	649	#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /!< SCB SHCSR: MONITORACT Mask /
xorjoep	3:4098b9d3d571	650
xorjoep	3:4098b9d3d571	651	#define SCB_SHCSR_SVCALLACT_Pos 7U /!< SCB SHCSR: SVCALLACT Position /
xorjoep	3:4098b9d3d571	652	#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
xorjoep	3:4098b9d3d571	653
xorjoep	3:4098b9d3d571	654	#define SCB_SHCSR_USGFAULTACT_Pos 3U /!< SCB SHCSR: USGFAULTACT Position /
xorjoep	3:4098b9d3d571	655	#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /!< SCB SHCSR: USGFAULTACT Mask /
xorjoep	3:4098b9d3d571	656
xorjoep	3:4098b9d3d571	657	#define SCB_SHCSR_BUSFAULTACT_Pos 1U /!< SCB SHCSR: BUSFAULTACT Position /
xorjoep	3:4098b9d3d571	658	#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /!< SCB SHCSR: BUSFAULTACT Mask /
xorjoep	3:4098b9d3d571	659
xorjoep	3:4098b9d3d571	660	#define SCB_SHCSR_MEMFAULTACT_Pos 0U /!< SCB SHCSR: MEMFAULTACT Position /
xorjoep	3:4098b9d3d571	661	#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /<< SCB_SHCSR_MEMFAULTACT_Pos/) /!< SCB SHCSR: MEMFAULTACT Mask /
xorjoep	3:4098b9d3d571	662
xorjoep	3:4098b9d3d571	663	/* SCB Configurable Fault Status Register Definitions */
xorjoep	3:4098b9d3d571	664	#define SCB_CFSR_USGFAULTSR_Pos 16U /!< SCB CFSR: Usage Fault Status Register Position /
xorjoep	3:4098b9d3d571	665	#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /!< SCB CFSR: Usage Fault Status Register Mask /
xorjoep	3:4098b9d3d571	666
xorjoep	3:4098b9d3d571	667	#define SCB_CFSR_BUSFAULTSR_Pos 8U /!< SCB CFSR: Bus Fault Status Register Position /
xorjoep	3:4098b9d3d571	668	#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /!< SCB CFSR: Bus Fault Status Register Mask /
xorjoep	3:4098b9d3d571	669
xorjoep	3:4098b9d3d571	670	#define SCB_CFSR_MEMFAULTSR_Pos 0U /!< SCB CFSR: Memory Manage Fault Status Register Position /
xorjoep	3:4098b9d3d571	671	#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /<< SCB_CFSR_MEMFAULTSR_Pos/) /!< SCB CFSR: Memory Manage Fault Status Register Mask /
xorjoep	3:4098b9d3d571	672
xorjoep	3:4098b9d3d571	673	/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
xorjoep	3:4098b9d3d571	674	#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /!< SCB CFSR (MMFSR): MMARVALID Position /
xorjoep	3:4098b9d3d571	675	#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /!< SCB CFSR (MMFSR): MMARVALID Mask /
xorjoep	3:4098b9d3d571	676
xorjoep	3:4098b9d3d571	677	#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /!< SCB CFSR (MMFSR): MLSPERR Position /
xorjoep	3:4098b9d3d571	678	#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /!< SCB CFSR (MMFSR): MLSPERR Mask /
xorjoep	3:4098b9d3d571	679
xorjoep	3:4098b9d3d571	680	#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /!< SCB CFSR (MMFSR): MSTKERR Position /
xorjoep	3:4098b9d3d571	681	#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /!< SCB CFSR (MMFSR): MSTKERR Mask /
xorjoep	3:4098b9d3d571	682
xorjoep	3:4098b9d3d571	683	#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /!< SCB CFSR (MMFSR): MUNSTKERR Position /
xorjoep	3:4098b9d3d571	684	#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /!< SCB CFSR (MMFSR): MUNSTKERR Mask /
xorjoep	3:4098b9d3d571	685
xorjoep	3:4098b9d3d571	686	#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /!< SCB CFSR (MMFSR): DACCVIOL Position /
xorjoep	3:4098b9d3d571	687	#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /!< SCB CFSR (MMFSR): DACCVIOL Mask /
xorjoep	3:4098b9d3d571	688
xorjoep	3:4098b9d3d571	689	#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /!< SCB CFSR (MMFSR): IACCVIOL Position /
xorjoep	3:4098b9d3d571	690	#define SCB_CFSR_IACCVIOL_Msk (1UL /<< SCB_CFSR_IACCVIOL_Pos/) /!< SCB CFSR (MMFSR): IACCVIOL Mask /
xorjoep	3:4098b9d3d571	691
xorjoep	3:4098b9d3d571	692	/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
xorjoep	3:4098b9d3d571	693	#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /!< SCB CFSR (BFSR): BFARVALID Position /
xorjoep	3:4098b9d3d571	694	#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /!< SCB CFSR (BFSR): BFARVALID Mask /
xorjoep	3:4098b9d3d571	695
xorjoep	3:4098b9d3d571	696	#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /!< SCB CFSR (BFSR): LSPERR Position /
xorjoep	3:4098b9d3d571	697	#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /!< SCB CFSR (BFSR): LSPERR Mask /
xorjoep	3:4098b9d3d571	698
xorjoep	3:4098b9d3d571	699	#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /!< SCB CFSR (BFSR): STKERR Position /
xorjoep	3:4098b9d3d571	700	#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /!< SCB CFSR (BFSR): STKERR Mask /
xorjoep	3:4098b9d3d571	701
xorjoep	3:4098b9d3d571	702	#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /!< SCB CFSR (BFSR): UNSTKERR Position /
xorjoep	3:4098b9d3d571	703	#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /!< SCB CFSR (BFSR): UNSTKERR Mask /
xorjoep	3:4098b9d3d571	704
xorjoep	3:4098b9d3d571	705	#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /!< SCB CFSR (BFSR): IMPRECISERR Position /
xorjoep	3:4098b9d3d571	706	#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /!< SCB CFSR (BFSR): IMPRECISERR Mask /
xorjoep	3:4098b9d3d571	707
xorjoep	3:4098b9d3d571	708	#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /!< SCB CFSR (BFSR): PRECISERR Position /
xorjoep	3:4098b9d3d571	709	#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /!< SCB CFSR (BFSR): PRECISERR Mask /
xorjoep	3:4098b9d3d571	710
xorjoep	3:4098b9d3d571	711	#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /!< SCB CFSR (BFSR): IBUSERR Position /
xorjoep	3:4098b9d3d571	712	#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /!< SCB CFSR (BFSR): IBUSERR Mask /
xorjoep	3:4098b9d3d571	713
xorjoep	3:4098b9d3d571	714	/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
xorjoep	3:4098b9d3d571	715	#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /!< SCB CFSR (UFSR): DIVBYZERO Position /
xorjoep	3:4098b9d3d571	716	#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /!< SCB CFSR (UFSR): DIVBYZERO Mask /
xorjoep	3:4098b9d3d571	717
xorjoep	3:4098b9d3d571	718	#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /!< SCB CFSR (UFSR): UNALIGNED Position /
xorjoep	3:4098b9d3d571	719	#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /!< SCB CFSR (UFSR): UNALIGNED Mask /
xorjoep	3:4098b9d3d571	720
xorjoep	3:4098b9d3d571	721	#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /!< SCB CFSR (UFSR): NOCP Position /
xorjoep	3:4098b9d3d571	722	#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /!< SCB CFSR (UFSR): NOCP Mask /
xorjoep	3:4098b9d3d571	723
xorjoep	3:4098b9d3d571	724	#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /!< SCB CFSR (UFSR): INVPC Position /
xorjoep	3:4098b9d3d571	725	#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /!< SCB CFSR (UFSR): INVPC Mask /
xorjoep	3:4098b9d3d571	726
xorjoep	3:4098b9d3d571	727	#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /!< SCB CFSR (UFSR): INVSTATE Position /
xorjoep	3:4098b9d3d571	728	#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /!< SCB CFSR (UFSR): INVSTATE Mask /
xorjoep	3:4098b9d3d571	729
xorjoep	3:4098b9d3d571	730	#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /!< SCB CFSR (UFSR): UNDEFINSTR Position /
xorjoep	3:4098b9d3d571	731	#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /!< SCB CFSR (UFSR): UNDEFINSTR Mask /
xorjoep	3:4098b9d3d571	732
xorjoep	3:4098b9d3d571	733	/* SCB Hard Fault Status Register Definitions */
xorjoep	3:4098b9d3d571	734	#define SCB_HFSR_DEBUGEVT_Pos 31U /!< SCB HFSR: DEBUGEVT Position /
xorjoep	3:4098b9d3d571	735	#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /!< SCB HFSR: DEBUGEVT Mask /
xorjoep	3:4098b9d3d571	736
xorjoep	3:4098b9d3d571	737	#define SCB_HFSR_FORCED_Pos 30U /!< SCB HFSR: FORCED Position /
xorjoep	3:4098b9d3d571	738	#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /!< SCB HFSR: FORCED Mask /
xorjoep	3:4098b9d3d571	739
xorjoep	3:4098b9d3d571	740	#define SCB_HFSR_VECTTBL_Pos 1U /!< SCB HFSR: VECTTBL Position /
xorjoep	3:4098b9d3d571	741	#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /!< SCB HFSR: VECTTBL Mask /
xorjoep	3:4098b9d3d571	742
xorjoep	3:4098b9d3d571	743	/* SCB Debug Fault Status Register Definitions */
xorjoep	3:4098b9d3d571	744	#define SCB_DFSR_EXTERNAL_Pos 4U /!< SCB DFSR: EXTERNAL Position /
xorjoep	3:4098b9d3d571	745	#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /!< SCB DFSR: EXTERNAL Mask /
xorjoep	3:4098b9d3d571	746
xorjoep	3:4098b9d3d571	747	#define SCB_DFSR_VCATCH_Pos 3U /!< SCB DFSR: VCATCH Position /
xorjoep	3:4098b9d3d571	748	#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /!< SCB DFSR: VCATCH Mask /
xorjoep	3:4098b9d3d571	749
xorjoep	3:4098b9d3d571	750	#define SCB_DFSR_DWTTRAP_Pos 2U /!< SCB DFSR: DWTTRAP Position /
xorjoep	3:4098b9d3d571	751	#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /!< SCB DFSR: DWTTRAP Mask /
xorjoep	3:4098b9d3d571	752
xorjoep	3:4098b9d3d571	753	#define SCB_DFSR_BKPT_Pos 1U /!< SCB DFSR: BKPT Position /
xorjoep	3:4098b9d3d571	754	#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /!< SCB DFSR: BKPT Mask /
xorjoep	3:4098b9d3d571	755
xorjoep	3:4098b9d3d571	756	#define SCB_DFSR_HALTED_Pos 0U /!< SCB DFSR: HALTED Position /
xorjoep	3:4098b9d3d571	757	#define SCB_DFSR_HALTED_Msk (1UL /<< SCB_DFSR_HALTED_Pos/) /!< SCB DFSR: HALTED Mask /
xorjoep	3:4098b9d3d571	758
xorjoep	3:4098b9d3d571	759	/* SCB Cache Level ID Register Definitions */
xorjoep	3:4098b9d3d571	760	#define SCB_CLIDR_LOUU_Pos 27U /!< SCB CLIDR: LoUU Position /
xorjoep	3:4098b9d3d571	761	#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /!< SCB CLIDR: LoUU Mask /
xorjoep	3:4098b9d3d571	762
xorjoep	3:4098b9d3d571	763	#define SCB_CLIDR_LOC_Pos 24U /!< SCB CLIDR: LoC Position /
xorjoep	3:4098b9d3d571	764	#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /!< SCB CLIDR: LoC Mask /
xorjoep	3:4098b9d3d571	765
xorjoep	3:4098b9d3d571	766	/* SCB Cache Type Register Definitions */
xorjoep	3:4098b9d3d571	767	#define SCB_CTR_FORMAT_Pos 29U /!< SCB CTR: Format Position /
xorjoep	3:4098b9d3d571	768	#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /!< SCB CTR: Format Mask /
xorjoep	3:4098b9d3d571	769
xorjoep	3:4098b9d3d571	770	#define SCB_CTR_CWG_Pos 24U /!< SCB CTR: CWG Position /
xorjoep	3:4098b9d3d571	771	#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /!< SCB CTR: CWG Mask /
xorjoep	3:4098b9d3d571	772
xorjoep	3:4098b9d3d571	773	#define SCB_CTR_ERG_Pos 20U /!< SCB CTR: ERG Position /
xorjoep	3:4098b9d3d571	774	#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /!< SCB CTR: ERG Mask /
xorjoep	3:4098b9d3d571	775
xorjoep	3:4098b9d3d571	776	#define SCB_CTR_DMINLINE_Pos 16U /!< SCB CTR: DminLine Position /
xorjoep	3:4098b9d3d571	777	#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /!< SCB CTR: DminLine Mask /
xorjoep	3:4098b9d3d571	778
xorjoep	3:4098b9d3d571	779	#define SCB_CTR_IMINLINE_Pos 0U /!< SCB CTR: ImInLine Position /
xorjoep	3:4098b9d3d571	780	#define SCB_CTR_IMINLINE_Msk (0xFUL /<< SCB_CTR_IMINLINE_Pos/) /!< SCB CTR: ImInLine Mask /
xorjoep	3:4098b9d3d571	781
xorjoep	3:4098b9d3d571	782	/* SCB Cache Size ID Register Definitions */
xorjoep	3:4098b9d3d571	783	#define SCB_CCSIDR_WT_Pos 31U /!< SCB CCSIDR: WT Position /
xorjoep	3:4098b9d3d571	784	#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /!< SCB CCSIDR: WT Mask /
xorjoep	3:4098b9d3d571	785
xorjoep	3:4098b9d3d571	786	#define SCB_CCSIDR_WB_Pos 30U /!< SCB CCSIDR: WB Position /
xorjoep	3:4098b9d3d571	787	#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /!< SCB CCSIDR: WB Mask /
xorjoep	3:4098b9d3d571	788
xorjoep	3:4098b9d3d571	789	#define SCB_CCSIDR_RA_Pos 29U /!< SCB CCSIDR: RA Position /
xorjoep	3:4098b9d3d571	790	#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /!< SCB CCSIDR: RA Mask /
xorjoep	3:4098b9d3d571	791
xorjoep	3:4098b9d3d571	792	#define SCB_CCSIDR_WA_Pos 28U /!< SCB CCSIDR: WA Position /
xorjoep	3:4098b9d3d571	793	#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /!< SCB CCSIDR: WA Mask /
xorjoep	3:4098b9d3d571	794
xorjoep	3:4098b9d3d571	795	#define SCB_CCSIDR_NUMSETS_Pos 13U /!< SCB CCSIDR: NumSets Position /
xorjoep	3:4098b9d3d571	796	#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /!< SCB CCSIDR: NumSets Mask /
xorjoep	3:4098b9d3d571	797
xorjoep	3:4098b9d3d571	798	#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /!< SCB CCSIDR: Associativity Position /
xorjoep	3:4098b9d3d571	799	#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /!< SCB CCSIDR: Associativity Mask /
xorjoep	3:4098b9d3d571	800
xorjoep	3:4098b9d3d571	801	#define SCB_CCSIDR_LINESIZE_Pos 0U /!< SCB CCSIDR: LineSize Position /
xorjoep	3:4098b9d3d571	802	#define SCB_CCSIDR_LINESIZE_Msk (7UL /<< SCB_CCSIDR_LINESIZE_Pos/) /!< SCB CCSIDR: LineSize Mask /
xorjoep	3:4098b9d3d571	803
xorjoep	3:4098b9d3d571	804	/* SCB Cache Size Selection Register Definitions */
xorjoep	3:4098b9d3d571	805	#define SCB_CSSELR_LEVEL_Pos 1U /!< SCB CSSELR: Level Position /
xorjoep	3:4098b9d3d571	806	#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /!< SCB CSSELR: Level Mask /
xorjoep	3:4098b9d3d571	807
xorjoep	3:4098b9d3d571	808	#define SCB_CSSELR_IND_Pos 0U /!< SCB CSSELR: InD Position /
xorjoep	3:4098b9d3d571	809	#define SCB_CSSELR_IND_Msk (1UL /<< SCB_CSSELR_IND_Pos/) /!< SCB CSSELR: InD Mask /
xorjoep	3:4098b9d3d571	810
xorjoep	3:4098b9d3d571	811	/* SCB Software Triggered Interrupt Register Definitions */
xorjoep	3:4098b9d3d571	812	#define SCB_STIR_INTID_Pos 0U /!< SCB STIR: INTID Position /
xorjoep	3:4098b9d3d571	813	#define SCB_STIR_INTID_Msk (0x1FFUL /<< SCB_STIR_INTID_Pos/) /!< SCB STIR: INTID Mask /
xorjoep	3:4098b9d3d571	814
xorjoep	3:4098b9d3d571	815	/* SCB D-Cache Invalidate by Set-way Register Definitions */
xorjoep	3:4098b9d3d571	816	#define SCB_DCISW_WAY_Pos 30U /!< SCB DCISW: Way Position /
xorjoep	3:4098b9d3d571	817	#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /!< SCB DCISW: Way Mask /
xorjoep	3:4098b9d3d571	818
xorjoep	3:4098b9d3d571	819	#define SCB_DCISW_SET_Pos 5U /!< SCB DCISW: Set Position /
xorjoep	3:4098b9d3d571	820	#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /!< SCB DCISW: Set Mask /
xorjoep	3:4098b9d3d571	821
xorjoep	3:4098b9d3d571	822	/* SCB D-Cache Clean by Set-way Register Definitions */
xorjoep	3:4098b9d3d571	823	#define SCB_DCCSW_WAY_Pos 30U /!< SCB DCCSW: Way Position /
xorjoep	3:4098b9d3d571	824	#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /!< SCB DCCSW: Way Mask /
xorjoep	3:4098b9d3d571	825
xorjoep	3:4098b9d3d571	826	#define SCB_DCCSW_SET_Pos 5U /!< SCB DCCSW: Set Position /
xorjoep	3:4098b9d3d571	827	#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /!< SCB DCCSW: Set Mask /
xorjoep	3:4098b9d3d571	828
xorjoep	3:4098b9d3d571	829	/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
xorjoep	3:4098b9d3d571	830	#define SCB_DCCISW_WAY_Pos 30U /!< SCB DCCISW: Way Position /
xorjoep	3:4098b9d3d571	831	#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /!< SCB DCCISW: Way Mask /
xorjoep	3:4098b9d3d571	832
xorjoep	3:4098b9d3d571	833	#define SCB_DCCISW_SET_Pos 5U /!< SCB DCCISW: Set Position /
xorjoep	3:4098b9d3d571	834	#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /!< SCB DCCISW: Set Mask /
xorjoep	3:4098b9d3d571	835
xorjoep	3:4098b9d3d571	836	/* Instruction Tightly-Coupled Memory Control Register Definitions */
xorjoep	3:4098b9d3d571	837	#define SCB_ITCMCR_SZ_Pos 3U /!< SCB ITCMCR: SZ Position /
xorjoep	3:4098b9d3d571	838	#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /!< SCB ITCMCR: SZ Mask /
xorjoep	3:4098b9d3d571	839
xorjoep	3:4098b9d3d571	840	#define SCB_ITCMCR_RETEN_Pos 2U /!< SCB ITCMCR: RETEN Position /
xorjoep	3:4098b9d3d571	841	#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /!< SCB ITCMCR: RETEN Mask /
xorjoep	3:4098b9d3d571	842
xorjoep	3:4098b9d3d571	843	#define SCB_ITCMCR_RMW_Pos 1U /!< SCB ITCMCR: RMW Position /
xorjoep	3:4098b9d3d571	844	#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /!< SCB ITCMCR: RMW Mask /
xorjoep	3:4098b9d3d571	845
xorjoep	3:4098b9d3d571	846	#define SCB_ITCMCR_EN_Pos 0U /!< SCB ITCMCR: EN Position /
xorjoep	3:4098b9d3d571	847	#define SCB_ITCMCR_EN_Msk (1UL /<< SCB_ITCMCR_EN_Pos/) /!< SCB ITCMCR: EN Mask /
xorjoep	3:4098b9d3d571	848
xorjoep	3:4098b9d3d571	849	/* Data Tightly-Coupled Memory Control Register Definitions */
xorjoep	3:4098b9d3d571	850	#define SCB_DTCMCR_SZ_Pos 3U /!< SCB DTCMCR: SZ Position /
xorjoep	3:4098b9d3d571	851	#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /!< SCB DTCMCR: SZ Mask /
xorjoep	3:4098b9d3d571	852
xorjoep	3:4098b9d3d571	853	#define SCB_DTCMCR_RETEN_Pos 2U /!< SCB DTCMCR: RETEN Position /
xorjoep	3:4098b9d3d571	854	#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /!< SCB DTCMCR: RETEN Mask /
xorjoep	3:4098b9d3d571	855
xorjoep	3:4098b9d3d571	856	#define SCB_DTCMCR_RMW_Pos 1U /!< SCB DTCMCR: RMW Position /
xorjoep	3:4098b9d3d571	857	#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /!< SCB DTCMCR: RMW Mask /
xorjoep	3:4098b9d3d571	858
xorjoep	3:4098b9d3d571	859	#define SCB_DTCMCR_EN_Pos 0U /!< SCB DTCMCR: EN Position /
xorjoep	3:4098b9d3d571	860	#define SCB_DTCMCR_EN_Msk (1UL /<< SCB_DTCMCR_EN_Pos/) /!< SCB DTCMCR: EN Mask /
xorjoep	3:4098b9d3d571	861
xorjoep	3:4098b9d3d571	862	/* AHBP Control Register Definitions */
xorjoep	3:4098b9d3d571	863	#define SCB_AHBPCR_SZ_Pos 1U /!< SCB AHBPCR: SZ Position /
xorjoep	3:4098b9d3d571	864	#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /!< SCB AHBPCR: SZ Mask /
xorjoep	3:4098b9d3d571	865
xorjoep	3:4098b9d3d571	866	#define SCB_AHBPCR_EN_Pos 0U /!< SCB AHBPCR: EN Position /
xorjoep	3:4098b9d3d571	867	#define SCB_AHBPCR_EN_Msk (1UL /<< SCB_AHBPCR_EN_Pos/) /!< SCB AHBPCR: EN Mask /
xorjoep	3:4098b9d3d571	868
xorjoep	3:4098b9d3d571	869	/* L1 Cache Control Register Definitions */
xorjoep	3:4098b9d3d571	870	#define SCB_CACR_FORCEWT_Pos 2U /!< SCB CACR: FORCEWT Position /
xorjoep	3:4098b9d3d571	871	#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /!< SCB CACR: FORCEWT Mask /
xorjoep	3:4098b9d3d571	872
xorjoep	3:4098b9d3d571	873	#define SCB_CACR_ECCEN_Pos 1U /!< SCB CACR: ECCEN Position /
xorjoep	3:4098b9d3d571	874	#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /!< SCB CACR: ECCEN Mask /
xorjoep	3:4098b9d3d571	875
xorjoep	3:4098b9d3d571	876	#define SCB_CACR_SIWT_Pos 0U /!< SCB CACR: SIWT Position /
xorjoep	3:4098b9d3d571	877	#define SCB_CACR_SIWT_Msk (1UL /<< SCB_CACR_SIWT_Pos/) /!< SCB CACR: SIWT Mask /
xorjoep	3:4098b9d3d571	878
xorjoep	3:4098b9d3d571	879	/* AHBS Control Register Definitions */
xorjoep	3:4098b9d3d571	880	#define SCB_AHBSCR_INITCOUNT_Pos 11U /!< SCB AHBSCR: INITCOUNT Position /
xorjoep	3:4098b9d3d571	881	#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /!< SCB AHBSCR: INITCOUNT Mask /
xorjoep	3:4098b9d3d571	882
xorjoep	3:4098b9d3d571	883	#define SCB_AHBSCR_TPRI_Pos 2U /!< SCB AHBSCR: TPRI Position /
xorjoep	3:4098b9d3d571	884	#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /!< SCB AHBSCR: TPRI Mask /
xorjoep	3:4098b9d3d571	885
xorjoep	3:4098b9d3d571	886	#define SCB_AHBSCR_CTL_Pos 0U /!< SCB AHBSCR: CTL Position/
xorjoep	3:4098b9d3d571	887	#define SCB_AHBSCR_CTL_Msk (3UL /<< SCB_AHBPCR_CTL_Pos/) /!< SCB AHBSCR: CTL Mask /
xorjoep	3:4098b9d3d571	888
xorjoep	3:4098b9d3d571	889	/* Auxiliary Bus Fault Status Register Definitions */
xorjoep	3:4098b9d3d571	890	#define SCB_ABFSR_AXIMTYPE_Pos 8U /!< SCB ABFSR: AXIMTYPE Position/
xorjoep	3:4098b9d3d571	891	#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /!< SCB ABFSR: AXIMTYPE Mask /
xorjoep	3:4098b9d3d571	892
xorjoep	3:4098b9d3d571	893	#define SCB_ABFSR_EPPB_Pos 4U /!< SCB ABFSR: EPPB Position/
xorjoep	3:4098b9d3d571	894	#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /!< SCB ABFSR: EPPB Mask /
xorjoep	3:4098b9d3d571	895
xorjoep	3:4098b9d3d571	896	#define SCB_ABFSR_AXIM_Pos 3U /!< SCB ABFSR: AXIM Position/
xorjoep	3:4098b9d3d571	897	#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /!< SCB ABFSR: AXIM Mask /
xorjoep	3:4098b9d3d571	898
xorjoep	3:4098b9d3d571	899	#define SCB_ABFSR_AHBP_Pos 2U /!< SCB ABFSR: AHBP Position/
xorjoep	3:4098b9d3d571	900	#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /!< SCB ABFSR: AHBP Mask /
xorjoep	3:4098b9d3d571	901
xorjoep	3:4098b9d3d571	902	#define SCB_ABFSR_DTCM_Pos 1U /!< SCB ABFSR: DTCM Position/
xorjoep	3:4098b9d3d571	903	#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /!< SCB ABFSR: DTCM Mask /
xorjoep	3:4098b9d3d571	904
xorjoep	3:4098b9d3d571	905	#define SCB_ABFSR_ITCM_Pos 0U /!< SCB ABFSR: ITCM Position/
xorjoep	3:4098b9d3d571	906	#define SCB_ABFSR_ITCM_Msk (1UL /<< SCB_ABFSR_ITCM_Pos/) /!< SCB ABFSR: ITCM Mask /
xorjoep	3:4098b9d3d571	907
xorjoep	3:4098b9d3d571	908	/@} end of group CMSIS_SCB /
xorjoep	3:4098b9d3d571	909
xorjoep	3:4098b9d3d571	910
xorjoep	3:4098b9d3d571	911	/**
xorjoep	3:4098b9d3d571	912	\ingroup CMSIS_core_register
xorjoep	3:4098b9d3d571	913	\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
xorjoep	3:4098b9d3d571	914	\brief Type definitions for the System Control and ID Register not in the SCB
xorjoep	3:4098b9d3d571	915	@{
xorjoep	3:4098b9d3d571	916	*/
xorjoep	3:4098b9d3d571	917
xorjoep	3:4098b9d3d571	918	/**
xorjoep	3:4098b9d3d571	919	\brief Structure type to access the System Control and ID Register not in the SCB.
xorjoep	3:4098b9d3d571	920	*/
xorjoep	3:4098b9d3d571	921	typedef struct
xorjoep	3:4098b9d3d571	922	{
xorjoep	3:4098b9d3d571	923	uint32_t RESERVED0[1U];
xorjoep	3:4098b9d3d571	924	__IM uint32_t ICTR; /!< Offset: 0x004 (R/ ) Interrupt Controller Type Register /
xorjoep	3:4098b9d3d571	925	__IOM uint32_t ACTLR; /!< Offset: 0x008 (R/W) Auxiliary Control Register /
xorjoep	3:4098b9d3d571	926	} SCnSCB_Type;
xorjoep	3:4098b9d3d571	927
xorjoep	3:4098b9d3d571	928	/* Interrupt Controller Type Register Definitions */
xorjoep	3:4098b9d3d571	929	#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /!< ICTR: INTLINESNUM Position /
xorjoep	3:4098b9d3d571	930	#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /<< SCnSCB_ICTR_INTLINESNUM_Pos/) /!< ICTR: INTLINESNUM Mask /
xorjoep	3:4098b9d3d571	931
xorjoep	3:4098b9d3d571	932	/* Auxiliary Control Register Definitions */
xorjoep	3:4098b9d3d571	933	#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /!< ACTLR: DISITMATBFLUSH Position /
xorjoep	3:4098b9d3d571	934	#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /!< ACTLR: DISITMATBFLUSH Mask /
xorjoep	3:4098b9d3d571	935
xorjoep	3:4098b9d3d571	936	#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /!< ACTLR: DISRAMODE Position /
xorjoep	3:4098b9d3d571	937	#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /!< ACTLR: DISRAMODE Mask /
xorjoep	3:4098b9d3d571	938
xorjoep	3:4098b9d3d571	939	#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /!< ACTLR: FPEXCODIS Position /
xorjoep	3:4098b9d3d571	940	#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /!< ACTLR: FPEXCODIS Mask /
xorjoep	3:4098b9d3d571	941
xorjoep	3:4098b9d3d571	942	#define SCnSCB_ACTLR_DISFOLD_Pos 2U /!< ACTLR: DISFOLD Position /
xorjoep	3:4098b9d3d571	943	#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /!< ACTLR: DISFOLD Mask /
xorjoep	3:4098b9d3d571	944
xorjoep	3:4098b9d3d571	945	#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /!< ACTLR: DISMCYCINT Position /
xorjoep	3:4098b9d3d571	946	#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /<< SCnSCB_ACTLR_DISMCYCINT_Pos/) /!< ACTLR: DISMCYCINT Mask /
xorjoep	3:4098b9d3d571	947
xorjoep	3:4098b9d3d571	948	/@} end of group CMSIS_SCnotSCB /
xorjoep	3:4098b9d3d571	949
xorjoep	3:4098b9d3d571	950
xorjoep	3:4098b9d3d571	951	/**
xorjoep	3:4098b9d3d571	952	\ingroup CMSIS_core_register
xorjoep	3:4098b9d3d571	953	\defgroup CMSIS_SysTick System Tick Timer (SysTick)
xorjoep	3:4098b9d3d571	954	\brief Type definitions for the System Timer Registers.
xorjoep	3:4098b9d3d571	955	@{
xorjoep	3:4098b9d3d571	956	*/
xorjoep	3:4098b9d3d571	957
xorjoep	3:4098b9d3d571	958	/**
xorjoep	3:4098b9d3d571	959	\brief Structure type to access the System Timer (SysTick).
xorjoep	3:4098b9d3d571	960	*/
xorjoep	3:4098b9d3d571	961	typedef struct
xorjoep	3:4098b9d3d571	962	{
xorjoep	3:4098b9d3d571	963	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) SysTick Control and Status Register /
xorjoep	3:4098b9d3d571	964	__IOM uint32_t LOAD; /!< Offset: 0x004 (R/W) SysTick Reload Value Register /
xorjoep	3:4098b9d3d571	965	__IOM uint32_t VAL; /!< Offset: 0x008 (R/W) SysTick Current Value Register /
xorjoep	3:4098b9d3d571	966	__IM uint32_t CALIB; /!< Offset: 0x00C (R/ ) SysTick Calibration Register /
xorjoep	3:4098b9d3d571	967	} SysTick_Type;
xorjoep	3:4098b9d3d571	968
xorjoep	3:4098b9d3d571	969	/* SysTick Control / Status Register Definitions */
xorjoep	3:4098b9d3d571	970	#define SysTick_CTRL_COUNTFLAG_Pos 16U /!< SysTick CTRL: COUNTFLAG Position /
xorjoep	3:4098b9d3d571	971	#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
xorjoep	3:4098b9d3d571	972
xorjoep	3:4098b9d3d571	973	#define SysTick_CTRL_CLKSOURCE_Pos 2U /!< SysTick CTRL: CLKSOURCE Position /
xorjoep	3:4098b9d3d571	974	#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
xorjoep	3:4098b9d3d571	975
xorjoep	3:4098b9d3d571	976	#define SysTick_CTRL_TICKINT_Pos 1U /!< SysTick CTRL: TICKINT Position /
xorjoep	3:4098b9d3d571	977	#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
xorjoep	3:4098b9d3d571	978
xorjoep	3:4098b9d3d571	979	#define SysTick_CTRL_ENABLE_Pos 0U /!< SysTick CTRL: ENABLE Position /
xorjoep	3:4098b9d3d571	980	#define SysTick_CTRL_ENABLE_Msk (1UL /<< SysTick_CTRL_ENABLE_Pos/) /!< SysTick CTRL: ENABLE Mask /
xorjoep	3:4098b9d3d571	981
xorjoep	3:4098b9d3d571	982	/* SysTick Reload Register Definitions */
xorjoep	3:4098b9d3d571	983	#define SysTick_LOAD_RELOAD_Pos 0U /!< SysTick LOAD: RELOAD Position /
xorjoep	3:4098b9d3d571	984	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /<< SysTick_LOAD_RELOAD_Pos/) /!< SysTick LOAD: RELOAD Mask /
xorjoep	3:4098b9d3d571	985
xorjoep	3:4098b9d3d571	986	/* SysTick Current Register Definitions */
xorjoep	3:4098b9d3d571	987	#define SysTick_VAL_CURRENT_Pos 0U /!< SysTick VAL: CURRENT Position /
xorjoep	3:4098b9d3d571	988	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /<< SysTick_VAL_CURRENT_Pos/) /!< SysTick VAL: CURRENT Mask /
xorjoep	3:4098b9d3d571	989
xorjoep	3:4098b9d3d571	990	/* SysTick Calibration Register Definitions */
xorjoep	3:4098b9d3d571	991	#define SysTick_CALIB_NOREF_Pos 31U /!< SysTick CALIB: NOREF Position /
xorjoep	3:4098b9d3d571	992	#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
xorjoep	3:4098b9d3d571	993
xorjoep	3:4098b9d3d571	994	#define SysTick_CALIB_SKEW_Pos 30U /!< SysTick CALIB: SKEW Position /
xorjoep	3:4098b9d3d571	995	#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
xorjoep	3:4098b9d3d571	996
xorjoep	3:4098b9d3d571	997	#define SysTick_CALIB_TENMS_Pos 0U /!< SysTick CALIB: TENMS Position /
xorjoep	3:4098b9d3d571	998	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /<< SysTick_CALIB_TENMS_Pos/) /!< SysTick CALIB: TENMS Mask /
xorjoep	3:4098b9d3d571	999
xorjoep	3:4098b9d3d571	1000	/@} end of group CMSIS_SysTick /
xorjoep	3:4098b9d3d571	1001
xorjoep	3:4098b9d3d571	1002
xorjoep	3:4098b9d3d571	1003	/**
xorjoep	3:4098b9d3d571	1004	\ingroup CMSIS_core_register
xorjoep	3:4098b9d3d571	1005	\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
xorjoep	3:4098b9d3d571	1006	\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
xorjoep	3:4098b9d3d571	1007	@{
xorjoep	3:4098b9d3d571	1008	*/
xorjoep	3:4098b9d3d571	1009
xorjoep	3:4098b9d3d571	1010	/**
xorjoep	3:4098b9d3d571	1011	\brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
xorjoep	3:4098b9d3d571	1012	*/
xorjoep	3:4098b9d3d571	1013	typedef struct
xorjoep	3:4098b9d3d571	1014	{
xorjoep	3:4098b9d3d571	1015	__OM union
xorjoep	3:4098b9d3d571	1016	{
xorjoep	3:4098b9d3d571	1017	__OM uint8_t u8; /!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit /
xorjoep	3:4098b9d3d571	1018	__OM uint16_t u16; /!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit /
xorjoep	3:4098b9d3d571	1019	__OM uint32_t u32; /!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit /
xorjoep	3:4098b9d3d571	1020	} PORT [32U]; /!< Offset: 0x000 ( /W) ITM Stimulus Port Registers /
xorjoep	3:4098b9d3d571	1021	uint32_t RESERVED0[864U];
xorjoep	3:4098b9d3d571	1022	__IOM uint32_t TER; /!< Offset: 0xE00 (R/W) ITM Trace Enable Register /
xorjoep	3:4098b9d3d571	1023	uint32_t RESERVED1[15U];
xorjoep	3:4098b9d3d571	1024	__IOM uint32_t TPR; /!< Offset: 0xE40 (R/W) ITM Trace Privilege Register /
xorjoep	3:4098b9d3d571	1025	uint32_t RESERVED2[15U];
xorjoep	3:4098b9d3d571	1026	__IOM uint32_t TCR; /!< Offset: 0xE80 (R/W) ITM Trace Control Register /
xorjoep	3:4098b9d3d571	1027	uint32_t RESERVED3[29U];
xorjoep	3:4098b9d3d571	1028	__OM uint32_t IWR; /!< Offset: 0xEF8 ( /W) ITM Integration Write Register /
xorjoep	3:4098b9d3d571	1029	__IM uint32_t IRR; /!< Offset: 0xEFC (R/ ) ITM Integration Read Register /
xorjoep	3:4098b9d3d571	1030	__IOM uint32_t IMCR; /!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register /
xorjoep	3:4098b9d3d571	1031	uint32_t RESERVED4[43U];
xorjoep	3:4098b9d3d571	1032	__OM uint32_t LAR; /!< Offset: 0xFB0 ( /W) ITM Lock Access Register /
xorjoep	3:4098b9d3d571	1033	__IM uint32_t LSR; /!< Offset: 0xFB4 (R/ ) ITM Lock Status Register /
xorjoep	3:4098b9d3d571	1034	uint32_t RESERVED5[6U];
xorjoep	3:4098b9d3d571	1035	__IM uint32_t PID4; /!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 /
xorjoep	3:4098b9d3d571	1036	__IM uint32_t PID5; /!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 /
xorjoep	3:4098b9d3d571	1037	__IM uint32_t PID6; /!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 /
xorjoep	3:4098b9d3d571	1038	__IM uint32_t PID7; /!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 /
xorjoep	3:4098b9d3d571	1039	__IM uint32_t PID0; /!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 /
xorjoep	3:4098b9d3d571	1040	__IM uint32_t PID1; /!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 /
xorjoep	3:4098b9d3d571	1041	__IM uint32_t PID2; /!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 /
xorjoep	3:4098b9d3d571	1042	__IM uint32_t PID3; /!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 /
xorjoep	3:4098b9d3d571	1043	__IM uint32_t CID0; /!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 /
xorjoep	3:4098b9d3d571	1044	__IM uint32_t CID1; /!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 /
xorjoep	3:4098b9d3d571	1045	__IM uint32_t CID2; /!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 /
xorjoep	3:4098b9d3d571	1046	__IM uint32_t CID3; /!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 /
xorjoep	3:4098b9d3d571	1047	} ITM_Type;
xorjoep	3:4098b9d3d571	1048
xorjoep	3:4098b9d3d571	1049	/* ITM Trace Privilege Register Definitions */
xorjoep	3:4098b9d3d571	1050	#define ITM_TPR_PRIVMASK_Pos 0U /!< ITM TPR: PRIVMASK Position /
xorjoep	3:4098b9d3d571	1051	#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /<< ITM_TPR_PRIVMASK_Pos/) /!< ITM TPR: PRIVMASK Mask /
xorjoep	3:4098b9d3d571	1052
xorjoep	3:4098b9d3d571	1053	/* ITM Trace Control Register Definitions */
xorjoep	3:4098b9d3d571	1054	#define ITM_TCR_BUSY_Pos 23U /!< ITM TCR: BUSY Position /
xorjoep	3:4098b9d3d571	1055	#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /!< ITM TCR: BUSY Mask /
xorjoep	3:4098b9d3d571	1056
xorjoep	3:4098b9d3d571	1057	#define ITM_TCR_TraceBusID_Pos 16U /!< ITM TCR: ATBID Position /
xorjoep	3:4098b9d3d571	1058	#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /!< ITM TCR: ATBID Mask /
xorjoep	3:4098b9d3d571	1059
xorjoep	3:4098b9d3d571	1060	#define ITM_TCR_GTSFREQ_Pos 10U /!< ITM TCR: Global timestamp frequency Position /
xorjoep	3:4098b9d3d571	1061	#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /!< ITM TCR: Global timestamp frequency Mask /
xorjoep	3:4098b9d3d571	1062
xorjoep	3:4098b9d3d571	1063	#define ITM_TCR_TSPrescale_Pos 8U /!< ITM TCR: TSPrescale Position /
xorjoep	3:4098b9d3d571	1064	#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /!< ITM TCR: TSPrescale Mask /
xorjoep	3:4098b9d3d571	1065
xorjoep	3:4098b9d3d571	1066	#define ITM_TCR_SWOENA_Pos 4U /!< ITM TCR: SWOENA Position /
xorjoep	3:4098b9d3d571	1067	#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /!< ITM TCR: SWOENA Mask /
xorjoep	3:4098b9d3d571	1068
xorjoep	3:4098b9d3d571	1069	#define ITM_TCR_DWTENA_Pos 3U /!< ITM TCR: DWTENA Position /
xorjoep	3:4098b9d3d571	1070	#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /!< ITM TCR: DWTENA Mask /
xorjoep	3:4098b9d3d571	1071
xorjoep	3:4098b9d3d571	1072	#define ITM_TCR_SYNCENA_Pos 2U /!< ITM TCR: SYNCENA Position /
xorjoep	3:4098b9d3d571	1073	#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /!< ITM TCR: SYNCENA Mask /
xorjoep	3:4098b9d3d571	1074
xorjoep	3:4098b9d3d571	1075	#define ITM_TCR_TSENA_Pos 1U /!< ITM TCR: TSENA Position /
xorjoep	3:4098b9d3d571	1076	#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /!< ITM TCR: TSENA Mask /
xorjoep	3:4098b9d3d571	1077
xorjoep	3:4098b9d3d571	1078	#define ITM_TCR_ITMENA_Pos 0U /!< ITM TCR: ITM Enable bit Position /
xorjoep	3:4098b9d3d571	1079	#define ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/) /!< ITM TCR: ITM Enable bit Mask /
xorjoep	3:4098b9d3d571	1080
xorjoep	3:4098b9d3d571	1081	/* ITM Integration Write Register Definitions */
xorjoep	3:4098b9d3d571	1082	#define ITM_IWR_ATVALIDM_Pos 0U /!< ITM IWR: ATVALIDM Position /
xorjoep	3:4098b9d3d571	1083	#define ITM_IWR_ATVALIDM_Msk (1UL /<< ITM_IWR_ATVALIDM_Pos/) /!< ITM IWR: ATVALIDM Mask /
xorjoep	3:4098b9d3d571	1084
xorjoep	3:4098b9d3d571	1085	/* ITM Integration Read Register Definitions */
xorjoep	3:4098b9d3d571	1086	#define ITM_IRR_ATREADYM_Pos 0U /!< ITM IRR: ATREADYM Position /
xorjoep	3:4098b9d3d571	1087	#define ITM_IRR_ATREADYM_Msk (1UL /<< ITM_IRR_ATREADYM_Pos/) /!< ITM IRR: ATREADYM Mask /
xorjoep	3:4098b9d3d571	1088
xorjoep	3:4098b9d3d571	1089	/* ITM Integration Mode Control Register Definitions */
xorjoep	3:4098b9d3d571	1090	#define ITM_IMCR_INTEGRATION_Pos 0U /!< ITM IMCR: INTEGRATION Position /
xorjoep	3:4098b9d3d571	1091	#define ITM_IMCR_INTEGRATION_Msk (1UL /<< ITM_IMCR_INTEGRATION_Pos/) /!< ITM IMCR: INTEGRATION Mask /
xorjoep	3:4098b9d3d571	1092
xorjoep	3:4098b9d3d571	1093	/* ITM Lock Status Register Definitions */
xorjoep	3:4098b9d3d571	1094	#define ITM_LSR_ByteAcc_Pos 2U /!< ITM LSR: ByteAcc Position /
xorjoep	3:4098b9d3d571	1095	#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /!< ITM LSR: ByteAcc Mask /
xorjoep	3:4098b9d3d571	1096
xorjoep	3:4098b9d3d571	1097	#define ITM_LSR_Access_Pos 1U /!< ITM LSR: Access Position /
xorjoep	3:4098b9d3d571	1098	#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /!< ITM LSR: Access Mask /
xorjoep	3:4098b9d3d571	1099
xorjoep	3:4098b9d3d571	1100	#define ITM_LSR_Present_Pos 0U /!< ITM LSR: Present Position /
xorjoep	3:4098b9d3d571	1101	#define ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/) /!< ITM LSR: Present Mask /
xorjoep	3:4098b9d3d571	1102
xorjoep	3:4098b9d3d571	1103	/@}/ /* end of group CMSIS_ITM */
xorjoep	3:4098b9d3d571	1104
xorjoep	3:4098b9d3d571	1105
xorjoep	3:4098b9d3d571	1106	/**
xorjoep	3:4098b9d3d571	1107	\ingroup CMSIS_core_register
xorjoep	3:4098b9d3d571	1108	\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
xorjoep	3:4098b9d3d571	1109	\brief Type definitions for the Data Watchpoint and Trace (DWT)
xorjoep	3:4098b9d3d571	1110	@{
xorjoep	3:4098b9d3d571	1111	*/
xorjoep	3:4098b9d3d571	1112
xorjoep	3:4098b9d3d571	1113	/**
xorjoep	3:4098b9d3d571	1114	\brief Structure type to access the Data Watchpoint and Trace Register (DWT).
xorjoep	3:4098b9d3d571	1115	*/
xorjoep	3:4098b9d3d571	1116	typedef struct
xorjoep	3:4098b9d3d571	1117	{
xorjoep	3:4098b9d3d571	1118	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) Control Register /
xorjoep	3:4098b9d3d571	1119	__IOM uint32_t CYCCNT; /!< Offset: 0x004 (R/W) Cycle Count Register /
xorjoep	3:4098b9d3d571	1120	__IOM uint32_t CPICNT; /!< Offset: 0x008 (R/W) CPI Count Register /
xorjoep	3:4098b9d3d571	1121	__IOM uint32_t EXCCNT; /!< Offset: 0x00C (R/W) Exception Overhead Count Register /
xorjoep	3:4098b9d3d571	1122	__IOM uint32_t SLEEPCNT; /!< Offset: 0x010 (R/W) Sleep Count Register /
xorjoep	3:4098b9d3d571	1123	__IOM uint32_t LSUCNT; /!< Offset: 0x014 (R/W) LSU Count Register /
xorjoep	3:4098b9d3d571	1124	__IOM uint32_t FOLDCNT; /!< Offset: 0x018 (R/W) Folded-instruction Count Register /
xorjoep	3:4098b9d3d571	1125	__IM uint32_t PCSR; /!< Offset: 0x01C (R/ ) Program Counter Sample Register /
xorjoep	3:4098b9d3d571	1126	__IOM uint32_t COMP0; /!< Offset: 0x020 (R/W) Comparator Register 0 /
xorjoep	3:4098b9d3d571	1127	__IOM uint32_t MASK0; /!< Offset: 0x024 (R/W) Mask Register 0 /
xorjoep	3:4098b9d3d571	1128	__IOM uint32_t FUNCTION0; /!< Offset: 0x028 (R/W) Function Register 0 /
xorjoep	3:4098b9d3d571	1129	uint32_t RESERVED0[1U];
xorjoep	3:4098b9d3d571	1130	__IOM uint32_t COMP1; /!< Offset: 0x030 (R/W) Comparator Register 1 /
xorjoep	3:4098b9d3d571	1131	__IOM uint32_t MASK1; /!< Offset: 0x034 (R/W) Mask Register 1 /
xorjoep	3:4098b9d3d571	1132	__IOM uint32_t FUNCTION1; /!< Offset: 0x038 (R/W) Function Register 1 /
xorjoep	3:4098b9d3d571	1133	uint32_t RESERVED1[1U];
xorjoep	3:4098b9d3d571	1134	__IOM uint32_t COMP2; /!< Offset: 0x040 (R/W) Comparator Register 2 /
xorjoep	3:4098b9d3d571	1135	__IOM uint32_t MASK2; /!< Offset: 0x044 (R/W) Mask Register 2 /
xorjoep	3:4098b9d3d571	1136	__IOM uint32_t FUNCTION2; /!< Offset: 0x048 (R/W) Function Register 2 /
xorjoep	3:4098b9d3d571	1137	uint32_t RESERVED2[1U];
xorjoep	3:4098b9d3d571	1138	__IOM uint32_t COMP3; /!< Offset: 0x050 (R/W) Comparator Register 3 /
xorjoep	3:4098b9d3d571	1139	__IOM uint32_t MASK3; /!< Offset: 0x054 (R/W) Mask Register 3 /
xorjoep	3:4098b9d3d571	1140	__IOM uint32_t FUNCTION3; /!< Offset: 0x058 (R/W) Function Register 3 /
xorjoep	3:4098b9d3d571	1141	uint32_t RESERVED3[981U];
xorjoep	3:4098b9d3d571	1142	__OM uint32_t LAR; /!< Offset: 0xFB0 ( W) Lock Access Register /
xorjoep	3:4098b9d3d571	1143	__IM uint32_t LSR; /!< Offset: 0xFB4 (R ) Lock Status Register /
xorjoep	3:4098b9d3d571	1144	} DWT_Type;
xorjoep	3:4098b9d3d571	1145
xorjoep	3:4098b9d3d571	1146	/* DWT Control Register Definitions */
xorjoep	3:4098b9d3d571	1147	#define DWT_CTRL_NUMCOMP_Pos 28U /!< DWT CTRL: NUMCOMP Position /
xorjoep	3:4098b9d3d571	1148	#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /!< DWT CTRL: NUMCOMP Mask /
xorjoep	3:4098b9d3d571	1149
xorjoep	3:4098b9d3d571	1150	#define DWT_CTRL_NOTRCPKT_Pos 27U /!< DWT CTRL: NOTRCPKT Position /
xorjoep	3:4098b9d3d571	1151	#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /!< DWT CTRL: NOTRCPKT Mask /
xorjoep	3:4098b9d3d571	1152
xorjoep	3:4098b9d3d571	1153	#define DWT_CTRL_NOEXTTRIG_Pos 26U /!< DWT CTRL: NOEXTTRIG Position /
xorjoep	3:4098b9d3d571	1154	#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /!< DWT CTRL: NOEXTTRIG Mask /
xorjoep	3:4098b9d3d571	1155
xorjoep	3:4098b9d3d571	1156	#define DWT_CTRL_NOCYCCNT_Pos 25U /!< DWT CTRL: NOCYCCNT Position /
xorjoep	3:4098b9d3d571	1157	#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /!< DWT CTRL: NOCYCCNT Mask /
xorjoep	3:4098b9d3d571	1158
xorjoep	3:4098b9d3d571	1159	#define DWT_CTRL_NOPRFCNT_Pos 24U /!< DWT CTRL: NOPRFCNT Position /
xorjoep	3:4098b9d3d571	1160	#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /!< DWT CTRL: NOPRFCNT Mask /
xorjoep	3:4098b9d3d571	1161
xorjoep	3:4098b9d3d571	1162	#define DWT_CTRL_CYCEVTENA_Pos 22U /!< DWT CTRL: CYCEVTENA Position /
xorjoep	3:4098b9d3d571	1163	#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /!< DWT CTRL: CYCEVTENA Mask /
xorjoep	3:4098b9d3d571	1164
xorjoep	3:4098b9d3d571	1165	#define DWT_CTRL_FOLDEVTENA_Pos 21U /!< DWT CTRL: FOLDEVTENA Position /
xorjoep	3:4098b9d3d571	1166	#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /!< DWT CTRL: FOLDEVTENA Mask /
xorjoep	3:4098b9d3d571	1167
xorjoep	3:4098b9d3d571	1168	#define DWT_CTRL_LSUEVTENA_Pos 20U /!< DWT CTRL: LSUEVTENA Position /
xorjoep	3:4098b9d3d571	1169	#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /!< DWT CTRL: LSUEVTENA Mask /
xorjoep	3:4098b9d3d571	1170
xorjoep	3:4098b9d3d571	1171	#define DWT_CTRL_SLEEPEVTENA_Pos 19U /!< DWT CTRL: SLEEPEVTENA Position /
xorjoep	3:4098b9d3d571	1172	#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /!< DWT CTRL: SLEEPEVTENA Mask /
xorjoep	3:4098b9d3d571	1173
xorjoep	3:4098b9d3d571	1174	#define DWT_CTRL_EXCEVTENA_Pos 18U /!< DWT CTRL: EXCEVTENA Position /
xorjoep	3:4098b9d3d571	1175	#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /!< DWT CTRL: EXCEVTENA Mask /
xorjoep	3:4098b9d3d571	1176
xorjoep	3:4098b9d3d571	1177	#define DWT_CTRL_CPIEVTENA_Pos 17U /!< DWT CTRL: CPIEVTENA Position /
xorjoep	3:4098b9d3d571	1178	#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /!< DWT CTRL: CPIEVTENA Mask /
xorjoep	3:4098b9d3d571	1179
xorjoep	3:4098b9d3d571	1180	#define DWT_CTRL_EXCTRCENA_Pos 16U /!< DWT CTRL: EXCTRCENA Position /
xorjoep	3:4098b9d3d571	1181	#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /!< DWT CTRL: EXCTRCENA Mask /
xorjoep	3:4098b9d3d571	1182
xorjoep	3:4098b9d3d571	1183	#define DWT_CTRL_PCSAMPLENA_Pos 12U /!< DWT CTRL: PCSAMPLENA Position /
xorjoep	3:4098b9d3d571	1184	#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /!< DWT CTRL: PCSAMPLENA Mask /
xorjoep	3:4098b9d3d571	1185
xorjoep	3:4098b9d3d571	1186	#define DWT_CTRL_SYNCTAP_Pos 10U /!< DWT CTRL: SYNCTAP Position /
xorjoep	3:4098b9d3d571	1187	#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /!< DWT CTRL: SYNCTAP Mask /
xorjoep	3:4098b9d3d571	1188
xorjoep	3:4098b9d3d571	1189	#define DWT_CTRL_CYCTAP_Pos 9U /!< DWT CTRL: CYCTAP Position /
xorjoep	3:4098b9d3d571	1190	#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /!< DWT CTRL: CYCTAP Mask /
xorjoep	3:4098b9d3d571	1191
xorjoep	3:4098b9d3d571	1192	#define DWT_CTRL_POSTINIT_Pos 5U /!< DWT CTRL: POSTINIT Position /
xorjoep	3:4098b9d3d571	1193	#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /!< DWT CTRL: POSTINIT Mask /
xorjoep	3:4098b9d3d571	1194
xorjoep	3:4098b9d3d571	1195	#define DWT_CTRL_POSTPRESET_Pos 1U /!< DWT CTRL: POSTPRESET Position /
xorjoep	3:4098b9d3d571	1196	#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /!< DWT CTRL: POSTPRESET Mask /
xorjoep	3:4098b9d3d571	1197
xorjoep	3:4098b9d3d571	1198	#define DWT_CTRL_CYCCNTENA_Pos 0U /!< DWT CTRL: CYCCNTENA Position /
xorjoep	3:4098b9d3d571	1199	#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /<< DWT_CTRL_CYCCNTENA_Pos/) /!< DWT CTRL: CYCCNTENA Mask /
xorjoep	3:4098b9d3d571	1200
xorjoep	3:4098b9d3d571	1201	/* DWT CPI Count Register Definitions */
xorjoep	3:4098b9d3d571	1202	#define DWT_CPICNT_CPICNT_Pos 0U /!< DWT CPICNT: CPICNT Position /
xorjoep	3:4098b9d3d571	1203	#define DWT_CPICNT_CPICNT_Msk (0xFFUL /<< DWT_CPICNT_CPICNT_Pos/) /!< DWT CPICNT: CPICNT Mask /
xorjoep	3:4098b9d3d571	1204
xorjoep	3:4098b9d3d571	1205	/* DWT Exception Overhead Count Register Definitions */
xorjoep	3:4098b9d3d571	1206	#define DWT_EXCCNT_EXCCNT_Pos 0U /!< DWT EXCCNT: EXCCNT Position /
xorjoep	3:4098b9d3d571	1207	#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /<< DWT_EXCCNT_EXCCNT_Pos/) /!< DWT EXCCNT: EXCCNT Mask /
xorjoep	3:4098b9d3d571	1208
xorjoep	3:4098b9d3d571	1209	/* DWT Sleep Count Register Definitions */
xorjoep	3:4098b9d3d571	1210	#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /!< DWT SLEEPCNT: SLEEPCNT Position /
xorjoep	3:4098b9d3d571	1211	#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /<< DWT_SLEEPCNT_SLEEPCNT_Pos/) /!< DWT SLEEPCNT: SLEEPCNT Mask /
xorjoep	3:4098b9d3d571	1212
xorjoep	3:4098b9d3d571	1213	/* DWT LSU Count Register Definitions */
xorjoep	3:4098b9d3d571	1214	#define DWT_LSUCNT_LSUCNT_Pos 0U /!< DWT LSUCNT: LSUCNT Position /
xorjoep	3:4098b9d3d571	1215	#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /<< DWT_LSUCNT_LSUCNT_Pos/) /!< DWT LSUCNT: LSUCNT Mask /
xorjoep	3:4098b9d3d571	1216
xorjoep	3:4098b9d3d571	1217	/* DWT Folded-instruction Count Register Definitions */
xorjoep	3:4098b9d3d571	1218	#define DWT_FOLDCNT_FOLDCNT_Pos 0U /!< DWT FOLDCNT: FOLDCNT Position /
xorjoep	3:4098b9d3d571	1219	#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /<< DWT_FOLDCNT_FOLDCNT_Pos/) /!< DWT FOLDCNT: FOLDCNT Mask /
xorjoep	3:4098b9d3d571	1220
xorjoep	3:4098b9d3d571	1221	/* DWT Comparator Mask Register Definitions */
xorjoep	3:4098b9d3d571	1222	#define DWT_MASK_MASK_Pos 0U /!< DWT MASK: MASK Position /
xorjoep	3:4098b9d3d571	1223	#define DWT_MASK_MASK_Msk (0x1FUL /<< DWT_MASK_MASK_Pos/) /!< DWT MASK: MASK Mask /
xorjoep	3:4098b9d3d571	1224
xorjoep	3:4098b9d3d571	1225	/* DWT Comparator Function Register Definitions */
xorjoep	3:4098b9d3d571	1226	#define DWT_FUNCTION_MATCHED_Pos 24U /!< DWT FUNCTION: MATCHED Position /
xorjoep	3:4098b9d3d571	1227	#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /!< DWT FUNCTION: MATCHED Mask /
xorjoep	3:4098b9d3d571	1228
xorjoep	3:4098b9d3d571	1229	#define DWT_FUNCTION_DATAVADDR1_Pos 16U /!< DWT FUNCTION: DATAVADDR1 Position /
xorjoep	3:4098b9d3d571	1230	#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /!< DWT FUNCTION: DATAVADDR1 Mask /
xorjoep	3:4098b9d3d571	1231
xorjoep	3:4098b9d3d571	1232	#define DWT_FUNCTION_DATAVADDR0_Pos 12U /!< DWT FUNCTION: DATAVADDR0 Position /
xorjoep	3:4098b9d3d571	1233	#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /!< DWT FUNCTION: DATAVADDR0 Mask /
xorjoep	3:4098b9d3d571	1234
xorjoep	3:4098b9d3d571	1235	#define DWT_FUNCTION_DATAVSIZE_Pos 10U /!< DWT FUNCTION: DATAVSIZE Position /
xorjoep	3:4098b9d3d571	1236	#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /!< DWT FUNCTION: DATAVSIZE Mask /
xorjoep	3:4098b9d3d571	1237
xorjoep	3:4098b9d3d571	1238	#define DWT_FUNCTION_LNK1ENA_Pos 9U /!< DWT FUNCTION: LNK1ENA Position /
xorjoep	3:4098b9d3d571	1239	#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /!< DWT FUNCTION: LNK1ENA Mask /
xorjoep	3:4098b9d3d571	1240
xorjoep	3:4098b9d3d571	1241	#define DWT_FUNCTION_DATAVMATCH_Pos 8U /!< DWT FUNCTION: DATAVMATCH Position /
xorjoep	3:4098b9d3d571	1242	#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /!< DWT FUNCTION: DATAVMATCH Mask /
xorjoep	3:4098b9d3d571	1243
xorjoep	3:4098b9d3d571	1244	#define DWT_FUNCTION_CYCMATCH_Pos 7U /!< DWT FUNCTION: CYCMATCH Position /
xorjoep	3:4098b9d3d571	1245	#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /!< DWT FUNCTION: CYCMATCH Mask /
xorjoep	3:4098b9d3d571	1246
xorjoep	3:4098b9d3d571	1247	#define DWT_FUNCTION_EMITRANGE_Pos 5U /!< DWT FUNCTION: EMITRANGE Position /
xorjoep	3:4098b9d3d571	1248	#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /!< DWT FUNCTION: EMITRANGE Mask /
xorjoep	3:4098b9d3d571	1249
xorjoep	3:4098b9d3d571	1250	#define DWT_FUNCTION_FUNCTION_Pos 0U /!< DWT FUNCTION: FUNCTION Position /
xorjoep	3:4098b9d3d571	1251	#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /<< DWT_FUNCTION_FUNCTION_Pos/) /!< DWT FUNCTION: FUNCTION Mask /
xorjoep	3:4098b9d3d571	1252
xorjoep	3:4098b9d3d571	1253	/@}/ /* end of group CMSIS_DWT */
xorjoep	3:4098b9d3d571	1254
xorjoep	3:4098b9d3d571	1255
xorjoep	3:4098b9d3d571	1256	/**
xorjoep	3:4098b9d3d571	1257	\ingroup CMSIS_core_register
xorjoep	3:4098b9d3d571	1258	\defgroup CMSIS_TPI Trace Port Interface (TPI)
xorjoep	3:4098b9d3d571	1259	\brief Type definitions for the Trace Port Interface (TPI)
xorjoep	3:4098b9d3d571	1260	@{
xorjoep	3:4098b9d3d571	1261	*/
xorjoep	3:4098b9d3d571	1262
xorjoep	3:4098b9d3d571	1263	/**
xorjoep	3:4098b9d3d571	1264	\brief Structure type to access the Trace Port Interface Register (TPI).
xorjoep	3:4098b9d3d571	1265	*/
xorjoep	3:4098b9d3d571	1266	typedef struct
xorjoep	3:4098b9d3d571	1267	{
xorjoep	3:4098b9d3d571	1268	__IM uint32_t SSPSR; /!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register /
xorjoep	3:4098b9d3d571	1269	__IOM uint32_t CSPSR; /!< Offset: 0x004 (R/W) Current Parallel Port Size Register /
xorjoep	3:4098b9d3d571	1270	uint32_t RESERVED0[2U];
xorjoep	3:4098b9d3d571	1271	__IOM uint32_t ACPR; /!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register /
xorjoep	3:4098b9d3d571	1272	uint32_t RESERVED1[55U];
xorjoep	3:4098b9d3d571	1273	__IOM uint32_t SPPR; /!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register /
xorjoep	3:4098b9d3d571	1274	uint32_t RESERVED2[131U];
xorjoep	3:4098b9d3d571	1275	__IM uint32_t FFSR; /!< Offset: 0x300 (R/ ) Formatter and Flush Status Register /
xorjoep	3:4098b9d3d571	1276	__IOM uint32_t FFCR; /!< Offset: 0x304 (R/W) Formatter and Flush Control Register /
xorjoep	3:4098b9d3d571	1277	__IM uint32_t FSCR; /!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register /
xorjoep	3:4098b9d3d571	1278	uint32_t RESERVED3[759U];
xorjoep	3:4098b9d3d571	1279	__IM uint32_t TRIGGER; /!< Offset: 0xEE8 (R/ ) TRIGGER Register /
xorjoep	3:4098b9d3d571	1280	__IM uint32_t FIFO0; /!< Offset: 0xEEC (R/ ) Integration ETM Data /
xorjoep	3:4098b9d3d571	1281	__IM uint32_t ITATBCTR2; /!< Offset: 0xEF0 (R/ ) ITATBCTR2 /
xorjoep	3:4098b9d3d571	1282	uint32_t RESERVED4[1U];
xorjoep	3:4098b9d3d571	1283	__IM uint32_t ITATBCTR0; /!< Offset: 0xEF8 (R/ ) ITATBCTR0 /
xorjoep	3:4098b9d3d571	1284	__IM uint32_t FIFO1; /!< Offset: 0xEFC (R/ ) Integration ITM Data /
xorjoep	3:4098b9d3d571	1285	__IOM uint32_t ITCTRL; /!< Offset: 0xF00 (R/W) Integration Mode Control /
xorjoep	3:4098b9d3d571	1286	uint32_t RESERVED5[39U];
xorjoep	3:4098b9d3d571	1287	__IOM uint32_t CLAIMSET; /!< Offset: 0xFA0 (R/W) Claim tag set /
xorjoep	3:4098b9d3d571	1288	__IOM uint32_t CLAIMCLR; /!< Offset: 0xFA4 (R/W) Claim tag clear /
xorjoep	3:4098b9d3d571	1289	uint32_t RESERVED7[8U];
xorjoep	3:4098b9d3d571	1290	__IM uint32_t DEVID; /!< Offset: 0xFC8 (R/ ) TPIU_DEVID /
xorjoep	3:4098b9d3d571	1291	__IM uint32_t DEVTYPE; /!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE /
xorjoep	3:4098b9d3d571	1292	} TPI_Type;
xorjoep	3:4098b9d3d571	1293
xorjoep	3:4098b9d3d571	1294	/* TPI Asynchronous Clock Prescaler Register Definitions */
xorjoep	3:4098b9d3d571	1295	#define TPI_ACPR_PRESCALER_Pos 0U /!< TPI ACPR: PRESCALER Position /
xorjoep	3:4098b9d3d571	1296	#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/) /!< TPI ACPR: PRESCALER Mask /
xorjoep	3:4098b9d3d571	1297
xorjoep	3:4098b9d3d571	1298	/* TPI Selected Pin Protocol Register Definitions */
xorjoep	3:4098b9d3d571	1299	#define TPI_SPPR_TXMODE_Pos 0U /!< TPI SPPR: TXMODE Position /
xorjoep	3:4098b9d3d571	1300	#define TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/) /!< TPI SPPR: TXMODE Mask /
xorjoep	3:4098b9d3d571	1301
xorjoep	3:4098b9d3d571	1302	/* TPI Formatter and Flush Status Register Definitions */
xorjoep	3:4098b9d3d571	1303	#define TPI_FFSR_FtNonStop_Pos 3U /!< TPI FFSR: FtNonStop Position /
xorjoep	3:4098b9d3d571	1304	#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /!< TPI FFSR: FtNonStop Mask /
xorjoep	3:4098b9d3d571	1305
xorjoep	3:4098b9d3d571	1306	#define TPI_FFSR_TCPresent_Pos 2U /!< TPI FFSR: TCPresent Position /
xorjoep	3:4098b9d3d571	1307	#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /!< TPI FFSR: TCPresent Mask /
xorjoep	3:4098b9d3d571	1308
xorjoep	3:4098b9d3d571	1309	#define TPI_FFSR_FtStopped_Pos 1U /!< TPI FFSR: FtStopped Position /
xorjoep	3:4098b9d3d571	1310	#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /!< TPI FFSR: FtStopped Mask /
xorjoep	3:4098b9d3d571	1311
xorjoep	3:4098b9d3d571	1312	#define TPI_FFSR_FlInProg_Pos 0U /!< TPI FFSR: FlInProg Position /
xorjoep	3:4098b9d3d571	1313	#define TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/) /!< TPI FFSR: FlInProg Mask /
xorjoep	3:4098b9d3d571	1314
xorjoep	3:4098b9d3d571	1315	/* TPI Formatter and Flush Control Register Definitions */
xorjoep	3:4098b9d3d571	1316	#define TPI_FFCR_TrigIn_Pos 8U /!< TPI FFCR: TrigIn Position /
xorjoep	3:4098b9d3d571	1317	#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /!< TPI FFCR: TrigIn Mask /
xorjoep	3:4098b9d3d571	1318
xorjoep	3:4098b9d3d571	1319	#define TPI_FFCR_EnFCont_Pos 1U /!< TPI FFCR: EnFCont Position /
xorjoep	3:4098b9d3d571	1320	#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /!< TPI FFCR: EnFCont Mask /
xorjoep	3:4098b9d3d571	1321
xorjoep	3:4098b9d3d571	1322	/* TPI TRIGGER Register Definitions */
xorjoep	3:4098b9d3d571	1323	#define TPI_TRIGGER_TRIGGER_Pos 0U /!< TPI TRIGGER: TRIGGER Position /
xorjoep	3:4098b9d3d571	1324	#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/) /!< TPI TRIGGER: TRIGGER Mask /
xorjoep	3:4098b9d3d571	1325
xorjoep	3:4098b9d3d571	1326	/* TPI Integration ETM Data Register Definitions (FIFO0) */
xorjoep	3:4098b9d3d571	1327	#define TPI_FIFO0_ITM_ATVALID_Pos 29U /!< TPI FIFO0: ITM_ATVALID Position /
xorjoep	3:4098b9d3d571	1328	#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /!< TPI FIFO0: ITM_ATVALID Mask /
xorjoep	3:4098b9d3d571	1329
xorjoep	3:4098b9d3d571	1330	#define TPI_FIFO0_ITM_bytecount_Pos 27U /!< TPI FIFO0: ITM_bytecount Position /
xorjoep	3:4098b9d3d571	1331	#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /!< TPI FIFO0: ITM_bytecount Mask /
xorjoep	3:4098b9d3d571	1332
xorjoep	3:4098b9d3d571	1333	#define TPI_FIFO0_ETM_ATVALID_Pos 26U /!< TPI FIFO0: ETM_ATVALID Position /
xorjoep	3:4098b9d3d571	1334	#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /!< TPI FIFO0: ETM_ATVALID Mask /
xorjoep	3:4098b9d3d571	1335
xorjoep	3:4098b9d3d571	1336	#define TPI_FIFO0_ETM_bytecount_Pos 24U /!< TPI FIFO0: ETM_bytecount Position /
xorjoep	3:4098b9d3d571	1337	#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /!< TPI FIFO0: ETM_bytecount Mask /
xorjoep	3:4098b9d3d571	1338
xorjoep	3:4098b9d3d571	1339	#define TPI_FIFO0_ETM2_Pos 16U /!< TPI FIFO0: ETM2 Position /
xorjoep	3:4098b9d3d571	1340	#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /!< TPI FIFO0: ETM2 Mask /
xorjoep	3:4098b9d3d571	1341
xorjoep	3:4098b9d3d571	1342	#define TPI_FIFO0_ETM1_Pos 8U /!< TPI FIFO0: ETM1 Position /
xorjoep	3:4098b9d3d571	1343	#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /!< TPI FIFO0: ETM1 Mask /
xorjoep	3:4098b9d3d571	1344
xorjoep	3:4098b9d3d571	1345	#define TPI_FIFO0_ETM0_Pos 0U /!< TPI FIFO0: ETM0 Position /
xorjoep	3:4098b9d3d571	1346	#define TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/) /!< TPI FIFO0: ETM0 Mask /
xorjoep	3:4098b9d3d571	1347
xorjoep	3:4098b9d3d571	1348	/* TPI ITATBCTR2 Register Definitions */
xorjoep	3:4098b9d3d571	1349	#define TPI_ITATBCTR2_ATREADY2_Pos 0U /!< TPI ITATBCTR2: ATREADY2 Position /
xorjoep	3:4098b9d3d571	1350	#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY2_Pos/) /!< TPI ITATBCTR2: ATREADY2 Mask /
xorjoep	3:4098b9d3d571	1351
xorjoep	3:4098b9d3d571	1352	#define TPI_ITATBCTR2_ATREADY1_Pos 0U /!< TPI ITATBCTR2: ATREADY1 Position /
xorjoep	3:4098b9d3d571	1353	#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY1_Pos/) /!< TPI ITATBCTR2: ATREADY1 Mask /
xorjoep	3:4098b9d3d571	1354
xorjoep	3:4098b9d3d571	1355	/* TPI Integration ITM Data Register Definitions (FIFO1) */
xorjoep	3:4098b9d3d571	1356	#define TPI_FIFO1_ITM_ATVALID_Pos 29U /!< TPI FIFO1: ITM_ATVALID Position /
xorjoep	3:4098b9d3d571	1357	#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /!< TPI FIFO1: ITM_ATVALID Mask /
xorjoep	3:4098b9d3d571	1358
xorjoep	3:4098b9d3d571	1359	#define TPI_FIFO1_ITM_bytecount_Pos 27U /!< TPI FIFO1: ITM_bytecount Position /
xorjoep	3:4098b9d3d571	1360	#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /!< TPI FIFO1: ITM_bytecount Mask /
xorjoep	3:4098b9d3d571	1361
xorjoep	3:4098b9d3d571	1362	#define TPI_FIFO1_ETM_ATVALID_Pos 26U /!< TPI FIFO1: ETM_ATVALID Position /
xorjoep	3:4098b9d3d571	1363	#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /!< TPI FIFO1: ETM_ATVALID Mask /
xorjoep	3:4098b9d3d571	1364
xorjoep	3:4098b9d3d571	1365	#define TPI_FIFO1_ETM_bytecount_Pos 24U /!< TPI FIFO1: ETM_bytecount Position /
xorjoep	3:4098b9d3d571	1366	#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /!< TPI FIFO1: ETM_bytecount Mask /
xorjoep	3:4098b9d3d571	1367
xorjoep	3:4098b9d3d571	1368	#define TPI_FIFO1_ITM2_Pos 16U /!< TPI FIFO1: ITM2 Position /
xorjoep	3:4098b9d3d571	1369	#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /!< TPI FIFO1: ITM2 Mask /
xorjoep	3:4098b9d3d571	1370
xorjoep	3:4098b9d3d571	1371	#define TPI_FIFO1_ITM1_Pos 8U /!< TPI FIFO1: ITM1 Position /
xorjoep	3:4098b9d3d571	1372	#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /!< TPI FIFO1: ITM1 Mask /
xorjoep	3:4098b9d3d571	1373
xorjoep	3:4098b9d3d571	1374	#define TPI_FIFO1_ITM0_Pos 0U /!< TPI FIFO1: ITM0 Position /
xorjoep	3:4098b9d3d571	1375	#define TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/) /!< TPI FIFO1: ITM0 Mask /
xorjoep	3:4098b9d3d571	1376
xorjoep	3:4098b9d3d571	1377	/* TPI ITATBCTR0 Register Definitions */
xorjoep	3:4098b9d3d571	1378	#define TPI_ITATBCTR0_ATREADY2_Pos 0U /!< TPI ITATBCTR0: ATREADY2 Position /
xorjoep	3:4098b9d3d571	1379	#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY2_Pos/) /!< TPI ITATBCTR0: ATREADY2 Mask /
xorjoep	3:4098b9d3d571	1380
xorjoep	3:4098b9d3d571	1381	#define TPI_ITATBCTR0_ATREADY1_Pos 0U /!< TPI ITATBCTR0: ATREADY1 Position /
xorjoep	3:4098b9d3d571	1382	#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY1_Pos/) /!< TPI ITATBCTR0: ATREADY1 Mask /
xorjoep	3:4098b9d3d571	1383
xorjoep	3:4098b9d3d571	1384	/* TPI Integration Mode Control Register Definitions */
xorjoep	3:4098b9d3d571	1385	#define TPI_ITCTRL_Mode_Pos 0U /!< TPI ITCTRL: Mode Position /
xorjoep	3:4098b9d3d571	1386	#define TPI_ITCTRL_Mode_Msk (0x3UL /<< TPI_ITCTRL_Mode_Pos/) /!< TPI ITCTRL: Mode Mask /
xorjoep	3:4098b9d3d571	1387
xorjoep	3:4098b9d3d571	1388	/* TPI DEVID Register Definitions */
xorjoep	3:4098b9d3d571	1389	#define TPI_DEVID_NRZVALID_Pos 11U /!< TPI DEVID: NRZVALID Position /
xorjoep	3:4098b9d3d571	1390	#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /!< TPI DEVID: NRZVALID Mask /
xorjoep	3:4098b9d3d571	1391
xorjoep	3:4098b9d3d571	1392	#define TPI_DEVID_MANCVALID_Pos 10U /!< TPI DEVID: MANCVALID Position /
xorjoep	3:4098b9d3d571	1393	#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /!< TPI DEVID: MANCVALID Mask /
xorjoep	3:4098b9d3d571	1394
xorjoep	3:4098b9d3d571	1395	#define TPI_DEVID_PTINVALID_Pos 9U /!< TPI DEVID: PTINVALID Position /
xorjoep	3:4098b9d3d571	1396	#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /!< TPI DEVID: PTINVALID Mask /
xorjoep	3:4098b9d3d571	1397
xorjoep	3:4098b9d3d571	1398	#define TPI_DEVID_MinBufSz_Pos 6U /!< TPI DEVID: MinBufSz Position /
xorjoep	3:4098b9d3d571	1399	#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /!< TPI DEVID: MinBufSz Mask /
xorjoep	3:4098b9d3d571	1400
xorjoep	3:4098b9d3d571	1401	#define TPI_DEVID_AsynClkIn_Pos 5U /!< TPI DEVID: AsynClkIn Position /
xorjoep	3:4098b9d3d571	1402	#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /!< TPI DEVID: AsynClkIn Mask /
xorjoep	3:4098b9d3d571	1403
xorjoep	3:4098b9d3d571	1404	#define TPI_DEVID_NrTraceInput_Pos 0U /!< TPI DEVID: NrTraceInput Position /
xorjoep	3:4098b9d3d571	1405	#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/) /!< TPI DEVID: NrTraceInput Mask /
xorjoep	3:4098b9d3d571	1406
xorjoep	3:4098b9d3d571	1407	/* TPI DEVTYPE Register Definitions */
xorjoep	3:4098b9d3d571	1408	#define TPI_DEVTYPE_SubType_Pos 4U /!< TPI DEVTYPE: SubType Position /
xorjoep	3:4098b9d3d571	1409	#define TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/) /!< TPI DEVTYPE: SubType Mask /
xorjoep	3:4098b9d3d571	1410
xorjoep	3:4098b9d3d571	1411	#define TPI_DEVTYPE_MajorType_Pos 0U /!< TPI DEVTYPE: MajorType Position /
xorjoep	3:4098b9d3d571	1412	#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /!< TPI DEVTYPE: MajorType Mask /
xorjoep	3:4098b9d3d571	1413
xorjoep	3:4098b9d3d571	1414	/@}/ /* end of group CMSIS_TPI */
xorjoep	3:4098b9d3d571	1415
xorjoep	3:4098b9d3d571	1416
xorjoep	3:4098b9d3d571	1417	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
xorjoep	3:4098b9d3d571	1418	/**
xorjoep	3:4098b9d3d571	1419	\ingroup CMSIS_core_register
xorjoep	3:4098b9d3d571	1420	\defgroup CMSIS_MPU Memory Protection Unit (MPU)
xorjoep	3:4098b9d3d571	1421	\brief Type definitions for the Memory Protection Unit (MPU)
xorjoep	3:4098b9d3d571	1422	@{
xorjoep	3:4098b9d3d571	1423	*/
xorjoep	3:4098b9d3d571	1424
xorjoep	3:4098b9d3d571	1425	/**
xorjoep	3:4098b9d3d571	1426	\brief Structure type to access the Memory Protection Unit (MPU).
xorjoep	3:4098b9d3d571	1427	*/
xorjoep	3:4098b9d3d571	1428	typedef struct
xorjoep	3:4098b9d3d571	1429	{
xorjoep	3:4098b9d3d571	1430	__IM uint32_t TYPE; /!< Offset: 0x000 (R/ ) MPU Type Register /
xorjoep	3:4098b9d3d571	1431	__IOM uint32_t CTRL; /!< Offset: 0x004 (R/W) MPU Control Register /
xorjoep	3:4098b9d3d571	1432	__IOM uint32_t RNR; /!< Offset: 0x008 (R/W) MPU Region RNRber Register /
xorjoep	3:4098b9d3d571	1433	__IOM uint32_t RBAR; /!< Offset: 0x00C (R/W) MPU Region Base Address Register /
xorjoep	3:4098b9d3d571	1434	__IOM uint32_t RASR; /!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register /
xorjoep	3:4098b9d3d571	1435	__IOM uint32_t RBAR_A1; /!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register /
xorjoep	3:4098b9d3d571	1436	__IOM uint32_t RASR_A1; /!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register /
xorjoep	3:4098b9d3d571	1437	__IOM uint32_t RBAR_A2; /!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register /
xorjoep	3:4098b9d3d571	1438	__IOM uint32_t RASR_A2; /!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register /
xorjoep	3:4098b9d3d571	1439	__IOM uint32_t RBAR_A3; /!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register /
xorjoep	3:4098b9d3d571	1440	__IOM uint32_t RASR_A3; /!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register /
xorjoep	3:4098b9d3d571	1441	} MPU_Type;
xorjoep	3:4098b9d3d571	1442
xorjoep	3:4098b9d3d571	1443	#define MPU_TYPE_RALIASES 4U
xorjoep	3:4098b9d3d571	1444
xorjoep	3:4098b9d3d571	1445	/* MPU Type Register Definitions */
xorjoep	3:4098b9d3d571	1446	#define MPU_TYPE_IREGION_Pos 16U /!< MPU TYPE: IREGION Position /
xorjoep	3:4098b9d3d571	1447	#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
xorjoep	3:4098b9d3d571	1448
xorjoep	3:4098b9d3d571	1449	#define MPU_TYPE_DREGION_Pos 8U /!< MPU TYPE: DREGION Position /
xorjoep	3:4098b9d3d571	1450	#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
xorjoep	3:4098b9d3d571	1451
xorjoep	3:4098b9d3d571	1452	#define MPU_TYPE_SEPARATE_Pos 0U /!< MPU TYPE: SEPARATE Position /
xorjoep	3:4098b9d3d571	1453	#define MPU_TYPE_SEPARATE_Msk (1UL /<< MPU_TYPE_SEPARATE_Pos/) /!< MPU TYPE: SEPARATE Mask /
xorjoep	3:4098b9d3d571	1454
xorjoep	3:4098b9d3d571	1455	/* MPU Control Register Definitions */
xorjoep	3:4098b9d3d571	1456	#define MPU_CTRL_PRIVDEFENA_Pos 2U /!< MPU CTRL: PRIVDEFENA Position /
xorjoep	3:4098b9d3d571	1457	#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
xorjoep	3:4098b9d3d571	1458
xorjoep	3:4098b9d3d571	1459	#define MPU_CTRL_HFNMIENA_Pos 1U /!< MPU CTRL: HFNMIENA Position /
xorjoep	3:4098b9d3d571	1460	#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
xorjoep	3:4098b9d3d571	1461
xorjoep	3:4098b9d3d571	1462	#define MPU_CTRL_ENABLE_Pos 0U /!< MPU CTRL: ENABLE Position /
xorjoep	3:4098b9d3d571	1463	#define MPU_CTRL_ENABLE_Msk (1UL /<< MPU_CTRL_ENABLE_Pos/) /!< MPU CTRL: ENABLE Mask /
xorjoep	3:4098b9d3d571	1464
xorjoep	3:4098b9d3d571	1465	/* MPU Region Number Register Definitions */
xorjoep	3:4098b9d3d571	1466	#define MPU_RNR_REGION_Pos 0U /!< MPU RNR: REGION Position /
xorjoep	3:4098b9d3d571	1467	#define MPU_RNR_REGION_Msk (0xFFUL /<< MPU_RNR_REGION_Pos/) /!< MPU RNR: REGION Mask /
xorjoep	3:4098b9d3d571	1468
xorjoep	3:4098b9d3d571	1469	/* MPU Region Base Address Register Definitions */
xorjoep	3:4098b9d3d571	1470	#define MPU_RBAR_ADDR_Pos 5U /!< MPU RBAR: ADDR Position /
xorjoep	3:4098b9d3d571	1471	#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /!< MPU RBAR: ADDR Mask /
xorjoep	3:4098b9d3d571	1472
xorjoep	3:4098b9d3d571	1473	#define MPU_RBAR_VALID_Pos 4U /!< MPU RBAR: VALID Position /
xorjoep	3:4098b9d3d571	1474	#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /!< MPU RBAR: VALID Mask /
xorjoep	3:4098b9d3d571	1475
xorjoep	3:4098b9d3d571	1476	#define MPU_RBAR_REGION_Pos 0U /!< MPU RBAR: REGION Position /
xorjoep	3:4098b9d3d571	1477	#define MPU_RBAR_REGION_Msk (0xFUL /<< MPU_RBAR_REGION_Pos/) /!< MPU RBAR: REGION Mask /
xorjoep	3:4098b9d3d571	1478
xorjoep	3:4098b9d3d571	1479	/* MPU Region Attribute and Size Register Definitions */
xorjoep	3:4098b9d3d571	1480	#define MPU_RASR_ATTRS_Pos 16U /!< MPU RASR: MPU Region Attribute field Position /
xorjoep	3:4098b9d3d571	1481	#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /!< MPU RASR: MPU Region Attribute field Mask /
xorjoep	3:4098b9d3d571	1482
xorjoep	3:4098b9d3d571	1483	#define MPU_RASR_XN_Pos 28U /!< MPU RASR: ATTRS.XN Position /
xorjoep	3:4098b9d3d571	1484	#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /!< MPU RASR: ATTRS.XN Mask /
xorjoep	3:4098b9d3d571	1485
xorjoep	3:4098b9d3d571	1486	#define MPU_RASR_AP_Pos 24U /!< MPU RASR: ATTRS.AP Position /
xorjoep	3:4098b9d3d571	1487	#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /!< MPU RASR: ATTRS.AP Mask /
xorjoep	3:4098b9d3d571	1488
xorjoep	3:4098b9d3d571	1489	#define MPU_RASR_TEX_Pos 19U /!< MPU RASR: ATTRS.TEX Position /
xorjoep	3:4098b9d3d571	1490	#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /!< MPU RASR: ATTRS.TEX Mask /
xorjoep	3:4098b9d3d571	1491
xorjoep	3:4098b9d3d571	1492	#define MPU_RASR_S_Pos 18U /!< MPU RASR: ATTRS.S Position /
xorjoep	3:4098b9d3d571	1493	#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /!< MPU RASR: ATTRS.S Mask /
xorjoep	3:4098b9d3d571	1494
xorjoep	3:4098b9d3d571	1495	#define MPU_RASR_C_Pos 17U /!< MPU RASR: ATTRS.C Position /
xorjoep	3:4098b9d3d571	1496	#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /!< MPU RASR: ATTRS.C Mask /
xorjoep	3:4098b9d3d571	1497
xorjoep	3:4098b9d3d571	1498	#define MPU_RASR_B_Pos 16U /!< MPU RASR: ATTRS.B Position /
xorjoep	3:4098b9d3d571	1499	#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /!< MPU RASR: ATTRS.B Mask /
xorjoep	3:4098b9d3d571	1500
xorjoep	3:4098b9d3d571	1501	#define MPU_RASR_SRD_Pos 8U /!< MPU RASR: Sub-Region Disable Position /
xorjoep	3:4098b9d3d571	1502	#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /!< MPU RASR: Sub-Region Disable Mask /
xorjoep	3:4098b9d3d571	1503
xorjoep	3:4098b9d3d571	1504	#define MPU_RASR_SIZE_Pos 1U /!< MPU RASR: Region Size Field Position /
xorjoep	3:4098b9d3d571	1505	#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /!< MPU RASR: Region Size Field Mask /
xorjoep	3:4098b9d3d571	1506
xorjoep	3:4098b9d3d571	1507	#define MPU_RASR_ENABLE_Pos 0U /!< MPU RASR: Region enable bit Position /
xorjoep	3:4098b9d3d571	1508	#define MPU_RASR_ENABLE_Msk (1UL /<< MPU_RASR_ENABLE_Pos/) /!< MPU RASR: Region enable bit Disable Mask /
xorjoep	3:4098b9d3d571	1509
xorjoep	3:4098b9d3d571	1510	/@} end of group CMSIS_MPU /
xorjoep	3:4098b9d3d571	1511	#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
xorjoep	3:4098b9d3d571	1512
xorjoep	3:4098b9d3d571	1513
xorjoep	3:4098b9d3d571	1514	/**
xorjoep	3:4098b9d3d571	1515	\ingroup CMSIS_core_register
xorjoep	3:4098b9d3d571	1516	\defgroup CMSIS_FPU Floating Point Unit (FPU)
xorjoep	3:4098b9d3d571	1517	\brief Type definitions for the Floating Point Unit (FPU)
xorjoep	3:4098b9d3d571	1518	@{
xorjoep	3:4098b9d3d571	1519	*/
xorjoep	3:4098b9d3d571	1520
xorjoep	3:4098b9d3d571	1521	/**
xorjoep	3:4098b9d3d571	1522	\brief Structure type to access the Floating Point Unit (FPU).
xorjoep	3:4098b9d3d571	1523	*/
xorjoep	3:4098b9d3d571	1524	typedef struct
xorjoep	3:4098b9d3d571	1525	{
xorjoep	3:4098b9d3d571	1526	uint32_t RESERVED0[1U];
xorjoep	3:4098b9d3d571	1527	__IOM uint32_t FPCCR; /!< Offset: 0x004 (R/W) Floating-Point Context Control Register /
xorjoep	3:4098b9d3d571	1528	__IOM uint32_t FPCAR; /!< Offset: 0x008 (R/W) Floating-Point Context Address Register /
xorjoep	3:4098b9d3d571	1529	__IOM uint32_t FPDSCR; /!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register /
xorjoep	3:4098b9d3d571	1530	__IM uint32_t MVFR0; /!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 /
xorjoep	3:4098b9d3d571	1531	__IM uint32_t MVFR1; /!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 /
xorjoep	3:4098b9d3d571	1532	__IM uint32_t MVFR2; /!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 /
xorjoep	3:4098b9d3d571	1533	} FPU_Type;
xorjoep	3:4098b9d3d571	1534
xorjoep	3:4098b9d3d571	1535	/* Floating-Point Context Control Register Definitions */
xorjoep	3:4098b9d3d571	1536	#define FPU_FPCCR_ASPEN_Pos 31U /!< FPCCR: ASPEN bit Position /
xorjoep	3:4098b9d3d571	1537	#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /!< FPCCR: ASPEN bit Mask /
xorjoep	3:4098b9d3d571	1538
xorjoep	3:4098b9d3d571	1539	#define FPU_FPCCR_LSPEN_Pos 30U /!< FPCCR: LSPEN Position /
xorjoep	3:4098b9d3d571	1540	#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /!< FPCCR: LSPEN bit Mask /
xorjoep	3:4098b9d3d571	1541
xorjoep	3:4098b9d3d571	1542	#define FPU_FPCCR_MONRDY_Pos 8U /!< FPCCR: MONRDY Position /
xorjoep	3:4098b9d3d571	1543	#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /!< FPCCR: MONRDY bit Mask /
xorjoep	3:4098b9d3d571	1544
xorjoep	3:4098b9d3d571	1545	#define FPU_FPCCR_BFRDY_Pos 6U /!< FPCCR: BFRDY Position /
xorjoep	3:4098b9d3d571	1546	#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /!< FPCCR: BFRDY bit Mask /
xorjoep	3:4098b9d3d571	1547
xorjoep	3:4098b9d3d571	1548	#define FPU_FPCCR_MMRDY_Pos 5U /!< FPCCR: MMRDY Position /
xorjoep	3:4098b9d3d571	1549	#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /!< FPCCR: MMRDY bit Mask /
xorjoep	3:4098b9d3d571	1550
xorjoep	3:4098b9d3d571	1551	#define FPU_FPCCR_HFRDY_Pos 4U /!< FPCCR: HFRDY Position /
xorjoep	3:4098b9d3d571	1552	#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /!< FPCCR: HFRDY bit Mask /
xorjoep	3:4098b9d3d571	1553
xorjoep	3:4098b9d3d571	1554	#define FPU_FPCCR_THREAD_Pos 3U /!< FPCCR: processor mode bit Position /
xorjoep	3:4098b9d3d571	1555	#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /!< FPCCR: processor mode active bit Mask /
xorjoep	3:4098b9d3d571	1556
xorjoep	3:4098b9d3d571	1557	#define FPU_FPCCR_USER_Pos 1U /!< FPCCR: privilege level bit Position /
xorjoep	3:4098b9d3d571	1558	#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /!< FPCCR: privilege level bit Mask /
xorjoep	3:4098b9d3d571	1559
xorjoep	3:4098b9d3d571	1560	#define FPU_FPCCR_LSPACT_Pos 0U /!< FPCCR: Lazy state preservation active bit Position /
xorjoep	3:4098b9d3d571	1561	#define FPU_FPCCR_LSPACT_Msk (1UL /<< FPU_FPCCR_LSPACT_Pos/) /!< FPCCR: Lazy state preservation active bit Mask /
xorjoep	3:4098b9d3d571	1562
xorjoep	3:4098b9d3d571	1563	/* Floating-Point Context Address Register Definitions */
xorjoep	3:4098b9d3d571	1564	#define FPU_FPCAR_ADDRESS_Pos 3U /!< FPCAR: ADDRESS bit Position /
xorjoep	3:4098b9d3d571	1565	#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /!< FPCAR: ADDRESS bit Mask /
xorjoep	3:4098b9d3d571	1566
xorjoep	3:4098b9d3d571	1567	/* Floating-Point Default Status Control Register Definitions */
xorjoep	3:4098b9d3d571	1568	#define FPU_FPDSCR_AHP_Pos 26U /!< FPDSCR: AHP bit Position /
xorjoep	3:4098b9d3d571	1569	#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /!< FPDSCR: AHP bit Mask /
xorjoep	3:4098b9d3d571	1570
xorjoep	3:4098b9d3d571	1571	#define FPU_FPDSCR_DN_Pos 25U /!< FPDSCR: DN bit Position /
xorjoep	3:4098b9d3d571	1572	#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /!< FPDSCR: DN bit Mask /
xorjoep	3:4098b9d3d571	1573
xorjoep	3:4098b9d3d571	1574	#define FPU_FPDSCR_FZ_Pos 24U /!< FPDSCR: FZ bit Position /
xorjoep	3:4098b9d3d571	1575	#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /!< FPDSCR: FZ bit Mask /
xorjoep	3:4098b9d3d571	1576
xorjoep	3:4098b9d3d571	1577	#define FPU_FPDSCR_RMode_Pos 22U /!< FPDSCR: RMode bit Position /
xorjoep	3:4098b9d3d571	1578	#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /!< FPDSCR: RMode bit Mask /
xorjoep	3:4098b9d3d571	1579
xorjoep	3:4098b9d3d571	1580	/* Media and FP Feature Register 0 Definitions */
xorjoep	3:4098b9d3d571	1581	#define FPU_MVFR0_FP_rounding_modes_Pos 28U /!< MVFR0: FP rounding modes bits Position /
xorjoep	3:4098b9d3d571	1582	#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /!< MVFR0: FP rounding modes bits Mask /
xorjoep	3:4098b9d3d571	1583
xorjoep	3:4098b9d3d571	1584	#define FPU_MVFR0_Short_vectors_Pos 24U /!< MVFR0: Short vectors bits Position /
xorjoep	3:4098b9d3d571	1585	#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /!< MVFR0: Short vectors bits Mask /
xorjoep	3:4098b9d3d571	1586
xorjoep	3:4098b9d3d571	1587	#define FPU_MVFR0_Square_root_Pos 20U /!< MVFR0: Square root bits Position /
xorjoep	3:4098b9d3d571	1588	#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /!< MVFR0: Square root bits Mask /
xorjoep	3:4098b9d3d571	1589
xorjoep	3:4098b9d3d571	1590	#define FPU_MVFR0_Divide_Pos 16U /!< MVFR0: Divide bits Position /
xorjoep	3:4098b9d3d571	1591	#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /!< MVFR0: Divide bits Mask /
xorjoep	3:4098b9d3d571	1592
xorjoep	3:4098b9d3d571	1593	#define FPU_MVFR0_FP_excep_trapping_Pos 12U /!< MVFR0: FP exception trapping bits Position /
xorjoep	3:4098b9d3d571	1594	#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /!< MVFR0: FP exception trapping bits Mask /
xorjoep	3:4098b9d3d571	1595
xorjoep	3:4098b9d3d571	1596	#define FPU_MVFR0_Double_precision_Pos 8U /!< MVFR0: Double-precision bits Position /
xorjoep	3:4098b9d3d571	1597	#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /!< MVFR0: Double-precision bits Mask /
xorjoep	3:4098b9d3d571	1598
xorjoep	3:4098b9d3d571	1599	#define FPU_MVFR0_Single_precision_Pos 4U /!< MVFR0: Single-precision bits Position /
xorjoep	3:4098b9d3d571	1600	#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /!< MVFR0: Single-precision bits Mask /
xorjoep	3:4098b9d3d571	1601
xorjoep	3:4098b9d3d571	1602	#define FPU_MVFR0_A_SIMD_registers_Pos 0U /!< MVFR0: A_SIMD registers bits Position /
xorjoep	3:4098b9d3d571	1603	#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /<< FPU_MVFR0_A_SIMD_registers_Pos/) /!< MVFR0: A_SIMD registers bits Mask /
xorjoep	3:4098b9d3d571	1604
xorjoep	3:4098b9d3d571	1605	/* Media and FP Feature Register 1 Definitions */
xorjoep	3:4098b9d3d571	1606	#define FPU_MVFR1_FP_fused_MAC_Pos 28U /!< MVFR1: FP fused MAC bits Position /
xorjoep	3:4098b9d3d571	1607	#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /!< MVFR1: FP fused MAC bits Mask /
xorjoep	3:4098b9d3d571	1608
xorjoep	3:4098b9d3d571	1609	#define FPU_MVFR1_FP_HPFP_Pos 24U /!< MVFR1: FP HPFP bits Position /
xorjoep	3:4098b9d3d571	1610	#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /!< MVFR1: FP HPFP bits Mask /
xorjoep	3:4098b9d3d571	1611
xorjoep	3:4098b9d3d571	1612	#define FPU_MVFR1_D_NaN_mode_Pos 4U /!< MVFR1: D_NaN mode bits Position /
xorjoep	3:4098b9d3d571	1613	#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /!< MVFR1: D_NaN mode bits Mask /
xorjoep	3:4098b9d3d571	1614
xorjoep	3:4098b9d3d571	1615	#define FPU_MVFR1_FtZ_mode_Pos 0U /!< MVFR1: FtZ mode bits Position /
xorjoep	3:4098b9d3d571	1616	#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /<< FPU_MVFR1_FtZ_mode_Pos/) /!< MVFR1: FtZ mode bits Mask /
xorjoep	3:4098b9d3d571	1617
xorjoep	3:4098b9d3d571	1618	/* Media and FP Feature Register 2 Definitions */
xorjoep	3:4098b9d3d571	1619
xorjoep	3:4098b9d3d571	1620	/@} end of group CMSIS_FPU /
xorjoep	3:4098b9d3d571	1621
xorjoep	3:4098b9d3d571	1622
xorjoep	3:4098b9d3d571	1623	/**
xorjoep	3:4098b9d3d571	1624	\ingroup CMSIS_core_register
xorjoep	3:4098b9d3d571	1625	\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
xorjoep	3:4098b9d3d571	1626	\brief Type definitions for the Core Debug Registers
xorjoep	3:4098b9d3d571	1627	@{
xorjoep	3:4098b9d3d571	1628	*/
xorjoep	3:4098b9d3d571	1629
xorjoep	3:4098b9d3d571	1630	/**
xorjoep	3:4098b9d3d571	1631	\brief Structure type to access the Core Debug Register (CoreDebug).
xorjoep	3:4098b9d3d571	1632	*/
xorjoep	3:4098b9d3d571	1633	typedef struct
xorjoep	3:4098b9d3d571	1634	{
xorjoep	3:4098b9d3d571	1635	__IOM uint32_t DHCSR; /!< Offset: 0x000 (R/W) Debug Halting Control and Status Register /
xorjoep	3:4098b9d3d571	1636	__OM uint32_t DCRSR; /!< Offset: 0x004 ( /W) Debug Core Register Selector Register /
xorjoep	3:4098b9d3d571	1637	__IOM uint32_t DCRDR; /!< Offset: 0x008 (R/W) Debug Core Register Data Register /
xorjoep	3:4098b9d3d571	1638	__IOM uint32_t DEMCR; /!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register /
xorjoep	3:4098b9d3d571	1639	} CoreDebug_Type;
xorjoep	3:4098b9d3d571	1640
xorjoep	3:4098b9d3d571	1641	/* Debug Halting Control and Status Register Definitions */
xorjoep	3:4098b9d3d571	1642	#define CoreDebug_DHCSR_DBGKEY_Pos 16U /!< CoreDebug DHCSR: DBGKEY Position /
xorjoep	3:4098b9d3d571	1643	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
xorjoep	3:4098b9d3d571	1644
xorjoep	3:4098b9d3d571	1645	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /!< CoreDebug DHCSR: S_RESET_ST Position /
xorjoep	3:4098b9d3d571	1646	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
xorjoep	3:4098b9d3d571	1647
xorjoep	3:4098b9d3d571	1648	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /!< CoreDebug DHCSR: S_RETIRE_ST Position /
xorjoep	3:4098b9d3d571	1649	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
xorjoep	3:4098b9d3d571	1650
xorjoep	3:4098b9d3d571	1651	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /!< CoreDebug DHCSR: S_LOCKUP Position /
xorjoep	3:4098b9d3d571	1652	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
xorjoep	3:4098b9d3d571	1653
xorjoep	3:4098b9d3d571	1654	#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /!< CoreDebug DHCSR: S_SLEEP Position /
xorjoep	3:4098b9d3d571	1655	#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
xorjoep	3:4098b9d3d571	1656
xorjoep	3:4098b9d3d571	1657	#define CoreDebug_DHCSR_S_HALT_Pos 17U /!< CoreDebug DHCSR: S_HALT Position /
xorjoep	3:4098b9d3d571	1658	#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
xorjoep	3:4098b9d3d571	1659
xorjoep	3:4098b9d3d571	1660	#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /!< CoreDebug DHCSR: S_REGRDY Position /
xorjoep	3:4098b9d3d571	1661	#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
xorjoep	3:4098b9d3d571	1662
xorjoep	3:4098b9d3d571	1663	#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /!< CoreDebug DHCSR: C_SNAPSTALL Position /
xorjoep	3:4098b9d3d571	1664	#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /!< CoreDebug DHCSR: C_SNAPSTALL Mask /
xorjoep	3:4098b9d3d571	1665
xorjoep	3:4098b9d3d571	1666	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /!< CoreDebug DHCSR: C_MASKINTS Position /
xorjoep	3:4098b9d3d571	1667	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
xorjoep	3:4098b9d3d571	1668
xorjoep	3:4098b9d3d571	1669	#define CoreDebug_DHCSR_C_STEP_Pos 2U /!< CoreDebug DHCSR: C_STEP Position /
xorjoep	3:4098b9d3d571	1670	#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
xorjoep	3:4098b9d3d571	1671
xorjoep	3:4098b9d3d571	1672	#define CoreDebug_DHCSR_C_HALT_Pos 1U /!< CoreDebug DHCSR: C_HALT Position /
xorjoep	3:4098b9d3d571	1673	#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
xorjoep	3:4098b9d3d571	1674
xorjoep	3:4098b9d3d571	1675	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /!< CoreDebug DHCSR: C_DEBUGEN Position /
xorjoep	3:4098b9d3d571	1676	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
xorjoep	3:4098b9d3d571	1677
xorjoep	3:4098b9d3d571	1678	/* Debug Core Register Selector Register Definitions */
xorjoep	3:4098b9d3d571	1679	#define CoreDebug_DCRSR_REGWnR_Pos 16U /!< CoreDebug DCRSR: REGWnR Position /
xorjoep	3:4098b9d3d571	1680	#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
xorjoep	3:4098b9d3d571	1681
xorjoep	3:4098b9d3d571	1682	#define CoreDebug_DCRSR_REGSEL_Pos 0U /!< CoreDebug DCRSR: REGSEL Position /
xorjoep	3:4098b9d3d571	1683	#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/) /!< CoreDebug DCRSR: REGSEL Mask /
xorjoep	3:4098b9d3d571	1684
xorjoep	3:4098b9d3d571	1685	/* Debug Exception and Monitor Control Register Definitions */
xorjoep	3:4098b9d3d571	1686	#define CoreDebug_DEMCR_TRCENA_Pos 24U /!< CoreDebug DEMCR: TRCENA Position /
xorjoep	3:4098b9d3d571	1687	#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /!< CoreDebug DEMCR: TRCENA Mask /
xorjoep	3:4098b9d3d571	1688
xorjoep	3:4098b9d3d571	1689	#define CoreDebug_DEMCR_MON_REQ_Pos 19U /!< CoreDebug DEMCR: MON_REQ Position /
xorjoep	3:4098b9d3d571	1690	#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /!< CoreDebug DEMCR: MON_REQ Mask /
xorjoep	3:4098b9d3d571	1691
xorjoep	3:4098b9d3d571	1692	#define CoreDebug_DEMCR_MON_STEP_Pos 18U /!< CoreDebug DEMCR: MON_STEP Position /
xorjoep	3:4098b9d3d571	1693	#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /!< CoreDebug DEMCR: MON_STEP Mask /
xorjoep	3:4098b9d3d571	1694
xorjoep	3:4098b9d3d571	1695	#define CoreDebug_DEMCR_MON_PEND_Pos 17U /!< CoreDebug DEMCR: MON_PEND Position /
xorjoep	3:4098b9d3d571	1696	#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /!< CoreDebug DEMCR: MON_PEND Mask /
xorjoep	3:4098b9d3d571	1697
xorjoep	3:4098b9d3d571	1698	#define CoreDebug_DEMCR_MON_EN_Pos 16U /!< CoreDebug DEMCR: MON_EN Position /
xorjoep	3:4098b9d3d571	1699	#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /!< CoreDebug DEMCR: MON_EN Mask /
xorjoep	3:4098b9d3d571	1700
xorjoep	3:4098b9d3d571	1701	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /!< CoreDebug DEMCR: VC_HARDERR Position /
xorjoep	3:4098b9d3d571	1702	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
xorjoep	3:4098b9d3d571	1703
xorjoep	3:4098b9d3d571	1704	#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /!< CoreDebug DEMCR: VC_INTERR Position /
xorjoep	3:4098b9d3d571	1705	#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /!< CoreDebug DEMCR: VC_INTERR Mask /
xorjoep	3:4098b9d3d571	1706
xorjoep	3:4098b9d3d571	1707	#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /!< CoreDebug DEMCR: VC_BUSERR Position /
xorjoep	3:4098b9d3d571	1708	#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /!< CoreDebug DEMCR: VC_BUSERR Mask /
xorjoep	3:4098b9d3d571	1709
xorjoep	3:4098b9d3d571	1710	#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /!< CoreDebug DEMCR: VC_STATERR Position /
xorjoep	3:4098b9d3d571	1711	#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /!< CoreDebug DEMCR: VC_STATERR Mask /
xorjoep	3:4098b9d3d571	1712
xorjoep	3:4098b9d3d571	1713	#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /!< CoreDebug DEMCR: VC_CHKERR Position /
xorjoep	3:4098b9d3d571	1714	#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /!< CoreDebug DEMCR: VC_CHKERR Mask /
xorjoep	3:4098b9d3d571	1715
xorjoep	3:4098b9d3d571	1716	#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /!< CoreDebug DEMCR: VC_NOCPERR Position /
xorjoep	3:4098b9d3d571	1717	#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /!< CoreDebug DEMCR: VC_NOCPERR Mask /
xorjoep	3:4098b9d3d571	1718
xorjoep	3:4098b9d3d571	1719	#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /!< CoreDebug DEMCR: VC_MMERR Position /
xorjoep	3:4098b9d3d571	1720	#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /!< CoreDebug DEMCR: VC_MMERR Mask /
xorjoep	3:4098b9d3d571	1721
xorjoep	3:4098b9d3d571	1722	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /!< CoreDebug DEMCR: VC_CORERESET Position /
xorjoep	3:4098b9d3d571	1723	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/) /!< CoreDebug DEMCR: VC_CORERESET Mask /
xorjoep	3:4098b9d3d571	1724
xorjoep	3:4098b9d3d571	1725	/@} end of group CMSIS_CoreDebug /
xorjoep	3:4098b9d3d571	1726
xorjoep	3:4098b9d3d571	1727
xorjoep	3:4098b9d3d571	1728	/**
xorjoep	3:4098b9d3d571	1729	\ingroup CMSIS_core_register
xorjoep	3:4098b9d3d571	1730	\defgroup CMSIS_core_bitfield Core register bit field macros
xorjoep	3:4098b9d3d571	1731	\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
xorjoep	3:4098b9d3d571	1732	@{
xorjoep	3:4098b9d3d571	1733	*/
xorjoep	3:4098b9d3d571	1734
xorjoep	3:4098b9d3d571	1735	/**
xorjoep	3:4098b9d3d571	1736	\brief Mask and shift a bit field value for use in a register bit range.
xorjoep	3:4098b9d3d571	1737	\param[in] field Name of the register bit field.
xorjoep	3:4098b9d3d571	1738	\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
xorjoep	3:4098b9d3d571	1739	\return Masked and shifted value.
xorjoep	3:4098b9d3d571	1740	*/
xorjoep	3:4098b9d3d571	1741	#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
xorjoep	3:4098b9d3d571	1742
xorjoep	3:4098b9d3d571	1743	/**
xorjoep	3:4098b9d3d571	1744	\brief Mask and shift a register value to extract a bit filed value.
xorjoep	3:4098b9d3d571	1745	\param[in] field Name of the register bit field.
xorjoep	3:4098b9d3d571	1746	\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
xorjoep	3:4098b9d3d571	1747	\return Masked and shifted bit field value.
xorjoep	3:4098b9d3d571	1748	*/
xorjoep	3:4098b9d3d571	1749	#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
xorjoep	3:4098b9d3d571	1750
xorjoep	3:4098b9d3d571	1751	/@} end of group CMSIS_core_bitfield /
xorjoep	3:4098b9d3d571	1752
xorjoep	3:4098b9d3d571	1753
xorjoep	3:4098b9d3d571	1754	/**
xorjoep	3:4098b9d3d571	1755	\ingroup CMSIS_core_register
xorjoep	3:4098b9d3d571	1756	\defgroup CMSIS_core_base Core Definitions
xorjoep	3:4098b9d3d571	1757	\brief Definitions for base addresses, unions, and structures.
xorjoep	3:4098b9d3d571	1758	@{
xorjoep	3:4098b9d3d571	1759	*/
xorjoep	3:4098b9d3d571	1760
xorjoep	3:4098b9d3d571	1761	/* Memory mapping of Core Hardware */
xorjoep	3:4098b9d3d571	1762	#define SCS_BASE (0xE000E000UL) /!< System Control Space Base Address /
xorjoep	3:4098b9d3d571	1763	#define ITM_BASE (0xE0000000UL) /!< ITM Base Address /
xorjoep	3:4098b9d3d571	1764	#define DWT_BASE (0xE0001000UL) /!< DWT Base Address /
xorjoep	3:4098b9d3d571	1765	#define TPI_BASE (0xE0040000UL) /!< TPI Base Address /
xorjoep	3:4098b9d3d571	1766	#define CoreDebug_BASE (0xE000EDF0UL) /!< Core Debug Base Address /
xorjoep	3:4098b9d3d571	1767	#define SysTick_BASE (SCS_BASE + 0x0010UL) /!< SysTick Base Address /
xorjoep	3:4098b9d3d571	1768	#define NVIC_BASE (SCS_BASE + 0x0100UL) /!< NVIC Base Address /
xorjoep	3:4098b9d3d571	1769	#define SCB_BASE (SCS_BASE + 0x0D00UL) /!< System Control Block Base Address /
xorjoep	3:4098b9d3d571	1770
xorjoep	3:4098b9d3d571	1771	#define SCnSCB ((SCnSCB_Type ) SCS_BASE ) /!< System control Register not in SCB */
xorjoep	3:4098b9d3d571	1772	#define SCB ((SCB_Type ) SCB_BASE ) /!< SCB configuration struct */
xorjoep	3:4098b9d3d571	1773	#define SysTick ((SysTick_Type ) SysTick_BASE ) /!< SysTick configuration struct */
xorjoep	3:4098b9d3d571	1774	#define NVIC ((NVIC_Type ) NVIC_BASE ) /!< NVIC configuration struct */
xorjoep	3:4098b9d3d571	1775	#define ITM ((ITM_Type ) ITM_BASE ) /!< ITM configuration struct */
xorjoep	3:4098b9d3d571	1776	#define DWT ((DWT_Type ) DWT_BASE ) /!< DWT configuration struct */
xorjoep	3:4098b9d3d571	1777	#define TPI ((TPI_Type ) TPI_BASE ) /!< TPI configuration struct */
xorjoep	3:4098b9d3d571	1778	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE) /!< Core Debug configuration struct */
xorjoep	3:4098b9d3d571	1779
xorjoep	3:4098b9d3d571	1780	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
xorjoep	3:4098b9d3d571	1781	#define MPU_BASE (SCS_BASE + 0x0D90UL) /!< Memory Protection Unit /
xorjoep	3:4098b9d3d571	1782	#define MPU ((MPU_Type ) MPU_BASE ) /!< Memory Protection Unit */
xorjoep	3:4098b9d3d571	1783	#endif
xorjoep	3:4098b9d3d571	1784
xorjoep	3:4098b9d3d571	1785	#define FPU_BASE (SCS_BASE + 0x0F30UL) /!< Floating Point Unit /
xorjoep	3:4098b9d3d571	1786	#define FPU ((FPU_Type ) FPU_BASE ) /!< Floating Point Unit */
xorjoep	3:4098b9d3d571	1787
xorjoep	3:4098b9d3d571	1788	/@} /
xorjoep	3:4098b9d3d571	1789
xorjoep	3:4098b9d3d571	1790
xorjoep	3:4098b9d3d571	1791
xorjoep	3:4098b9d3d571	1792	/*******************************************************************************
xorjoep	3:4098b9d3d571	1793	* Hardware Abstraction Layer
xorjoep	3:4098b9d3d571	1794	Core Function Interface contains:
xorjoep	3:4098b9d3d571	1795	- Core NVIC Functions
xorjoep	3:4098b9d3d571	1796	- Core SysTick Functions
xorjoep	3:4098b9d3d571	1797	- Core Debug Functions
xorjoep	3:4098b9d3d571	1798	- Core Register Access Functions
xorjoep	3:4098b9d3d571	1799	******************************************************************************/
xorjoep	3:4098b9d3d571	1800	/**
xorjoep	3:4098b9d3d571	1801	\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
xorjoep	3:4098b9d3d571	1802	*/
xorjoep	3:4098b9d3d571	1803
xorjoep	3:4098b9d3d571	1804
xorjoep	3:4098b9d3d571	1805
xorjoep	3:4098b9d3d571	1806	/* ########################## NVIC functions #################################### */
xorjoep	3:4098b9d3d571	1807	/**
xorjoep	3:4098b9d3d571	1808	\ingroup CMSIS_Core_FunctionInterface
xorjoep	3:4098b9d3d571	1809	\defgroup CMSIS_Core_NVICFunctions NVIC Functions
xorjoep	3:4098b9d3d571	1810	\brief Functions that manage interrupts and exceptions via the NVIC.
xorjoep	3:4098b9d3d571	1811	@{
xorjoep	3:4098b9d3d571	1812	*/
xorjoep	3:4098b9d3d571	1813
xorjoep	3:4098b9d3d571	1814	#ifdef CMSIS_NVIC_VIRTUAL
xorjoep	3:4098b9d3d571	1815	#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
xorjoep	3:4098b9d3d571	1816	#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
xorjoep	3:4098b9d3d571	1817	#endif
xorjoep	3:4098b9d3d571	1818	#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
xorjoep	3:4098b9d3d571	1819	#else
xorjoep	3:4098b9d3d571	1820	#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
xorjoep	3:4098b9d3d571	1821	#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
xorjoep	3:4098b9d3d571	1822	#define NVIC_EnableIRQ __NVIC_EnableIRQ
xorjoep	3:4098b9d3d571	1823	#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
xorjoep	3:4098b9d3d571	1824	#define NVIC_DisableIRQ __NVIC_DisableIRQ
xorjoep	3:4098b9d3d571	1825	#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
xorjoep	3:4098b9d3d571	1826	#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
xorjoep	3:4098b9d3d571	1827	#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
xorjoep	3:4098b9d3d571	1828	#define NVIC_GetActive __NVIC_GetActive
xorjoep	3:4098b9d3d571	1829	#define NVIC_SetPriority __NVIC_SetPriority
xorjoep	3:4098b9d3d571	1830	#define NVIC_GetPriority __NVIC_GetPriority
xorjoep	3:4098b9d3d571	1831	#define NVIC_SystemReset __NVIC_SystemReset
xorjoep	3:4098b9d3d571	1832	#endif /* CMSIS_NVIC_VIRTUAL */
xorjoep	3:4098b9d3d571	1833
xorjoep	3:4098b9d3d571	1834	#ifdef CMSIS_VECTAB_VIRTUAL
xorjoep	3:4098b9d3d571	1835	#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
xorjoep	3:4098b9d3d571	1836	#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
xorjoep	3:4098b9d3d571	1837	#endif
xorjoep	3:4098b9d3d571	1838	#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
xorjoep	3:4098b9d3d571	1839	#else
xorjoep	3:4098b9d3d571	1840	#define NVIC_SetVector __NVIC_SetVector
xorjoep	3:4098b9d3d571	1841	#define NVIC_GetVector __NVIC_GetVector
xorjoep	3:4098b9d3d571	1842	#endif /* (CMSIS_VECTAB_VIRTUAL) */
xorjoep	3:4098b9d3d571	1843
xorjoep	3:4098b9d3d571	1844	#define NVIC_USER_IRQ_OFFSET 16
xorjoep	3:4098b9d3d571	1845
xorjoep	3:4098b9d3d571	1846
xorjoep	3:4098b9d3d571	1847	/* The following EXC_RETURN values are saved the LR on exception entry */
xorjoep	3:4098b9d3d571	1848	#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
xorjoep	3:4098b9d3d571	1849	#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
xorjoep	3:4098b9d3d571	1850	#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
xorjoep	3:4098b9d3d571	1851	#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */
xorjoep	3:4098b9d3d571	1852	#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */
xorjoep	3:4098b9d3d571	1853	#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */
xorjoep	3:4098b9d3d571	1854
xorjoep	3:4098b9d3d571	1855
xorjoep	3:4098b9d3d571	1856	/**
xorjoep	3:4098b9d3d571	1857	\brief Set Priority Grouping
xorjoep	3:4098b9d3d571	1858	\details Sets the priority grouping field using the required unlock sequence.
xorjoep	3:4098b9d3d571	1859	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
xorjoep	3:4098b9d3d571	1860	Only values from 0..7 are used.
xorjoep	3:4098b9d3d571	1861	In case of a conflict between priority grouping and available
xorjoep	3:4098b9d3d571	1862	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
xorjoep	3:4098b9d3d571	1863	\param [in] PriorityGroup Priority grouping field.
xorjoep	3:4098b9d3d571	1864	*/
xorjoep	3:4098b9d3d571	1865	__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
xorjoep	3:4098b9d3d571	1866	{
xorjoep	3:4098b9d3d571	1867	uint32_t reg_value;
xorjoep	3:4098b9d3d571	1868	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
xorjoep	3:4098b9d3d571	1869
xorjoep	3:4098b9d3d571	1870	reg_value = SCB->AIRCR; /* read old register configuration */
xorjoep	3:4098b9d3d571	1871	reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
xorjoep	3:4098b9d3d571	1872	reg_value = (reg_value \|
xorjoep	3:4098b9d3d571	1873	((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
xorjoep	3:4098b9d3d571	1874	(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
xorjoep	3:4098b9d3d571	1875	SCB->AIRCR = reg_value;
xorjoep	3:4098b9d3d571	1876	}
xorjoep	3:4098b9d3d571	1877
xorjoep	3:4098b9d3d571	1878
xorjoep	3:4098b9d3d571	1879	/**
xorjoep	3:4098b9d3d571	1880	\brief Get Priority Grouping
xorjoep	3:4098b9d3d571	1881	\details Reads the priority grouping field from the NVIC Interrupt Controller.
xorjoep	3:4098b9d3d571	1882	\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
xorjoep	3:4098b9d3d571	1883	*/
xorjoep	3:4098b9d3d571	1884	__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
xorjoep	3:4098b9d3d571	1885	{
xorjoep	3:4098b9d3d571	1886	return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
xorjoep	3:4098b9d3d571	1887	}
xorjoep	3:4098b9d3d571	1888
xorjoep	3:4098b9d3d571	1889
xorjoep	3:4098b9d3d571	1890	/**
xorjoep	3:4098b9d3d571	1891	\brief Enable Interrupt
xorjoep	3:4098b9d3d571	1892	\details Enables a device specific interrupt in the NVIC interrupt controller.
xorjoep	3:4098b9d3d571	1893	\param [in] IRQn Device specific interrupt number.
xorjoep	3:4098b9d3d571	1894	\note IRQn must not be negative.
xorjoep	3:4098b9d3d571	1895	*/
xorjoep	3:4098b9d3d571	1896	__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
xorjoep	3:4098b9d3d571	1897	{
xorjoep	3:4098b9d3d571	1898	if ((int32_t)(IRQn) >= 0)
xorjoep	3:4098b9d3d571	1899	{
xorjoep	3:4098b9d3d571	1900	NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
xorjoep	3:4098b9d3d571	1901	}
xorjoep	3:4098b9d3d571	1902	}
xorjoep	3:4098b9d3d571	1903
xorjoep	3:4098b9d3d571	1904
xorjoep	3:4098b9d3d571	1905	/**
xorjoep	3:4098b9d3d571	1906	\brief Get Interrupt Enable status
xorjoep	3:4098b9d3d571	1907	\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
xorjoep	3:4098b9d3d571	1908	\param [in] IRQn Device specific interrupt number.
xorjoep	3:4098b9d3d571	1909	\return 0 Interrupt is not enabled.
xorjoep	3:4098b9d3d571	1910	\return 1 Interrupt is enabled.
xorjoep	3:4098b9d3d571	1911	\note IRQn must not be negative.
xorjoep	3:4098b9d3d571	1912	*/
xorjoep	3:4098b9d3d571	1913	__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
xorjoep	3:4098b9d3d571	1914	{
xorjoep	3:4098b9d3d571	1915	if ((int32_t)(IRQn) >= 0)
xorjoep	3:4098b9d3d571	1916	{
xorjoep	3:4098b9d3d571	1917	return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
xorjoep	3:4098b9d3d571	1918	}
xorjoep	3:4098b9d3d571	1919	else
xorjoep	3:4098b9d3d571	1920	{
xorjoep	3:4098b9d3d571	1921	return(0U);
xorjoep	3:4098b9d3d571	1922	}
xorjoep	3:4098b9d3d571	1923	}
xorjoep	3:4098b9d3d571	1924
xorjoep	3:4098b9d3d571	1925
xorjoep	3:4098b9d3d571	1926	/**
xorjoep	3:4098b9d3d571	1927	\brief Disable Interrupt
xorjoep	3:4098b9d3d571	1928	\details Disables a device specific interrupt in the NVIC interrupt controller.
xorjoep	3:4098b9d3d571	1929	\param [in] IRQn Device specific interrupt number.
xorjoep	3:4098b9d3d571	1930	\note IRQn must not be negative.
xorjoep	3:4098b9d3d571	1931	*/
xorjoep	3:4098b9d3d571	1932	__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
xorjoep	3:4098b9d3d571	1933	{
xorjoep	3:4098b9d3d571	1934	if ((int32_t)(IRQn) >= 0)
xorjoep	3:4098b9d3d571	1935	{
xorjoep	3:4098b9d3d571	1936	NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
xorjoep	3:4098b9d3d571	1937	__DSB();
xorjoep	3:4098b9d3d571	1938	__ISB();
xorjoep	3:4098b9d3d571	1939	}
xorjoep	3:4098b9d3d571	1940	}
xorjoep	3:4098b9d3d571	1941
xorjoep	3:4098b9d3d571	1942
xorjoep	3:4098b9d3d571	1943	/**
xorjoep	3:4098b9d3d571	1944	\brief Get Pending Interrupt
xorjoep	3:4098b9d3d571	1945	\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
xorjoep	3:4098b9d3d571	1946	\param [in] IRQn Device specific interrupt number.
xorjoep	3:4098b9d3d571	1947	\return 0 Interrupt status is not pending.
xorjoep	3:4098b9d3d571	1948	\return 1 Interrupt status is pending.
xorjoep	3:4098b9d3d571	1949	\note IRQn must not be negative.
xorjoep	3:4098b9d3d571	1950	*/
xorjoep	3:4098b9d3d571	1951	__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
xorjoep	3:4098b9d3d571	1952	{
xorjoep	3:4098b9d3d571	1953	if ((int32_t)(IRQn) >= 0)
xorjoep	3:4098b9d3d571	1954	{
xorjoep	3:4098b9d3d571	1955	return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
xorjoep	3:4098b9d3d571	1956	}
xorjoep	3:4098b9d3d571	1957	else
xorjoep	3:4098b9d3d571	1958	{
xorjoep	3:4098b9d3d571	1959	return(0U);
xorjoep	3:4098b9d3d571	1960	}
xorjoep	3:4098b9d3d571	1961	}
xorjoep	3:4098b9d3d571	1962
xorjoep	3:4098b9d3d571	1963
xorjoep	3:4098b9d3d571	1964	/**
xorjoep	3:4098b9d3d571	1965	\brief Set Pending Interrupt
xorjoep	3:4098b9d3d571	1966	\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
xorjoep	3:4098b9d3d571	1967	\param [in] IRQn Device specific interrupt number.
xorjoep	3:4098b9d3d571	1968	\note IRQn must not be negative.
xorjoep	3:4098b9d3d571	1969	*/
xorjoep	3:4098b9d3d571	1970	__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
xorjoep	3:4098b9d3d571	1971	{
xorjoep	3:4098b9d3d571	1972	if ((int32_t)(IRQn) >= 0)
xorjoep	3:4098b9d3d571	1973	{
xorjoep	3:4098b9d3d571	1974	NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
xorjoep	3:4098b9d3d571	1975	}
xorjoep	3:4098b9d3d571	1976	}
xorjoep	3:4098b9d3d571	1977
xorjoep	3:4098b9d3d571	1978
xorjoep	3:4098b9d3d571	1979	/**
xorjoep	3:4098b9d3d571	1980	\brief Clear Pending Interrupt
xorjoep	3:4098b9d3d571	1981	\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
xorjoep	3:4098b9d3d571	1982	\param [in] IRQn Device specific interrupt number.
xorjoep	3:4098b9d3d571	1983	\note IRQn must not be negative.
xorjoep	3:4098b9d3d571	1984	*/
xorjoep	3:4098b9d3d571	1985	__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
xorjoep	3:4098b9d3d571	1986	{
xorjoep	3:4098b9d3d571	1987	if ((int32_t)(IRQn) >= 0)
xorjoep	3:4098b9d3d571	1988	{
xorjoep	3:4098b9d3d571	1989	NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
xorjoep	3:4098b9d3d571	1990	}
xorjoep	3:4098b9d3d571	1991	}
xorjoep	3:4098b9d3d571	1992
xorjoep	3:4098b9d3d571	1993
xorjoep	3:4098b9d3d571	1994	/**
xorjoep	3:4098b9d3d571	1995	\brief Get Active Interrupt
xorjoep	3:4098b9d3d571	1996	\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
xorjoep	3:4098b9d3d571	1997	\param [in] IRQn Device specific interrupt number.
xorjoep	3:4098b9d3d571	1998	\return 0 Interrupt status is not active.
xorjoep	3:4098b9d3d571	1999	\return 1 Interrupt status is active.
xorjoep	3:4098b9d3d571	2000	\note IRQn must not be negative.
xorjoep	3:4098b9d3d571	2001	*/
xorjoep	3:4098b9d3d571	2002	__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
xorjoep	3:4098b9d3d571	2003	{
xorjoep	3:4098b9d3d571	2004	if ((int32_t)(IRQn) >= 0)
xorjoep	3:4098b9d3d571	2005	{
xorjoep	3:4098b9d3d571	2006	return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
xorjoep	3:4098b9d3d571	2007	}
xorjoep	3:4098b9d3d571	2008	else
xorjoep	3:4098b9d3d571	2009	{
xorjoep	3:4098b9d3d571	2010	return(0U);
xorjoep	3:4098b9d3d571	2011	}
xorjoep	3:4098b9d3d571	2012	}
xorjoep	3:4098b9d3d571	2013
xorjoep	3:4098b9d3d571	2014
xorjoep	3:4098b9d3d571	2015	/**
xorjoep	3:4098b9d3d571	2016	\brief Set Interrupt Priority
xorjoep	3:4098b9d3d571	2017	\details Sets the priority of a device specific interrupt or a processor exception.
xorjoep	3:4098b9d3d571	2018	The interrupt number can be positive to specify a device specific interrupt,
xorjoep	3:4098b9d3d571	2019	or negative to specify a processor exception.
xorjoep	3:4098b9d3d571	2020	\param [in] IRQn Interrupt number.
xorjoep	3:4098b9d3d571	2021	\param [in] priority Priority to set.
xorjoep	3:4098b9d3d571	2022	\note The priority cannot be set for every processor exception.
xorjoep	3:4098b9d3d571	2023	*/
xorjoep	3:4098b9d3d571	2024	__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
xorjoep	3:4098b9d3d571	2025	{
xorjoep	3:4098b9d3d571	2026	if ((int32_t)(IRQn) >= 0)
xorjoep	3:4098b9d3d571	2027	{
xorjoep	3:4098b9d3d571	2028	NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
xorjoep	3:4098b9d3d571	2029	}
xorjoep	3:4098b9d3d571	2030	else
xorjoep	3:4098b9d3d571	2031	{
xorjoep	3:4098b9d3d571	2032	SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
xorjoep	3:4098b9d3d571	2033	}
xorjoep	3:4098b9d3d571	2034	}
xorjoep	3:4098b9d3d571	2035
xorjoep	3:4098b9d3d571	2036
xorjoep	3:4098b9d3d571	2037	/**
xorjoep	3:4098b9d3d571	2038	\brief Get Interrupt Priority
xorjoep	3:4098b9d3d571	2039	\details Reads the priority of a device specific interrupt or a processor exception.
xorjoep	3:4098b9d3d571	2040	The interrupt number can be positive to specify a device specific interrupt,
xorjoep	3:4098b9d3d571	2041	or negative to specify a processor exception.
xorjoep	3:4098b9d3d571	2042	\param [in] IRQn Interrupt number.
xorjoep	3:4098b9d3d571	2043	\return Interrupt Priority.
xorjoep	3:4098b9d3d571	2044	Value is aligned automatically to the implemented priority bits of the microcontroller.
xorjoep	3:4098b9d3d571	2045	*/
xorjoep	3:4098b9d3d571	2046	__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
xorjoep	3:4098b9d3d571	2047	{
xorjoep	3:4098b9d3d571	2048
xorjoep	3:4098b9d3d571	2049	if ((int32_t)(IRQn) >= 0)
xorjoep	3:4098b9d3d571	2050	{
xorjoep	3:4098b9d3d571	2051	return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
xorjoep	3:4098b9d3d571	2052	}
xorjoep	3:4098b9d3d571	2053	else
xorjoep	3:4098b9d3d571	2054	{
xorjoep	3:4098b9d3d571	2055	return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
xorjoep	3:4098b9d3d571	2056	}
xorjoep	3:4098b9d3d571	2057	}
xorjoep	3:4098b9d3d571	2058
xorjoep	3:4098b9d3d571	2059
xorjoep	3:4098b9d3d571	2060	/**
xorjoep	3:4098b9d3d571	2061	\brief Encode Priority
xorjoep	3:4098b9d3d571	2062	\details Encodes the priority for an interrupt with the given priority group,
xorjoep	3:4098b9d3d571	2063	preemptive priority value, and subpriority value.
xorjoep	3:4098b9d3d571	2064	In case of a conflict between priority grouping and available
xorjoep	3:4098b9d3d571	2065	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
xorjoep	3:4098b9d3d571	2066	\param [in] PriorityGroup Used priority group.
xorjoep	3:4098b9d3d571	2067	\param [in] PreemptPriority Preemptive priority value (starting from 0).
xorjoep	3:4098b9d3d571	2068	\param [in] SubPriority Subpriority value (starting from 0).
xorjoep	3:4098b9d3d571	2069	\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
xorjoep	3:4098b9d3d571	2070	*/
xorjoep	3:4098b9d3d571	2071	__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
xorjoep	3:4098b9d3d571	2072	{
xorjoep	3:4098b9d3d571	2073	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
xorjoep	3:4098b9d3d571	2074	uint32_t PreemptPriorityBits;
xorjoep	3:4098b9d3d571	2075	uint32_t SubPriorityBits;
xorjoep	3:4098b9d3d571	2076
xorjoep	3:4098b9d3d571	2077	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
xorjoep	3:4098b9d3d571	2078	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
xorjoep	3:4098b9d3d571	2079
xorjoep	3:4098b9d3d571	2080	return (
xorjoep	3:4098b9d3d571	2081	((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) \|
xorjoep	3:4098b9d3d571	2082	((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
xorjoep	3:4098b9d3d571	2083	);
xorjoep	3:4098b9d3d571	2084	}
xorjoep	3:4098b9d3d571	2085
xorjoep	3:4098b9d3d571	2086
xorjoep	3:4098b9d3d571	2087	/**
xorjoep	3:4098b9d3d571	2088	\brief Decode Priority
xorjoep	3:4098b9d3d571	2089	\details Decodes an interrupt priority value with a given priority group to
xorjoep	3:4098b9d3d571	2090	preemptive priority value and subpriority value.
xorjoep	3:4098b9d3d571	2091	In case of a conflict between priority grouping and available
xorjoep	3:4098b9d3d571	2092	priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
xorjoep	3:4098b9d3d571	2093	\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
xorjoep	3:4098b9d3d571	2094	\param [in] PriorityGroup Used priority group.
xorjoep	3:4098b9d3d571	2095	\param [out] pPreemptPriority Preemptive priority value (starting from 0).
xorjoep	3:4098b9d3d571	2096	\param [out] pSubPriority Subpriority value (starting from 0).
xorjoep	3:4098b9d3d571	2097	*/
xorjoep	3:4098b9d3d571	2098	__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
xorjoep	3:4098b9d3d571	2099	{
xorjoep	3:4098b9d3d571	2100	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
xorjoep	3:4098b9d3d571	2101	uint32_t PreemptPriorityBits;
xorjoep	3:4098b9d3d571	2102	uint32_t SubPriorityBits;
xorjoep	3:4098b9d3d571	2103
xorjoep	3:4098b9d3d571	2104	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
xorjoep	3:4098b9d3d571	2105	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
xorjoep	3:4098b9d3d571	2106
xorjoep	3:4098b9d3d571	2107	*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
xorjoep	3:4098b9d3d571	2108	*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
xorjoep	3:4098b9d3d571	2109	}
xorjoep	3:4098b9d3d571	2110
xorjoep	3:4098b9d3d571	2111
xorjoep	3:4098b9d3d571	2112	/**
xorjoep	3:4098b9d3d571	2113	\brief Set Interrupt Vector
xorjoep	3:4098b9d3d571	2114	\details Sets an interrupt vector in SRAM based interrupt vector table.
xorjoep	3:4098b9d3d571	2115	The interrupt number can be positive to specify a device specific interrupt,
xorjoep	3:4098b9d3d571	2116	or negative to specify a processor exception.
xorjoep	3:4098b9d3d571	2117	VTOR must been relocated to SRAM before.
xorjoep	3:4098b9d3d571	2118	\param [in] IRQn Interrupt number
xorjoep	3:4098b9d3d571	2119	\param [in] vector Address of interrupt handler function
xorjoep	3:4098b9d3d571	2120	*/
xorjoep	3:4098b9d3d571	2121	__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
xorjoep	3:4098b9d3d571	2122	{
xorjoep	3:4098b9d3d571	2123	uint32_t vectors = (uint32_t )SCB->VTOR;
xorjoep	3:4098b9d3d571	2124	vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
xorjoep	3:4098b9d3d571	2125	}
xorjoep	3:4098b9d3d571	2126
xorjoep	3:4098b9d3d571	2127
xorjoep	3:4098b9d3d571	2128	/**
xorjoep	3:4098b9d3d571	2129	\brief Get Interrupt Vector
xorjoep	3:4098b9d3d571	2130	\details Reads an interrupt vector from interrupt vector table.
xorjoep	3:4098b9d3d571	2131	The interrupt number can be positive to specify a device specific interrupt,
xorjoep	3:4098b9d3d571	2132	or negative to specify a processor exception.
xorjoep	3:4098b9d3d571	2133	\param [in] IRQn Interrupt number.
xorjoep	3:4098b9d3d571	2134	\return Address of interrupt handler function
xorjoep	3:4098b9d3d571	2135	*/
xorjoep	3:4098b9d3d571	2136	__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
xorjoep	3:4098b9d3d571	2137	{
xorjoep	3:4098b9d3d571	2138	uint32_t vectors = (uint32_t )SCB->VTOR;
xorjoep	3:4098b9d3d571	2139	return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
xorjoep	3:4098b9d3d571	2140	}
xorjoep	3:4098b9d3d571	2141
xorjoep	3:4098b9d3d571	2142
xorjoep	3:4098b9d3d571	2143	/**
xorjoep	3:4098b9d3d571	2144	\brief System Reset
xorjoep	3:4098b9d3d571	2145	\details Initiates a system reset request to reset the MCU.
xorjoep	3:4098b9d3d571	2146	*/
xorjoep	3:4098b9d3d571	2147	__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
xorjoep	3:4098b9d3d571	2148	{
xorjoep	3:4098b9d3d571	2149	__DSB(); /* Ensure all outstanding memory accesses included
xorjoep	3:4098b9d3d571	2150	buffered write are completed before reset */
xorjoep	3:4098b9d3d571	2151	SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
xorjoep	3:4098b9d3d571	2152	(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) \|
xorjoep	3:4098b9d3d571	2153	SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
xorjoep	3:4098b9d3d571	2154	__DSB(); /* Ensure completion of memory access */
xorjoep	3:4098b9d3d571	2155
xorjoep	3:4098b9d3d571	2156	for(;;) /* wait until reset */
xorjoep	3:4098b9d3d571	2157	{
xorjoep	3:4098b9d3d571	2158	__NOP();
xorjoep	3:4098b9d3d571	2159	}
xorjoep	3:4098b9d3d571	2160	}
xorjoep	3:4098b9d3d571	2161
xorjoep	3:4098b9d3d571	2162	/@} end of CMSIS_Core_NVICFunctions /
xorjoep	3:4098b9d3d571	2163
xorjoep	3:4098b9d3d571	2164	/* ########################## MPU functions #################################### */
xorjoep	3:4098b9d3d571	2165
xorjoep	3:4098b9d3d571	2166	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
xorjoep	3:4098b9d3d571	2167
xorjoep	3:4098b9d3d571	2168	#include "mpu_armv7.h"
xorjoep	3:4098b9d3d571	2169
xorjoep	3:4098b9d3d571	2170	#endif
xorjoep	3:4098b9d3d571	2171
xorjoep	3:4098b9d3d571	2172	/* ########################## FPU functions #################################### */
xorjoep	3:4098b9d3d571	2173	/**
xorjoep	3:4098b9d3d571	2174	\ingroup CMSIS_Core_FunctionInterface
xorjoep	3:4098b9d3d571	2175	\defgroup CMSIS_Core_FpuFunctions FPU Functions
xorjoep	3:4098b9d3d571	2176	\brief Function that provides FPU type.
xorjoep	3:4098b9d3d571	2177	@{
xorjoep	3:4098b9d3d571	2178	*/
xorjoep	3:4098b9d3d571	2179
xorjoep	3:4098b9d3d571	2180	/**
xorjoep	3:4098b9d3d571	2181	\brief get FPU type
xorjoep	3:4098b9d3d571	2182	\details returns the FPU type
xorjoep	3:4098b9d3d571	2183	\returns
xorjoep	3:4098b9d3d571	2184	- \b 0: No FPU
xorjoep	3:4098b9d3d571	2185	- \b 1: Single precision FPU
xorjoep	3:4098b9d3d571	2186	- \b 2: Double + Single precision FPU
xorjoep	3:4098b9d3d571	2187	*/
xorjoep	3:4098b9d3d571	2188	__STATIC_INLINE uint32_t SCB_GetFPUType(void)
xorjoep	3:4098b9d3d571	2189	{
xorjoep	3:4098b9d3d571	2190	uint32_t mvfr0;
xorjoep	3:4098b9d3d571	2191
xorjoep	3:4098b9d3d571	2192	mvfr0 = SCB->MVFR0;
xorjoep	3:4098b9d3d571	2193	if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk \| FPU_MVFR0_Double_precision_Msk)) == 0x220U)
xorjoep	3:4098b9d3d571	2194	{
xorjoep	3:4098b9d3d571	2195	return 2U; /* Double + Single precision FPU */
xorjoep	3:4098b9d3d571	2196	}
xorjoep	3:4098b9d3d571	2197	else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk \| FPU_MVFR0_Double_precision_Msk)) == 0x020U)
xorjoep	3:4098b9d3d571	2198	{
xorjoep	3:4098b9d3d571	2199	return 1U; /* Single precision FPU */
xorjoep	3:4098b9d3d571	2200	}
xorjoep	3:4098b9d3d571	2201	else
xorjoep	3:4098b9d3d571	2202	{
xorjoep	3:4098b9d3d571	2203	return 0U; /* No FPU */
xorjoep	3:4098b9d3d571	2204	}
xorjoep	3:4098b9d3d571	2205	}
xorjoep	3:4098b9d3d571	2206
xorjoep	3:4098b9d3d571	2207
xorjoep	3:4098b9d3d571	2208	/@} end of CMSIS_Core_FpuFunctions /
xorjoep	3:4098b9d3d571	2209
xorjoep	3:4098b9d3d571	2210
xorjoep	3:4098b9d3d571	2211
xorjoep	3:4098b9d3d571	2212	/* ########################## Cache functions #################################### */
xorjoep	3:4098b9d3d571	2213	/**
xorjoep	3:4098b9d3d571	2214	\ingroup CMSIS_Core_FunctionInterface
xorjoep	3:4098b9d3d571	2215	\defgroup CMSIS_Core_CacheFunctions Cache Functions
xorjoep	3:4098b9d3d571	2216	\brief Functions that configure Instruction and Data cache.
xorjoep	3:4098b9d3d571	2217	@{
xorjoep	3:4098b9d3d571	2218	*/
xorjoep	3:4098b9d3d571	2219
xorjoep	3:4098b9d3d571	2220	/* Cache Size ID Register Macros */
xorjoep	3:4098b9d3d571	2221	#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
xorjoep	3:4098b9d3d571	2222	#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
xorjoep	3:4098b9d3d571	2223
xorjoep	3:4098b9d3d571	2224
xorjoep	3:4098b9d3d571	2225	/**
xorjoep	3:4098b9d3d571	2226	\brief Enable I-Cache
xorjoep	3:4098b9d3d571	2227	\details Turns on I-Cache
xorjoep	3:4098b9d3d571	2228	*/
xorjoep	3:4098b9d3d571	2229	__STATIC_INLINE void SCB_EnableICache (void)
xorjoep	3:4098b9d3d571	2230	{
xorjoep	3:4098b9d3d571	2231	#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
xorjoep	3:4098b9d3d571	2232	__DSB();
xorjoep	3:4098b9d3d571	2233	__ISB();
xorjoep	3:4098b9d3d571	2234	SCB->ICIALLU = 0UL; /* invalidate I-Cache */
xorjoep	3:4098b9d3d571	2235	__DSB();
xorjoep	3:4098b9d3d571	2236	__ISB();
xorjoep	3:4098b9d3d571	2237	SCB->CCR \|= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */
xorjoep	3:4098b9d3d571	2238	__DSB();
xorjoep	3:4098b9d3d571	2239	__ISB();
xorjoep	3:4098b9d3d571	2240	#endif
xorjoep	3:4098b9d3d571	2241	}
xorjoep	3:4098b9d3d571	2242
xorjoep	3:4098b9d3d571	2243
xorjoep	3:4098b9d3d571	2244	/**
xorjoep	3:4098b9d3d571	2245	\brief Disable I-Cache
xorjoep	3:4098b9d3d571	2246	\details Turns off I-Cache
xorjoep	3:4098b9d3d571	2247	*/
xorjoep	3:4098b9d3d571	2248	__STATIC_INLINE void SCB_DisableICache (void)
xorjoep	3:4098b9d3d571	2249	{
xorjoep	3:4098b9d3d571	2250	#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
xorjoep	3:4098b9d3d571	2251	__DSB();
xorjoep	3:4098b9d3d571	2252	__ISB();
xorjoep	3:4098b9d3d571	2253	SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */
xorjoep	3:4098b9d3d571	2254	SCB->ICIALLU = 0UL; /* invalidate I-Cache */
xorjoep	3:4098b9d3d571	2255	__DSB();
xorjoep	3:4098b9d3d571	2256	__ISB();
xorjoep	3:4098b9d3d571	2257	#endif
xorjoep	3:4098b9d3d571	2258	}
xorjoep	3:4098b9d3d571	2259
xorjoep	3:4098b9d3d571	2260
xorjoep	3:4098b9d3d571	2261	/**
xorjoep	3:4098b9d3d571	2262	\brief Invalidate I-Cache
xorjoep	3:4098b9d3d571	2263	\details Invalidates I-Cache
xorjoep	3:4098b9d3d571	2264	*/
xorjoep	3:4098b9d3d571	2265	__STATIC_INLINE void SCB_InvalidateICache (void)
xorjoep	3:4098b9d3d571	2266	{
xorjoep	3:4098b9d3d571	2267	#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
xorjoep	3:4098b9d3d571	2268	__DSB();
xorjoep	3:4098b9d3d571	2269	__ISB();
xorjoep	3:4098b9d3d571	2270	SCB->ICIALLU = 0UL;
xorjoep	3:4098b9d3d571	2271	__DSB();
xorjoep	3:4098b9d3d571	2272	__ISB();
xorjoep	3:4098b9d3d571	2273	#endif
xorjoep	3:4098b9d3d571	2274	}
xorjoep	3:4098b9d3d571	2275
xorjoep	3:4098b9d3d571	2276
xorjoep	3:4098b9d3d571	2277	/**
xorjoep	3:4098b9d3d571	2278	\brief Enable D-Cache
xorjoep	3:4098b9d3d571	2279	\details Turns on D-Cache
xorjoep	3:4098b9d3d571	2280	*/
xorjoep	3:4098b9d3d571	2281	__STATIC_INLINE void SCB_EnableDCache (void)
xorjoep	3:4098b9d3d571	2282	{
xorjoep	3:4098b9d3d571	2283	#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
xorjoep	3:4098b9d3d571	2284	uint32_t ccsidr;
xorjoep	3:4098b9d3d571	2285	uint32_t sets;
xorjoep	3:4098b9d3d571	2286	uint32_t ways;
xorjoep	3:4098b9d3d571	2287
xorjoep	3:4098b9d3d571	2288	SCB->CSSELR = 0U; /(0U << 1U) \| 0U;/ /* Level 1 data cache */
xorjoep	3:4098b9d3d571	2289	__DSB();
xorjoep	3:4098b9d3d571	2290
xorjoep	3:4098b9d3d571	2291	ccsidr = SCB->CCSIDR;
xorjoep	3:4098b9d3d571	2292
xorjoep	3:4098b9d3d571	2293	/* invalidate D-Cache */
xorjoep	3:4098b9d3d571	2294	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
xorjoep	3:4098b9d3d571	2295	do {
xorjoep	3:4098b9d3d571	2296	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
xorjoep	3:4098b9d3d571	2297	do {
xorjoep	3:4098b9d3d571	2298	SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) \|
xorjoep	3:4098b9d3d571	2299	((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
xorjoep	3:4098b9d3d571	2300	#if defined ( __CC_ARM )
xorjoep	3:4098b9d3d571	2301	__schedule_barrier();
xorjoep	3:4098b9d3d571	2302	#endif
xorjoep	3:4098b9d3d571	2303	} while (ways-- != 0U);
xorjoep	3:4098b9d3d571	2304	} while(sets-- != 0U);
xorjoep	3:4098b9d3d571	2305	__DSB();
xorjoep	3:4098b9d3d571	2306
xorjoep	3:4098b9d3d571	2307	SCB->CCR \|= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */
xorjoep	3:4098b9d3d571	2308
xorjoep	3:4098b9d3d571	2309	__DSB();
xorjoep	3:4098b9d3d571	2310	__ISB();
xorjoep	3:4098b9d3d571	2311	#endif
xorjoep	3:4098b9d3d571	2312	}
xorjoep	3:4098b9d3d571	2313
xorjoep	3:4098b9d3d571	2314
xorjoep	3:4098b9d3d571	2315	/**
xorjoep	3:4098b9d3d571	2316	\brief Disable D-Cache
xorjoep	3:4098b9d3d571	2317	\details Turns off D-Cache
xorjoep	3:4098b9d3d571	2318	*/
xorjoep	3:4098b9d3d571	2319	__STATIC_INLINE void SCB_DisableDCache (void)
xorjoep	3:4098b9d3d571	2320	{
xorjoep	3:4098b9d3d571	2321	#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
xorjoep	3:4098b9d3d571	2322	uint32_t ccsidr;
xorjoep	3:4098b9d3d571	2323	uint32_t sets;
xorjoep	3:4098b9d3d571	2324	uint32_t ways;
xorjoep	3:4098b9d3d571	2325
xorjoep	3:4098b9d3d571	2326	SCB->CSSELR = 0U; /(0U << 1U) \| 0U;/ /* Level 1 data cache */
xorjoep	3:4098b9d3d571	2327	__DSB();
xorjoep	3:4098b9d3d571	2328
xorjoep	3:4098b9d3d571	2329	SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */
xorjoep	3:4098b9d3d571	2330	__DSB();
xorjoep	3:4098b9d3d571	2331
xorjoep	3:4098b9d3d571	2332	ccsidr = SCB->CCSIDR;
xorjoep	3:4098b9d3d571	2333
xorjoep	3:4098b9d3d571	2334	/* clean & invalidate D-Cache */
xorjoep	3:4098b9d3d571	2335	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
xorjoep	3:4098b9d3d571	2336	do {
xorjoep	3:4098b9d3d571	2337	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
xorjoep	3:4098b9d3d571	2338	do {
xorjoep	3:4098b9d3d571	2339	SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) \|
xorjoep	3:4098b9d3d571	2340	((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
xorjoep	3:4098b9d3d571	2341	#if defined ( __CC_ARM )
xorjoep	3:4098b9d3d571	2342	__schedule_barrier();
xorjoep	3:4098b9d3d571	2343	#endif
xorjoep	3:4098b9d3d571	2344	} while (ways-- != 0U);
xorjoep	3:4098b9d3d571	2345	} while(sets-- != 0U);
xorjoep	3:4098b9d3d571	2346
xorjoep	3:4098b9d3d571	2347	__DSB();
xorjoep	3:4098b9d3d571	2348	__ISB();
xorjoep	3:4098b9d3d571	2349	#endif
xorjoep	3:4098b9d3d571	2350	}
xorjoep	3:4098b9d3d571	2351
xorjoep	3:4098b9d3d571	2352
xorjoep	3:4098b9d3d571	2353	/**
xorjoep	3:4098b9d3d571	2354	\brief Invalidate D-Cache
xorjoep	3:4098b9d3d571	2355	\details Invalidates D-Cache
xorjoep	3:4098b9d3d571	2356	*/
xorjoep	3:4098b9d3d571	2357	__STATIC_INLINE void SCB_InvalidateDCache (void)
xorjoep	3:4098b9d3d571	2358	{
xorjoep	3:4098b9d3d571	2359	#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
xorjoep	3:4098b9d3d571	2360	uint32_t ccsidr;
xorjoep	3:4098b9d3d571	2361	uint32_t sets;
xorjoep	3:4098b9d3d571	2362	uint32_t ways;
xorjoep	3:4098b9d3d571	2363
xorjoep	3:4098b9d3d571	2364	SCB->CSSELR = 0U; /(0U << 1U) \| 0U;/ /* Level 1 data cache */
xorjoep	3:4098b9d3d571	2365	__DSB();
xorjoep	3:4098b9d3d571	2366
xorjoep	3:4098b9d3d571	2367	ccsidr = SCB->CCSIDR;
xorjoep	3:4098b9d3d571	2368
xorjoep	3:4098b9d3d571	2369	/* invalidate D-Cache */
xorjoep	3:4098b9d3d571	2370	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
xorjoep	3:4098b9d3d571	2371	do {
xorjoep	3:4098b9d3d571	2372	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
xorjoep	3:4098b9d3d571	2373	do {
xorjoep	3:4098b9d3d571	2374	SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) \|
xorjoep	3:4098b9d3d571	2375	((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
xorjoep	3:4098b9d3d571	2376	#if defined ( __CC_ARM )
xorjoep	3:4098b9d3d571	2377	__schedule_barrier();
xorjoep	3:4098b9d3d571	2378	#endif
xorjoep	3:4098b9d3d571	2379	} while (ways-- != 0U);
xorjoep	3:4098b9d3d571	2380	} while(sets-- != 0U);
xorjoep	3:4098b9d3d571	2381
xorjoep	3:4098b9d3d571	2382	__DSB();
xorjoep	3:4098b9d3d571	2383	__ISB();
xorjoep	3:4098b9d3d571	2384	#endif
xorjoep	3:4098b9d3d571	2385	}
xorjoep	3:4098b9d3d571	2386
xorjoep	3:4098b9d3d571	2387
xorjoep	3:4098b9d3d571	2388	/**
xorjoep	3:4098b9d3d571	2389	\brief Clean D-Cache
xorjoep	3:4098b9d3d571	2390	\details Cleans D-Cache
xorjoep	3:4098b9d3d571	2391	*/
xorjoep	3:4098b9d3d571	2392	__STATIC_INLINE void SCB_CleanDCache (void)
xorjoep	3:4098b9d3d571	2393	{
xorjoep	3:4098b9d3d571	2394	#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
xorjoep	3:4098b9d3d571	2395	uint32_t ccsidr;
xorjoep	3:4098b9d3d571	2396	uint32_t sets;
xorjoep	3:4098b9d3d571	2397	uint32_t ways;
xorjoep	3:4098b9d3d571	2398
xorjoep	3:4098b9d3d571	2399	SCB->CSSELR = 0U; /(0U << 1U) \| 0U;/ /* Level 1 data cache */
xorjoep	3:4098b9d3d571	2400	__DSB();
xorjoep	3:4098b9d3d571	2401
xorjoep	3:4098b9d3d571	2402	ccsidr = SCB->CCSIDR;
xorjoep	3:4098b9d3d571	2403
xorjoep	3:4098b9d3d571	2404	/* clean D-Cache */
xorjoep	3:4098b9d3d571	2405	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
xorjoep	3:4098b9d3d571	2406	do {
xorjoep	3:4098b9d3d571	2407	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
xorjoep	3:4098b9d3d571	2408	do {
xorjoep	3:4098b9d3d571	2409	SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) \|
xorjoep	3:4098b9d3d571	2410	((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) );
xorjoep	3:4098b9d3d571	2411	#if defined ( __CC_ARM )
xorjoep	3:4098b9d3d571	2412	__schedule_barrier();
xorjoep	3:4098b9d3d571	2413	#endif
xorjoep	3:4098b9d3d571	2414	} while (ways-- != 0U);
xorjoep	3:4098b9d3d571	2415	} while(sets-- != 0U);
xorjoep	3:4098b9d3d571	2416
xorjoep	3:4098b9d3d571	2417	__DSB();
xorjoep	3:4098b9d3d571	2418	__ISB();
xorjoep	3:4098b9d3d571	2419	#endif
xorjoep	3:4098b9d3d571	2420	}
xorjoep	3:4098b9d3d571	2421
xorjoep	3:4098b9d3d571	2422
xorjoep	3:4098b9d3d571	2423	/**
xorjoep	3:4098b9d3d571	2424	\brief Clean & Invalidate D-Cache
xorjoep	3:4098b9d3d571	2425	\details Cleans and Invalidates D-Cache
xorjoep	3:4098b9d3d571	2426	*/
xorjoep	3:4098b9d3d571	2427	__STATIC_INLINE void SCB_CleanInvalidateDCache (void)
xorjoep	3:4098b9d3d571	2428	{
xorjoep	3:4098b9d3d571	2429	#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
xorjoep	3:4098b9d3d571	2430	uint32_t ccsidr;
xorjoep	3:4098b9d3d571	2431	uint32_t sets;
xorjoep	3:4098b9d3d571	2432	uint32_t ways;
xorjoep	3:4098b9d3d571	2433
xorjoep	3:4098b9d3d571	2434	SCB->CSSELR = 0U; /(0U << 1U) \| 0U;/ /* Level 1 data cache */
xorjoep	3:4098b9d3d571	2435	__DSB();
xorjoep	3:4098b9d3d571	2436
xorjoep	3:4098b9d3d571	2437	ccsidr = SCB->CCSIDR;
xorjoep	3:4098b9d3d571	2438
xorjoep	3:4098b9d3d571	2439	/* clean & invalidate D-Cache */
xorjoep	3:4098b9d3d571	2440	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
xorjoep	3:4098b9d3d571	2441	do {
xorjoep	3:4098b9d3d571	2442	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
xorjoep	3:4098b9d3d571	2443	do {
xorjoep	3:4098b9d3d571	2444	SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) \|
xorjoep	3:4098b9d3d571	2445	((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
xorjoep	3:4098b9d3d571	2446	#if defined ( __CC_ARM )
xorjoep	3:4098b9d3d571	2447	__schedule_barrier();
xorjoep	3:4098b9d3d571	2448	#endif
xorjoep	3:4098b9d3d571	2449	} while (ways-- != 0U);
xorjoep	3:4098b9d3d571	2450	} while(sets-- != 0U);
xorjoep	3:4098b9d3d571	2451
xorjoep	3:4098b9d3d571	2452	__DSB();
xorjoep	3:4098b9d3d571	2453	__ISB();
xorjoep	3:4098b9d3d571	2454	#endif
xorjoep	3:4098b9d3d571	2455	}
xorjoep	3:4098b9d3d571	2456
xorjoep	3:4098b9d3d571	2457
xorjoep	3:4098b9d3d571	2458	/**
xorjoep	3:4098b9d3d571	2459	\brief D-Cache Invalidate by address
xorjoep	3:4098b9d3d571	2460	\details Invalidates D-Cache for the given address
xorjoep	3:4098b9d3d571	2461	\param[in] addr address (aligned to 32-byte boundary)
xorjoep	3:4098b9d3d571	2462	\param[in] dsize size of memory block (in number of bytes)
xorjoep	3:4098b9d3d571	2463	*/
xorjoep	3:4098b9d3d571	2464	__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
xorjoep	3:4098b9d3d571	2465	{
xorjoep	3:4098b9d3d571	2466	#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
xorjoep	3:4098b9d3d571	2467	int32_t op_size = dsize;
xorjoep	3:4098b9d3d571	2468	uint32_t op_addr = (uint32_t)addr;
xorjoep	3:4098b9d3d571	2469	int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
xorjoep	3:4098b9d3d571	2470
xorjoep	3:4098b9d3d571	2471	__DSB();
xorjoep	3:4098b9d3d571	2472
xorjoep	3:4098b9d3d571	2473	while (op_size > 0) {
xorjoep	3:4098b9d3d571	2474	SCB->DCIMVAC = op_addr;
xorjoep	3:4098b9d3d571	2475	op_addr += (uint32_t)linesize;
xorjoep	3:4098b9d3d571	2476	op_size -= linesize;
xorjoep	3:4098b9d3d571	2477	}
xorjoep	3:4098b9d3d571	2478
xorjoep	3:4098b9d3d571	2479	__DSB();
xorjoep	3:4098b9d3d571	2480	__ISB();
xorjoep	3:4098b9d3d571	2481	#endif
xorjoep	3:4098b9d3d571	2482	}
xorjoep	3:4098b9d3d571	2483
xorjoep	3:4098b9d3d571	2484
xorjoep	3:4098b9d3d571	2485	/**
xorjoep	3:4098b9d3d571	2486	\brief D-Cache Clean by address
xorjoep	3:4098b9d3d571	2487	\details Cleans D-Cache for the given address
xorjoep	3:4098b9d3d571	2488	\param[in] addr address (aligned to 32-byte boundary)
xorjoep	3:4098b9d3d571	2489	\param[in] dsize size of memory block (in number of bytes)
xorjoep	3:4098b9d3d571	2490	*/
xorjoep	3:4098b9d3d571	2491	__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
xorjoep	3:4098b9d3d571	2492	{
xorjoep	3:4098b9d3d571	2493	#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
xorjoep	3:4098b9d3d571	2494	int32_t op_size = dsize;
xorjoep	3:4098b9d3d571	2495	uint32_t op_addr = (uint32_t) addr;
xorjoep	3:4098b9d3d571	2496	int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
xorjoep	3:4098b9d3d571	2497
xorjoep	3:4098b9d3d571	2498	__DSB();
xorjoep	3:4098b9d3d571	2499
xorjoep	3:4098b9d3d571	2500	while (op_size > 0) {
xorjoep	3:4098b9d3d571	2501	SCB->DCCMVAC = op_addr;
xorjoep	3:4098b9d3d571	2502	op_addr += (uint32_t)linesize;
xorjoep	3:4098b9d3d571	2503	op_size -= linesize;
xorjoep	3:4098b9d3d571	2504	}
xorjoep	3:4098b9d3d571	2505
xorjoep	3:4098b9d3d571	2506	__DSB();
xorjoep	3:4098b9d3d571	2507	__ISB();
xorjoep	3:4098b9d3d571	2508	#endif
xorjoep	3:4098b9d3d571	2509	}
xorjoep	3:4098b9d3d571	2510
xorjoep	3:4098b9d3d571	2511
xorjoep	3:4098b9d3d571	2512	/**
xorjoep	3:4098b9d3d571	2513	\brief D-Cache Clean and Invalidate by address
xorjoep	3:4098b9d3d571	2514	\details Cleans and invalidates D_Cache for the given address
xorjoep	3:4098b9d3d571	2515	\param[in] addr address (aligned to 32-byte boundary)
xorjoep	3:4098b9d3d571	2516	\param[in] dsize size of memory block (in number of bytes)
xorjoep	3:4098b9d3d571	2517	*/
xorjoep	3:4098b9d3d571	2518	__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
xorjoep	3:4098b9d3d571	2519	{
xorjoep	3:4098b9d3d571	2520	#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
xorjoep	3:4098b9d3d571	2521	int32_t op_size = dsize;
xorjoep	3:4098b9d3d571	2522	uint32_t op_addr = (uint32_t) addr;
xorjoep	3:4098b9d3d571	2523	int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
xorjoep	3:4098b9d3d571	2524
xorjoep	3:4098b9d3d571	2525	__DSB();
xorjoep	3:4098b9d3d571	2526
xorjoep	3:4098b9d3d571	2527	while (op_size > 0) {
xorjoep	3:4098b9d3d571	2528	SCB->DCCIMVAC = op_addr;
xorjoep	3:4098b9d3d571	2529	op_addr += (uint32_t)linesize;
xorjoep	3:4098b9d3d571	2530	op_size -= linesize;
xorjoep	3:4098b9d3d571	2531	}
xorjoep	3:4098b9d3d571	2532
xorjoep	3:4098b9d3d571	2533	__DSB();
xorjoep	3:4098b9d3d571	2534	__ISB();
xorjoep	3:4098b9d3d571	2535	#endif
xorjoep	3:4098b9d3d571	2536	}
xorjoep	3:4098b9d3d571	2537
xorjoep	3:4098b9d3d571	2538
xorjoep	3:4098b9d3d571	2539	/@} end of CMSIS_Core_CacheFunctions /
xorjoep	3:4098b9d3d571	2540
xorjoep	3:4098b9d3d571	2541
xorjoep	3:4098b9d3d571	2542
xorjoep	3:4098b9d3d571	2543	/* ################################## SysTick function ############################################ */
xorjoep	3:4098b9d3d571	2544	/**
xorjoep	3:4098b9d3d571	2545	\ingroup CMSIS_Core_FunctionInterface
xorjoep	3:4098b9d3d571	2546	\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
xorjoep	3:4098b9d3d571	2547	\brief Functions that configure the System.
xorjoep	3:4098b9d3d571	2548	@{
xorjoep	3:4098b9d3d571	2549	*/
xorjoep	3:4098b9d3d571	2550
xorjoep	3:4098b9d3d571	2551	#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
xorjoep	3:4098b9d3d571	2552
xorjoep	3:4098b9d3d571	2553	/**
xorjoep	3:4098b9d3d571	2554	\brief System Tick Configuration
xorjoep	3:4098b9d3d571	2555	\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
xorjoep	3:4098b9d3d571	2556	Counter is in free running mode to generate periodic interrupts.
xorjoep	3:4098b9d3d571	2557	\param [in] ticks Number of ticks between two interrupts.
xorjoep	3:4098b9d3d571	2558	\return 0 Function succeeded.
xorjoep	3:4098b9d3d571	2559	\return 1 Function failed.
xorjoep	3:4098b9d3d571	2560	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
xorjoep	3:4098b9d3d571	2561	function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
xorjoep	3:4098b9d3d571	2562	must contain a vendor-specific implementation of this function.
xorjoep	3:4098b9d3d571	2563	*/
xorjoep	3:4098b9d3d571	2564	__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
xorjoep	3:4098b9d3d571	2565	{
xorjoep	3:4098b9d3d571	2566	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
xorjoep	3:4098b9d3d571	2567	{
xorjoep	3:4098b9d3d571	2568	return (1UL); /* Reload value impossible */
xorjoep	3:4098b9d3d571	2569	}
xorjoep	3:4098b9d3d571	2570
xorjoep	3:4098b9d3d571	2571	SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
xorjoep	3:4098b9d3d571	2572	NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
xorjoep	3:4098b9d3d571	2573	SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
xorjoep	3:4098b9d3d571	2574	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
xorjoep	3:4098b9d3d571	2575	SysTick_CTRL_TICKINT_Msk \|
xorjoep	3:4098b9d3d571	2576	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
xorjoep	3:4098b9d3d571	2577	return (0UL); /* Function successful */
xorjoep	3:4098b9d3d571	2578	}
xorjoep	3:4098b9d3d571	2579
xorjoep	3:4098b9d3d571	2580	#endif
xorjoep	3:4098b9d3d571	2581
xorjoep	3:4098b9d3d571	2582	/@} end of CMSIS_Core_SysTickFunctions /
xorjoep	3:4098b9d3d571	2583
xorjoep	3:4098b9d3d571	2584
xorjoep	3:4098b9d3d571	2585
xorjoep	3:4098b9d3d571	2586	/* ##################################### Debug In/Output function ########################################### */
xorjoep	3:4098b9d3d571	2587	/**
xorjoep	3:4098b9d3d571	2588	\ingroup CMSIS_Core_FunctionInterface
xorjoep	3:4098b9d3d571	2589	\defgroup CMSIS_core_DebugFunctions ITM Functions
xorjoep	3:4098b9d3d571	2590	\brief Functions that access the ITM debug interface.
xorjoep	3:4098b9d3d571	2591	@{
xorjoep	3:4098b9d3d571	2592	*/
xorjoep	3:4098b9d3d571	2593
xorjoep	3:4098b9d3d571	2594	extern volatile int32_t ITM_RxBuffer; /!< External variable to receive characters. /
xorjoep	3:4098b9d3d571	2595	#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /!< Value identifying \ref ITM_RxBuffer is ready for next character. /
xorjoep	3:4098b9d3d571	2596
xorjoep	3:4098b9d3d571	2597
xorjoep	3:4098b9d3d571	2598	/**
xorjoep	3:4098b9d3d571	2599	\brief ITM Send Character
xorjoep	3:4098b9d3d571	2600	\details Transmits a character via the ITM channel 0, and
xorjoep	3:4098b9d3d571	2601	\li Just returns when no debugger is connected that has booked the output.
xorjoep	3:4098b9d3d571	2602	\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
xorjoep	3:4098b9d3d571	2603	\param [in] ch Character to transmit.
xorjoep	3:4098b9d3d571	2604	\returns Character to transmit.
xorjoep	3:4098b9d3d571	2605	*/
xorjoep	3:4098b9d3d571	2606	__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
xorjoep	3:4098b9d3d571	2607	{
xorjoep	3:4098b9d3d571	2608	if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
xorjoep	3:4098b9d3d571	2609	((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
xorjoep	3:4098b9d3d571	2610	{
xorjoep	3:4098b9d3d571	2611	while (ITM->PORT[0U].u32 == 0UL)
xorjoep	3:4098b9d3d571	2612	{
xorjoep	3:4098b9d3d571	2613	__NOP();
xorjoep	3:4098b9d3d571	2614	}
xorjoep	3:4098b9d3d571	2615	ITM->PORT[0U].u8 = (uint8_t)ch;
xorjoep	3:4098b9d3d571	2616	}
xorjoep	3:4098b9d3d571	2617	return (ch);
xorjoep	3:4098b9d3d571	2618	}
xorjoep	3:4098b9d3d571	2619
xorjoep	3:4098b9d3d571	2620
xorjoep	3:4098b9d3d571	2621	/**
xorjoep	3:4098b9d3d571	2622	\brief ITM Receive Character
xorjoep	3:4098b9d3d571	2623	\details Inputs a character via the external variable \ref ITM_RxBuffer.
xorjoep	3:4098b9d3d571	2624	\return Received character.
xorjoep	3:4098b9d3d571	2625	\return -1 No character pending.
xorjoep	3:4098b9d3d571	2626	*/
xorjoep	3:4098b9d3d571	2627	__STATIC_INLINE int32_t ITM_ReceiveChar (void)
xorjoep	3:4098b9d3d571	2628	{
xorjoep	3:4098b9d3d571	2629	int32_t ch = -1; /* no character available */
xorjoep	3:4098b9d3d571	2630
xorjoep	3:4098b9d3d571	2631	if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
xorjoep	3:4098b9d3d571	2632	{
xorjoep	3:4098b9d3d571	2633	ch = ITM_RxBuffer;
xorjoep	3:4098b9d3d571	2634	ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
xorjoep	3:4098b9d3d571	2635	}
xorjoep	3:4098b9d3d571	2636
xorjoep	3:4098b9d3d571	2637	return (ch);
xorjoep	3:4098b9d3d571	2638	}
xorjoep	3:4098b9d3d571	2639
xorjoep	3:4098b9d3d571	2640
xorjoep	3:4098b9d3d571	2641	/**
xorjoep	3:4098b9d3d571	2642	\brief ITM Check Character
xorjoep	3:4098b9d3d571	2643	\details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
xorjoep	3:4098b9d3d571	2644	\return 0 No character available.
xorjoep	3:4098b9d3d571	2645	\return 1 Character available.
xorjoep	3:4098b9d3d571	2646	*/
xorjoep	3:4098b9d3d571	2647	__STATIC_INLINE int32_t ITM_CheckChar (void)
xorjoep	3:4098b9d3d571	2648	{
xorjoep	3:4098b9d3d571	2649
xorjoep	3:4098b9d3d571	2650	if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
xorjoep	3:4098b9d3d571	2651	{
xorjoep	3:4098b9d3d571	2652	return (0); /* no character available */
xorjoep	3:4098b9d3d571	2653	}
xorjoep	3:4098b9d3d571	2654	else
xorjoep	3:4098b9d3d571	2655	{
xorjoep	3:4098b9d3d571	2656	return (1); /* character available */
xorjoep	3:4098b9d3d571	2657	}
xorjoep	3:4098b9d3d571	2658	}
xorjoep	3:4098b9d3d571	2659
xorjoep	3:4098b9d3d571	2660	/@} end of CMSIS_core_DebugFunctions /
xorjoep	3:4098b9d3d571	2661
xorjoep	3:4098b9d3d571	2662
xorjoep	3:4098b9d3d571	2663
xorjoep	3:4098b9d3d571	2664
xorjoep	3:4098b9d3d571	2665	#ifdef __cplusplus
xorjoep	3:4098b9d3d571	2666	}
xorjoep	3:4098b9d3d571	2667	#endif
xorjoep	3:4098b9d3d571	2668
xorjoep	3:4098b9d3d571	2669	#endif /* __CORE_CM7_H_DEPENDANT */
xorjoep	3:4098b9d3d571	2670
xorjoep	3:4098b9d3d571	2671	#endif /* __CMSIS_GENERIC */

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Type:	Library
Created:	20 Jun 2018
Imports:	227
Forks:	0
Commits:	4
Dependents:	10
Dependencies:	0
Followers:	6

headers/core_cm7.h@3:4098b9d3d571, 2018-06-21 (annotated)

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