w mx / Mbed 2 deprecated finalcar

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Dependencies:   mbed

DebugConfig/finalcar_STM32F103RB_1.0.0.dbgconf@2:4a9ba34cd90a, 2018-08-04 (annotated)

Committer:
xmwmx
Date:
Sat Aug 04 04:17:02 2018 +0000
Revision:
2:4a9ba34cd90a
Parent:
0:5d8b03e224fd 
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Who changed what in which revision?

UserRevisionLine numberNew contents of line
xmwmx 0:5d8b03e224fd 1 // <<< Use Configuration Wizard in Context Menu >>>
xmwmx 0:5d8b03e224fd 2 // <h> Debug MCU Configuration
xmwmx 0:5d8b03e224fd 3 // <o0.0> DBG_SLEEP
xmwmx 0:5d8b03e224fd 4 // <i> Debug Sleep Mode
xmwmx 0:5d8b03e224fd 5 // <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
xmwmx 0:5d8b03e224fd 6 // <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
xmwmx 0:5d8b03e224fd 7 // <o0.1> DBG_STOP
xmwmx 0:5d8b03e224fd 8 // <i> Debug Stop Mode
xmwmx 0:5d8b03e224fd 9 // <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
xmwmx 0:5d8b03e224fd 10 // <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
xmwmx 0:5d8b03e224fd 11 // <o0.2> DBG_STANDBY
xmwmx 0:5d8b03e224fd 12 // <i> Debug Standby Mode
xmwmx 0:5d8b03e224fd 13 // <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
xmwmx 0:5d8b03e224fd 14 // <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
xmwmx 0:5d8b03e224fd 15 // <o0.8> DBG_IWDG_STOP
xmwmx 0:5d8b03e224fd 16 // <i> Debug independent watchdog stopped when core is halted
xmwmx 0:5d8b03e224fd 17 // <i> 0: The watchdog counter clock continues even if the core is halted
xmwmx 0:5d8b03e224fd 18 // <i> 1: The watchdog counter clock is stopped when the core is halted
xmwmx 0:5d8b03e224fd 19 // <o0.9> DBG_WWDG_STOP
xmwmx 0:5d8b03e224fd 20 // <i> Debug window watchdog stopped when core is halted
xmwmx 0:5d8b03e224fd 21 // <i> 0: The window watchdog counter clock continues even if the core is halted
xmwmx 0:5d8b03e224fd 22 // <i> 1: The window watchdog counter clock is stopped when the core is halted
xmwmx 0:5d8b03e224fd 23 // <o0.10> DBG_TIM1_STOP
xmwmx 0:5d8b03e224fd 24 // <i> Timer 1 counter stopped when core is halted
xmwmx 0:5d8b03e224fd 25 // <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
xmwmx 0:5d8b03e224fd 26 // <i> 1: The clock of the involved Timer counter is stopped when the core is halted
xmwmx 0:5d8b03e224fd 27 // <o0.11> DBG_TIM2_STOP
xmwmx 0:5d8b03e224fd 28 // <i> Timer 2 counter stopped when core is halted
xmwmx 0:5d8b03e224fd 29 // <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
xmwmx 0:5d8b03e224fd 30 // <i> 1: The clock of the involved Timer counter is stopped when the core is halted
xmwmx 0:5d8b03e224fd 31 // <o0.12> DBG_TIM3_STOP
xmwmx 0:5d8b03e224fd 32 // <i> Timer 3 counter stopped when core is halted
xmwmx 0:5d8b03e224fd 33 // <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
xmwmx 0:5d8b03e224fd 34 // <i> 1: The clock of the involved Timer counter is stopped when the core is halted
xmwmx 0:5d8b03e224fd 35 // <o0.13> DBG_TIM4_STOP
xmwmx 0:5d8b03e224fd 36 // <i> Timer 4 counter stopped when core is halted
xmwmx 0:5d8b03e224fd 37 // <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
xmwmx 0:5d8b03e224fd 38 // <i> 1: The clock of the involved Timer counter is stopped when the core is halted
xmwmx 0:5d8b03e224fd 39 // <o0.14> DBG_CAN1_STOP
xmwmx 0:5d8b03e224fd 40 // <i> Debug CAN1 stopped when Core is halted
xmwmx 0:5d8b03e224fd 41 // <i> 0: Same behavior as in normal mode
xmwmx 0:5d8b03e224fd 42 // <i> 1: CAN1 receive registers are frozen
xmwmx 0:5d8b03e224fd 43 // <o0.15> DBG_I2C1_SMBUS_TIMEOUT
xmwmx 0:5d8b03e224fd 44 // <i> I2C1 SMBUS timeout mode stopped when Core is halted
xmwmx 0:5d8b03e224fd 45 // <i> 0: Same behavior as in normal mode
xmwmx 0:5d8b03e224fd 46 // <i> 1: The SMBUS timeout is frozen
xmwmx 0:5d8b03e224fd 47 // <o0.16> DBG_I2C2_SMBUS_TIMEOUT
xmwmx 0:5d8b03e224fd 48 // <i> I2C2 SMBUS timeout mode stopped when Core is halted
xmwmx 0:5d8b03e224fd 49 // <i> 0: Same behavior as in normal mode
xmwmx 0:5d8b03e224fd 50 // <i> 1: The SMBUS timeout is frozen
xmwmx 0:5d8b03e224fd 51 // <o0.17> DBG_TIM8_STOP
xmwmx 0:5d8b03e224fd 52 // <i> Timer 8 counter stopped when core is halted
xmwmx 0:5d8b03e224fd 53 // <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
xmwmx 0:5d8b03e224fd 54 // <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
xmwmx 0:5d8b03e224fd 55 // <o0.18> DBG_TIM5_STOP
xmwmx 0:5d8b03e224fd 56 // <i> Timer 5 counter stopped when core is halted
xmwmx 0:5d8b03e224fd 57 // <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
xmwmx 0:5d8b03e224fd 58 // <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
xmwmx 0:5d8b03e224fd 59 // <o0.19> DBG_TIM6_STOP
xmwmx 0:5d8b03e224fd 60 // <i> Timer 6 counter stopped when core is halted
xmwmx 0:5d8b03e224fd 61 // <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
xmwmx 0:5d8b03e224fd 62 // <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
xmwmx 0:5d8b03e224fd 63 // <o0.20> DBG_TIM7_STOP
xmwmx 0:5d8b03e224fd 64 // <i> Timer 7 counter stopped when core is halted
xmwmx 0:5d8b03e224fd 65 // <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
xmwmx 0:5d8b03e224fd 66 // <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
xmwmx 0:5d8b03e224fd 67 // <o0.21> DBG_CAN2_STOP
xmwmx 0:5d8b03e224fd 68 // <i> Debug CAN2 stopped when Core is halted
xmwmx 0:5d8b03e224fd 69 // <i> 0: Same behavior as in normal mode
xmwmx 0:5d8b03e224fd 70 // <i> 1: CAN2 receive registers are frozen
xmwmx 0:5d8b03e224fd 71 // <o0.25> DBG_TIM12_STOP
xmwmx 0:5d8b03e224fd 72 // <i> Timer 12 counter stopped when core is halted
xmwmx 0:5d8b03e224fd 73 // <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
xmwmx 0:5d8b03e224fd 74 // <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
xmwmx 0:5d8b03e224fd 75 // <o0.26> DBG_TIM13_STOP
xmwmx 0:5d8b03e224fd 76 // <i> Timer 13 counter stopped when core is halted
xmwmx 0:5d8b03e224fd 77 // <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
xmwmx 0:5d8b03e224fd 78 // <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
xmwmx 0:5d8b03e224fd 79 // <o0.27> DBG_TIM14_STOP
xmwmx 0:5d8b03e224fd 80 // <i> Timer 14 counter stopped when core is halted
xmwmx 0:5d8b03e224fd 81 // <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
xmwmx 0:5d8b03e224fd 82 // <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
xmwmx 0:5d8b03e224fd 83 // <o0.28> DBG_TIM9_STOP
xmwmx 0:5d8b03e224fd 84 // <i> Timer 9 counter stopped when core is halted
xmwmx 0:5d8b03e224fd 85 // <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
xmwmx 0:5d8b03e224fd 86 // <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
xmwmx 0:5d8b03e224fd 87 // <o0.29> DBG_TIM10_STOP
xmwmx 0:5d8b03e224fd 88 // <i> Timer 10 counter stopped when core is halted
xmwmx 0:5d8b03e224fd 89 // <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
xmwmx 0:5d8b03e224fd 90 // <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
xmwmx 0:5d8b03e224fd 91 // <o0.30> DBG_TIM11_STOP
xmwmx 0:5d8b03e224fd 92 // <i> Timer 11 counter stopped when core is halted
xmwmx 0:5d8b03e224fd 93 // <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
xmwmx 0:5d8b03e224fd 94 // <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
xmwmx 0:5d8b03e224fd 95 // </h>
xmwmx 0:5d8b03e224fd 96 DbgMCU_CR = 0x00000007;
xmwmx 0:5d8b03e224fd 97 // <<< end of configuration section >>>