Raphael Kwon / W5500

W5500 Driver

Dependents:   Ethernet Ethernet

w5500.h@0:4f25c0dc00f7, 2014-02-18 (annotated)

Committer:
xeon011
Date:
Tue Feb 18 05:25:12 2014 +0000
Revision:
0:4f25c0dc00f7
First release;   - WIZnet Library for W5500

Who changed what in which revision?

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xeon011 0:4f25c0dc00f7 1 //*****************************************************************************
xeon011 0:4f25c0dc00f7 2 //
xeon011 0:4f25c0dc00f7 3 //! \file w5500.h
xeon011 0:4f25c0dc00f7 4 //! \brief W5500 HAL Header File.
xeon011 0:4f25c0dc00f7 5 //! \version 1.0.0
xeon011 0:4f25c0dc00f7 6 //! \date 2013/10/01
xeon011 0:4f25c0dc00f7 7 //! \par Revision history
xeon011 0:4f25c0dc00f7 8 //! <2013/10/01> 1st Release
xeon011 0:4f25c0dc00f7 9 //! \author MidnightCow
xeon011 0:4f25c0dc00f7 10 //! \copyright
xeon011 0:4f25c0dc00f7 11 //!
xeon011 0:4f25c0dc00f7 12 //! Copyright (c) 2013, WIZnet Co., LTD.
xeon011 0:4f25c0dc00f7 13 //! All rights reserved.
xeon011 0:4f25c0dc00f7 14 //!
xeon011 0:4f25c0dc00f7 15 //! Redistribution and use in source and binary forms, with or without
xeon011 0:4f25c0dc00f7 16 //! modification, are permitted provided that the following conditions
xeon011 0:4f25c0dc00f7 17 //! are met:
xeon011 0:4f25c0dc00f7 18 //!
xeon011 0:4f25c0dc00f7 19 //! * Redistributions of source code must retain the above copyright
xeon011 0:4f25c0dc00f7 20 //! notice, this list of conditions and the following disclaimer.
xeon011 0:4f25c0dc00f7 21 //! * Redistributions in binary form must reproduce the above copyright
xeon011 0:4f25c0dc00f7 22 //! notice, this list of conditions and the following disclaimer in the
xeon011 0:4f25c0dc00f7 23 //! documentation and/or other materials provided with the distribution.
xeon011 0:4f25c0dc00f7 24 //! * Neither the name of the <ORGANIZATION> nor the names of its
xeon011 0:4f25c0dc00f7 25 //! contributors may be used to endorse or promote products derived
xeon011 0:4f25c0dc00f7 26 //! from this software without specific prior written permission.
xeon011 0:4f25c0dc00f7 27 //!
xeon011 0:4f25c0dc00f7 28 //! THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
xeon011 0:4f25c0dc00f7 29 //! AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
xeon011 0:4f25c0dc00f7 30 //! IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
xeon011 0:4f25c0dc00f7 31 //! ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
xeon011 0:4f25c0dc00f7 32 //! LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
xeon011 0:4f25c0dc00f7 33 //! CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
xeon011 0:4f25c0dc00f7 34 //! SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
xeon011 0:4f25c0dc00f7 35 //! INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
xeon011 0:4f25c0dc00f7 36 //! CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
xeon011 0:4f25c0dc00f7 37 //! ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
xeon011 0:4f25c0dc00f7 38 //! THE POSSIBILITY OF SUCH DAMAGE.
xeon011 0:4f25c0dc00f7 39 //
xeon011 0:4f25c0dc00f7 40 //*****************************************************************************
xeon011 0:4f25c0dc00f7 41
xeon011 0:4f25c0dc00f7 42 #ifndef _W5500_H_
xeon011 0:4f25c0dc00f7 43 #define _W5500_H_
xeon011 0:4f25c0dc00f7 44
xeon011 0:4f25c0dc00f7 45 #include <stdint.h>
xeon011 0:4f25c0dc00f7 46 #include "Ethernet/wizchip_conf.h"
xeon011 0:4f25c0dc00f7 47
xeon011 0:4f25c0dc00f7 48 #define _W5500_IO_BASE_ 0x00000000
xeon011 0:4f25c0dc00f7 49
xeon011 0:4f25c0dc00f7 50 #define _W5500_SPI_READ_ (0x00 << 2) //< SPI interface Read operation in Control Phase
xeon011 0:4f25c0dc00f7 51 #define _W5500_SPI_WRITE_ (0x01 << 2) //< SPI interface Write operation in Control Phase
xeon011 0:4f25c0dc00f7 52
xeon011 0:4f25c0dc00f7 53 #define WIZCHIP_CREG_BLOCK 0x00 //< Common register block
xeon011 0:4f25c0dc00f7 54 #define WIZCHIP_SREG_BLOCK(N) (1+4*N) //< Socket N register block
xeon011 0:4f25c0dc00f7 55 #define WIZCHIP_TXBUF_BLOCK(N) (2+4*N) //< Socket N Tx buffer address block
xeon011 0:4f25c0dc00f7 56 #define WIZCHIP_RXBUF_BLOCK(N) (3+4*N) //< Socket N Rx buffer address block
xeon011 0:4f25c0dc00f7 57
xeon011 0:4f25c0dc00f7 58 #define WIZCHIP_OFFSET_INC(ADDR, N) (ADDR + (N<<8)) //< Increase offset address
xeon011 0:4f25c0dc00f7 59
xeon011 0:4f25c0dc00f7 60
xeon011 0:4f25c0dc00f7 61
xeon011 0:4f25c0dc00f7 62 //////////////////////////////
xeon011 0:4f25c0dc00f7 63 //-------------------------- defgroup ---------------------------------
xeon011 0:4f25c0dc00f7 64 /**
xeon011 0:4f25c0dc00f7 65 * @defgroup W5500 W5500
xeon011 0:4f25c0dc00f7 66 *
xeon011 0:4f25c0dc00f7 67 * @brief WHIZCHIP register defines and I/O functions of @b W5500.
xeon011 0:4f25c0dc00f7 68 *
xeon011 0:4f25c0dc00f7 69 * - @ref WIZCHIP_register : @ref Common_register_group and @ref Socket_register_group
xeon011 0:4f25c0dc00f7 70 * - @ref WIZCHIP_IO_Functions : @ref Basic_IO_function, @ref Common_register_access_function and @ref Socket_register_access_function
xeon011 0:4f25c0dc00f7 71 */
xeon011 0:4f25c0dc00f7 72
xeon011 0:4f25c0dc00f7 73
xeon011 0:4f25c0dc00f7 74 /**
xeon011 0:4f25c0dc00f7 75 * @defgroup WIZCHIP_register WIZCHIP register
xeon011 0:4f25c0dc00f7 76 * @ingroup W5500
xeon011 0:4f25c0dc00f7 77 *
xeon011 0:4f25c0dc00f7 78 * @brief WHIZCHIP register defines register group of @b W5500.
xeon011 0:4f25c0dc00f7 79 *
xeon011 0:4f25c0dc00f7 80 * - @ref Common_register_group : Common register group
xeon011 0:4f25c0dc00f7 81 * - @ref Socket_register_group : \c SOCKET n register group
xeon011 0:4f25c0dc00f7 82 */
xeon011 0:4f25c0dc00f7 83
xeon011 0:4f25c0dc00f7 84
xeon011 0:4f25c0dc00f7 85 /**
xeon011 0:4f25c0dc00f7 86 * @defgroup WIZCHIP_IO_Functions WIZCHIP I/O functions
xeon011 0:4f25c0dc00f7 87 * @ingroup W5500
xeon011 0:4f25c0dc00f7 88 *
xeon011 0:4f25c0dc00f7 89 * @brief This supports the basic I/O functions for @ref WIZCHIP_register.
xeon011 0:4f25c0dc00f7 90 *
xeon011 0:4f25c0dc00f7 91 * - <b> Basic I/O function </b> \n
xeon011 0:4f25c0dc00f7 92 * WIZCHIP_READ(), WIZCHIP_WRITE(), WIZCHIP_READ_BUF(), WIZCHIP_WRITE_BUF() \n\n
xeon011 0:4f25c0dc00f7 93 *
xeon011 0:4f25c0dc00f7 94 * - @ref Common_register_group <b>access functions</b> \n
xeon011 0:4f25c0dc00f7 95 * -# @b Mode \n
xeon011 0:4f25c0dc00f7 96 * getMR(), setMR()
xeon011 0:4f25c0dc00f7 97 * -# @b Interrupt \n
xeon011 0:4f25c0dc00f7 98 * getIR(), setIR(), getIMR(), setIMR(), getSIR(), setSIR(), getSIMR(), setSIMR(), getINTLEVEL(), setINTLEVEL()
xeon011 0:4f25c0dc00f7 99 * -# <b> Network Information </b> \n
xeon011 0:4f25c0dc00f7 100 * getSHAR(), setSHAR(), getGAR(), setGAR(), getSUBR(), setSUBR(), getSIPR(), setSIPR()
xeon011 0:4f25c0dc00f7 101 * -# @b Retransmission \n
xeon011 0:4f25c0dc00f7 102 * getRCR(), setRCR(), getRTR(), setRTR()
xeon011 0:4f25c0dc00f7 103 * -# @b PPPoE \n
xeon011 0:4f25c0dc00f7 104 * getPTIMER(), setPTIMER(), getPMAGIC(), getPMAGIC(), getPSID(), setPSID(), getPHAR(), setPHAR(), getPMRU(), setPMRU()
xeon011 0:4f25c0dc00f7 105 * -# <b> ICMP packet </b>\n
xeon011 0:4f25c0dc00f7 106 * getUIPR(), getUPORTR()
xeon011 0:4f25c0dc00f7 107 * -# @b etc. \n
xeon011 0:4f25c0dc00f7 108 * getPHYCFGR(), setPHYCFGR(), getVERSIONR() \n\n
xeon011 0:4f25c0dc00f7 109 *
xeon011 0:4f25c0dc00f7 110 * - \ref Socket_register_group <b>access functions</b> \n
xeon011 0:4f25c0dc00f7 111 * -# <b> SOCKET control</b> \n
xeon011 0:4f25c0dc00f7 112 * getSn_MR(), setSn_MR(), getSn_CR(), setSn_CR(), getSn_IMR(), setSn_IMR(), getSn_IR(), setSn_IR()
xeon011 0:4f25c0dc00f7 113 * -# <b> SOCKET information</b> \n
xeon011 0:4f25c0dc00f7 114 * getSn_SR(), getSn_DHAR(), setSn_DHAR(), getSn_PORT(), setSn_PORT(), getSn_DIPR(), setSn_DIPR(), getSn_DPORT(), setSn_DPORT()
xeon011 0:4f25c0dc00f7 115 * getSn_MSSR(), setSn_MSSR()
xeon011 0:4f25c0dc00f7 116 * -# <b> SOCKET communication </b> \n
xeon011 0:4f25c0dc00f7 117 * getSn_RXBUF_SIZE(), setSn_RXBUF_SIZE(), getSn_TXBUF_SIZE(), setSn_TXBUF_SIZE() \n
xeon011 0:4f25c0dc00f7 118 * getSn_TX_RD(), getSn_TX_WR(), setSn_TX_WR() \n
xeon011 0:4f25c0dc00f7 119 * getSn_RX_RD(), setSn_RX_RD(), getSn_RX_WR() \n
xeon011 0:4f25c0dc00f7 120 * getSn_TX_FSR(), getSn_RX_RSR(), getSn_KPALVTR(), setSn_KPALVTR()
xeon011 0:4f25c0dc00f7 121 * -# <b> IP header field </b> \n
xeon011 0:4f25c0dc00f7 122 * getSn_FRAG(), setSn_FRAG(), getSn_TOS(), setSn_TOS() \n
xeon011 0:4f25c0dc00f7 123 * getSn_TTL(), setSn_TTL()
xeon011 0:4f25c0dc00f7 124 */
xeon011 0:4f25c0dc00f7 125
xeon011 0:4f25c0dc00f7 126
xeon011 0:4f25c0dc00f7 127
xeon011 0:4f25c0dc00f7 128 /**
xeon011 0:4f25c0dc00f7 129 * @defgroup Common_register_group Common register
xeon011 0:4f25c0dc00f7 130 * @ingroup WIZCHIP_register
xeon011 0:4f25c0dc00f7 131 *
xeon011 0:4f25c0dc00f7 132 * @brief Common register group\n
xeon011 0:4f25c0dc00f7 133 * It set the basic for the networking\n
xeon011 0:4f25c0dc00f7 134 * It set the configuration such as interrupt, network information, ICMP, etc.
xeon011 0:4f25c0dc00f7 135 * @details
xeon011 0:4f25c0dc00f7 136 * @sa MR : Mode register.
xeon011 0:4f25c0dc00f7 137 * @sa GAR, SUBR, SHAR, SIPR
xeon011 0:4f25c0dc00f7 138 * @sa INTLEVEL, IR, IMR, SIR, SIMR : Interrupt.
xeon011 0:4f25c0dc00f7 139 * @sa RTR, RCR : Data retransmission.
xeon011 0:4f25c0dc00f7 140 * @sa PTIMER, PMAGIC, PHAR, PSID, PMRU : PPPoE.
xeon011 0:4f25c0dc00f7 141 * @sa UIPR, UPORTR : ICMP message.
xeon011 0:4f25c0dc00f7 142 * @sa PHYCFGR, VERSIONR : etc.
xeon011 0:4f25c0dc00f7 143 */
xeon011 0:4f25c0dc00f7 144
xeon011 0:4f25c0dc00f7 145
xeon011 0:4f25c0dc00f7 146
xeon011 0:4f25c0dc00f7 147 /**
xeon011 0:4f25c0dc00f7 148 * @defgroup Socket_register_group Socket register
xeon011 0:4f25c0dc00f7 149 * @ingroup WIZCHIP_register
xeon011 0:4f25c0dc00f7 150 *
xeon011 0:4f25c0dc00f7 151 * @brief Socket register group.\n
xeon011 0:4f25c0dc00f7 152 * Socket register configures and control SOCKETn which is necessary to data communication.
xeon011 0:4f25c0dc00f7 153 * @details
xeon011 0:4f25c0dc00f7 154 * @sa Sn_MR, Sn_CR, Sn_IR, Sn_IMR : SOCKETn Control
xeon011 0:4f25c0dc00f7 155 * @sa Sn_SR, Sn_PORT, Sn_DHAR, Sn_DIPR, Sn_DPORT : SOCKETn Information
xeon011 0:4f25c0dc00f7 156 * @sa Sn_MSSR, Sn_TOS, Sn_TTL, Sn_KPALVTR, Sn_FRAG : Internet protocol.
xeon011 0:4f25c0dc00f7 157 * @sa Sn_RXBUF_SIZE, Sn_TXBUF_SIZE, Sn_TX_FSR, Sn_TX_RD, Sn_TX_WR, Sn_RX_RSR, Sn_RX_RD, Sn_RX_WR : Data communication
xeon011 0:4f25c0dc00f7 158 */
xeon011 0:4f25c0dc00f7 159
xeon011 0:4f25c0dc00f7 160
xeon011 0:4f25c0dc00f7 161
xeon011 0:4f25c0dc00f7 162 /**
xeon011 0:4f25c0dc00f7 163 * @defgroup Basic_IO_function Basic I/O function
xeon011 0:4f25c0dc00f7 164 * @ingroup WIZCHIP_IO_Functions
xeon011 0:4f25c0dc00f7 165 * @brief These are basic input/output functions to read values from register or write values to register.
xeon011 0:4f25c0dc00f7 166 */
xeon011 0:4f25c0dc00f7 167
xeon011 0:4f25c0dc00f7 168 /**
xeon011 0:4f25c0dc00f7 169 * @defgroup Common_register_access_function Common register access functions
xeon011 0:4f25c0dc00f7 170 * @ingroup WIZCHIP_IO_Functions
xeon011 0:4f25c0dc00f7 171 * @brief These are functions to access <b>common registers</b>.
xeon011 0:4f25c0dc00f7 172 */
xeon011 0:4f25c0dc00f7 173
xeon011 0:4f25c0dc00f7 174 /**
xeon011 0:4f25c0dc00f7 175 * @defgroup Socket_register_access_function Socket register access functions
xeon011 0:4f25c0dc00f7 176 * @ingroup WIZCHIP_IO_Functions
xeon011 0:4f25c0dc00f7 177 * @brief These are functions to access <b>socket registers</b>.
xeon011 0:4f25c0dc00f7 178 */
xeon011 0:4f25c0dc00f7 179
xeon011 0:4f25c0dc00f7 180 //------------------------------- defgroup end --------------------------------------------
xeon011 0:4f25c0dc00f7 181 //----------------------------- W5500 Common Registers IOMAP -----------------------------
xeon011 0:4f25c0dc00f7 182 /**
xeon011 0:4f25c0dc00f7 183 * @ingroup Common_register_group
xeon011 0:4f25c0dc00f7 184 * @brief Mode Register address(R/W)\n
xeon011 0:4f25c0dc00f7 185 * @ref MR is used for S/W reset, ping block mode, PPPoE mode and etc.
xeon011 0:4f25c0dc00f7 186 * @details Each bit of @ref MR defined as follows.
xeon011 0:4f25c0dc00f7 187 * <table>
xeon011 0:4f25c0dc00f7 188 * <tr> <td>7</td> <td>6</td> <td>5</td> <td>4</td> <td>3</td> <td>2</td> <td>1</td> <td>0</td> </tr>
xeon011 0:4f25c0dc00f7 189 * <tr> <td>RST</td> <td>Reserved</td> <td>WOL</td> <td>PB</td> <td>PPPoE</td> <td>Reserved</td> <td>FARP</td> <td>Reserved</td> </tr>
xeon011 0:4f25c0dc00f7 190 * </table>
xeon011 0:4f25c0dc00f7 191 * - \ref MR_RST : Reset
xeon011 0:4f25c0dc00f7 192 * - \ref MR_WOL : Wake on LAN
xeon011 0:4f25c0dc00f7 193 * - \ref MR_PB : Ping block
xeon011 0:4f25c0dc00f7 194 * - \ref MR_PPPOE : PPPoE mode
xeon011 0:4f25c0dc00f7 195 * - \ref MR_FARP : Force ARP mode
xeon011 0:4f25c0dc00f7 196 */
xeon011 0:4f25c0dc00f7 197 #define MR (_W5500_IO_BASE_ + (0x0000 << 8) + (WIZCHIP_CREG_BLOCK << 3))
xeon011 0:4f25c0dc00f7 198
xeon011 0:4f25c0dc00f7 199 /**
xeon011 0:4f25c0dc00f7 200 * @ingroup Common_register_group
xeon011 0:4f25c0dc00f7 201 * @brief Gateway IP Register address(R/W)
xeon011 0:4f25c0dc00f7 202 * @details @ref GAR configures the default gateway address.
xeon011 0:4f25c0dc00f7 203 */
xeon011 0:4f25c0dc00f7 204 #define GAR (_W5500_IO_BASE_ + (0x0001 << 8) + (WIZCHIP_CREG_BLOCK << 3))
xeon011 0:4f25c0dc00f7 205
xeon011 0:4f25c0dc00f7 206 /**
xeon011 0:4f25c0dc00f7 207 * @ingroup Common_register_group
xeon011 0:4f25c0dc00f7 208 * @brief Subnet mask Register address(R/W)
xeon011 0:4f25c0dc00f7 209 * @details @ref SUBR configures the subnet mask address.
xeon011 0:4f25c0dc00f7 210 */
xeon011 0:4f25c0dc00f7 211 #define SUBR (_W5500_IO_BASE_ + (0x0005 << 8) + (WIZCHIP_CREG_BLOCK << 3))
xeon011 0:4f25c0dc00f7 212
xeon011 0:4f25c0dc00f7 213 /**
xeon011 0:4f25c0dc00f7 214 * @ingroup Common_register_group
xeon011 0:4f25c0dc00f7 215 * @brief Source MAC Register address(R/W)
xeon011 0:4f25c0dc00f7 216 * @details @ref SHAR configures the source hardware address.
xeon011 0:4f25c0dc00f7 217 */
xeon011 0:4f25c0dc00f7 218 #define SHAR (_W5500_IO_BASE_ + (0x0009 << 8) + (WIZCHIP_CREG_BLOCK << 3))
xeon011 0:4f25c0dc00f7 219
xeon011 0:4f25c0dc00f7 220 /**
xeon011 0:4f25c0dc00f7 221 * @ingroup Common_register_group
xeon011 0:4f25c0dc00f7 222 * @brief Source IP Register address(R/W)
xeon011 0:4f25c0dc00f7 223 * @details @ref SIPR configures the source IP address.
xeon011 0:4f25c0dc00f7 224 */
xeon011 0:4f25c0dc00f7 225 #define SIPR (_W5500_IO_BASE_ + (0x000F << 8) + (WIZCHIP_CREG_BLOCK << 3))
xeon011 0:4f25c0dc00f7 226
xeon011 0:4f25c0dc00f7 227 /**
xeon011 0:4f25c0dc00f7 228 * @ingroup Common_register_group
xeon011 0:4f25c0dc00f7 229 * @brief Set Interrupt low level timer register address(R/W)
xeon011 0:4f25c0dc00f7 230 * @details @ref INTLEVEL configures the Interrupt Assert Time.
xeon011 0:4f25c0dc00f7 231 */
xeon011 0:4f25c0dc00f7 232 #define INTLEVEL (_W5500_IO_BASE_ + (0x0013 << 8) + (WIZCHIP_CREG_BLOCK << 3))
xeon011 0:4f25c0dc00f7 233
xeon011 0:4f25c0dc00f7 234 /**
xeon011 0:4f25c0dc00f7 235 * @ingroup Common_register_group
xeon011 0:4f25c0dc00f7 236 * @brief Interrupt Register(R/W)
xeon011 0:4f25c0dc00f7 237 * @details @ref IR indicates the interrupt status. Each bit of @ref IR will be still until the bit will be written to by the host.
xeon011 0:4f25c0dc00f7 238 * If @ref IR is not equal to x00 INTn PIN is asserted to low until it is x00\n\n
xeon011 0:4f25c0dc00f7 239 * Each bit of @ref IR defined as follows.
xeon011 0:4f25c0dc00f7 240 * <table>
xeon011 0:4f25c0dc00f7 241 * <tr> <td>7</td> <td>6</td> <td>5</td> <td>4</td> <td>3</td> <td>2</td> <td>1</td> <td>0</td> </tr>
xeon011 0:4f25c0dc00f7 242 * <tr> <td>CONFLICT</td> <td>UNREACH</td> <td>PPPoE</td> <td>MP</td> <td>Reserved</td> <td>Reserved</td> <td>Reserved</td> <td>Reserved</td> </tr>
xeon011 0:4f25c0dc00f7 243 * </table>
xeon011 0:4f25c0dc00f7 244 * - \ref IR_CONFLICT : IP conflict
xeon011 0:4f25c0dc00f7 245 * - \ref IR_UNREACH : Destination unreachable
xeon011 0:4f25c0dc00f7 246 * - \ref IR_PPPoE : PPPoE connection close
xeon011 0:4f25c0dc00f7 247 * - \ref IR_MP : Magic packet
xeon011 0:4f25c0dc00f7 248 */
xeon011 0:4f25c0dc00f7 249 #define IR (_W5500_IO_BASE_ + (0x0015 << 8) + (WIZCHIP_CREG_BLOCK << 3))
xeon011 0:4f25c0dc00f7 250
xeon011 0:4f25c0dc00f7 251 /**
xeon011 0:4f25c0dc00f7 252 * @ingroup Common_register_group
xeon011 0:4f25c0dc00f7 253 * @brief Interrupt mask register(R/W)
xeon011 0:4f25c0dc00f7 254 * @details @ref IMR is used to mask interrupts. Each bit of @ref IMR corresponds to each bit of @ref IR.
xeon011 0:4f25c0dc00f7 255 * When a bit of @ref IMR is and the corresponding bit of @ref IR is an interrupt will be issued. In other words,
xeon011 0:4f25c0dc00f7 256 * if a bit of @ref IMR is an interrupt will not be issued even if the corresponding bit of @ref IR is \n\n
xeon011 0:4f25c0dc00f7 257 * Each bit of @ref IMR defined as the following.
xeon011 0:4f25c0dc00f7 258 * <table>
xeon011 0:4f25c0dc00f7 259 * <tr> <td>7</td> <td>6</td> <td>5</td> <td>4</td> <td>3</td> <td>2</td> <td>1</td> <td>0</td> </tr>
xeon011 0:4f25c0dc00f7 260 * <tr> <td>IM_IR7</td> <td>IM_IR6</td> <td>IM_IR5</td> <td>IM_IR4</td> <td>Reserved</td> <td>Reserved</td> <td>Reserved</td> <td>Reserved</td> </tr>
xeon011 0:4f25c0dc00f7 261 * </table>
xeon011 0:4f25c0dc00f7 262 * - \ref IM_IR7 : IP Conflict Interrupt Mask
xeon011 0:4f25c0dc00f7 263 * - \ref IM_IR6 : Destination unreachable Interrupt Mask
xeon011 0:4f25c0dc00f7 264 * - \ref IM_IR5 : PPPoE Close Interrupt Mask
xeon011 0:4f25c0dc00f7 265 * - \ref IM_IR4 : Magic Packet Interrupt Mask
xeon011 0:4f25c0dc00f7 266 */
xeon011 0:4f25c0dc00f7 267 #define IMR (_W5500_IO_BASE_ + (0x0016 << 8) + (WIZCHIP_CREG_BLOCK << 3))
xeon011 0:4f25c0dc00f7 268
xeon011 0:4f25c0dc00f7 269 /**
xeon011 0:4f25c0dc00f7 270 * @ingroup Common_register_group
xeon011 0:4f25c0dc00f7 271 * @brief Socket Interrupt Register(R/W)
xeon011 0:4f25c0dc00f7 272 * @details @ref SIR indicates the interrupt status of Socket.\n
xeon011 0:4f25c0dc00f7 273 * Each bit of @ref SIR be still until @ref Sn_IR is cleared by the host.\n
xeon011 0:4f25c0dc00f7 274 * If @ref Sn_IR is not equal to x00 the n-th bit of @ref SIR is and INTn PIN is asserted until @ref SIR is x00 */
xeon011 0:4f25c0dc00f7 275 #define SIR (_W5500_IO_BASE_ + (0x0017 << 8) + (WIZCHIP_CREG_BLOCK << 3))
xeon011 0:4f25c0dc00f7 276
xeon011 0:4f25c0dc00f7 277 /**
xeon011 0:4f25c0dc00f7 278 * @ingroup Common_register_group
xeon011 0:4f25c0dc00f7 279 * @brief Socket Interrupt Mask Register(R/W)
xeon011 0:4f25c0dc00f7 280 * @details Each bit of @ref SIMR corresponds to each bit of @ref SIR.
xeon011 0:4f25c0dc00f7 281 * When a bit of @ref SIMR is and the corresponding bit of @ref SIR is Interrupt will be issued.
xeon011 0:4f25c0dc00f7 282 * In other words, if a bit of @ref SIMR is an interrupt will be not issued even if the corresponding bit of @ref SIR is
xeon011 0:4f25c0dc00f7 283 */
xeon011 0:4f25c0dc00f7 284 #define SIMR (_W5500_IO_BASE_ + (0x0018 << 8) + (WIZCHIP_CREG_BLOCK << 3))
xeon011 0:4f25c0dc00f7 285
xeon011 0:4f25c0dc00f7 286 /**
xeon011 0:4f25c0dc00f7 287 * @ingroup Common_register_group
xeon011 0:4f25c0dc00f7 288 * @brief Timeout register address( 1 is 100us )(R/W)
xeon011 0:4f25c0dc00f7 289 * @details @ref RTR configures the retransmission timeout period. The unit of timeout period is 100us and the default of @ref RTR is x07D0or 000
xeon011 0:4f25c0dc00f7 290 * And so the default timeout period is 200ms(100us X 2000). During the time configured by @ref RTR, W5500 waits for the peer response
xeon011 0:4f25c0dc00f7 291 * to the packet that is transmitted by \ref Sn_CR (CONNECT, DISCON, CLOSE, SEND, SEND_MAC, SEND_KEEP command).
xeon011 0:4f25c0dc00f7 292 * If the peer does not respond within the @ref RTR time, W5500 retransmits the packet or issues timeout.
xeon011 0:4f25c0dc00f7 293 */
xeon011 0:4f25c0dc00f7 294 #define RTR (_W5500_IO_BASE_ + (0x0019 << 8) + (WIZCHIP_CREG_BLOCK << 3))
xeon011 0:4f25c0dc00f7 295
xeon011 0:4f25c0dc00f7 296 /**
xeon011 0:4f25c0dc00f7 297 * @ingroup Common_register_group
xeon011 0:4f25c0dc00f7 298 * @brief Retry count register(R/W)
xeon011 0:4f25c0dc00f7 299 * @details @ref RCR configures the number of time of retransmission.
xeon011 0:4f25c0dc00f7 300 * When retransmission occurs as many as ref RCR+1 Timeout interrupt is issued (@ref Sn_IR[TIMEOUT] = .
xeon011 0:4f25c0dc00f7 301 */
xeon011 0:4f25c0dc00f7 302 #define RCR (_W5500_IO_BASE_ + (0x001B << 8) + (WIZCHIP_CREG_BLOCK << 3))
xeon011 0:4f25c0dc00f7 303
xeon011 0:4f25c0dc00f7 304 /**
xeon011 0:4f25c0dc00f7 305 * @ingroup Common_register_group
xeon011 0:4f25c0dc00f7 306 * @brief PPP LCP Request Timer register in PPPoE mode(R/W)
xeon011 0:4f25c0dc00f7 307 * @details @ref PTIMER configures the time for sending LCP echo request. The unit of time is 25ms.
xeon011 0:4f25c0dc00f7 308 */
xeon011 0:4f25c0dc00f7 309 #define PTIMER (_W5500_IO_BASE_ + (0x001C << 8) + (WIZCHIP_CREG_BLOCK << 3))
xeon011 0:4f25c0dc00f7 310
xeon011 0:4f25c0dc00f7 311 /**
xeon011 0:4f25c0dc00f7 312 * @ingroup Common_register_group
xeon011 0:4f25c0dc00f7 313 * @brief PPP LCP Magic number register in PPPoE mode(R/W)
xeon011 0:4f25c0dc00f7 314 * @details @ref PMAGIC configures the 4bytes magic number to be used in LCP negotiation.
xeon011 0:4f25c0dc00f7 315 */
xeon011 0:4f25c0dc00f7 316 #define PMAGIC (_W5500_IO_BASE_ + (0x001D << 8) + (WIZCHIP_CREG_BLOCK << 3))
xeon011 0:4f25c0dc00f7 317
xeon011 0:4f25c0dc00f7 318 /**
xeon011 0:4f25c0dc00f7 319 * @ingroup Common_register_group
xeon011 0:4f25c0dc00f7 320 * @brief PPP Destination MAC Register address(R/W)
xeon011 0:4f25c0dc00f7 321 * @details @ref PHAR configures the PPPoE server hardware address that is acquired during PPPoE connection process.
xeon011 0:4f25c0dc00f7 322 */
xeon011 0:4f25c0dc00f7 323 #define PHAR (_W5500_IO_BASE_ + (0x001E << 8) + (WIZCHIP_CREG_BLOCK << 3))
xeon011 0:4f25c0dc00f7 324
xeon011 0:4f25c0dc00f7 325 /**
xeon011 0:4f25c0dc00f7 326 * @ingroup Common_register_group
xeon011 0:4f25c0dc00f7 327 * @brief PPP Session Identification Register(R/W)
xeon011 0:4f25c0dc00f7 328 * @details @ref PSID configures the PPPoE sever session ID acquired during PPPoE connection process.
xeon011 0:4f25c0dc00f7 329 */
xeon011 0:4f25c0dc00f7 330 #define PSID (_W5500_IO_BASE_ + (0x0024 << 8) + (WIZCHIP_CREG_BLOCK << 3))
xeon011 0:4f25c0dc00f7 331
xeon011 0:4f25c0dc00f7 332 /**
xeon011 0:4f25c0dc00f7 333 * @ingroup Common_register_group
xeon011 0:4f25c0dc00f7 334 * @brief PPP Maximum Segment Size(MSS) register(R/W)
xeon011 0:4f25c0dc00f7 335 * @details @ref PMRU configures the maximum receive unit of PPPoE.
xeon011 0:4f25c0dc00f7 336 */
xeon011 0:4f25c0dc00f7 337 #define PMRU (_W5500_IO_BASE_ + (0x0026 << 8) + (WIZCHIP_CREG_BLOCK << 3))
xeon011 0:4f25c0dc00f7 338
xeon011 0:4f25c0dc00f7 339 /**
xeon011 0:4f25c0dc00f7 340 * @ingroup Common_register_group
xeon011 0:4f25c0dc00f7 341 * @brief Unreachable IP register address in UDP mode(R)
xeon011 0:4f25c0dc00f7 342 * @details W5500 receives an ICMP packet(Destination port unreachable) when data is sent to a port number
xeon011 0:4f25c0dc00f7 343 * which socket is not open and @ref UNREACH bit of @ref IR becomes and @ref UIPR & @ref UPORTR indicates
xeon011 0:4f25c0dc00f7 344 * the destination IP address & port number respectively.
xeon011 0:4f25c0dc00f7 345 */
xeon011 0:4f25c0dc00f7 346 #define UIPR (_W5500_IO_BASE_ + (0x0028 << 8) + (WIZCHIP_CREG_BLOCK << 3))
xeon011 0:4f25c0dc00f7 347
xeon011 0:4f25c0dc00f7 348 /**
xeon011 0:4f25c0dc00f7 349 * @ingroup Common_register_group
xeon011 0:4f25c0dc00f7 350 * @brief Unreachable Port register address in UDP mode(R)
xeon011 0:4f25c0dc00f7 351 * @details W5500 receives an ICMP packet(Destination port unreachable) when data is sent to a port number
xeon011 0:4f25c0dc00f7 352 * which socket is not open and @ref UNREACH bit of @ref IR becomes and @ref UIPR & @ref UPORTR
xeon011 0:4f25c0dc00f7 353 * indicates the destination IP address & port number respectively.
xeon011 0:4f25c0dc00f7 354 */
xeon011 0:4f25c0dc00f7 355 #define UPORTR (_W5500_IO_BASE_ + (0x002C << 8) + (WIZCHIP_CREG_BLOCK << 3))
xeon011 0:4f25c0dc00f7 356
xeon011 0:4f25c0dc00f7 357 /**
xeon011 0:4f25c0dc00f7 358 * @ingroup Common_register_group
xeon011 0:4f25c0dc00f7 359 * @brief PHY Status Register(R/W)
xeon011 0:4f25c0dc00f7 360 * @details @ref PHYCFGR configures PHY operation mode and resets PHY. In addition, @ref PHYCFGR indicates the status of PHY such as duplex, Speed, Link.
xeon011 0:4f25c0dc00f7 361 */
xeon011 0:4f25c0dc00f7 362 #define PHYCFGR (_W5500_IO_BASE_ + (0x002E << 8) + (WIZCHIP_CREG_BLOCK << 3))
xeon011 0:4f25c0dc00f7 363
xeon011 0:4f25c0dc00f7 364 // Reserved (_W5500_IO_BASE_ + (0x002F << 8) + (WIZCHIP_CREG_BLOCK << 3))
xeon011 0:4f25c0dc00f7 365 // Reserved (_W5500_IO_BASE_ + (0x0030 << 8) + (WIZCHIP_CREG_BLOCK << 3))
xeon011 0:4f25c0dc00f7 366 // Reserved (_W5500_IO_BASE_ + (0x0031 << 8) + (WIZCHIP_CREG_BLOCK << 3))
xeon011 0:4f25c0dc00f7 367 // Reserved (_W5500_IO_BASE_ + (0x0032 << 8) + (WIZCHIP_CREG_BLOCK << 3))
xeon011 0:4f25c0dc00f7 368 // Reserved (_W5500_IO_BASE_ + (0x0033 << 8) + (WIZCHIP_CREG_BLOCK << 3))
xeon011 0:4f25c0dc00f7 369 // Reserved (_W5500_IO_BASE_ + (0x0034 << 8) + (WIZCHIP_CREG_BLOCK << 3))
xeon011 0:4f25c0dc00f7 370 // Reserved (_W5500_IO_BASE_ + (0x0035 << 8) + (WIZCHIP_CREG_BLOCK << 3))
xeon011 0:4f25c0dc00f7 371 // Reserved (_W5500_IO_BASE_ + (0x0036 << 8) + (WIZCHIP_CREG_BLOCK << 3))
xeon011 0:4f25c0dc00f7 372 // Reserved (_W5500_IO_BASE_ + (0x0037 << 8) + (WIZCHIP_CREG_BLOCK << 3))
xeon011 0:4f25c0dc00f7 373 // Reserved (_W5500_IO_BASE_ + (0x0038 << 8) + (WIZCHIP_CREG_BLOCK << 3))
xeon011 0:4f25c0dc00f7 374
xeon011 0:4f25c0dc00f7 375 /**
xeon011 0:4f25c0dc00f7 376 * @ingroup Common_register_group
xeon011 0:4f25c0dc00f7 377 * @brief chip version register address(R)
xeon011 0:4f25c0dc00f7 378 * @details @ref VERSIONR always indicates the W5500 version as @b 0x04.
xeon011 0:4f25c0dc00f7 379 */
xeon011 0:4f25c0dc00f7 380 #define VERSIONR (_W5500_IO_BASE_ + (0x0039 << 8) + (WIZCHIP_CREG_BLOCK << 3))
xeon011 0:4f25c0dc00f7 381
xeon011 0:4f25c0dc00f7 382
xeon011 0:4f25c0dc00f7 383 //----------------------------- W5500 Socket Registers IOMAP -----------------------------
xeon011 0:4f25c0dc00f7 384 /**
xeon011 0:4f25c0dc00f7 385 * @ingroup Socket_register_group
xeon011 0:4f25c0dc00f7 386 * @brief socket Mode register(R/W)
xeon011 0:4f25c0dc00f7 387 * @details @ref Sn_MR configures the option or protocol type of Socket n.\n\n
xeon011 0:4f25c0dc00f7 388 * Each bit of @ref Sn_MR defined as the following.
xeon011 0:4f25c0dc00f7 389 * <table>
xeon011 0:4f25c0dc00f7 390 * <tr> <td>7</td> <td>6</td> <td>5</td> <td>4</td> <td>3</td> <td>2</td> <td>1</td> <td>0</td> </tr>
xeon011 0:4f25c0dc00f7 391 * <tr> <td>MULTI/MFEN</td> <td>BCASTB</td> <td>ND/MC/MMB</td> <td>UCASTB/MIP6B</td> <td>Protocol[3]</td> <td>Protocol[2]</td> <td>Protocol[1]</td> <td>Protocol[0]</td> </tr>
xeon011 0:4f25c0dc00f7 392 * </table>
xeon011 0:4f25c0dc00f7 393 * - @ref Sn_MR_MULTI : Support UDP Multicasting
xeon011 0:4f25c0dc00f7 394 * - @ref Sn_MR_BCASTB : Broadcast block <b>in UDP Multicasting</b>
xeon011 0:4f25c0dc00f7 395 * - @ref Sn_MR_ND : No Delayed Ack(TCP) flag
xeon011 0:4f25c0dc00f7 396 * - @ref Sn_MR_MC : IGMP version used <b>in UDP mulitcasting</b>
xeon011 0:4f25c0dc00f7 397 * - @ref Sn_MR_MMB : Multicast Blocking <b>in @ref Sn_MR_MACRAW mode</b>
xeon011 0:4f25c0dc00f7 398 * - @ref Sn_MR_UCASTB : Unicast Block <b>in UDP Multicating</b>
xeon011 0:4f25c0dc00f7 399 * - @ref Sn_MR_MIP6B : IPv6 packet Blocking <b>in @ref Sn_MR_MACRAW mode</b>
xeon011 0:4f25c0dc00f7 400 * - <b>Protocol</b>
xeon011 0:4f25c0dc00f7 401 * <table>
xeon011 0:4f25c0dc00f7 402 * <tr> <td><b>Protocol[3]</b></td> <td><b>Protocol[2]</b></td> <td><b>Protocol[1]</b></td> <td><b>Protocol[0]</b></td> <td>@b Meaning</td> </tr>
xeon011 0:4f25c0dc00f7 403 * <tr> <td>0</td> <td>0</td> <td>0</td> <td>0</td> <td>Closed</td> </tr>
xeon011 0:4f25c0dc00f7 404 * <tr> <td>0</td> <td>0</td> <td>0</td> <td>1</td> <td>TCP</td> </tr>
xeon011 0:4f25c0dc00f7 405 * <tr> <td>0</td> <td>0</td> <td>1</td> <td>0</td> <td>UDP</td> </tr>
xeon011 0:4f25c0dc00f7 406 * <tr> <td>0</td> <td>1</td> <td>0</td> <td>0</td> <td>MACRAW</td> </tr>
xeon011 0:4f25c0dc00f7 407 * </table>
xeon011 0:4f25c0dc00f7 408 * - @ref Sn_MR_MACRAW : MAC LAYER RAW SOCK \n
xeon011 0:4f25c0dc00f7 409 * - @ref Sn_MR_UDP : UDP
xeon011 0:4f25c0dc00f7 410 * - @ref Sn_MR_TCP : TCP
xeon011 0:4f25c0dc00f7 411 * - @ref Sn_MR_CLOSE : Unused socket
xeon011 0:4f25c0dc00f7 412 * @note MACRAW mode should be only used in Socket 0.
xeon011 0:4f25c0dc00f7 413 */
xeon011 0:4f25c0dc00f7 414 #define Sn_MR(N) (_W5500_IO_BASE_ + (0x0000 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
xeon011 0:4f25c0dc00f7 415
xeon011 0:4f25c0dc00f7 416 /**
xeon011 0:4f25c0dc00f7 417 * @ingroup Socket_register_group
xeon011 0:4f25c0dc00f7 418 * @brief Socket command register(R/W)
xeon011 0:4f25c0dc00f7 419 * @details This is used to set the command for Socket n such as OPEN, CLOSE, CONNECT, LISTEN, SEND, and RECEIVE.\n
xeon011 0:4f25c0dc00f7 420 * After W5500 accepts the command, the @ref Sn_CR register is automatically cleared to 0x00.
xeon011 0:4f25c0dc00f7 421 * Even though @ref Sn_CR is cleared to 0x00, the command is still being processed.\n
xeon011 0:4f25c0dc00f7 422 * To check whether the command is completed or not, please check the @ref Sn_IR or @ref Sn_SR.
xeon011 0:4f25c0dc00f7 423 * - @ref Sn_CR_OPEN : Initialize or open socket.
xeon011 0:4f25c0dc00f7 424 * - @ref Sn_CR_LISTEN : Wait connection request in TCP mode(<b>Server mode</b>)
xeon011 0:4f25c0dc00f7 425 * - @ref Sn_CR_CONNECT : Send connection request in TCP mode(<b>Client mode</b>)
xeon011 0:4f25c0dc00f7 426 * - @ref Sn_CR_DISCON : Send closing request in TCP mode.
xeon011 0:4f25c0dc00f7 427 * - @ref Sn_CR_CLOSE : Close socket.
xeon011 0:4f25c0dc00f7 428 * - @ref Sn_CR_SEND : Update TX buffer pointer and send data.
xeon011 0:4f25c0dc00f7 429 * - @ref Sn_CR_SEND_MAC : Send data with MAC address, so without ARP process.
xeon011 0:4f25c0dc00f7 430 * - @ref Sn_CR_SEND_KEEP : Send keep alive message.
xeon011 0:4f25c0dc00f7 431 * - @ref Sn_CR_RECV : Update RX buffer pointer and receive data.
xeon011 0:4f25c0dc00f7 432 */
xeon011 0:4f25c0dc00f7 433 #define Sn_CR(N) (_W5500_IO_BASE_ + (0x0001 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
xeon011 0:4f25c0dc00f7 434
xeon011 0:4f25c0dc00f7 435 /**
xeon011 0:4f25c0dc00f7 436 * @ingroup Socket_register_group
xeon011 0:4f25c0dc00f7 437 * @brief Socket interrupt register(R)
xeon011 0:4f25c0dc00f7 438 * @details @ref Sn_IR indicates the status of Socket Interrupt such as establishment, termination, receiving data, timeout).\n
xeon011 0:4f25c0dc00f7 439 * When an interrupt occurs and the corresponding bit of @ref Sn_IMR is the corresponding bit of @ref Sn_IR becomes \n
xeon011 0:4f25c0dc00f7 440 * In order to clear the @ref Sn_IR bit, the host should write the bit to \n
xeon011 0:4f25c0dc00f7 441 * <table>
xeon011 0:4f25c0dc00f7 442 * <tr> <td>7</td> <td>6</td> <td>5</td> <td>4</td> <td>3</td> <td>2</td> <td>1</td> <td>0</td> </tr>
xeon011 0:4f25c0dc00f7 443 * <tr> <td>Reserved</td> <td>Reserved</td> <td>Reserved</td> <td>SEND_OK</td> <td>TIMEOUT</td> <td>RECV</td> <td>DISCON</td> <td>CON</td> </tr>
xeon011 0:4f25c0dc00f7 444 * </table>
xeon011 0:4f25c0dc00f7 445 * - \ref Sn_IR_SENDOK : <b>SEND_OK Interrupt</b>
xeon011 0:4f25c0dc00f7 446 * - \ref Sn_IR_TIMEOUT : <b>TIMEOUT Interrupt</b>
xeon011 0:4f25c0dc00f7 447 * - \ref Sn_IR_RECV : <b>RECV Interrupt</b>
xeon011 0:4f25c0dc00f7 448 * - \ref Sn_IR_DISCON : <b>DISCON Interrupt</b>
xeon011 0:4f25c0dc00f7 449 * - \ref Sn_IR_CON : <b>CON Interrupt</b>
xeon011 0:4f25c0dc00f7 450 */
xeon011 0:4f25c0dc00f7 451 #define Sn_IR(N) (_W5500_IO_BASE_ + (0x0002 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
xeon011 0:4f25c0dc00f7 452
xeon011 0:4f25c0dc00f7 453 /**
xeon011 0:4f25c0dc00f7 454 * @ingroup Socket_register_group
xeon011 0:4f25c0dc00f7 455 * @brief Socket status register(R)
xeon011 0:4f25c0dc00f7 456 * @details @ref Sn_SR indicates the status of Socket n.\n
xeon011 0:4f25c0dc00f7 457 * The status of Socket n is changed by @ref Sn_CR or some special control packet as SYN, FIN packet in TCP.
xeon011 0:4f25c0dc00f7 458 * @par Normal status
xeon011 0:4f25c0dc00f7 459 * - @ref SOCK_CLOSED : Closed
xeon011 0:4f25c0dc00f7 460 * - @ref SOCK_INIT : Initiate state
xeon011 0:4f25c0dc00f7 461 * - @ref SOCK_LISTEN : Listen state
xeon011 0:4f25c0dc00f7 462 * - @ref SOCK_ESTABLISHED : Success to connect
xeon011 0:4f25c0dc00f7 463 * - @ref SOCK_CLOSE_WAIT : Closing state
xeon011 0:4f25c0dc00f7 464 * - @ref SOCK_UDP : UDP socket
xeon011 0:4f25c0dc00f7 465 * - @ref SOCK_MACRAW : MAC raw mode socket
xeon011 0:4f25c0dc00f7 466 *@par Temporary status during changing the status of Socket n.
xeon011 0:4f25c0dc00f7 467 * - @ref SOCK_SYNSENT : This indicates Socket n sent the connect-request packet (SYN packet) to a peer.
xeon011 0:4f25c0dc00f7 468 * - @ref SOCK_SYNRECV : It indicates Socket n successfully received the connect-request packet (SYN packet) from a peer.
xeon011 0:4f25c0dc00f7 469 * - @ref SOCK_FIN_WAIT : Connection state
xeon011 0:4f25c0dc00f7 470 * - @ref SOCK_CLOSING : Closing state
xeon011 0:4f25c0dc00f7 471 * - @ref SOCK_TIME_WAIT : Closing state
xeon011 0:4f25c0dc00f7 472 * - @ref SOCK_LAST_ACK : Closing state
xeon011 0:4f25c0dc00f7 473 */
xeon011 0:4f25c0dc00f7 474 #define Sn_SR(N) (_W5500_IO_BASE_ + (0x0003 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
xeon011 0:4f25c0dc00f7 475
xeon011 0:4f25c0dc00f7 476 /**
xeon011 0:4f25c0dc00f7 477 * @ingroup Socket_register_group
xeon011 0:4f25c0dc00f7 478 * @brief source port register(R/W)
xeon011 0:4f25c0dc00f7 479 * @details @ref Sn_PORT configures the source port number of Socket n.
xeon011 0:4f25c0dc00f7 480 * It is valid when Socket n is used in TCP/UPD mode. It should be set before OPEN command is ordered.
xeon011 0:4f25c0dc00f7 481 */
xeon011 0:4f25c0dc00f7 482 #define Sn_PORT(N) (_W5500_IO_BASE_ + (0x0004 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
xeon011 0:4f25c0dc00f7 483
xeon011 0:4f25c0dc00f7 484 /**
xeon011 0:4f25c0dc00f7 485 * @ingroup Socket_register_group
xeon011 0:4f25c0dc00f7 486 * @brief Peer MAC register address(R/W)
xeon011 0:4f25c0dc00f7 487 * @details @ref Sn_DHAR configures the destination hardware address of Socket n when using SEND_MAC command in UDP mode or
xeon011 0:4f25c0dc00f7 488 * it indicates that it is acquired in ARP-process by CONNECT/SEND command.
xeon011 0:4f25c0dc00f7 489 */
xeon011 0:4f25c0dc00f7 490 #define Sn_DHAR(N) (_W5500_IO_BASE_ + (0x0006 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
xeon011 0:4f25c0dc00f7 491
xeon011 0:4f25c0dc00f7 492 /**
xeon011 0:4f25c0dc00f7 493 * @ingroup Socket_register_group
xeon011 0:4f25c0dc00f7 494 * @brief Peer IP register address(R/W)
xeon011 0:4f25c0dc00f7 495 * @details @ref Sn_DIPR configures or indicates the destination IP address of Socket n. It is valid when Socket n is used in TCP/UDP mode.
xeon011 0:4f25c0dc00f7 496 * In TCP client mode, it configures an IP address of �TCP serverbefore CONNECT command.
xeon011 0:4f25c0dc00f7 497 * In TCP server mode, it indicates an IP address of �TCP clientafter successfully establishing connection.
xeon011 0:4f25c0dc00f7 498 * In UDP mode, it configures an IP address of peer to be received the UDP packet by SEND or SEND_MAC command.
xeon011 0:4f25c0dc00f7 499 */
xeon011 0:4f25c0dc00f7 500 #define Sn_DIPR(N) (_W5500_IO_BASE_ + (0x000C << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
xeon011 0:4f25c0dc00f7 501
xeon011 0:4f25c0dc00f7 502 /**
xeon011 0:4f25c0dc00f7 503 * @ingroup Socket_register_group
xeon011 0:4f25c0dc00f7 504 * @brief Peer port register address(R/W)
xeon011 0:4f25c0dc00f7 505 * @details @ref Sn_DPORT configures or indicates the destination port number of Socket n. It is valid when Socket n is used in TCP/UDP mode.
xeon011 0:4f25c0dc00f7 506 * In �TCP clientmode, it configures the listen port number of �TCP serverbefore CONNECT command.
xeon011 0:4f25c0dc00f7 507 * In �TCP Servermode, it indicates the port number of TCP client after successfully establishing connection.
xeon011 0:4f25c0dc00f7 508 * In UDP mode, it configures the port number of peer to be transmitted the UDP packet by SEND/SEND_MAC command.
xeon011 0:4f25c0dc00f7 509 */
xeon011 0:4f25c0dc00f7 510 #define Sn_DPORT(N) (_W5500_IO_BASE_ + (0x0010 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
xeon011 0:4f25c0dc00f7 511
xeon011 0:4f25c0dc00f7 512 /**
xeon011 0:4f25c0dc00f7 513 * @ingroup Socket_register_group
xeon011 0:4f25c0dc00f7 514 * @brief Maximum Segment Size(Sn_MSSR0) register address(R/W)
xeon011 0:4f25c0dc00f7 515 * @details @ref Sn_MSSR configures or indicates the MTU(Maximum Transfer Unit) of Socket n.
xeon011 0:4f25c0dc00f7 516 */
xeon011 0:4f25c0dc00f7 517 #define Sn_MSSR(N) (_W5500_IO_BASE_ + (0x0012 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
xeon011 0:4f25c0dc00f7 518
xeon011 0:4f25c0dc00f7 519 // Reserved (_W5500_IO_BASE_ + (0x0014 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
xeon011 0:4f25c0dc00f7 520
xeon011 0:4f25c0dc00f7 521 /**
xeon011 0:4f25c0dc00f7 522 * @ingroup Socket_register_group
xeon011 0:4f25c0dc00f7 523 * @brief IP Type of Service(TOS) Register(R/W)
xeon011 0:4f25c0dc00f7 524 * @details @ref Sn_TOS configures the TOS(Type Of Service field in IP Header) of Socket n.
xeon011 0:4f25c0dc00f7 525 * It is set before OPEN command.
xeon011 0:4f25c0dc00f7 526 */
xeon011 0:4f25c0dc00f7 527 #define Sn_TOS(N) (_W5500_IO_BASE_ + (0x0015 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
xeon011 0:4f25c0dc00f7 528 /**
xeon011 0:4f25c0dc00f7 529 * @ingroup Socket_register_group
xeon011 0:4f25c0dc00f7 530 * @brief IP Time to live(TTL) Register(R/W)
xeon011 0:4f25c0dc00f7 531 * @details @ref Sn_TTL configures the TTL(Time To Live field in IP header) of Socket n.
xeon011 0:4f25c0dc00f7 532 * It is set before OPEN command.
xeon011 0:4f25c0dc00f7 533 */
xeon011 0:4f25c0dc00f7 534 #define Sn_TTL(N) (_W5500_IO_BASE_ + (0x0016 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
xeon011 0:4f25c0dc00f7 535 // Reserved (_W5500_IO_BASE_ + (0x0017 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
xeon011 0:4f25c0dc00f7 536 // Reserved (_W5500_IO_BASE_ + (0x0018 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
xeon011 0:4f25c0dc00f7 537 // Reserved (_W5500_IO_BASE_ + (0x0019 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
xeon011 0:4f25c0dc00f7 538 // Reserved (_W5500_IO_BASE_ + (0x001A << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
xeon011 0:4f25c0dc00f7 539 // Reserved (_W5500_IO_BASE_ + (0x001B << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
xeon011 0:4f25c0dc00f7 540 // Reserved (_W5500_IO_BASE_ + (0x001C << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
xeon011 0:4f25c0dc00f7 541 // Reserved (_W5500_IO_BASE_ + (0x001D << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
xeon011 0:4f25c0dc00f7 542
xeon011 0:4f25c0dc00f7 543 /**
xeon011 0:4f25c0dc00f7 544 * @ingroup Socket_register_group
xeon011 0:4f25c0dc00f7 545 * @brief Receive memory size register(R/W)
xeon011 0:4f25c0dc00f7 546 * @details @ref Sn_RXBUF_SIZE configures the RX buffer block size of Socket n.
xeon011 0:4f25c0dc00f7 547 * Socket n RX Buffer Block size can be configured with 1,2,4,8, and 16 Kbytes.
xeon011 0:4f25c0dc00f7 548 * If a different size is configured, the data cannot be normally received from a peer.
xeon011 0:4f25c0dc00f7 549 * Although Socket n RX Buffer Block size is initially configured to 2Kbytes,
xeon011 0:4f25c0dc00f7 550 * user can re-configure its size using @ref Sn_RXBUF_SIZE. The total sum of @ref Sn_RXBUF_SIZE can not be exceed 16Kbytes.
xeon011 0:4f25c0dc00f7 551 * When exceeded, the data reception error is occurred.
xeon011 0:4f25c0dc00f7 552 */
xeon011 0:4f25c0dc00f7 553 #define Sn_RXBUF_SIZE(N) (_W5500_IO_BASE_ + (0x001E << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
xeon011 0:4f25c0dc00f7 554
xeon011 0:4f25c0dc00f7 555 /**
xeon011 0:4f25c0dc00f7 556 * @ingroup Socket_register_group
xeon011 0:4f25c0dc00f7 557 * @brief Transmit memory size register(R/W)
xeon011 0:4f25c0dc00f7 558 * @details @ref Sn_TXBUF_SIZE configures the TX buffer block size of Socket n. Socket n TX Buffer Block size can be configured with 1,2,4,8, and 16 Kbytes.
xeon011 0:4f25c0dc00f7 559 * If a different size is configured, the data can�t be normally transmitted to a peer.
xeon011 0:4f25c0dc00f7 560 * Although Socket n TX Buffer Block size is initially configured to 2Kbytes,
xeon011 0:4f25c0dc00f7 561 * user can be re-configure its size using @ref Sn_TXBUF_SIZE. The total sum of @ref Sn_TXBUF_SIZE can not be exceed 16Kbytes.
xeon011 0:4f25c0dc00f7 562 * When exceeded, the data transmission error is occurred.
xeon011 0:4f25c0dc00f7 563 */
xeon011 0:4f25c0dc00f7 564 #define Sn_TXBUF_SIZE(N) (_W5500_IO_BASE_ + (0x001F << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
xeon011 0:4f25c0dc00f7 565
xeon011 0:4f25c0dc00f7 566 /**
xeon011 0:4f25c0dc00f7 567 * @ingroup Socket_register_group
xeon011 0:4f25c0dc00f7 568 * @brief Transmit free memory size register(R)
xeon011 0:4f25c0dc00f7 569 * @details @ref Sn_TX_FSR indicates the free size of Socket n TX Buffer Block. It is initialized to the configured size by @ref Sn_TXBUF_SIZE.
xeon011 0:4f25c0dc00f7 570 * Data bigger than @ref Sn_TX_FSR should not be saved in the Socket n TX Buffer because the bigger data overwrites the previous saved data not yet sent.
xeon011 0:4f25c0dc00f7 571 * Therefore, check before saving the data to the Socket n TX Buffer, and if data is equal or smaller than its checked size,
xeon011 0:4f25c0dc00f7 572 * transmit the data with SEND/SEND_MAC command after saving the data in Socket n TX buffer. But, if data is bigger than its checked size,
xeon011 0:4f25c0dc00f7 573 * transmit the data after dividing into the checked size and saving in the Socket n TX buffer.
xeon011 0:4f25c0dc00f7 574 */
xeon011 0:4f25c0dc00f7 575 #define Sn_TX_FSR(N) (_W5500_IO_BASE_ + (0x0020 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
xeon011 0:4f25c0dc00f7 576
xeon011 0:4f25c0dc00f7 577 /**
xeon011 0:4f25c0dc00f7 578 * @ingroup Socket_register_group
xeon011 0:4f25c0dc00f7 579 * @brief Transmit memory read pointer register address(R)
xeon011 0:4f25c0dc00f7 580 * @details @ref Sn_TX_RD is initialized by OPEN command. However, if Sn_MR(P[3:0]) is TCP mode(001, it is re-initialized while connecting with TCP.
xeon011 0:4f25c0dc00f7 581 * After its initialization, it is auto-increased by SEND command.
xeon011 0:4f25c0dc00f7 582 * SEND command transmits the saved data from the current @ref Sn_TX_RD to the @ref Sn_TX_WR in the Socket n TX Buffer.
xeon011 0:4f25c0dc00f7 583 * After transmitting the saved data, the SEND command increases the @ref Sn_TX_RD as same as the @ref Sn_TX_WR.
xeon011 0:4f25c0dc00f7 584 * If its increment value exceeds the maximum value 0xFFFF, (greater than 0x10000 and the carry bit occurs),
xeon011 0:4f25c0dc00f7 585 * then the carry bit is ignored and will automatically update with the lower 16bits value.
xeon011 0:4f25c0dc00f7 586 */
xeon011 0:4f25c0dc00f7 587 #define Sn_TX_RD(N) (_W5500_IO_BASE_ + (0x0022 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
xeon011 0:4f25c0dc00f7 588
xeon011 0:4f25c0dc00f7 589 /**
xeon011 0:4f25c0dc00f7 590 * @ingroup Socket_register_group
xeon011 0:4f25c0dc00f7 591 * @brief Transmit memory write pointer register address(R/W)
xeon011 0:4f25c0dc00f7 592 * @details @ref Sn_TX_WR is initialized by OPEN command. However, if Sn_MR(P[3:0]) is TCP mode(001, it is re-initialized while connecting with TCP.\n
xeon011 0:4f25c0dc00f7 593 * It should be read or be updated like as follows.\n
xeon011 0:4f25c0dc00f7 594 * 1. Read the starting address for saving the transmitting data.\n
xeon011 0:4f25c0dc00f7 595 * 2. Save the transmitting data from the starting address of Socket n TX buffer.\n
xeon011 0:4f25c0dc00f7 596 * 3. After saving the transmitting data, update @ref Sn_TX_WR to the increased value as many as transmitting data size.
xeon011 0:4f25c0dc00f7 597 * If the increment value exceeds the maximum value 0xFFFF(greater than 0x10000 and the carry bit occurs),
xeon011 0:4f25c0dc00f7 598 * then the carry bit is ignored and will automatically update with the lower 16bits value.\n
xeon011 0:4f25c0dc00f7 599 * 4. Transmit the saved data in Socket n TX Buffer by using SEND/SEND command
xeon011 0:4f25c0dc00f7 600 */
xeon011 0:4f25c0dc00f7 601 #define Sn_TX_WR(N) (_W5500_IO_BASE_ + (0x0024 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
xeon011 0:4f25c0dc00f7 602
xeon011 0:4f25c0dc00f7 603 /**
xeon011 0:4f25c0dc00f7 604 * @ingroup Socket_register_group
xeon011 0:4f25c0dc00f7 605 * @brief Received data size register(R)
xeon011 0:4f25c0dc00f7 606 * @details @ref Sn_RX_RSR indicates the data size received and saved in Socket n RX Buffer.
xeon011 0:4f25c0dc00f7 607 * @ref Sn_RX_RSR does not exceed the @ref Sn_RXBUF_SIZE and is calculated as the difference between
xeon011 0:4f25c0dc00f7 608 * �Socket n RX Write Pointer (@ref Sn_RX_WR)and �Socket n RX Read Pointer (@ref Sn_RX_RD)
xeon011 0:4f25c0dc00f7 609 */
xeon011 0:4f25c0dc00f7 610 #define Sn_RX_RSR(N) (_W5500_IO_BASE_ + (0x0026 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
xeon011 0:4f25c0dc00f7 611
xeon011 0:4f25c0dc00f7 612 /**
xeon011 0:4f25c0dc00f7 613 * @ingroup Socket_register_group
xeon011 0:4f25c0dc00f7 614 * @brief Read point of Receive memory(R/W)
xeon011 0:4f25c0dc00f7 615 * @details @ref Sn_RX_RD is initialized by OPEN command. Make sure to be read or updated as follows.\n
xeon011 0:4f25c0dc00f7 616 * 1. Read the starting save address of the received data.\n
xeon011 0:4f25c0dc00f7 617 * 2. Read data from the starting address of Socket n RX Buffer.\n
xeon011 0:4f25c0dc00f7 618 * 3. After reading the received data, Update @ref Sn_RX_RD to the increased value as many as the reading size.
xeon011 0:4f25c0dc00f7 619 * If the increment value exceeds the maximum value 0xFFFF, that is, is greater than 0x10000 and the carry bit occurs,
xeon011 0:4f25c0dc00f7 620 * update with the lower 16bits value ignored the carry bit.\n
xeon011 0:4f25c0dc00f7 621 * 4. Order RECV command is for notifying the updated @ref Sn_RX_RD to W5500.
xeon011 0:4f25c0dc00f7 622 */
xeon011 0:4f25c0dc00f7 623 #define Sn_RX_RD(N) (_W5500_IO_BASE_ + (0x0028 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
xeon011 0:4f25c0dc00f7 624
xeon011 0:4f25c0dc00f7 625 /**
xeon011 0:4f25c0dc00f7 626 * @ingroup Socket_register_group
xeon011 0:4f25c0dc00f7 627 * @brief Write point of Receive memory(R)
xeon011 0:4f25c0dc00f7 628 * @details @ref Sn_RX_WR is initialized by OPEN command and it is auto-increased by the data reception.
xeon011 0:4f25c0dc00f7 629 * If the increased value exceeds the maximum value 0xFFFF, (greater than 0x10000 and the carry bit occurs),
xeon011 0:4f25c0dc00f7 630 * then the carry bit is ignored and will automatically update with the lower 16bits value.
xeon011 0:4f25c0dc00f7 631 */
xeon011 0:4f25c0dc00f7 632 #define Sn_RX_WR(N) (_W5500_IO_BASE_ + (0x002A << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
xeon011 0:4f25c0dc00f7 633
xeon011 0:4f25c0dc00f7 634 /**
xeon011 0:4f25c0dc00f7 635 * @ingroup Socket_register_group
xeon011 0:4f25c0dc00f7 636 * @brief socket interrupt mask register(R)
xeon011 0:4f25c0dc00f7 637 * @details @ref Sn_IMR masks the interrupt of Socket n.
xeon011 0:4f25c0dc00f7 638 * Each bit corresponds to each bit of @ref Sn_IR. When a Socket n Interrupt is occurred and the corresponding bit of @ref Sn_IMR is
xeon011 0:4f25c0dc00f7 639 * the corresponding bit of @ref Sn_IR becomes When both the corresponding bit of @ref Sn_IMR and @ref Sn_IR are and the n-th bit of @ref IR is
xeon011 0:4f25c0dc00f7 640 * Host is interrupted by asserted INTn PIN to low.
xeon011 0:4f25c0dc00f7 641 */
xeon011 0:4f25c0dc00f7 642 #define Sn_IMR(N) (_W5500_IO_BASE_ + (0x002C << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
xeon011 0:4f25c0dc00f7 643
xeon011 0:4f25c0dc00f7 644 /**
xeon011 0:4f25c0dc00f7 645 * @ingroup Socket_register_group
xeon011 0:4f25c0dc00f7 646 * @brief Fragment field value in IP header register(R/W)
xeon011 0:4f25c0dc00f7 647 * @details @ref Sn_FRAG configures the FRAG(Fragment field in IP header).
xeon011 0:4f25c0dc00f7 648 */
xeon011 0:4f25c0dc00f7 649 #define Sn_FRAG(N) (_W5500_IO_BASE_ + (0x002D << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
xeon011 0:4f25c0dc00f7 650
xeon011 0:4f25c0dc00f7 651 /**
xeon011 0:4f25c0dc00f7 652 * @ingroup Socket_register_group
xeon011 0:4f25c0dc00f7 653 * @brief Keep Alive Timer register(R/W)
xeon011 0:4f25c0dc00f7 654 * @details @ref Sn_KPALVTR configures the transmitting timer of �KEEP ALIVE(KA)packet of SOCKETn. It is valid only in TCP mode,
xeon011 0:4f25c0dc00f7 655 * and ignored in other modes. The time unit is 5s.
xeon011 0:4f25c0dc00f7 656 * KA packet is transmittable after @ref Sn_SR is changed to SOCK_ESTABLISHED and after the data is transmitted or received to/from a peer at least once.
xeon011 0:4f25c0dc00f7 657 * In case of '@ref Sn_KPALVTR > 0', W5500 automatically transmits KA packet after time-period for checking the TCP connection (Auto-keepalive-process).
xeon011 0:4f25c0dc00f7 658 * In case of '@ref Sn_KPALVTR = 0', Auto-keep-alive-process will not operate,
xeon011 0:4f25c0dc00f7 659 * and KA packet can be transmitted by SEND_KEEP command by the host (Manual-keep-alive-process).
xeon011 0:4f25c0dc00f7 660 * Manual-keep-alive-process is ignored in case of '@ref Sn_KPALVTR > 0'.
xeon011 0:4f25c0dc00f7 661 */
xeon011 0:4f25c0dc00f7 662 #define Sn_KPALVTR(N) (_W5500_IO_BASE_ + (0x002F << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
xeon011 0:4f25c0dc00f7 663
xeon011 0:4f25c0dc00f7 664 //#define Sn_TSR(N) (_W5500_IO_BASE_ + (0x0030 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
xeon011 0:4f25c0dc00f7 665
xeon011 0:4f25c0dc00f7 666
xeon011 0:4f25c0dc00f7 667 //----------------------------- W5500 Register values -----------------------------
xeon011 0:4f25c0dc00f7 668
xeon011 0:4f25c0dc00f7 669 /* MODE register values */
xeon011 0:4f25c0dc00f7 670 /**
xeon011 0:4f25c0dc00f7 671 * @brief Reset
xeon011 0:4f25c0dc00f7 672 * @details If this bit is All internal registers will be initialized. It will be automatically cleared as after S/W reset.
xeon011 0:4f25c0dc00f7 673 */
xeon011 0:4f25c0dc00f7 674 #define MR_RST 0x80
xeon011 0:4f25c0dc00f7 675
xeon011 0:4f25c0dc00f7 676 /**
xeon011 0:4f25c0dc00f7 677 * @brief Wake on LAN
xeon011 0:4f25c0dc00f7 678 * @details 0 : Disable WOL mode\n
xeon011 0:4f25c0dc00f7 679 * 1 : Enable WOL mode\n
xeon011 0:4f25c0dc00f7 680 * If WOL mode is enabled and the received magic packet over UDP has been normally processed, the Interrupt PIN (INTn) asserts to low.
xeon011 0:4f25c0dc00f7 681 * When using WOL mode, the UDP Socket should be opened with any source port number. (Refer to Socket n Mode Register (@ref Sn_MR) for opening Socket.)
xeon011 0:4f25c0dc00f7 682 * @note The magic packet over UDP supported by W5500 consists of 6 bytes synchronization stream (xFFFFFFFFFFFF and
xeon011 0:4f25c0dc00f7 683 * 16 times Target MAC address stream in UDP payload. The options such like password are ignored. You can use any UDP source port number for WOL mode.
xeon011 0:4f25c0dc00f7 684 */
xeon011 0:4f25c0dc00f7 685 #define MR_WOL 0x20
xeon011 0:4f25c0dc00f7 686
xeon011 0:4f25c0dc00f7 687 /**
xeon011 0:4f25c0dc00f7 688 * @brief Ping block
xeon011 0:4f25c0dc00f7 689 * @details 0 : Disable Ping block\n
xeon011 0:4f25c0dc00f7 690 * 1 : Enable Ping block\n
xeon011 0:4f25c0dc00f7 691 * If the bit is it blocks the response to a ping request.
xeon011 0:4f25c0dc00f7 692 */
xeon011 0:4f25c0dc00f7 693 #define MR_PB 0x10
xeon011 0:4f25c0dc00f7 694
xeon011 0:4f25c0dc00f7 695 /**
xeon011 0:4f25c0dc00f7 696 * @brief Enable PPPoE
xeon011 0:4f25c0dc00f7 697 * @details 0 : DisablePPPoE mode\n
xeon011 0:4f25c0dc00f7 698 * 1 : EnablePPPoE mode\n
xeon011 0:4f25c0dc00f7 699 * If you use ADSL, this bit should be
xeon011 0:4f25c0dc00f7 700 */
xeon011 0:4f25c0dc00f7 701 #define MR_PPPOE 0x08
xeon011 0:4f25c0dc00f7 702
xeon011 0:4f25c0dc00f7 703 /**
xeon011 0:4f25c0dc00f7 704 * @brief Enable UDP_FORCE_ARP CHECHK
xeon011 0:4f25c0dc00f7 705 * @details 0 : Disable Force ARP mode\n
xeon011 0:4f25c0dc00f7 706 * 1 : Enable Force ARP mode\n
xeon011 0:4f25c0dc00f7 707 * In Force ARP mode, It forces on sending ARP Request whenever data is sent.
xeon011 0:4f25c0dc00f7 708 */
xeon011 0:4f25c0dc00f7 709 #define MR_FARP 0x02
xeon011 0:4f25c0dc00f7 710
xeon011 0:4f25c0dc00f7 711 /* IR register values */
xeon011 0:4f25c0dc00f7 712 /**
xeon011 0:4f25c0dc00f7 713 * @brief Check IP conflict.
xeon011 0:4f25c0dc00f7 714 * @details Bit is set as when own source IP address is same with the sender IP address in the received ARP request.
xeon011 0:4f25c0dc00f7 715 */
xeon011 0:4f25c0dc00f7 716 #define IR_CONFLICT 0x80
xeon011 0:4f25c0dc00f7 717
xeon011 0:4f25c0dc00f7 718 /**
xeon011 0:4f25c0dc00f7 719 * @brief Get the destination unreachable message in UDP sending.
xeon011 0:4f25c0dc00f7 720 * @details When receiving the ICMP (Destination port unreachable) packet, this bit is set as
xeon011 0:4f25c0dc00f7 721 * When this bit is Destination Information such as IP address and Port number may be checked with the corresponding @ref UIPR & @ref UPORTR.
xeon011 0:4f25c0dc00f7 722 */
xeon011 0:4f25c0dc00f7 723 #define IR_UNREACH 0x40
xeon011 0:4f25c0dc00f7 724
xeon011 0:4f25c0dc00f7 725 /**
xeon011 0:4f25c0dc00f7 726 * @brief Get the PPPoE close message.
xeon011 0:4f25c0dc00f7 727 * @details When PPPoE is disconnected during PPPoE mode, this bit is set.
xeon011 0:4f25c0dc00f7 728 */
xeon011 0:4f25c0dc00f7 729 #define IR_PPPoE 0x20
xeon011 0:4f25c0dc00f7 730
xeon011 0:4f25c0dc00f7 731 /**
xeon011 0:4f25c0dc00f7 732 * @brief Get the magic packet interrupt.
xeon011 0:4f25c0dc00f7 733 * @details When WOL mode is enabled and receives the magic packet over UDP, this bit is set.
xeon011 0:4f25c0dc00f7 734 */
xeon011 0:4f25c0dc00f7 735 #define IR_MP 0x10
xeon011 0:4f25c0dc00f7 736
xeon011 0:4f25c0dc00f7 737
xeon011 0:4f25c0dc00f7 738 /* PHYCFGR register value */
xeon011 0:4f25c0dc00f7 739 #define PHYCFGR_RST ~(1<<7) //< For PHY reset, must operate AND mask.
xeon011 0:4f25c0dc00f7 740 #define PHYCFGR_OPMD (1<<6) // Configre PHY with OPMDC value
xeon011 0:4f25c0dc00f7 741 #define PHYCFGR_OPMDC_ALLA (7<<3)
xeon011 0:4f25c0dc00f7 742 #define PHYCFGR_OPMDC_PDOWN (6<<3)
xeon011 0:4f25c0dc00f7 743 #define PHYCFGR_OPMDC_NA (5<<3)
xeon011 0:4f25c0dc00f7 744 #define PHYCFGR_OPMDC_100FA (4<<3)
xeon011 0:4f25c0dc00f7 745 #define PHYCFGR_OPMDC_100F (3<<3)
xeon011 0:4f25c0dc00f7 746 #define PHYCFGR_OPMDC_100H (2<<3)
xeon011 0:4f25c0dc00f7 747 #define PHYCFGR_OPMDC_10F (1<<3)
xeon011 0:4f25c0dc00f7 748 #define PHYCFGR_OPMDC_10H (0<<3)
xeon011 0:4f25c0dc00f7 749 #define PHYCFGR_DPX_FULL (1<<2)
xeon011 0:4f25c0dc00f7 750 #define PHYCFGR_DPX_HALF (0<<2)
xeon011 0:4f25c0dc00f7 751 #define PHYCFGR_SPD_100 (1<<1)
xeon011 0:4f25c0dc00f7 752 #define PHYCFGR_SPD_10 (0<<1)
xeon011 0:4f25c0dc00f7 753 #define PHYCFGR_LNK_ON (1<<0)
xeon011 0:4f25c0dc00f7 754 #define PHYCFGR_LNK_OFF (0<<0)
xeon011 0:4f25c0dc00f7 755
xeon011 0:4f25c0dc00f7 756 /* IMR register values */
xeon011 0:4f25c0dc00f7 757 /**
xeon011 0:4f25c0dc00f7 758 * @brief IP Conflict Interrupt Mask.
xeon011 0:4f25c0dc00f7 759 * @details 0: Disable IP Conflict Interrupt\n
xeon011 0:4f25c0dc00f7 760 * 1: Enable IP Conflict Interrupt
xeon011 0:4f25c0dc00f7 761 */
xeon011 0:4f25c0dc00f7 762 #define IM_IR7 0x80
xeon011 0:4f25c0dc00f7 763
xeon011 0:4f25c0dc00f7 764 /**
xeon011 0:4f25c0dc00f7 765 * @brief Destination unreachable Interrupt Mask.
xeon011 0:4f25c0dc00f7 766 * @details 0: Disable Destination unreachable Interrupt\n
xeon011 0:4f25c0dc00f7 767 * 1: Enable Destination unreachable Interrupt
xeon011 0:4f25c0dc00f7 768 */
xeon011 0:4f25c0dc00f7 769 #define IM_IR6 0x40
xeon011 0:4f25c0dc00f7 770
xeon011 0:4f25c0dc00f7 771 /**
xeon011 0:4f25c0dc00f7 772 * @brief PPPoE Close Interrupt Mask.
xeon011 0:4f25c0dc00f7 773 * @details 0: Disable PPPoE Close Interrupt\n
xeon011 0:4f25c0dc00f7 774 * 1: Enable PPPoE Close Interrupt
xeon011 0:4f25c0dc00f7 775 */
xeon011 0:4f25c0dc00f7 776 #define IM_IR5 0x20
xeon011 0:4f25c0dc00f7 777
xeon011 0:4f25c0dc00f7 778 /**
xeon011 0:4f25c0dc00f7 779 * @brief Magic Packet Interrupt Mask.
xeon011 0:4f25c0dc00f7 780 * @details 0: Disable Magic Packet Interrupt\n
xeon011 0:4f25c0dc00f7 781 * 1: Enable Magic Packet Interrupt
xeon011 0:4f25c0dc00f7 782 */
xeon011 0:4f25c0dc00f7 783 #define IM_IR4 0x10
xeon011 0:4f25c0dc00f7 784
xeon011 0:4f25c0dc00f7 785 /* Sn_MR Default values */
xeon011 0:4f25c0dc00f7 786 /**
xeon011 0:4f25c0dc00f7 787 * @brief Support UDP Multicasting
xeon011 0:4f25c0dc00f7 788 * @details 0 : disable Multicasting\n
xeon011 0:4f25c0dc00f7 789 * 1 : enable Multicasting\n
xeon011 0:4f25c0dc00f7 790 * This bit is applied only during UDP mode(P[3:0] = 010.\n
xeon011 0:4f25c0dc00f7 791 * To use multicasting, @ref Sn_DIPR & @ref Sn_DPORT should be respectively configured with the multicast group IP address & port number
xeon011 0:4f25c0dc00f7 792 * before Socket n is opened by OPEN command of @ref Sn_CR.
xeon011 0:4f25c0dc00f7 793 */
xeon011 0:4f25c0dc00f7 794 #define Sn_MR_MULTI 0x80
xeon011 0:4f25c0dc00f7 795
xeon011 0:4f25c0dc00f7 796 /**
xeon011 0:4f25c0dc00f7 797 * @brief Broadcast block in UDP Multicasting.
xeon011 0:4f25c0dc00f7 798 * @details 0 : disable Broadcast Blocking\n
xeon011 0:4f25c0dc00f7 799 * 1 : enable Broadcast Blocking\n
xeon011 0:4f25c0dc00f7 800 * This bit blocks to receive broadcasting packet during UDP mode(P[3:0] = 010.\m
xeon011 0:4f25c0dc00f7 801 * In addition, This bit does when MACRAW mode(P[3:0] = 100
xeon011 0:4f25c0dc00f7 802 */
xeon011 0:4f25c0dc00f7 803 #define Sn_MR_BCASTB 0x40
xeon011 0:4f25c0dc00f7 804
xeon011 0:4f25c0dc00f7 805 /**
xeon011 0:4f25c0dc00f7 806 * @brief No Delayed Ack(TCP), Multicast flag
xeon011 0:4f25c0dc00f7 807 * @details 0 : Disable No Delayed ACK option\n
xeon011 0:4f25c0dc00f7 808 * 1 : Enable No Delayed ACK option\n
xeon011 0:4f25c0dc00f7 809 * This bit is applied only during TCP mode (P[3:0] = 001.\n
xeon011 0:4f25c0dc00f7 810 * When this bit is It sends the ACK packet without delay as soon as a Data packet is received from a peer.\n
xeon011 0:4f25c0dc00f7 811 * When this bit is It sends the ACK packet after waiting for the timeout time configured by @ref RTR.
xeon011 0:4f25c0dc00f7 812 */
xeon011 0:4f25c0dc00f7 813 #define Sn_MR_ND 0x20
xeon011 0:4f25c0dc00f7 814
xeon011 0:4f25c0dc00f7 815 /**
xeon011 0:4f25c0dc00f7 816 * @brief Unicast Block in UDP Multicasting
xeon011 0:4f25c0dc00f7 817 * @details 0 : disable Unicast Blocking\n
xeon011 0:4f25c0dc00f7 818 * 1 : enable Unicast Blocking\n
xeon011 0:4f25c0dc00f7 819 * This bit blocks receiving the unicast packet during UDP mode(P[3:0] = 010 and MULTI =
xeon011 0:4f25c0dc00f7 820 */
xeon011 0:4f25c0dc00f7 821 #define Sn_MR_UCASTB 0x10
xeon011 0:4f25c0dc00f7 822
xeon011 0:4f25c0dc00f7 823 /**
xeon011 0:4f25c0dc00f7 824 * @brief MAC LAYER RAW SOCK
xeon011 0:4f25c0dc00f7 825 * @details This configures the protocol mode of Socket n.
xeon011 0:4f25c0dc00f7 826 * @note MACRAW mode should be only used in Socket 0.
xeon011 0:4f25c0dc00f7 827 */
xeon011 0:4f25c0dc00f7 828 #define Sn_MR_MACRAW 0x04
xeon011 0:4f25c0dc00f7 829
xeon011 0:4f25c0dc00f7 830 //#define Sn_MR_IPRAW 0x03 /**< IP LAYER RAW SOCK */
xeon011 0:4f25c0dc00f7 831
xeon011 0:4f25c0dc00f7 832 /**
xeon011 0:4f25c0dc00f7 833 * @brief UDP
xeon011 0:4f25c0dc00f7 834 * @details This configures the protocol mode of Socket n.
xeon011 0:4f25c0dc00f7 835 */
xeon011 0:4f25c0dc00f7 836 #define Sn_MR_UDP 0x02
xeon011 0:4f25c0dc00f7 837
xeon011 0:4f25c0dc00f7 838 /**
xeon011 0:4f25c0dc00f7 839 * @brief TCP
xeon011 0:4f25c0dc00f7 840 * @details This configures the protocol mode of Socket n.
xeon011 0:4f25c0dc00f7 841 */
xeon011 0:4f25c0dc00f7 842 #define Sn_MR_TCP 0x01
xeon011 0:4f25c0dc00f7 843
xeon011 0:4f25c0dc00f7 844 /**
xeon011 0:4f25c0dc00f7 845 * @brief Unused socket
xeon011 0:4f25c0dc00f7 846 * @details This configures the protocol mode of Socket n.
xeon011 0:4f25c0dc00f7 847 */
xeon011 0:4f25c0dc00f7 848 #define Sn_MR_CLOSE 0x00
xeon011 0:4f25c0dc00f7 849
xeon011 0:4f25c0dc00f7 850 /* Sn_MR values used with Sn_MR_MACRAW */
xeon011 0:4f25c0dc00f7 851 /**
xeon011 0:4f25c0dc00f7 852 * @brief MAC filter enable in @ref Sn_MR_MACRAW mode
xeon011 0:4f25c0dc00f7 853 * @details 0 : disable MAC Filtering\n
xeon011 0:4f25c0dc00f7 854 * 1 : enable MAC Filtering\n
xeon011 0:4f25c0dc00f7 855 * This bit is applied only during MACRAW mode(P[3:0] = 100.\n
xeon011 0:4f25c0dc00f7 856 * When set as W5500 can only receive broadcasting packet or packet sent to itself.
xeon011 0:4f25c0dc00f7 857 * When this bit is W5500 can receive all packets on Ethernet.
xeon011 0:4f25c0dc00f7 858 * If user wants to implement Hybrid TCP/IP stack,
xeon011 0:4f25c0dc00f7 859 * it is recommended that this bit is set as for reducing host overhead to process the all received packets.
xeon011 0:4f25c0dc00f7 860 */
xeon011 0:4f25c0dc00f7 861 #define Sn_MR_MFEN Sn_MR_MULTI
xeon011 0:4f25c0dc00f7 862
xeon011 0:4f25c0dc00f7 863 /**
xeon011 0:4f25c0dc00f7 864 * @brief Multicast Blocking in @ref Sn_MR_MACRAW mode
xeon011 0:4f25c0dc00f7 865 * @details 0 : using IGMP version 2\n
xeon011 0:4f25c0dc00f7 866 * 1 : using IGMP version 1\n
xeon011 0:4f25c0dc00f7 867 * This bit is applied only during UDP mode(P[3:0] = 010 and MULTI =
xeon011 0:4f25c0dc00f7 868 * It configures the version for IGMP messages (Join/Leave/Report).
xeon011 0:4f25c0dc00f7 869 */
xeon011 0:4f25c0dc00f7 870 #define Sn_MR_MMB Sn_MR_ND
xeon011 0:4f25c0dc00f7 871
xeon011 0:4f25c0dc00f7 872 /**
xeon011 0:4f25c0dc00f7 873 * @brief IPv6 packet Blocking in @ref Sn_MR_MACRAW mode
xeon011 0:4f25c0dc00f7 874 * @details 0 : disable IPv6 Blocking\n
xeon011 0:4f25c0dc00f7 875 * 1 : enable IPv6 Blocking\n
xeon011 0:4f25c0dc00f7 876 * This bit is applied only during MACRAW mode (P[3:0] = 100. It blocks to receiving the IPv6 packet.
xeon011 0:4f25c0dc00f7 877 */
xeon011 0:4f25c0dc00f7 878 #define Sn_MR_MIP6B Sn_MR_UCASTB
xeon011 0:4f25c0dc00f7 879
xeon011 0:4f25c0dc00f7 880 /* Sn_MR value used with Sn_MR_UDP & Sn_MR_MULTI */
xeon011 0:4f25c0dc00f7 881 /**
xeon011 0:4f25c0dc00f7 882 * @brief IGMP version used in UDP mulitcasting
xeon011 0:4f25c0dc00f7 883 * @details 0 : disable Multicast Blocking\n
xeon011 0:4f25c0dc00f7 884 * 1 : enable Multicast Blocking\n
xeon011 0:4f25c0dc00f7 885 * This bit is applied only when MACRAW mode(P[3:0] = 100. It blocks to receive the packet with multicast MAC address.
xeon011 0:4f25c0dc00f7 886 */
xeon011 0:4f25c0dc00f7 887 #define Sn_MR_MC Sn_MR_ND
xeon011 0:4f25c0dc00f7 888
xeon011 0:4f25c0dc00f7 889 /* Sn_MR alternate values */
xeon011 0:4f25c0dc00f7 890 /**
xeon011 0:4f25c0dc00f7 891 * @brief For Berkeley Socket API
xeon011 0:4f25c0dc00f7 892 */
xeon011 0:4f25c0dc00f7 893 #define SOCK_STREAM Sn_MR_TCP
xeon011 0:4f25c0dc00f7 894
xeon011 0:4f25c0dc00f7 895 /**
xeon011 0:4f25c0dc00f7 896 * @brief For Berkeley Socket API
xeon011 0:4f25c0dc00f7 897 */
xeon011 0:4f25c0dc00f7 898 #define SOCK_DGRAM Sn_MR_UDP
xeon011 0:4f25c0dc00f7 899
xeon011 0:4f25c0dc00f7 900
xeon011 0:4f25c0dc00f7 901 /* Sn_CR values */
xeon011 0:4f25c0dc00f7 902 /**
xeon011 0:4f25c0dc00f7 903 * @brief Initialize or open socket
xeon011 0:4f25c0dc00f7 904 * @details Socket n is initialized and opened according to the protocol selected in Sn_MR(P3:P0).
xeon011 0:4f25c0dc00f7 905 * The table below shows the value of @ref Sn_SR corresponding to @ref Sn_MR.\n
xeon011 0:4f25c0dc00f7 906 * <table>
xeon011 0:4f25c0dc00f7 907 * <tr> <td>\b Sn_MR (P[3:0])</td> <td>\b Sn_SR</td> </tr>
xeon011 0:4f25c0dc00f7 908 * <tr> <td>Sn_MR_CLOSE (000</td> <td></td> </tr>
xeon011 0:4f25c0dc00f7 909 * <tr> <td>Sn_MR_TCP (001</td> <td>SOCK_INIT (0x13)</td> </tr>
xeon011 0:4f25c0dc00f7 910 * <tr> <td>Sn_MR_UDP (010</td> <td>SOCK_UDP (0x22)</td> </tr>
xeon011 0:4f25c0dc00f7 911 * <tr> <td>S0_MR_MACRAW (100</td> <td>SOCK_MACRAW (0x02)</td> </tr>
xeon011 0:4f25c0dc00f7 912 * </table>
xeon011 0:4f25c0dc00f7 913 */
xeon011 0:4f25c0dc00f7 914 #define Sn_CR_OPEN 0x01
xeon011 0:4f25c0dc00f7 915
xeon011 0:4f25c0dc00f7 916 /**
xeon011 0:4f25c0dc00f7 917 * @brief Wait connection request in TCP mode(Server mode)
xeon011 0:4f25c0dc00f7 918 * @details This is valid only in TCP mode (Sn_MR(P3:P0) = Sn_MR_TCP).
xeon011 0:4f25c0dc00f7 919 * In this mode, Socket n operates as a �TCP serverand waits for connection-request (SYN packet) from any �TCP client
xeon011 0:4f25c0dc00f7 920 * The @ref Sn_SR changes the state from SOCK_INIT to SOCKET_LISTEN.
xeon011 0:4f25c0dc00f7 921 * When a �TCP clientconnection request is successfully established,
xeon011 0:4f25c0dc00f7 922 * the @ref Sn_SR changes from SOCK_LISTEN to SOCK_ESTABLISHED and the Sn_IR(0) becomes
xeon011 0:4f25c0dc00f7 923 * But when a �TCP clientconnection request is failed, Sn_IR(3) becomes and the status of @ref Sn_SR changes to SOCK_CLOSED.
xeon011 0:4f25c0dc00f7 924 */
xeon011 0:4f25c0dc00f7 925 #define Sn_CR_LISTEN 0x02
xeon011 0:4f25c0dc00f7 926
xeon011 0:4f25c0dc00f7 927 /**
xeon011 0:4f25c0dc00f7 928 * @brief Send connection request in TCP mode(Client mode)
xeon011 0:4f25c0dc00f7 929 * @details To connect, a connect-request (SYN packet) is sent to b>TCP server</b>configured by @ref Sn_DIPR & Sn_DPORT(destination address & port).
xeon011 0:4f25c0dc00f7 930 * If the connect-request is successful, the @ref Sn_SR is changed to @ref SOCK_ESTABLISHED and the Sn_IR(0) becomes \n\n
xeon011 0:4f25c0dc00f7 931 * The connect-request fails in the following three cases.\n
xeon011 0:4f25c0dc00f7 932 * 1. When a @b ARPTO occurs (@ref Sn_IR[3] = ) because destination hardware address is not acquired through the ARP-process.\n
xeon011 0:4f25c0dc00f7 933 * 2. When a @b SYN/ACK packet is not received and @b TCPTO (Sn_IR(3) = )\n
xeon011 0:4f25c0dc00f7 934 * 3. When a @b RST packet is received instead of a @b SYN/ACK packet. In these cases, @ref Sn_SR is changed to @ref SOCK_CLOSED.
xeon011 0:4f25c0dc00f7 935 * @note This is valid only in TCP mode and operates when Socket n acts as b>TCP client</b>
xeon011 0:4f25c0dc00f7 936 */
xeon011 0:4f25c0dc00f7 937 #define Sn_CR_CONNECT 0x04
xeon011 0:4f25c0dc00f7 938
xeon011 0:4f25c0dc00f7 939 /**
xeon011 0:4f25c0dc00f7 940 * @brief Send closing request in TCP mode
xeon011 0:4f25c0dc00f7 941 * @details Regardless of b>TCP server</b>or b>TCP client</b> the DISCON command processes the disconnect-process (b>Active close</b>or b>Passive close</b>.\n
xeon011 0:4f25c0dc00f7 942 * @par Active close
xeon011 0:4f25c0dc00f7 943 * it transmits disconnect-request(FIN packet) to the connected peer\n
xeon011 0:4f25c0dc00f7 944 * @par Passive close
xeon011 0:4f25c0dc00f7 945 * When FIN packet is received from peer, a FIN packet is replied back to the peer.\n
xeon011 0:4f25c0dc00f7 946 * @details When the disconnect-process is successful (that is, FIN/ACK packet is received successfully), @ref Sn_SR is changed to @ref SOCK_CLOSED.\n
xeon011 0:4f25c0dc00f7 947 * Otherwise, TCPTO occurs (Sn_IR(3)=)= and then @ref Sn_SR is changed to @ref SOCK_CLOSED.
xeon011 0:4f25c0dc00f7 948 * @note Valid only in TCP mode.
xeon011 0:4f25c0dc00f7 949 */
xeon011 0:4f25c0dc00f7 950 #define Sn_CR_DISCON 0x08
xeon011 0:4f25c0dc00f7 951
xeon011 0:4f25c0dc00f7 952 /**
xeon011 0:4f25c0dc00f7 953 * @brief Close socket
xeon011 0:4f25c0dc00f7 954 * @details Sn_SR is changed to @ref SOCK_CLOSED.
xeon011 0:4f25c0dc00f7 955 */
xeon011 0:4f25c0dc00f7 956 #define Sn_CR_CLOSE 0x10
xeon011 0:4f25c0dc00f7 957
xeon011 0:4f25c0dc00f7 958 /**
xeon011 0:4f25c0dc00f7 959 * @brief Update TX buffer pointer and send data
xeon011 0:4f25c0dc00f7 960 * @details SEND transmits all the data in the Socket n TX buffer.\n
xeon011 0:4f25c0dc00f7 961 * For more details, please refer to Socket n TX Free Size Register (@ref Sn_TX_FSR), Socket n,
xeon011 0:4f25c0dc00f7 962 * TX Write Pointer Register(@ref Sn_TX_WR), and Socket n TX Read Pointer Register(@ref Sn_TX_RD).
xeon011 0:4f25c0dc00f7 963 */
xeon011 0:4f25c0dc00f7 964 #define Sn_CR_SEND 0x20
xeon011 0:4f25c0dc00f7 965
xeon011 0:4f25c0dc00f7 966 /**
xeon011 0:4f25c0dc00f7 967 * @brief Send data with MAC address, so without ARP process
xeon011 0:4f25c0dc00f7 968 * @details The basic operation is same as SEND.\n
xeon011 0:4f25c0dc00f7 969 * Normally SEND transmits data after destination hardware address is acquired by the automatic ARP-process(Address Resolution Protocol).\n
xeon011 0:4f25c0dc00f7 970 * But SEND_MAC transmits data without the automatic ARP-process.\n
xeon011 0:4f25c0dc00f7 971 * In this case, the destination hardware address is acquired from @ref Sn_DHAR configured by host, instead of APR-process.
xeon011 0:4f25c0dc00f7 972 * @note Valid only in UDP mode.
xeon011 0:4f25c0dc00f7 973 */
xeon011 0:4f25c0dc00f7 974 #define Sn_CR_SEND_MAC 0x21
xeon011 0:4f25c0dc00f7 975
xeon011 0:4f25c0dc00f7 976 /**
xeon011 0:4f25c0dc00f7 977 * @brief Send keep alive message
xeon011 0:4f25c0dc00f7 978 * @details It checks the connection status by sending 1byte keep-alive packet.\n
xeon011 0:4f25c0dc00f7 979 * If the peer can not respond to the keep-alive packet during timeout time, the connection is terminated and the timeout interrupt will occur.
xeon011 0:4f25c0dc00f7 980 * @note Valid only in TCP mode.
xeon011 0:4f25c0dc00f7 981 */
xeon011 0:4f25c0dc00f7 982 #define Sn_CR_SEND_KEEP 0x22
xeon011 0:4f25c0dc00f7 983
xeon011 0:4f25c0dc00f7 984 /**
xeon011 0:4f25c0dc00f7 985 * @brief Update RX buffer pointer and receive data
xeon011 0:4f25c0dc00f7 986 * @details RECV completes the processing of the received data in Socket n RX Buffer by using a RX read pointer register (@ref Sn_RX_RD).\n
xeon011 0:4f25c0dc00f7 987 * For more details, refer to Socket n RX Received Size Register (@ref Sn_RX_RSR), Socket n RX Write Pointer Register (@ref Sn_RX_WR),
xeon011 0:4f25c0dc00f7 988 * and Socket n RX Read Pointer Register (@ref Sn_RX_RD).
xeon011 0:4f25c0dc00f7 989 */
xeon011 0:4f25c0dc00f7 990 #define Sn_CR_RECV 0x40
xeon011 0:4f25c0dc00f7 991
xeon011 0:4f25c0dc00f7 992 /* Sn_IR values */
xeon011 0:4f25c0dc00f7 993 /**
xeon011 0:4f25c0dc00f7 994 * @brief SEND_OK Interrupt
xeon011 0:4f25c0dc00f7 995 * @details This is issued when SEND command is completed.
xeon011 0:4f25c0dc00f7 996 */
xeon011 0:4f25c0dc00f7 997 #define Sn_IR_SENDOK 0x10
xeon011 0:4f25c0dc00f7 998
xeon011 0:4f25c0dc00f7 999 /**
xeon011 0:4f25c0dc00f7 1000 * @brief TIMEOUT Interrupt
xeon011 0:4f25c0dc00f7 1001 * @details This is issued when ARPTO or TCPTO occurs.
xeon011 0:4f25c0dc00f7 1002 */
xeon011 0:4f25c0dc00f7 1003 #define Sn_IR_TIMEOUT 0x08
xeon011 0:4f25c0dc00f7 1004
xeon011 0:4f25c0dc00f7 1005 /**
xeon011 0:4f25c0dc00f7 1006 * @brief RECV Interrupt
xeon011 0:4f25c0dc00f7 1007 * @details This is issued whenever data is received from a peer.
xeon011 0:4f25c0dc00f7 1008 */
xeon011 0:4f25c0dc00f7 1009 #define Sn_IR_RECV 0x04
xeon011 0:4f25c0dc00f7 1010
xeon011 0:4f25c0dc00f7 1011 /**
xeon011 0:4f25c0dc00f7 1012 * @brief DISCON Interrupt
xeon011 0:4f25c0dc00f7 1013 * @details This is issued when FIN or FIN/ACK packet is received from a peer.
xeon011 0:4f25c0dc00f7 1014 */
xeon011 0:4f25c0dc00f7 1015 #define Sn_IR_DISCON 0x02
xeon011 0:4f25c0dc00f7 1016
xeon011 0:4f25c0dc00f7 1017 /**
xeon011 0:4f25c0dc00f7 1018 * @brief CON Interrupt
xeon011 0:4f25c0dc00f7 1019 * @details This is issued one time when the connection with peer is successful and then @ref Sn_SR is changed to @ref SOCK_ESTABLISHED.
xeon011 0:4f25c0dc00f7 1020 */
xeon011 0:4f25c0dc00f7 1021 #define Sn_IR_CON 0x01
xeon011 0:4f25c0dc00f7 1022
xeon011 0:4f25c0dc00f7 1023 /* Sn_SR values */
xeon011 0:4f25c0dc00f7 1024 /**
xeon011 0:4f25c0dc00f7 1025 * @brief Closed
xeon011 0:4f25c0dc00f7 1026 * @details This indicates that Socket n is released.\N
xeon011 0:4f25c0dc00f7 1027 * When DICON, CLOSE command is ordered, or when a timeout occurs, it is changed to @ref SOCK_CLOSED regardless of previous status.
xeon011 0:4f25c0dc00f7 1028 */
xeon011 0:4f25c0dc00f7 1029 #define SOCK_CLOSED 0x00
xeon011 0:4f25c0dc00f7 1030
xeon011 0:4f25c0dc00f7 1031 /**
xeon011 0:4f25c0dc00f7 1032 * @brief Initiate state
xeon011 0:4f25c0dc00f7 1033 * @details This indicates Socket n is opened with TCP mode.\N
xeon011 0:4f25c0dc00f7 1034 * It is changed to @ref SOCK_INIT when Sn_MR(P[3:0]) = 001and OPEN command is ordered.\N
xeon011 0:4f25c0dc00f7 1035 * After @ref SOCK_INIT, user can use LISTEN /CONNECT command.
xeon011 0:4f25c0dc00f7 1036 */
xeon011 0:4f25c0dc00f7 1037 #define SOCK_INIT 0x13
xeon011 0:4f25c0dc00f7 1038
xeon011 0:4f25c0dc00f7 1039 /**
xeon011 0:4f25c0dc00f7 1040 * @brief Listen state
xeon011 0:4f25c0dc00f7 1041 * @details This indicates Socket n is operating as b>TCP server</b>mode and waiting for connection-request (SYN packet) from a peer (b>TCP client</b>.\n
xeon011 0:4f25c0dc00f7 1042 * It will change to @ref SOCK_ESTALBLISHED when the connection-request is successfully accepted.\n
xeon011 0:4f25c0dc00f7 1043 * Otherwise it will change to @ref SOCK_CLOSED after TCPTO occurred (Sn_IR(TIMEOUT) = .
xeon011 0:4f25c0dc00f7 1044 */
xeon011 0:4f25c0dc00f7 1045 #define SOCK_LISTEN 0x14
xeon011 0:4f25c0dc00f7 1046
xeon011 0:4f25c0dc00f7 1047 /**
xeon011 0:4f25c0dc00f7 1048 * @brief Connection state
xeon011 0:4f25c0dc00f7 1049 * @details This indicates Socket n sent the connect-request packet (SYN packet) to a peer.\n
xeon011 0:4f25c0dc00f7 1050 * It is temporarily shown when @ref Sn_SR is changed from @ref SOCK_INIT to @ref SOCK_ESTABLISHED by CONNECT command.\n
xeon011 0:4f25c0dc00f7 1051 * If connect-accept(SYN/ACK packet) is received from the peer at SOCK_SYNSENT, it changes to @ref SOCK_ESTABLISHED.\n
xeon011 0:4f25c0dc00f7 1052 * Otherwise, it changes to @ref SOCK_CLOSED after TCPTO (@ref Sn_IR[TIMEOUT] = is occurred.
xeon011 0:4f25c0dc00f7 1053 */
xeon011 0:4f25c0dc00f7 1054 #define SOCK_SYNSENT 0x15
xeon011 0:4f25c0dc00f7 1055
xeon011 0:4f25c0dc00f7 1056 /**
xeon011 0:4f25c0dc00f7 1057 * @brief Connection state
xeon011 0:4f25c0dc00f7 1058 * @details It indicates Socket n successfully received the connect-request packet (SYN packet) from a peer.\n
xeon011 0:4f25c0dc00f7 1059 * If socket n sends the response (SYN/ACK packet) to the peer successfully, it changes to @ref SOCK_ESTABLISHED. \n
xeon011 0:4f25c0dc00f7 1060 * If not, it changes to @ref SOCK_CLOSED after timeout occurs (@ref Sn_IR[TIMEOUT] = .
xeon011 0:4f25c0dc00f7 1061 */
xeon011 0:4f25c0dc00f7 1062 #define SOCK_SYNRECV 0x16
xeon011 0:4f25c0dc00f7 1063
xeon011 0:4f25c0dc00f7 1064 /**
xeon011 0:4f25c0dc00f7 1065 * @brief Success to connect
xeon011 0:4f25c0dc00f7 1066 * @details This indicates the status of the connection of Socket n.\n
xeon011 0:4f25c0dc00f7 1067 * It changes to @ref SOCK_ESTABLISHED when the b>TCP SERVER</b>processed the SYN packet from the b>TCP CLIENT</b>during @ref SOCK_LISTEN, or
xeon011 0:4f25c0dc00f7 1068 * when the CONNECT command is successful.\n
xeon011 0:4f25c0dc00f7 1069 * During @ref SOCK_ESTABLISHED, DATA packet can be transferred using SEND or RECV command.
xeon011 0:4f25c0dc00f7 1070 */
xeon011 0:4f25c0dc00f7 1071 #define SOCK_ESTABLISHED 0x17
xeon011 0:4f25c0dc00f7 1072
xeon011 0:4f25c0dc00f7 1073 /**
xeon011 0:4f25c0dc00f7 1074 * @brief Closing state
xeon011 0:4f25c0dc00f7 1075 * @details These indicate Socket n is closing.\n
xeon011 0:4f25c0dc00f7 1076 * These are shown in disconnect-process such as active-close and passive-close.\n
xeon011 0:4f25c0dc00f7 1077 * When Disconnect-process is successfully completed, or when timeout occurs, these change to @ref SOCK_CLOSED.
xeon011 0:4f25c0dc00f7 1078 */
xeon011 0:4f25c0dc00f7 1079 #define SOCK_FIN_WAIT 0x18
xeon011 0:4f25c0dc00f7 1080
xeon011 0:4f25c0dc00f7 1081 /**
xeon011 0:4f25c0dc00f7 1082 * @brief Closing state
xeon011 0:4f25c0dc00f7 1083 * @details These indicate Socket n is closing.\n
xeon011 0:4f25c0dc00f7 1084 * These are shown in disconnect-process such as active-close and passive-close.\n
xeon011 0:4f25c0dc00f7 1085 * When Disconnect-process is successfully completed, or when timeout occurs, these change to @ref SOCK_CLOSED.
xeon011 0:4f25c0dc00f7 1086 */
xeon011 0:4f25c0dc00f7 1087 #define SOCK_CLOSING 0x1A
xeon011 0:4f25c0dc00f7 1088
xeon011 0:4f25c0dc00f7 1089 /**
xeon011 0:4f25c0dc00f7 1090 * @brief Closing state
xeon011 0:4f25c0dc00f7 1091 * @details These indicate Socket n is closing.\n
xeon011 0:4f25c0dc00f7 1092 * These are shown in disconnect-process such as active-close and passive-close.\n
xeon011 0:4f25c0dc00f7 1093 * When Disconnect-process is successfully completed, or when timeout occurs, these change to @ref SOCK_CLOSED.
xeon011 0:4f25c0dc00f7 1094 */
xeon011 0:4f25c0dc00f7 1095 #define SOCK_TIME_WAIT 0x1B
xeon011 0:4f25c0dc00f7 1096
xeon011 0:4f25c0dc00f7 1097 /**
xeon011 0:4f25c0dc00f7 1098 * @brief Closing state
xeon011 0:4f25c0dc00f7 1099 * @details This indicates Socket n received the disconnect-request (FIN packet) from the connected peer.\n
xeon011 0:4f25c0dc00f7 1100 * This is half-closing status, and data can be transferred.\n
xeon011 0:4f25c0dc00f7 1101 * For full-closing, DISCON command is used. But For just-closing, CLOSE command is used.
xeon011 0:4f25c0dc00f7 1102 */
xeon011 0:4f25c0dc00f7 1103 #define SOCK_CLOSE_WAIT 0x1C
xeon011 0:4f25c0dc00f7 1104
xeon011 0:4f25c0dc00f7 1105 /**
xeon011 0:4f25c0dc00f7 1106 * @brief Closing state
xeon011 0:4f25c0dc00f7 1107 * @details This indicates Socket n is waiting for the response (FIN/ACK packet) to the disconnect-request (FIN packet) by passive-close.\n
xeon011 0:4f25c0dc00f7 1108 * It changes to @ref SOCK_CLOSED when Socket n received the response successfully, or when timeout occurs (@ref Sn_IR[TIMEOUT] = .
xeon011 0:4f25c0dc00f7 1109 */
xeon011 0:4f25c0dc00f7 1110 #define SOCK_LAST_ACK 0x1D
xeon011 0:4f25c0dc00f7 1111
xeon011 0:4f25c0dc00f7 1112 /**
xeon011 0:4f25c0dc00f7 1113 * @brief UDP socket
xeon011 0:4f25c0dc00f7 1114 * @details This indicates Socket n is opened in UDP mode(Sn_MR(P[3:0]) = 010.\n
xeon011 0:4f25c0dc00f7 1115 * It changes to SOCK_UPD when Sn_MR(P[3:0]) = 010 and OPEN command is ordered.\n
xeon011 0:4f25c0dc00f7 1116 * Unlike TCP mode, data can be transfered without the connection-process.
xeon011 0:4f25c0dc00f7 1117 */
xeon011 0:4f25c0dc00f7 1118 #define SOCK_UDP 0x22
xeon011 0:4f25c0dc00f7 1119
xeon011 0:4f25c0dc00f7 1120 //#define SOCK_IPRAW 0x32 /**< IP raw mode socket */
xeon011 0:4f25c0dc00f7 1121
xeon011 0:4f25c0dc00f7 1122 /**
xeon011 0:4f25c0dc00f7 1123 * @brief MAC raw mode socket
xeon011 0:4f25c0dc00f7 1124 * @details This indicates Socket 0 is opened in MACRAW mode (S0_MR(P[3:0]) = 100and is valid only in Socket 0.\n
xeon011 0:4f25c0dc00f7 1125 * It changes to SOCK_MACRAW when S0_MR(P[3:0] = 100and OPEN command is ordered.\n
xeon011 0:4f25c0dc00f7 1126 * Like UDP mode socket, MACRAW mode Socket 0 can transfer a MAC packet (Ethernet frame) without the connection-process.
xeon011 0:4f25c0dc00f7 1127 */
xeon011 0:4f25c0dc00f7 1128 #define SOCK_MACRAW 0x42
xeon011 0:4f25c0dc00f7 1129
xeon011 0:4f25c0dc00f7 1130 //#define SOCK_PPPOE 0x5F
xeon011 0:4f25c0dc00f7 1131
xeon011 0:4f25c0dc00f7 1132 /* IP PROTOCOL */
xeon011 0:4f25c0dc00f7 1133 #define IPPROTO_IP 0 //< Dummy for IP
xeon011 0:4f25c0dc00f7 1134 #define IPPROTO_ICMP 1 //< Control message protocol
xeon011 0:4f25c0dc00f7 1135 #define IPPROTO_IGMP 2 //< Internet group management protocol
xeon011 0:4f25c0dc00f7 1136 #define IPPROTO_GGP 3 //< Gateway^2 (deprecated)
xeon011 0:4f25c0dc00f7 1137 #define IPPROTO_TCP 6 //< TCP
xeon011 0:4f25c0dc00f7 1138 #define IPPROTO_PUP 12 //< PUP
xeon011 0:4f25c0dc00f7 1139 #define IPPROTO_UDP 17 //< UDP
xeon011 0:4f25c0dc00f7 1140 #define IPPROTO_IDP 22 //< XNS idp
xeon011 0:4f25c0dc00f7 1141 #define IPPROTO_ND 77 //< UNOFFICIAL net disk protocol
xeon011 0:4f25c0dc00f7 1142 #define IPPROTO_RAW 255 //< Raw IP packet
xeon011 0:4f25c0dc00f7 1143
xeon011 0:4f25c0dc00f7 1144
xeon011 0:4f25c0dc00f7 1145 /**
xeon011 0:4f25c0dc00f7 1146 * @brief Enter a critical section
xeon011 0:4f25c0dc00f7 1147 *
xeon011 0:4f25c0dc00f7 1148 * @details It is provided to protect your shared code which are executed without distribution. \n \n
xeon011 0:4f25c0dc00f7 1149 *
xeon011 0:4f25c0dc00f7 1150 * In non-OS environment, It can be just implemented by disabling whole interrupt.\n
xeon011 0:4f25c0dc00f7 1151 * In OS environment, You can replace it to critical section api supported by OS.
xeon011 0:4f25c0dc00f7 1152 *
xeon011 0:4f25c0dc00f7 1153 * \sa WIZCHIP_READ(), WIZCHIP_WRITE(), WIZCHIP_READ_BUF(), WIZCHIP_WRITE_BUF()
xeon011 0:4f25c0dc00f7 1154 * \sa WIZCHIP_CRITICAL_EXIT()
xeon011 0:4f25c0dc00f7 1155 */
xeon011 0:4f25c0dc00f7 1156 #define WIZCHIP_CRITICAL_ENTER() WIZCHIP.CRIS._enter()
xeon011 0:4f25c0dc00f7 1157
xeon011 0:4f25c0dc00f7 1158 /**
xeon011 0:4f25c0dc00f7 1159 * @brief Exit a critical section
xeon011 0:4f25c0dc00f7 1160 *
xeon011 0:4f25c0dc00f7 1161 * @details It is provided to protect your shared code which are executed without distribution. \n\n
xeon011 0:4f25c0dc00f7 1162 *
xeon011 0:4f25c0dc00f7 1163 * In non-OS environment, It can be just implemented by disabling whole interrupt. \n
xeon011 0:4f25c0dc00f7 1164 * In OS environment, You can replace it to critical section api supported by OS.
xeon011 0:4f25c0dc00f7 1165 *
xeon011 0:4f25c0dc00f7 1166 * @sa WIZCHIP_READ(), WIZCHIP_WRITE(), WIZCHIP_READ_BUF(), WIZCHIP_WRITE_BUF()
xeon011 0:4f25c0dc00f7 1167 * @sa WIZCHIP_CRITICAL_ENTER()
xeon011 0:4f25c0dc00f7 1168 */
xeon011 0:4f25c0dc00f7 1169 #define WIZCHIP_CRITICAL_EXIT() WIZCHIP.CRIS._exit()
xeon011 0:4f25c0dc00f7 1170
xeon011 0:4f25c0dc00f7 1171
xeon011 0:4f25c0dc00f7 1172
xeon011 0:4f25c0dc00f7 1173 ////////////////////////
xeon011 0:4f25c0dc00f7 1174 // Basic I/O Function //
xeon011 0:4f25c0dc00f7 1175 ////////////////////////
xeon011 0:4f25c0dc00f7 1176
xeon011 0:4f25c0dc00f7 1177 /**
xeon011 0:4f25c0dc00f7 1178 * @ingroup Basic_IO_function
xeon011 0:4f25c0dc00f7 1179 * @brief It reads 1 byte value from a register.
xeon011 0:4f25c0dc00f7 1180 * @param AddrSel Register address
xeon011 0:4f25c0dc00f7 1181 * @return The value of register
xeon011 0:4f25c0dc00f7 1182 */
xeon011 0:4f25c0dc00f7 1183 uint8_t WIZCHIP_READ (uint32_t AddrSel);
xeon011 0:4f25c0dc00f7 1184
xeon011 0:4f25c0dc00f7 1185 /**
xeon011 0:4f25c0dc00f7 1186 * @ingroup Basic_IO_function
xeon011 0:4f25c0dc00f7 1187 * @brief It writes 1 byte value to a register.
xeon011 0:4f25c0dc00f7 1188 * @param AddrSel Register address
xeon011 0:4f25c0dc00f7 1189 * @param wb Write data
xeon011 0:4f25c0dc00f7 1190 * @return void
xeon011 0:4f25c0dc00f7 1191 */
xeon011 0:4f25c0dc00f7 1192 void WIZCHIP_WRITE(uint32_t AddrSel, uint8_t wb );
xeon011 0:4f25c0dc00f7 1193
xeon011 0:4f25c0dc00f7 1194 /**
xeon011 0:4f25c0dc00f7 1195 * @ingroup Basic_IO_function
xeon011 0:4f25c0dc00f7 1196 * @brief It reads sequence data from registers.
xeon011 0:4f25c0dc00f7 1197 * @param AddrSel Register address
xeon011 0:4f25c0dc00f7 1198 * @param pBuf Pointer buffer to read data
xeon011 0:4f25c0dc00f7 1199 * @param len Data length
xeon011 0:4f25c0dc00f7 1200 */
xeon011 0:4f25c0dc00f7 1201 void WIZCHIP_READ_BUF (uint32_t AddrSel, uint8_t* pBuf, uint16_t len);
xeon011 0:4f25c0dc00f7 1202
xeon011 0:4f25c0dc00f7 1203 /**
xeon011 0:4f25c0dc00f7 1204 * @ingroup Basic_IO_function
xeon011 0:4f25c0dc00f7 1205 * @brief It writes sequence data to registers.
xeon011 0:4f25c0dc00f7 1206 * @param AddrSel Register address
xeon011 0:4f25c0dc00f7 1207 * @param pBuf Pointer buffer to write data
xeon011 0:4f25c0dc00f7 1208 * @param len Data length
xeon011 0:4f25c0dc00f7 1209 */
xeon011 0:4f25c0dc00f7 1210 void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, uint16_t len);
xeon011 0:4f25c0dc00f7 1211
xeon011 0:4f25c0dc00f7 1212 /////////////////////////////////
xeon011 0:4f25c0dc00f7 1213 // Common Register I/O function //
xeon011 0:4f25c0dc00f7 1214 /////////////////////////////////
xeon011 0:4f25c0dc00f7 1215 /**
xeon011 0:4f25c0dc00f7 1216 * @ingroup Common_register_access_function
xeon011 0:4f25c0dc00f7 1217 * @brief Set Mode Register
xeon011 0:4f25c0dc00f7 1218 * @param (uint8_t)mr The value to be set.
xeon011 0:4f25c0dc00f7 1219 * @sa getMR()
xeon011 0:4f25c0dc00f7 1220 */
xeon011 0:4f25c0dc00f7 1221 #define setMR(mr) \
xeon011 0:4f25c0dc00f7 1222 WIZCHIP_WRITE(MR,mr)
xeon011 0:4f25c0dc00f7 1223
xeon011 0:4f25c0dc00f7 1224
xeon011 0:4f25c0dc00f7 1225 /**
xeon011 0:4f25c0dc00f7 1226 * @ingroup Common_register_access_function
xeon011 0:4f25c0dc00f7 1227 * @brief Get Mode Register
xeon011 0:4f25c0dc00f7 1228 * @return uint8_t. The value of Mode register.
xeon011 0:4f25c0dc00f7 1229 * @sa setMR()
xeon011 0:4f25c0dc00f7 1230 */
xeon011 0:4f25c0dc00f7 1231 #define getMR() \
xeon011 0:4f25c0dc00f7 1232 WIZCHIP_READ(MR)
xeon011 0:4f25c0dc00f7 1233
xeon011 0:4f25c0dc00f7 1234 /**
xeon011 0:4f25c0dc00f7 1235 * @ingroup Common_register_access_function
xeon011 0:4f25c0dc00f7 1236 * @brief Set gateway IP address
xeon011 0:4f25c0dc00f7 1237 * @param (uint8_t*)gar Pointer variable to set gateway IP address. It should be allocated 4 bytes.
xeon011 0:4f25c0dc00f7 1238 * @sa getGAR()
xeon011 0:4f25c0dc00f7 1239 */
xeon011 0:4f25c0dc00f7 1240 #define setGAR(gar) \
xeon011 0:4f25c0dc00f7 1241 WIZCHIP_WRITE_BUF(GAR,gar,4)
xeon011 0:4f25c0dc00f7 1242
xeon011 0:4f25c0dc00f7 1243 /**
xeon011 0:4f25c0dc00f7 1244 * @ingroup Common_register_access_function
xeon011 0:4f25c0dc00f7 1245 * @brief Get gateway IP address
xeon011 0:4f25c0dc00f7 1246 * @param (uint8_t*)gar Pointer variable to get gateway IP address. It should be allocated 4 bytes.
xeon011 0:4f25c0dc00f7 1247 * @sa setGAR()
xeon011 0:4f25c0dc00f7 1248 */
xeon011 0:4f25c0dc00f7 1249 #define getGAR(gar) \
xeon011 0:4f25c0dc00f7 1250 WIZCHIP_READ_BUF(GAR,gar,4)
xeon011 0:4f25c0dc00f7 1251
xeon011 0:4f25c0dc00f7 1252 /**
xeon011 0:4f25c0dc00f7 1253 * @ingroup Common_register_access_function
xeon011 0:4f25c0dc00f7 1254 * @brief Set subnet mask address
xeon011 0:4f25c0dc00f7 1255 * @param (uint8_t*)subr Pointer variable to set subnet mask address. It should be allocated 4 bytes.
xeon011 0:4f25c0dc00f7 1256 * @sa getSUBR()
xeon011 0:4f25c0dc00f7 1257 */
xeon011 0:4f25c0dc00f7 1258 #define setSUBR(subr) \
xeon011 0:4f25c0dc00f7 1259 WIZCHIP_WRITE_BUF(SUBR, subr,4)
xeon011 0:4f25c0dc00f7 1260
xeon011 0:4f25c0dc00f7 1261
xeon011 0:4f25c0dc00f7 1262 /**
xeon011 0:4f25c0dc00f7 1263 * @ingroup Common_register_access_function
xeon011 0:4f25c0dc00f7 1264 * @brief Get subnet mask address
xeon011 0:4f25c0dc00f7 1265 * @param (uint8_t*)subr Pointer variable to get subnet mask address. It should be allocated 4 bytes.
xeon011 0:4f25c0dc00f7 1266 * @sa setSUBR()
xeon011 0:4f25c0dc00f7 1267 */
xeon011 0:4f25c0dc00f7 1268 #define getSUBR(subr) \
xeon011 0:4f25c0dc00f7 1269 WIZCHIP_READ_BUF(SUBR, subr, 4)
xeon011 0:4f25c0dc00f7 1270
xeon011 0:4f25c0dc00f7 1271 /**
xeon011 0:4f25c0dc00f7 1272 * @ingroup Common_register_access_function
xeon011 0:4f25c0dc00f7 1273 * @brief Set local MAC address
xeon011 0:4f25c0dc00f7 1274 * @param (uint8_t*)shar Pointer variable to set local MAC address. It should be allocated 6 bytes.
xeon011 0:4f25c0dc00f7 1275 * @sa getSHAR()
xeon011 0:4f25c0dc00f7 1276 */
xeon011 0:4f25c0dc00f7 1277 #define setSHAR(shar) \
xeon011 0:4f25c0dc00f7 1278 WIZCHIP_WRITE_BUF(SHAR, shar, 6)
xeon011 0:4f25c0dc00f7 1279
xeon011 0:4f25c0dc00f7 1280 /**
xeon011 0:4f25c0dc00f7 1281 * @ingroup Common_register_access_function
xeon011 0:4f25c0dc00f7 1282 * @brief Get local MAC address
xeon011 0:4f25c0dc00f7 1283 * @param (uint8_t*)shar Pointer variable to get local MAC address. It should be allocated 6 bytes.
xeon011 0:4f25c0dc00f7 1284 * @sa setSHAR()
xeon011 0:4f25c0dc00f7 1285 */
xeon011 0:4f25c0dc00f7 1286 #define getSHAR(shar) \
xeon011 0:4f25c0dc00f7 1287 WIZCHIP_READ_BUF(SHAR, shar, 6)
xeon011 0:4f25c0dc00f7 1288
xeon011 0:4f25c0dc00f7 1289 /**
xeon011 0:4f25c0dc00f7 1290 * @ingroup Common_register_access_function
xeon011 0:4f25c0dc00f7 1291 * @brief Set local IP address
xeon011 0:4f25c0dc00f7 1292 * @param (uint8_t*)sipr Pointer variable to set local IP address. It should be allocated 4 bytes.
xeon011 0:4f25c0dc00f7 1293 * @sa getSIPR()
xeon011 0:4f25c0dc00f7 1294 */
xeon011 0:4f25c0dc00f7 1295 #define setSIPR(sipr) \
xeon011 0:4f25c0dc00f7 1296 WIZCHIP_WRITE_BUF(SIPR, sipr, 4)
xeon011 0:4f25c0dc00f7 1297
xeon011 0:4f25c0dc00f7 1298 /**
xeon011 0:4f25c0dc00f7 1299 * @ingroup Common_register_access_function
xeon011 0:4f25c0dc00f7 1300 * @brief Get local IP address
xeon011 0:4f25c0dc00f7 1301 * @param (uint8_t*)sipr Pointer variable to get local IP address. It should be allocated 4 bytes.
xeon011 0:4f25c0dc00f7 1302 * @sa setSIPR()
xeon011 0:4f25c0dc00f7 1303 */
xeon011 0:4f25c0dc00f7 1304 #define getSIPR(sipr) \
xeon011 0:4f25c0dc00f7 1305 WIZCHIP_READ_BUF(SIPR, sipr, 4)
xeon011 0:4f25c0dc00f7 1306
xeon011 0:4f25c0dc00f7 1307 /**
xeon011 0:4f25c0dc00f7 1308 * @ingroup Common_register_access_function
xeon011 0:4f25c0dc00f7 1309 * @brief Set INTLEVEL register
xeon011 0:4f25c0dc00f7 1310 * @param (uint16_t)intlevel Value to set @ref INTLEVEL register.
xeon011 0:4f25c0dc00f7 1311 * @sa getINTLEVEL()
xeon011 0:4f25c0dc00f7 1312 */
xeon011 0:4f25c0dc00f7 1313 #define setINTLEVEL(intlevel) {\
xeon011 0:4f25c0dc00f7 1314 WIZCHIP_WRITE(INTLEVEL, (uint8_t)(intlevel >> 8)); \
xeon011 0:4f25c0dc00f7 1315 WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(INTLEVEL,1), (uint8_t) intlevel); \
xeon011 0:4f25c0dc00f7 1316 }
xeon011 0:4f25c0dc00f7 1317
xeon011 0:4f25c0dc00f7 1318
xeon011 0:4f25c0dc00f7 1319 /**
xeon011 0:4f25c0dc00f7 1320 * @ingroup Common_register_access_function
xeon011 0:4f25c0dc00f7 1321 * @brief Get INTLEVEL register
xeon011 0:4f25c0dc00f7 1322 * @return uint16_t. Value of @ref INTLEVEL register.
xeon011 0:4f25c0dc00f7 1323 * @sa setINTLEVEL()
xeon011 0:4f25c0dc00f7 1324 */
xeon011 0:4f25c0dc00f7 1325 #define getINTLEVEL() \
xeon011 0:4f25c0dc00f7 1326 ((WIZCHIP_READ(INTLEVEL) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(INTLEVEL,1)))
xeon011 0:4f25c0dc00f7 1327
xeon011 0:4f25c0dc00f7 1328 /**
xeon011 0:4f25c0dc00f7 1329 * @ingroup Common_register_access_function
xeon011 0:4f25c0dc00f7 1330 * @brief Set @ref IR register
xeon011 0:4f25c0dc00f7 1331 * @param (uint8_t)ir Value to set @ref IR register.
xeon011 0:4f25c0dc00f7 1332 * @sa getIR()
xeon011 0:4f25c0dc00f7 1333 */
xeon011 0:4f25c0dc00f7 1334 #define setIR(ir) \
xeon011 0:4f25c0dc00f7 1335 WIZCHIP_WRITE(IR, (ir & 0xF0))
xeon011 0:4f25c0dc00f7 1336
xeon011 0:4f25c0dc00f7 1337 /**
xeon011 0:4f25c0dc00f7 1338 * @ingroup Common_register_access_function
xeon011 0:4f25c0dc00f7 1339 * @brief Get @ref IR register
xeon011 0:4f25c0dc00f7 1340 * @return uint8_t. Value of @ref IR register.
xeon011 0:4f25c0dc00f7 1341 * @sa setIR()
xeon011 0:4f25c0dc00f7 1342 */
xeon011 0:4f25c0dc00f7 1343 #define getIR() \
xeon011 0:4f25c0dc00f7 1344 (WIZCHIP_READ(IR) & 0xF0)
xeon011 0:4f25c0dc00f7 1345 /**
xeon011 0:4f25c0dc00f7 1346 * @ingroup Common_register_access_function
xeon011 0:4f25c0dc00f7 1347 * @brief Set @ref IMR register
xeon011 0:4f25c0dc00f7 1348 * @param (uint8_t)imr Value to set @ref IMR register.
xeon011 0:4f25c0dc00f7 1349 * @sa getIMR()
xeon011 0:4f25c0dc00f7 1350 */
xeon011 0:4f25c0dc00f7 1351 #define setIMR(imr) \
xeon011 0:4f25c0dc00f7 1352 WIZCHIP_WRITE(IMR, imr)
xeon011 0:4f25c0dc00f7 1353
xeon011 0:4f25c0dc00f7 1354 /**
xeon011 0:4f25c0dc00f7 1355 * @ingroup Common_register_access_function
xeon011 0:4f25c0dc00f7 1356 * @brief Get @ref IMR register
xeon011 0:4f25c0dc00f7 1357 * @return uint8_t. Value of @ref IMR register.
xeon011 0:4f25c0dc00f7 1358 * @sa setIMR()
xeon011 0:4f25c0dc00f7 1359 */
xeon011 0:4f25c0dc00f7 1360 #define getIMR() \
xeon011 0:4f25c0dc00f7 1361 WIZCHIP_READ(IMR)
xeon011 0:4f25c0dc00f7 1362
xeon011 0:4f25c0dc00f7 1363
xeon011 0:4f25c0dc00f7 1364 /**
xeon011 0:4f25c0dc00f7 1365 * @ingroup Common_register_access_function
xeon011 0:4f25c0dc00f7 1366 * @brief Set @ref SIR register
xeon011 0:4f25c0dc00f7 1367 * @param (uint8_t)sir Value to set @ref SIR register.
xeon011 0:4f25c0dc00f7 1368 * @sa getSIR()
xeon011 0:4f25c0dc00f7 1369 */
xeon011 0:4f25c0dc00f7 1370 #define setSIR(sir) \
xeon011 0:4f25c0dc00f7 1371 WIZCHIP_WRITE(SIR, sir)
xeon011 0:4f25c0dc00f7 1372
xeon011 0:4f25c0dc00f7 1373 /**
xeon011 0:4f25c0dc00f7 1374 * @ingroup Common_register_access_function
xeon011 0:4f25c0dc00f7 1375 * @brief Get @ref SIR register
xeon011 0:4f25c0dc00f7 1376 * @return uint8_t. Value of @ref SIR register.
xeon011 0:4f25c0dc00f7 1377 * @sa setSIR()
xeon011 0:4f25c0dc00f7 1378 */
xeon011 0:4f25c0dc00f7 1379 #define getSIR() \
xeon011 0:4f25c0dc00f7 1380 WIZCHIP_READ(SIR)
xeon011 0:4f25c0dc00f7 1381 /**
xeon011 0:4f25c0dc00f7 1382 * @ingroup Common_register_access_function
xeon011 0:4f25c0dc00f7 1383 * @brief Set @ref SIMR register
xeon011 0:4f25c0dc00f7 1384 * @param (uint8_t)simr Value to set @ref SIMR register.
xeon011 0:4f25c0dc00f7 1385 * @sa getSIMR()
xeon011 0:4f25c0dc00f7 1386 */
xeon011 0:4f25c0dc00f7 1387 #define setSIMR(simr) \
xeon011 0:4f25c0dc00f7 1388 WIZCHIP_WRITE(SIMR, simr)
xeon011 0:4f25c0dc00f7 1389
xeon011 0:4f25c0dc00f7 1390 /**
xeon011 0:4f25c0dc00f7 1391 * @ingroup Common_register_access_function
xeon011 0:4f25c0dc00f7 1392 * @brief Get @ref SIMR register
xeon011 0:4f25c0dc00f7 1393 * @return uint8_t. Value of @ref SIMR register.
xeon011 0:4f25c0dc00f7 1394 * @sa setSIMR()
xeon011 0:4f25c0dc00f7 1395 */
xeon011 0:4f25c0dc00f7 1396 #define getSIMR() \
xeon011 0:4f25c0dc00f7 1397 WIZCHIP_READ(SIMR)
xeon011 0:4f25c0dc00f7 1398
xeon011 0:4f25c0dc00f7 1399 /**
xeon011 0:4f25c0dc00f7 1400 * @ingroup Common_register_access_function
xeon011 0:4f25c0dc00f7 1401 * @brief Set @ref RTR register
xeon011 0:4f25c0dc00f7 1402 * @param (uint16_t)rtr Value to set @ref RTR register.
xeon011 0:4f25c0dc00f7 1403 * @sa getRTR()
xeon011 0:4f25c0dc00f7 1404 */
xeon011 0:4f25c0dc00f7 1405 #define setRTR(rtr) {\
xeon011 0:4f25c0dc00f7 1406 WIZCHIP_WRITE(RTR, (uint8_t)(rtr >> 8)); \
xeon011 0:4f25c0dc00f7 1407 WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(RTR,1), (uint8_t) rtr); \
xeon011 0:4f25c0dc00f7 1408 }
xeon011 0:4f25c0dc00f7 1409
xeon011 0:4f25c0dc00f7 1410 /**
xeon011 0:4f25c0dc00f7 1411 * @ingroup Common_register_access_function
xeon011 0:4f25c0dc00f7 1412 * @brief Get @ref RTR register
xeon011 0:4f25c0dc00f7 1413 * @return uint16_t. Value of @ref RTR register.
xeon011 0:4f25c0dc00f7 1414 * @sa setRTR()
xeon011 0:4f25c0dc00f7 1415 */
xeon011 0:4f25c0dc00f7 1416 #define getRTR() \
xeon011 0:4f25c0dc00f7 1417 ((WIZCHIP_READ(RTR) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(RTR,1)))
xeon011 0:4f25c0dc00f7 1418
xeon011 0:4f25c0dc00f7 1419 /**
xeon011 0:4f25c0dc00f7 1420 * @ingroup Common_register_access_function
xeon011 0:4f25c0dc00f7 1421 * @brief Set @ref RCR register
xeon011 0:4f25c0dc00f7 1422 * @param (uint8_t)rcr Value to set @ref RCR register.
xeon011 0:4f25c0dc00f7 1423 * @sa getRCR()
xeon011 0:4f25c0dc00f7 1424 */
xeon011 0:4f25c0dc00f7 1425 #define setRCR(rcr) \
xeon011 0:4f25c0dc00f7 1426 WIZCHIP_WRITE(RCR, rcr)
xeon011 0:4f25c0dc00f7 1427
xeon011 0:4f25c0dc00f7 1428 /**
xeon011 0:4f25c0dc00f7 1429 * @ingroup Common_register_access_function
xeon011 0:4f25c0dc00f7 1430 * @brief Get @ref RCR register
xeon011 0:4f25c0dc00f7 1431 * @return uint8_t. Value of @ref RCR register.
xeon011 0:4f25c0dc00f7 1432 * @sa setRCR()
xeon011 0:4f25c0dc00f7 1433 */
xeon011 0:4f25c0dc00f7 1434 #define getRCR() \
xeon011 0:4f25c0dc00f7 1435 WIZCHIP_READ(RCR)
xeon011 0:4f25c0dc00f7 1436
xeon011 0:4f25c0dc00f7 1437 //================================================== test done ===========================================================
xeon011 0:4f25c0dc00f7 1438
xeon011 0:4f25c0dc00f7 1439 /**
xeon011 0:4f25c0dc00f7 1440 * @ingroup Common_register_access_function
xeon011 0:4f25c0dc00f7 1441 * @brief Set @ref PTIMER register
xeon011 0:4f25c0dc00f7 1442 * @param (uint8_t)ptimer Value to set @ref PTIMER register.
xeon011 0:4f25c0dc00f7 1443 * @sa getPTIMER()
xeon011 0:4f25c0dc00f7 1444 */
xeon011 0:4f25c0dc00f7 1445 #define setPTIMER(ptimer) \
xeon011 0:4f25c0dc00f7 1446 WIZCHIP_WRITE(PTIMER, ptimer)
xeon011 0:4f25c0dc00f7 1447
xeon011 0:4f25c0dc00f7 1448 /**
xeon011 0:4f25c0dc00f7 1449 * @ingroup Common_register_access_function
xeon011 0:4f25c0dc00f7 1450 * @brief Get @ref PTIMER register
xeon011 0:4f25c0dc00f7 1451 * @return uint8_t. Value of @ref PTIMER register.
xeon011 0:4f25c0dc00f7 1452 * @sa setPTIMER()
xeon011 0:4f25c0dc00f7 1453 */
xeon011 0:4f25c0dc00f7 1454 #define getPTIMER() \
xeon011 0:4f25c0dc00f7 1455 WIZCHIP_READ(PTIMER)
xeon011 0:4f25c0dc00f7 1456
xeon011 0:4f25c0dc00f7 1457 /**
xeon011 0:4f25c0dc00f7 1458 * @ingroup Common_register_access_function
xeon011 0:4f25c0dc00f7 1459 * @brief Set @ref PMAGIC register
xeon011 0:4f25c0dc00f7 1460 * @param (uint8_t)pmagic Value to set @ref PMAGIC register.
xeon011 0:4f25c0dc00f7 1461 * @sa getPMAGIC()
xeon011 0:4f25c0dc00f7 1462 */
xeon011 0:4f25c0dc00f7 1463 #define setPMAGIC(pmagic) \
xeon011 0:4f25c0dc00f7 1464 WIZCHIP_WRITE(PMAGIC, pmagic)
xeon011 0:4f25c0dc00f7 1465
xeon011 0:4f25c0dc00f7 1466 /**
xeon011 0:4f25c0dc00f7 1467 * @ingroup Common_register_access_function
xeon011 0:4f25c0dc00f7 1468 * @brief Get @ref PMAGIC register
xeon011 0:4f25c0dc00f7 1469 * @return uint8_t. Value of @ref PMAGIC register.
xeon011 0:4f25c0dc00f7 1470 * @sa setPMAGIC()
xeon011 0:4f25c0dc00f7 1471 */
xeon011 0:4f25c0dc00f7 1472 #define getPMAGIC() \
xeon011 0:4f25c0dc00f7 1473 WIZCHIP_READ(PMAGIC)
xeon011 0:4f25c0dc00f7 1474
xeon011 0:4f25c0dc00f7 1475 /**
xeon011 0:4f25c0dc00f7 1476 * @ingroup Common_register_access_function
xeon011 0:4f25c0dc00f7 1477 * @brief Set PHAR address
xeon011 0:4f25c0dc00f7 1478 * @param (uint8_t*)phar Pointer variable to set PPP destination MAC register address. It should be allocated 6 bytes.
xeon011 0:4f25c0dc00f7 1479 * @sa getPHAR()
xeon011 0:4f25c0dc00f7 1480 */
xeon011 0:4f25c0dc00f7 1481 #define setPHAR(phar) \
xeon011 0:4f25c0dc00f7 1482 WIZCHIP_WRITE_BUF(PHAR, phar, 6)
xeon011 0:4f25c0dc00f7 1483
xeon011 0:4f25c0dc00f7 1484 /**
xeon011 0:4f25c0dc00f7 1485 * @ingroup Common_register_access_function
xeon011 0:4f25c0dc00f7 1486 * @brief Get local IP address
xeon011 0:4f25c0dc00f7 1487 * @param (uint8_t*)phar Pointer variable to PPP destination MAC register address. It should be allocated 6 bytes.
xeon011 0:4f25c0dc00f7 1488 * @sa setPHAR()
xeon011 0:4f25c0dc00f7 1489 */
xeon011 0:4f25c0dc00f7 1490 #define getPHAR(phar) \
xeon011 0:4f25c0dc00f7 1491 WIZCHIP_READ_BUF(PHAR, phar, 6)
xeon011 0:4f25c0dc00f7 1492
xeon011 0:4f25c0dc00f7 1493 /**
xeon011 0:4f25c0dc00f7 1494 * @ingroup Common_register_access_function
xeon011 0:4f25c0dc00f7 1495 * @brief Set @ref PSID register
xeon011 0:4f25c0dc00f7 1496 * @param (uint16_t)psid Value to set @ref PSID register.
xeon011 0:4f25c0dc00f7 1497 * @sa getPSID()
xeon011 0:4f25c0dc00f7 1498 */
xeon011 0:4f25c0dc00f7 1499 #define setPSID(psid) {\
xeon011 0:4f25c0dc00f7 1500 WIZCHIP_WRITE(PSID, (uint8_t)(psid >> 8)); \
xeon011 0:4f25c0dc00f7 1501 WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(PSID,1), (uint8_t) psid); \
xeon011 0:4f25c0dc00f7 1502 }
xeon011 0:4f25c0dc00f7 1503
xeon011 0:4f25c0dc00f7 1504 /**
xeon011 0:4f25c0dc00f7 1505 * @ingroup Common_register_access_function
xeon011 0:4f25c0dc00f7 1506 * @brief Get @ref PSID register
xeon011 0:4f25c0dc00f7 1507 * @return uint16_t. Value of @ref PSID register.
xeon011 0:4f25c0dc00f7 1508 * @sa setPSID()
xeon011 0:4f25c0dc00f7 1509 */
xeon011 0:4f25c0dc00f7 1510 //uint16_t getPSID(void);
xeon011 0:4f25c0dc00f7 1511 #define getPSID() \
xeon011 0:4f25c0dc00f7 1512 ((WIZCHIP_READ(PSID) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(PSID,1)))
xeon011 0:4f25c0dc00f7 1513
xeon011 0:4f25c0dc00f7 1514 /**
xeon011 0:4f25c0dc00f7 1515 * @ingroup Common_register_access_function
xeon011 0:4f25c0dc00f7 1516 * @brief Set @ref PMRU register
xeon011 0:4f25c0dc00f7 1517 * @param (uint16_t)pmru Value to set @ref PMRU register.
xeon011 0:4f25c0dc00f7 1518 * @sa getPMRU()
xeon011 0:4f25c0dc00f7 1519 */
xeon011 0:4f25c0dc00f7 1520 #define setPMRU(pmru) { \
xeon011 0:4f25c0dc00f7 1521 WIZCHIP_WRITE(PMRU, (uint8_t)(pmru>>8)); \
xeon011 0:4f25c0dc00f7 1522 WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(PMRU,1), (uint8_t) pmru); \
xeon011 0:4f25c0dc00f7 1523 }
xeon011 0:4f25c0dc00f7 1524
xeon011 0:4f25c0dc00f7 1525 /**
xeon011 0:4f25c0dc00f7 1526 * @ingroup Common_register_access_function
xeon011 0:4f25c0dc00f7 1527 * @brief Get @ref PMRU register
xeon011 0:4f25c0dc00f7 1528 * @return uint16_t. Value of @ref PMRU register.
xeon011 0:4f25c0dc00f7 1529 * @sa setPMRU()
xeon011 0:4f25c0dc00f7 1530 */
xeon011 0:4f25c0dc00f7 1531 #define getPMRU() \
xeon011 0:4f25c0dc00f7 1532 ((WIZCHIP_READ(PMRU) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(PMRU,1)))
xeon011 0:4f25c0dc00f7 1533
xeon011 0:4f25c0dc00f7 1534 /**
xeon011 0:4f25c0dc00f7 1535 * @ingroup Common_register_access_function
xeon011 0:4f25c0dc00f7 1536 * @brief Get unreachable IP address
xeon011 0:4f25c0dc00f7 1537 * @param (uint8_t*)uipr Pointer variable to get unreachable IP address. It should be allocated 4 bytes.
xeon011 0:4f25c0dc00f7 1538 */
xeon011 0:4f25c0dc00f7 1539 #define getUIPR(uipr) \
xeon011 0:4f25c0dc00f7 1540 WIZCHIP_READ_BUF(UIPR,uipr,6)
xeon011 0:4f25c0dc00f7 1541
xeon011 0:4f25c0dc00f7 1542 /**
xeon011 0:4f25c0dc00f7 1543 * @ingroup Common_register_access_function
xeon011 0:4f25c0dc00f7 1544 * @brief Get @ref UPORTR register
xeon011 0:4f25c0dc00f7 1545 * @return uint16_t. Value of @ref UPORTR register.
xeon011 0:4f25c0dc00f7 1546 */
xeon011 0:4f25c0dc00f7 1547 #define getUPORTR() \
xeon011 0:4f25c0dc00f7 1548 ((WIZCHIP_READ(UPORTR) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(UPORTR,1)))
xeon011 0:4f25c0dc00f7 1549
xeon011 0:4f25c0dc00f7 1550 /**
xeon011 0:4f25c0dc00f7 1551 * @ingroup Common_register_access_function
xeon011 0:4f25c0dc00f7 1552 * @brief Set @ref PHYCFGR register
xeon011 0:4f25c0dc00f7 1553 * @param (uint8_t)phycfgr Value to set @ref PHYCFGR register.
xeon011 0:4f25c0dc00f7 1554 * @sa getPHYCFGR()
xeon011 0:4f25c0dc00f7 1555 */
xeon011 0:4f25c0dc00f7 1556 #define setPHYCFGR(phycfgr) \
xeon011 0:4f25c0dc00f7 1557 WIZCHIP_WRITE(PHYCFGR, phycfgr)
xeon011 0:4f25c0dc00f7 1558
xeon011 0:4f25c0dc00f7 1559 /**
xeon011 0:4f25c0dc00f7 1560 * @ingroup Common_register_access_function
xeon011 0:4f25c0dc00f7 1561 * @brief Get @ref PHYCFGR register
xeon011 0:4f25c0dc00f7 1562 * @return uint8_t. Value of @ref PHYCFGR register.
xeon011 0:4f25c0dc00f7 1563 * @sa setPHYCFGR()
xeon011 0:4f25c0dc00f7 1564 */
xeon011 0:4f25c0dc00f7 1565 #define getPHYCFGR() \
xeon011 0:4f25c0dc00f7 1566 WIZCHIP_READ(PHYCFGR)
xeon011 0:4f25c0dc00f7 1567
xeon011 0:4f25c0dc00f7 1568 /**
xeon011 0:4f25c0dc00f7 1569 * @ingroup Common_register_access_function
xeon011 0:4f25c0dc00f7 1570 * @brief Get @ref VERSIONR register
xeon011 0:4f25c0dc00f7 1571 * @return uint8_t. Value of @ref VERSIONR register.
xeon011 0:4f25c0dc00f7 1572 */
xeon011 0:4f25c0dc00f7 1573 #define getVERSIONR() \
xeon011 0:4f25c0dc00f7 1574 WIZCHIP_READ(VERSIONR)
xeon011 0:4f25c0dc00f7 1575
xeon011 0:4f25c0dc00f7 1576 /////////////////////////////////////
xeon011 0:4f25c0dc00f7 1577
xeon011 0:4f25c0dc00f7 1578 ///////////////////////////////////
xeon011 0:4f25c0dc00f7 1579 // Socket N register I/O function //
xeon011 0:4f25c0dc00f7 1580 ///////////////////////////////////
xeon011 0:4f25c0dc00f7 1581 /**
xeon011 0:4f25c0dc00f7 1582 * @ingroup Socket_register_access_function
xeon011 0:4f25c0dc00f7 1583 * @brief Set @ref Sn_MR register
xeon011 0:4f25c0dc00f7 1584 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
xeon011 0:4f25c0dc00f7 1585 * @param (uint8_t)mr Value to set @ref Sn_MR
xeon011 0:4f25c0dc00f7 1586 * @sa getSn_MR()
xeon011 0:4f25c0dc00f7 1587 */
xeon011 0:4f25c0dc00f7 1588 #define setSn_MR(sn, mr) \
xeon011 0:4f25c0dc00f7 1589 WIZCHIP_WRITE(Sn_MR(sn),mr)
xeon011 0:4f25c0dc00f7 1590
xeon011 0:4f25c0dc00f7 1591 /**
xeon011 0:4f25c0dc00f7 1592 * @ingroup Socket_register_access_function
xeon011 0:4f25c0dc00f7 1593 * @brief Get @ref Sn_MR register
xeon011 0:4f25c0dc00f7 1594 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
xeon011 0:4f25c0dc00f7 1595 * @return uint8_t. Value of @ref Sn_MR.
xeon011 0:4f25c0dc00f7 1596 * @sa setSn_MR()
xeon011 0:4f25c0dc00f7 1597 */
xeon011 0:4f25c0dc00f7 1598 #define getSn_MR(sn) \
xeon011 0:4f25c0dc00f7 1599 WIZCHIP_READ(Sn_MR(sn))
xeon011 0:4f25c0dc00f7 1600
xeon011 0:4f25c0dc00f7 1601 /**
xeon011 0:4f25c0dc00f7 1602 * @ingroup Socket_register_access_function
xeon011 0:4f25c0dc00f7 1603 * @brief Set @ref Sn_CR register
xeon011 0:4f25c0dc00f7 1604 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
xeon011 0:4f25c0dc00f7 1605 * @param (uint8_t)cr Value to set @ref Sn_CR
xeon011 0:4f25c0dc00f7 1606 * @sa getSn_CR()
xeon011 0:4f25c0dc00f7 1607 */
xeon011 0:4f25c0dc00f7 1608 #define setSn_CR(sn, cr) \
xeon011 0:4f25c0dc00f7 1609 WIZCHIP_WRITE(Sn_CR(sn), cr)
xeon011 0:4f25c0dc00f7 1610
xeon011 0:4f25c0dc00f7 1611 /**
xeon011 0:4f25c0dc00f7 1612 * @ingroup Socket_register_access_function
xeon011 0:4f25c0dc00f7 1613 * @brief Get @ref Sn_CR register
xeon011 0:4f25c0dc00f7 1614 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
xeon011 0:4f25c0dc00f7 1615 * @return uint8_t. Value of @ref Sn_CR.
xeon011 0:4f25c0dc00f7 1616 * @sa setSn_CR()
xeon011 0:4f25c0dc00f7 1617 */
xeon011 0:4f25c0dc00f7 1618 #define getSn_CR(sn) \
xeon011 0:4f25c0dc00f7 1619 WIZCHIP_READ(Sn_CR(sn))
xeon011 0:4f25c0dc00f7 1620
xeon011 0:4f25c0dc00f7 1621 /**
xeon011 0:4f25c0dc00f7 1622 * @ingroup Socket_register_access_function
xeon011 0:4f25c0dc00f7 1623 * @brief Set @ref Sn_IR register
xeon011 0:4f25c0dc00f7 1624 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
xeon011 0:4f25c0dc00f7 1625 * @param (uint8_t)ir Value to set @ref Sn_IR
xeon011 0:4f25c0dc00f7 1626 * @sa getSn_IR()
xeon011 0:4f25c0dc00f7 1627 */
xeon011 0:4f25c0dc00f7 1628 #define setSn_IR(sn, ir) \
xeon011 0:4f25c0dc00f7 1629 WIZCHIP_WRITE(Sn_IR(sn), (ir & 0x1F))
xeon011 0:4f25c0dc00f7 1630
xeon011 0:4f25c0dc00f7 1631 /**
xeon011 0:4f25c0dc00f7 1632 * @ingroup Socket_register_access_function
xeon011 0:4f25c0dc00f7 1633 * @brief Get @ref Sn_IR register
xeon011 0:4f25c0dc00f7 1634 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
xeon011 0:4f25c0dc00f7 1635 * @return uint8_t. Value of @ref Sn_IR.
xeon011 0:4f25c0dc00f7 1636 * @sa setSn_IR()
xeon011 0:4f25c0dc00f7 1637 */
xeon011 0:4f25c0dc00f7 1638 #define getSn_IR(sn) \
xeon011 0:4f25c0dc00f7 1639 (WIZCHIP_READ(Sn_IR(sn)) & 0x1F)
xeon011 0:4f25c0dc00f7 1640
xeon011 0:4f25c0dc00f7 1641 /**
xeon011 0:4f25c0dc00f7 1642 * @ingroup Socket_register_access_function
xeon011 0:4f25c0dc00f7 1643 * @brief Set @ref Sn_IMR register
xeon011 0:4f25c0dc00f7 1644 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
xeon011 0:4f25c0dc00f7 1645 * @param (uint8_t)imr Value to set @ref Sn_IMR
xeon011 0:4f25c0dc00f7 1646 * @sa getSn_IMR()
xeon011 0:4f25c0dc00f7 1647 */
xeon011 0:4f25c0dc00f7 1648 #define setSn_IMR(sn, imr) \
xeon011 0:4f25c0dc00f7 1649 WIZCHIP_WRITE(Sn_IMR(sn), (imr & 0x1F))
xeon011 0:4f25c0dc00f7 1650
xeon011 0:4f25c0dc00f7 1651 /**
xeon011 0:4f25c0dc00f7 1652 * @ingroup Socket_register_access_function
xeon011 0:4f25c0dc00f7 1653 * @brief Get @ref Sn_IMR register
xeon011 0:4f25c0dc00f7 1654 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
xeon011 0:4f25c0dc00f7 1655 * @return uint8_t. Value of @ref Sn_IMR.
xeon011 0:4f25c0dc00f7 1656 * @sa setSn_IMR()
xeon011 0:4f25c0dc00f7 1657 */
xeon011 0:4f25c0dc00f7 1658 #define getSn_IMR(sn) \
xeon011 0:4f25c0dc00f7 1659 (WIZCHIP_READ(Sn_IMR(sn)) & 0x1F)
xeon011 0:4f25c0dc00f7 1660
xeon011 0:4f25c0dc00f7 1661 /**
xeon011 0:4f25c0dc00f7 1662 * @ingroup Socket_register_access_function
xeon011 0:4f25c0dc00f7 1663 * @brief Get @ref Sn_SR register
xeon011 0:4f25c0dc00f7 1664 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
xeon011 0:4f25c0dc00f7 1665 * @return uint8_t. Value of @ref Sn_SR.
xeon011 0:4f25c0dc00f7 1666 */
xeon011 0:4f25c0dc00f7 1667 #define getSn_SR(sn) \
xeon011 0:4f25c0dc00f7 1668 WIZCHIP_READ(Sn_SR(sn))
xeon011 0:4f25c0dc00f7 1669
xeon011 0:4f25c0dc00f7 1670 /**
xeon011 0:4f25c0dc00f7 1671 * @ingroup Socket_register_access_function
xeon011 0:4f25c0dc00f7 1672 * @brief Set @ref Sn_PORT register
xeon011 0:4f25c0dc00f7 1673 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
xeon011 0:4f25c0dc00f7 1674 * @param (uint16_t)port Value to set @ref Sn_PORT.
xeon011 0:4f25c0dc00f7 1675 * @sa getSn_PORT()
xeon011 0:4f25c0dc00f7 1676 */
xeon011 0:4f25c0dc00f7 1677 #define setSn_PORT(sn, port) { \
xeon011 0:4f25c0dc00f7 1678 WIZCHIP_WRITE(Sn_PORT(sn), (uint8_t)(port >> 8)); \
xeon011 0:4f25c0dc00f7 1679 WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_PORT(sn),1), (uint8_t) port); \
xeon011 0:4f25c0dc00f7 1680 }
xeon011 0:4f25c0dc00f7 1681
xeon011 0:4f25c0dc00f7 1682 /**
xeon011 0:4f25c0dc00f7 1683 * @ingroup Socket_register_access_function
xeon011 0:4f25c0dc00f7 1684 * @brief Get @ref Sn_PORT register
xeon011 0:4f25c0dc00f7 1685 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
xeon011 0:4f25c0dc00f7 1686 * @return uint16_t. Value of @ref Sn_PORT.
xeon011 0:4f25c0dc00f7 1687 * @sa setSn_PORT()
xeon011 0:4f25c0dc00f7 1688 */
xeon011 0:4f25c0dc00f7 1689 #define getSn_PORT(sn) \
xeon011 0:4f25c0dc00f7 1690 ((WIZCHIP_READ(Sn_PORT(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_PORT(sn),1)))
xeon011 0:4f25c0dc00f7 1691
xeon011 0:4f25c0dc00f7 1692 /**
xeon011 0:4f25c0dc00f7 1693 * @ingroup Socket_register_access_function
xeon011 0:4f25c0dc00f7 1694 * @brief Set @ref Sn_DHAR register
xeon011 0:4f25c0dc00f7 1695 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
xeon011 0:4f25c0dc00f7 1696 * @param (uint8_t*)dhar Pointer variable to set socket n destination hardware address. It should be allocated 6 bytes.
xeon011 0:4f25c0dc00f7 1697 * @sa getSn_DHAR()
xeon011 0:4f25c0dc00f7 1698 */
xeon011 0:4f25c0dc00f7 1699 #define setSn_DHAR(sn, dhar) \
xeon011 0:4f25c0dc00f7 1700 WIZCHIP_WRITE_BUF(Sn_DHAR(sn), dhar, 6)
xeon011 0:4f25c0dc00f7 1701
xeon011 0:4f25c0dc00f7 1702 /**
xeon011 0:4f25c0dc00f7 1703 * @ingroup Socket_register_access_function
xeon011 0:4f25c0dc00f7 1704 * @brief Get @ref Sn_MR register
xeon011 0:4f25c0dc00f7 1705 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
xeon011 0:4f25c0dc00f7 1706 * @param (uint8_t*)dhar Pointer variable to get socket n destination hardware address. It should be allocated 6 bytes.
xeon011 0:4f25c0dc00f7 1707 * @sa setSn_DHAR()
xeon011 0:4f25c0dc00f7 1708 */
xeon011 0:4f25c0dc00f7 1709 #define getSn_DHAR(sn, dhar) \
xeon011 0:4f25c0dc00f7 1710 WIZCHIP_READ_BUF(Sn_DHAR(sn), dhar, 6)
xeon011 0:4f25c0dc00f7 1711
xeon011 0:4f25c0dc00f7 1712 /**
xeon011 0:4f25c0dc00f7 1713 * @ingroup Socket_register_access_function
xeon011 0:4f25c0dc00f7 1714 * @brief Set @ref Sn_DIPR register
xeon011 0:4f25c0dc00f7 1715 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
xeon011 0:4f25c0dc00f7 1716 * @param (uint8_t*)dipr Pointer variable to set socket n destination IP address. It should be allocated 4 bytes.
xeon011 0:4f25c0dc00f7 1717 * @sa getSn_DIPR()
xeon011 0:4f25c0dc00f7 1718 */
xeon011 0:4f25c0dc00f7 1719 #define setSn_DIPR(sn, dipr) \
xeon011 0:4f25c0dc00f7 1720 WIZCHIP_WRITE_BUF(Sn_DIPR(sn), dipr, 4)
xeon011 0:4f25c0dc00f7 1721
xeon011 0:4f25c0dc00f7 1722 /**
xeon011 0:4f25c0dc00f7 1723 * @ingroup Socket_register_access_function
xeon011 0:4f25c0dc00f7 1724 * @brief Get @ref Sn_DIPR register
xeon011 0:4f25c0dc00f7 1725 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
xeon011 0:4f25c0dc00f7 1726 * @param (uint8_t*)dipr Pointer variable to get socket n destination IP address. It should be allocated 4 bytes.
xeon011 0:4f25c0dc00f7 1727 * @sa SetSn_DIPR()
xeon011 0:4f25c0dc00f7 1728 */
xeon011 0:4f25c0dc00f7 1729 #define getSn_DIPR(sn, dipr) \
xeon011 0:4f25c0dc00f7 1730 WIZCHIP_READ_BUF(Sn_DIPR(sn), dipr, 4)
xeon011 0:4f25c0dc00f7 1731
xeon011 0:4f25c0dc00f7 1732 /**
xeon011 0:4f25c0dc00f7 1733 * @ingroup Socket_register_access_function
xeon011 0:4f25c0dc00f7 1734 * @brief Set @ref Sn_DPORT register
xeon011 0:4f25c0dc00f7 1735 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
xeon011 0:4f25c0dc00f7 1736 * @param (uint16_t)dport Value to set @ref Sn_DPORT
xeon011 0:4f25c0dc00f7 1737 * @sa getSn_DPORT()
xeon011 0:4f25c0dc00f7 1738 */
xeon011 0:4f25c0dc00f7 1739 #define setSn_DPORT(sn, dport) { \
xeon011 0:4f25c0dc00f7 1740 WIZCHIP_WRITE(Sn_DPORT(sn), (uint8_t) (dport>>8)); \
xeon011 0:4f25c0dc00f7 1741 WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_DPORT(sn),1), (uint8_t) dport); \
xeon011 0:4f25c0dc00f7 1742 }
xeon011 0:4f25c0dc00f7 1743
xeon011 0:4f25c0dc00f7 1744 /**
xeon011 0:4f25c0dc00f7 1745 * @ingroup Socket_register_access_function
xeon011 0:4f25c0dc00f7 1746 * @brief Get @ref Sn_DPORT register
xeon011 0:4f25c0dc00f7 1747 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
xeon011 0:4f25c0dc00f7 1748 * @return uint16_t. Value of @ref Sn_DPORT.
xeon011 0:4f25c0dc00f7 1749 * @sa setSn_DPORT()
xeon011 0:4f25c0dc00f7 1750 */
xeon011 0:4f25c0dc00f7 1751 #define getSn_DPORT(sn) \
xeon011 0:4f25c0dc00f7 1752 ((WIZCHIP_READ(Sn_DPORT(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_DPORT(sn),1)))
xeon011 0:4f25c0dc00f7 1753
xeon011 0:4f25c0dc00f7 1754 /**
xeon011 0:4f25c0dc00f7 1755 * @ingroup Socket_register_access_function
xeon011 0:4f25c0dc00f7 1756 * @brief Set @ref Sn_MSSR register
xeon011 0:4f25c0dc00f7 1757 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
xeon011 0:4f25c0dc00f7 1758 * @param (uint16_t)mss Value to set @ref Sn_MSSR
xeon011 0:4f25c0dc00f7 1759 * @sa setSn_MSSR()
xeon011 0:4f25c0dc00f7 1760 */
xeon011 0:4f25c0dc00f7 1761 #define setSn_MSSR(sn, mss) { \
xeon011 0:4f25c0dc00f7 1762 WIZCHIP_WRITE(Sn_MSSR(sn), (uint8_t)(mss>>8)); \
xeon011 0:4f25c0dc00f7 1763 WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_MSSR(sn),1), (uint8_t) mss); \
xeon011 0:4f25c0dc00f7 1764 }
xeon011 0:4f25c0dc00f7 1765
xeon011 0:4f25c0dc00f7 1766 /**
xeon011 0:4f25c0dc00f7 1767 * @ingroup Socket_register_access_function
xeon011 0:4f25c0dc00f7 1768 * @brief Get @ref Sn_MSSR register
xeon011 0:4f25c0dc00f7 1769 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
xeon011 0:4f25c0dc00f7 1770 * @return uint16_t. Value of @ref Sn_MSSR.
xeon011 0:4f25c0dc00f7 1771 * @sa setSn_MSSR()
xeon011 0:4f25c0dc00f7 1772 */
xeon011 0:4f25c0dc00f7 1773 #define getSn_MSSR(sn) \
xeon011 0:4f25c0dc00f7 1774 ((WIZCHIP_READ(Sn_MSSR(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_MSSR(sn),1)))
xeon011 0:4f25c0dc00f7 1775
xeon011 0:4f25c0dc00f7 1776 /**
xeon011 0:4f25c0dc00f7 1777 * @ingroup Socket_register_access_function
xeon011 0:4f25c0dc00f7 1778 * @brief Set @ref Sn_TOS register
xeon011 0:4f25c0dc00f7 1779 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
xeon011 0:4f25c0dc00f7 1780 * @param (uint8_t)tos Value to set @ref Sn_TOS
xeon011 0:4f25c0dc00f7 1781 * @sa getSn_TOS()
xeon011 0:4f25c0dc00f7 1782 */
xeon011 0:4f25c0dc00f7 1783 #define setSn_TOS(sn, tos) \
xeon011 0:4f25c0dc00f7 1784 WIZCHIP_WRITE(Sn_TOS(sn), tos)
xeon011 0:4f25c0dc00f7 1785
xeon011 0:4f25c0dc00f7 1786 /**
xeon011 0:4f25c0dc00f7 1787 * @ingroup Socket_register_access_function
xeon011 0:4f25c0dc00f7 1788 * @brief Get @ref Sn_TOS register
xeon011 0:4f25c0dc00f7 1789 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
xeon011 0:4f25c0dc00f7 1790 * @return uint8_t. Value of Sn_TOS.
xeon011 0:4f25c0dc00f7 1791 * @sa setSn_TOS()
xeon011 0:4f25c0dc00f7 1792 */
xeon011 0:4f25c0dc00f7 1793 #define getSn_TOS(sn) \
xeon011 0:4f25c0dc00f7 1794 WIZCHIP_READ(Sn_TOS(sn))
xeon011 0:4f25c0dc00f7 1795
xeon011 0:4f25c0dc00f7 1796 /**
xeon011 0:4f25c0dc00f7 1797 * @ingroup Socket_register_access_function
xeon011 0:4f25c0dc00f7 1798 * @brief Set @ref Sn_TTL register
xeon011 0:4f25c0dc00f7 1799 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
xeon011 0:4f25c0dc00f7 1800 * @param (uint8_t)ttl Value to set @ref Sn_TTL
xeon011 0:4f25c0dc00f7 1801 * @sa getSn_TTL()
xeon011 0:4f25c0dc00f7 1802 */
xeon011 0:4f25c0dc00f7 1803 #define setSn_TTL(sn, ttl) \
xeon011 0:4f25c0dc00f7 1804 WIZCHIP_WRITE(Sn_TTL(sn), ttl)
xeon011 0:4f25c0dc00f7 1805
xeon011 0:4f25c0dc00f7 1806
xeon011 0:4f25c0dc00f7 1807 /**
xeon011 0:4f25c0dc00f7 1808 * @ingroup Socket_register_access_function
xeon011 0:4f25c0dc00f7 1809 * @brief Get @ref Sn_TTL register
xeon011 0:4f25c0dc00f7 1810 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
xeon011 0:4f25c0dc00f7 1811 * @return uint8_t. Value of @ref Sn_TTL.
xeon011 0:4f25c0dc00f7 1812 * @sa setSn_TTL()
xeon011 0:4f25c0dc00f7 1813 */
xeon011 0:4f25c0dc00f7 1814 #define getSn_TTL(sn) \
xeon011 0:4f25c0dc00f7 1815 WIZCHIP_READ(Sn_TTL(sn))
xeon011 0:4f25c0dc00f7 1816
xeon011 0:4f25c0dc00f7 1817
xeon011 0:4f25c0dc00f7 1818 /**
xeon011 0:4f25c0dc00f7 1819 * @ingroup Socket_register_access_function
xeon011 0:4f25c0dc00f7 1820 * @brief Set @ref Sn_RXBUF_SIZE register
xeon011 0:4f25c0dc00f7 1821 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
xeon011 0:4f25c0dc00f7 1822 * @param (uint8_t)rxbufsize Value to set @ref Sn_RXBUF_SIZE
xeon011 0:4f25c0dc00f7 1823 * @sa getSn_RXBUF_SIZE()
xeon011 0:4f25c0dc00f7 1824 */
xeon011 0:4f25c0dc00f7 1825 #define setSn_RXBUF_SIZE(sn, rxbufsize) \
xeon011 0:4f25c0dc00f7 1826 WIZCHIP_WRITE(Sn_RXBUF_SIZE(sn),rxbufsize)
xeon011 0:4f25c0dc00f7 1827
xeon011 0:4f25c0dc00f7 1828
xeon011 0:4f25c0dc00f7 1829 /**
xeon011 0:4f25c0dc00f7 1830 * @ingroup Socket_register_access_function
xeon011 0:4f25c0dc00f7 1831 * @brief Get @ref Sn_RXBUF_SIZE register
xeon011 0:4f25c0dc00f7 1832 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
xeon011 0:4f25c0dc00f7 1833 * @return uint8_t. Value of @ref Sn_RXBUF_SIZE.
xeon011 0:4f25c0dc00f7 1834 * @sa setSn_RXBUF_SIZE()
xeon011 0:4f25c0dc00f7 1835 */
xeon011 0:4f25c0dc00f7 1836 #define getSn_RXBUF_SIZE(sn) \
xeon011 0:4f25c0dc00f7 1837 WIZCHIP_READ(Sn_RXBUF_SIZE(sn))
xeon011 0:4f25c0dc00f7 1838
xeon011 0:4f25c0dc00f7 1839 /**
xeon011 0:4f25c0dc00f7 1840 * @ingroup Socket_register_access_function
xeon011 0:4f25c0dc00f7 1841 * @brief Set @ref Sn_TXBUF_SIZE register
xeon011 0:4f25c0dc00f7 1842 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
xeon011 0:4f25c0dc00f7 1843 * @param (uint8_t)txbufsize Value to set @ref Sn_TXBUF_SIZE
xeon011 0:4f25c0dc00f7 1844 * @sa getSn_TXBUF_SIZE()
xeon011 0:4f25c0dc00f7 1845 */
xeon011 0:4f25c0dc00f7 1846 #define setSn_TXBUF_SIZE(sn, txbufsize) \
xeon011 0:4f25c0dc00f7 1847 WIZCHIP_WRITE(Sn_TXBUF_SIZE(sn), txbufsize)
xeon011 0:4f25c0dc00f7 1848
xeon011 0:4f25c0dc00f7 1849 /**
xeon011 0:4f25c0dc00f7 1850 * @ingroup Socket_register_access_function
xeon011 0:4f25c0dc00f7 1851 * @brief Get @ref Sn_TXBUF_SIZE register
xeon011 0:4f25c0dc00f7 1852 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
xeon011 0:4f25c0dc00f7 1853 * @return uint8_t. Value of @ref Sn_TXBUF_SIZE.
xeon011 0:4f25c0dc00f7 1854 * @sa setSn_TXBUF_SIZE()
xeon011 0:4f25c0dc00f7 1855 */
xeon011 0:4f25c0dc00f7 1856 #define getSn_TXBUF_SIZE(sn) \
xeon011 0:4f25c0dc00f7 1857 WIZCHIP_READ(Sn_TXBUF_SIZE(sn))
xeon011 0:4f25c0dc00f7 1858
xeon011 0:4f25c0dc00f7 1859 /**
xeon011 0:4f25c0dc00f7 1860 * @ingroup Socket_register_access_function
xeon011 0:4f25c0dc00f7 1861 * @brief Get @ref Sn_TX_FSR register
xeon011 0:4f25c0dc00f7 1862 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
xeon011 0:4f25c0dc00f7 1863 * @return uint16_t. Value of @ref Sn_TX_FSR.
xeon011 0:4f25c0dc00f7 1864 */
xeon011 0:4f25c0dc00f7 1865 uint16_t getSn_TX_FSR(uint8_t sn);
xeon011 0:4f25c0dc00f7 1866
xeon011 0:4f25c0dc00f7 1867 /**
xeon011 0:4f25c0dc00f7 1868 * @ingroup Socket_register_access_function
xeon011 0:4f25c0dc00f7 1869 * @brief Get @ref Sn_TX_RD register
xeon011 0:4f25c0dc00f7 1870 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
xeon011 0:4f25c0dc00f7 1871 * @return uint16_t. Value of @ref Sn_TX_RD.
xeon011 0:4f25c0dc00f7 1872 */
xeon011 0:4f25c0dc00f7 1873 #define getSn_TX_RD(sn) \
xeon011 0:4f25c0dc00f7 1874 ((WIZCHIP_READ(Sn_TX_RD(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_TX_RD(sn),1)))
xeon011 0:4f25c0dc00f7 1875
xeon011 0:4f25c0dc00f7 1876 /**
xeon011 0:4f25c0dc00f7 1877 * @ingroup Socket_register_access_function
xeon011 0:4f25c0dc00f7 1878 * @brief Set @ref Sn_TX_WR register
xeon011 0:4f25c0dc00f7 1879 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
xeon011 0:4f25c0dc00f7 1880 * @param (uint16_t)txwr Value to set @ref Sn_TX_WR
xeon011 0:4f25c0dc00f7 1881 * @sa GetSn_TX_WR()
xeon011 0:4f25c0dc00f7 1882 */
xeon011 0:4f25c0dc00f7 1883 #define setSn_TX_WR(sn, txwr) { \
xeon011 0:4f25c0dc00f7 1884 WIZCHIP_WRITE(Sn_TX_WR(sn), (uint8_t)(txwr>>8)); \
xeon011 0:4f25c0dc00f7 1885 WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_TX_WR(sn),1), (uint8_t) txwr); \
xeon011 0:4f25c0dc00f7 1886 }
xeon011 0:4f25c0dc00f7 1887
xeon011 0:4f25c0dc00f7 1888 /**
xeon011 0:4f25c0dc00f7 1889 * @ingroup Socket_register_access_function
xeon011 0:4f25c0dc00f7 1890 * @brief Get @ref Sn_TX_WR register
xeon011 0:4f25c0dc00f7 1891 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
xeon011 0:4f25c0dc00f7 1892 * @return uint16_t. Value of @ref Sn_TX_WR.
xeon011 0:4f25c0dc00f7 1893 * @sa setSn_TX_WR()
xeon011 0:4f25c0dc00f7 1894 */
xeon011 0:4f25c0dc00f7 1895 #define getSn_TX_WR(sn) \
xeon011 0:4f25c0dc00f7 1896 ((WIZCHIP_READ(Sn_TX_WR(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_TX_WR(sn),1)))
xeon011 0:4f25c0dc00f7 1897
xeon011 0:4f25c0dc00f7 1898
xeon011 0:4f25c0dc00f7 1899 /**
xeon011 0:4f25c0dc00f7 1900 * @ingroup Socket_register_access_function
xeon011 0:4f25c0dc00f7 1901 * @brief Get @ref Sn_RX_RSR register
xeon011 0:4f25c0dc00f7 1902 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
xeon011 0:4f25c0dc00f7 1903 * @return uint16_t. Value of @ref Sn_RX_RSR.
xeon011 0:4f25c0dc00f7 1904 */
xeon011 0:4f25c0dc00f7 1905 uint16_t getSn_RX_RSR(uint8_t sn);
xeon011 0:4f25c0dc00f7 1906
xeon011 0:4f25c0dc00f7 1907
xeon011 0:4f25c0dc00f7 1908 /**
xeon011 0:4f25c0dc00f7 1909 * @ingroup Socket_register_access_function
xeon011 0:4f25c0dc00f7 1910 * @brief Set @ref Sn_RX_RD register
xeon011 0:4f25c0dc00f7 1911 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
xeon011 0:4f25c0dc00f7 1912 * @param (uint16_t)rxrd Value to set @ref Sn_RX_RD
xeon011 0:4f25c0dc00f7 1913 * @sa getSn_RX_RD()
xeon011 0:4f25c0dc00f7 1914 */
xeon011 0:4f25c0dc00f7 1915 #define setSn_RX_RD(sn, rxrd) { \
xeon011 0:4f25c0dc00f7 1916 WIZCHIP_WRITE(Sn_RX_RD(sn), (uint8_t)(rxrd>>8)); \
xeon011 0:4f25c0dc00f7 1917 WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_RX_RD(sn),1), (uint8_t) rxrd); \
xeon011 0:4f25c0dc00f7 1918 }
xeon011 0:4f25c0dc00f7 1919
xeon011 0:4f25c0dc00f7 1920 /**
xeon011 0:4f25c0dc00f7 1921 * @ingroup Socket_register_access_function
xeon011 0:4f25c0dc00f7 1922 * @brief Get @ref Sn_RX_RD register
xeon011 0:4f25c0dc00f7 1923 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
xeon011 0:4f25c0dc00f7 1924 * @regurn uint16_t. Value of @ref Sn_RX_RD.
xeon011 0:4f25c0dc00f7 1925 * @sa setSn_RX_RD()
xeon011 0:4f25c0dc00f7 1926 */
xeon011 0:4f25c0dc00f7 1927 #define getSn_RX_RD(sn) \
xeon011 0:4f25c0dc00f7 1928 ((WIZCHIP_READ(Sn_RX_RD(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_RX_RD(sn),1)))
xeon011 0:4f25c0dc00f7 1929
xeon011 0:4f25c0dc00f7 1930 /**
xeon011 0:4f25c0dc00f7 1931 * @ingroup Socket_register_access_function
xeon011 0:4f25c0dc00f7 1932 * @brief Get @ref Sn_RX_WR register
xeon011 0:4f25c0dc00f7 1933 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
xeon011 0:4f25c0dc00f7 1934 * @return uint16_t. Value of @ref Sn_RX_WR.
xeon011 0:4f25c0dc00f7 1935 */
xeon011 0:4f25c0dc00f7 1936 #define getSn_RX_WR(sn) \
xeon011 0:4f25c0dc00f7 1937 ((WIZCHIP_READ(Sn_RX_WR(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_RX_WR(sn),1)))
xeon011 0:4f25c0dc00f7 1938
xeon011 0:4f25c0dc00f7 1939
xeon011 0:4f25c0dc00f7 1940 /**
xeon011 0:4f25c0dc00f7 1941 * @ingroup Socket_register_access_function
xeon011 0:4f25c0dc00f7 1942 * @brief Set @ref Sn_FRAG register
xeon011 0:4f25c0dc00f7 1943 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
xeon011 0:4f25c0dc00f7 1944 * @param (uint16_t)frag Value to set @ref Sn_FRAG
xeon011 0:4f25c0dc00f7 1945 * @sa getSn_FRAD()
xeon011 0:4f25c0dc00f7 1946 */
xeon011 0:4f25c0dc00f7 1947 #define setSn_FRAG(sn, frag) { \
xeon011 0:4f25c0dc00f7 1948 WIZCHIP_WRITE(Sn_FRAG(sn), (uint8_t)(frag >>8)); \
xeon011 0:4f25c0dc00f7 1949 WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_FRAG(sn),1), (uint8_t) frag); \
xeon011 0:4f25c0dc00f7 1950 }
xeon011 0:4f25c0dc00f7 1951
xeon011 0:4f25c0dc00f7 1952 /**
xeon011 0:4f25c0dc00f7 1953 * @ingroup Socket_register_access_function
xeon011 0:4f25c0dc00f7 1954 * @brief Get @ref Sn_FRAG register
xeon011 0:4f25c0dc00f7 1955 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
xeon011 0:4f25c0dc00f7 1956 * @return uint16_t. Value of @ref Sn_FRAG.
xeon011 0:4f25c0dc00f7 1957 * @sa setSn_FRAG()
xeon011 0:4f25c0dc00f7 1958 */
xeon011 0:4f25c0dc00f7 1959 #define getSn_FRAG(sn) \
xeon011 0:4f25c0dc00f7 1960 ((WIZCHIP_READ(Sn_FRAG(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_FRAG(sn),1)))
xeon011 0:4f25c0dc00f7 1961
xeon011 0:4f25c0dc00f7 1962 /**
xeon011 0:4f25c0dc00f7 1963 * @ingroup Socket_register_access_function
xeon011 0:4f25c0dc00f7 1964 * @brief Set @ref Sn_KPALVTR register
xeon011 0:4f25c0dc00f7 1965 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
xeon011 0:4f25c0dc00f7 1966 * @param (uint8_t)kpalvt Value to set @ref Sn_KPALVTR
xeon011 0:4f25c0dc00f7 1967 * @sa getSn_KPALVTR()
xeon011 0:4f25c0dc00f7 1968 */
xeon011 0:4f25c0dc00f7 1969 #define setSn_KPALVTR(sn, kpalvt) \
xeon011 0:4f25c0dc00f7 1970 WIZCHIP_WRITE(Sn_KPALVTR(sn), kpalvt)
xeon011 0:4f25c0dc00f7 1971
xeon011 0:4f25c0dc00f7 1972 /**
xeon011 0:4f25c0dc00f7 1973 * @ingroup Socket_register_access_function
xeon011 0:4f25c0dc00f7 1974 * @brief Get @ref Sn_KPALVTR register
xeon011 0:4f25c0dc00f7 1975 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
xeon011 0:4f25c0dc00f7 1976 * @return uint8_t. Value of @ref Sn_KPALVTR.
xeon011 0:4f25c0dc00f7 1977 * @sa setSn_KPALVTR()
xeon011 0:4f25c0dc00f7 1978 */
xeon011 0:4f25c0dc00f7 1979 #define getSn_KPALVTR(sn) \
xeon011 0:4f25c0dc00f7 1980 WIZCHIP_READ(Sn_KPALVTR(sn))
xeon011 0:4f25c0dc00f7 1981
xeon011 0:4f25c0dc00f7 1982 //////////////////////////////////////
xeon011 0:4f25c0dc00f7 1983
xeon011 0:4f25c0dc00f7 1984 /////////////////////////////////////
xeon011 0:4f25c0dc00f7 1985 // Sn_TXBUF & Sn_RXBUF IO function //
xeon011 0:4f25c0dc00f7 1986 /////////////////////////////////////
xeon011 0:4f25c0dc00f7 1987 /**
xeon011 0:4f25c0dc00f7 1988 * @brief Gets the max buffer size of socket sn passed as parameter.
xeon011 0:4f25c0dc00f7 1989 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
xeon011 0:4f25c0dc00f7 1990 * @return uint16_t. Value of Socket n RX max buffer size.
xeon011 0:4f25c0dc00f7 1991 */
xeon011 0:4f25c0dc00f7 1992 #define getSn_RxMAX(sn) \
xeon011 0:4f25c0dc00f7 1993 (getSn_RXBUF_SIZE(sn) << 10)
xeon011 0:4f25c0dc00f7 1994
xeon011 0:4f25c0dc00f7 1995 /**
xeon011 0:4f25c0dc00f7 1996 * @brief Gets the max buffer size of socket sn passed as parameters.
xeon011 0:4f25c0dc00f7 1997 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
xeon011 0:4f25c0dc00f7 1998 * @return uint16_t. Value of Socket n TX max buffer size.
xeon011 0:4f25c0dc00f7 1999 */
xeon011 0:4f25c0dc00f7 2000 //uint16_t getSn_TxMAX(uint8_t sn);
xeon011 0:4f25c0dc00f7 2001 #define getSn_TxMAX(sn) \
xeon011 0:4f25c0dc00f7 2002 (getSn_TXBUF_SIZE(sn) << 10)
xeon011 0:4f25c0dc00f7 2003
xeon011 0:4f25c0dc00f7 2004 /**
xeon011 0:4f25c0dc00f7 2005 * @ingroup Basic_IO_function
xeon011 0:4f25c0dc00f7 2006 * @brief It copies data to internal TX memory
xeon011 0:4f25c0dc00f7 2007 *
xeon011 0:4f25c0dc00f7 2008 * @details This function reads the Tx write pointer register and after that,
xeon011 0:4f25c0dc00f7 2009 * it copies the <i>wizdata(pointer buffer)</i> of the length of <i>len(variable)</i> bytes to internal TX memory
xeon011 0:4f25c0dc00f7 2010 * and updates the Tx write pointer register.
xeon011 0:4f25c0dc00f7 2011 * This function is being called by send() and sendto() function also.
xeon011 0:4f25c0dc00f7 2012 *
xeon011 0:4f25c0dc00f7 2013 * @note User should read upper byte first and lower byte later to get proper value.
xeon011 0:4f25c0dc00f7 2014 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
xeon011 0:4f25c0dc00f7 2015 * @param wizdata Pointer buffer to write data
xeon011 0:4f25c0dc00f7 2016 * @param len Data length
xeon011 0:4f25c0dc00f7 2017 * @sa wiz_recv_data()
xeon011 0:4f25c0dc00f7 2018 */
xeon011 0:4f25c0dc00f7 2019 void wiz_send_data(uint8_t sn, uint8_t *wizdata, uint16_t len);
xeon011 0:4f25c0dc00f7 2020
xeon011 0:4f25c0dc00f7 2021 /**
xeon011 0:4f25c0dc00f7 2022 * @ingroup Basic_IO_function
xeon011 0:4f25c0dc00f7 2023 * @brief It copies data to your buffer from internal RX memory
xeon011 0:4f25c0dc00f7 2024 *
xeon011 0:4f25c0dc00f7 2025 * @details This function read the Rx read pointer register and after that,
xeon011 0:4f25c0dc00f7 2026 * it copies the received data from internal RX memory
xeon011 0:4f25c0dc00f7 2027 * to <i>wizdata(pointer variable)</i> of the length of <i>len(variable)</i> bytes.
xeon011 0:4f25c0dc00f7 2028 * This function is being called by recv() also.
xeon011 0:4f25c0dc00f7 2029 *
xeon011 0:4f25c0dc00f7 2030 * @note User should read upper byte first and lower byte later to get proper value.
xeon011 0:4f25c0dc00f7 2031 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
xeon011 0:4f25c0dc00f7 2032 * @param wizdata Pointer buffer to read data
xeon011 0:4f25c0dc00f7 2033 * @param len Data length
xeon011 0:4f25c0dc00f7 2034 * @sa wiz_send_data()
xeon011 0:4f25c0dc00f7 2035 */
xeon011 0:4f25c0dc00f7 2036 void wiz_recv_data(uint8_t sn, uint8_t *wizdata, uint16_t len);
xeon011 0:4f25c0dc00f7 2037
xeon011 0:4f25c0dc00f7 2038 /**
xeon011 0:4f25c0dc00f7 2039 * @ingroup Basic_IO_function
xeon011 0:4f25c0dc00f7 2040 * @brief It discard the received data in RX memory.
xeon011 0:4f25c0dc00f7 2041 * @details It discards the data of the length of <i>len(variable)</i> bytes in internal RX memory.
xeon011 0:4f25c0dc00f7 2042 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
xeon011 0:4f25c0dc00f7 2043 * @param len Data length
xeon011 0:4f25c0dc00f7 2044 */
xeon011 0:4f25c0dc00f7 2045 void wiz_recv_ignore(uint8_t sn, uint16_t len);
xeon011 0:4f25c0dc00f7 2046
xeon011 0:4f25c0dc00f7 2047 #endif // _W5500_H_