Liqun Wu / Mbed 2 deprecated 90418_mbed_controller

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Dependencies:   mbed

i2c_mbed_fpga.cpp@0:be95bfb06686, 2022-01-17 (annotated)

Committer:
wuliqunyy
Date:
Mon Jan 17 13:20:09 2022 +0000
Revision:
0:be95bfb06686
a working non_flat + adc_didt for ehp regulation version

Who changed what in which revision?

UserRevisionLine numberNew contents of line
wuliqunyy 0:be95bfb06686 1 #include "mbed.h"
wuliqunyy 0:be95bfb06686 2 #include "i2c_mbed_fpga.h"
wuliqunyy 0:be95bfb06686 3
wuliqunyy 0:be95bfb06686 4 #define COMM_STATE_I2C_IDLE (1u)
wuliqunyy 0:be95bfb06686 5 #define COMM_STATE_I2C_APPLICATION (2u)
wuliqunyy 0:be95bfb06686 6 #define COMM_STATE_DIRECT_IDLE (4u)
wuliqunyy 0:be95bfb06686 7 #define COMM_STATE_DIRECT_APPLICATION (6u)
wuliqunyy 0:be95bfb06686 8
wuliqunyy 0:be95bfb06686 9 void i2c_mbed_fpga::wait_for_idle_state(void)
wuliqunyy 0:be95bfb06686 10 {
wuliqunyy 0:be95bfb06686 11 int comm_state = 0;
wuliqunyy 0:be95bfb06686 12 do {
wuliqunyy 0:be95bfb06686 13 uint16_t tmp;
wuliqunyy 0:be95bfb06686 14 this->i2c_word_read_simple(I2C_STATE, &tmp);
wuliqunyy 0:be95bfb06686 15 comm_state = (tmp & I2C_STATE_COMM_STATE_MASK) >> I2C_STATE_COMM_STATE_OFFSET;
wuliqunyy 0:be95bfb06686 16 wait_us(500);
wuliqunyy 0:be95bfb06686 17 } while((comm_state != COMM_STATE_I2C_IDLE)&&(comm_state != COMM_STATE_DIRECT_IDLE));
wuliqunyy 0:be95bfb06686 18 }
wuliqunyy 0:be95bfb06686 19
wuliqunyy 0:be95bfb06686 20 void i2c_mbed_fpga::wait_for_application_state(void)
wuliqunyy 0:be95bfb06686 21 {
wuliqunyy 0:be95bfb06686 22 int comm_state = 0;
wuliqunyy 0:be95bfb06686 23 do {
wuliqunyy 0:be95bfb06686 24 uint16_t tmp;
wuliqunyy 0:be95bfb06686 25 this->i2c_word_read_simple(I2C_STATE, &tmp);
wuliqunyy 0:be95bfb06686 26 comm_state = (tmp & I2C_STATE_COMM_STATE_MASK) >> I2C_STATE_COMM_STATE_OFFSET;
wuliqunyy 0:be95bfb06686 27 wait_us(500);
wuliqunyy 0:be95bfb06686 28 } while((comm_state != COMM_STATE_I2C_APPLICATION)&&(comm_state != COMM_STATE_DIRECT_APPLICATION));
wuliqunyy 0:be95bfb06686 29 }
wuliqunyy 0:be95bfb06686 30
wuliqunyy 0:be95bfb06686 31
wuliqunyy 0:be95bfb06686 32
wuliqunyy 0:be95bfb06686 33 /** i2c read from slave DUT using the command interpreter feature
wuliqunyy 0:be95bfb06686 34 * retun 0 on success, otherwise fails
wuliqunyy 0:be95bfb06686 35 *
wuliqunyy 0:be95bfb06686 36 * @param[in] address 16-bit address to read from
wuliqunyy 0:be95bfb06686 37 * @param[out] return value Pointer to the value read at address
wuliqunyy 0:be95bfb06686 38 * @retval 0 Read failed
wuliqunyy 0:be95bfb06686 39 * @retval 1 Read successful
wuliqunyy 0:be95bfb06686 40 */
wuliqunyy 0:be95bfb06686 41 int i2c_mbed_fpga::i2c_word_read_interpreter(uint16_t address, uint16_t* return_value){
wuliqunyy 0:be95bfb06686 42 uint16_t read_value;
wuliqunyy 0:be95bfb06686 43 int busy;
wuliqunyy 0:be95bfb06686 44 int ack = 0;
wuliqunyy 0:be95bfb06686 45 while(i2c_check_busy_flag()) {
wuliqunyy 0:be95bfb06686 46 /* Wait for the busy flag to clear */
wuliqunyy 0:be95bfb06686 47 }
wuliqunyy 0:be95bfb06686 48 ack += this->i2c_word_write_simple(I2C_CMD_INTERPRETER_ADDRESS, (address | 0x1)); /* Write the address with the LSB set to 1 to indicate a read operation */
wuliqunyy 0:be95bfb06686 49 wait_us(100);
wuliqunyy 0:be95bfb06686 50 /* Check if the command is finished by polling the LSB of CMD_INTERPRETER_ADDRESS */
wuliqunyy 0:be95bfb06686 51 do {
wuliqunyy 0:be95bfb06686 52 ack += this->i2c_word_read_simple(I2C_CMD_INTERPRETER_ADDRESS, &read_value);
wuliqunyy 0:be95bfb06686 53 if((read_value & 0x1) == 1u) {
wuliqunyy 0:be95bfb06686 54 busy = true;
wuliqunyy 0:be95bfb06686 55 } else {
wuliqunyy 0:be95bfb06686 56 busy = false;
wuliqunyy 0:be95bfb06686 57 }
wuliqunyy 0:be95bfb06686 58 wait_us(100);
wuliqunyy 0:be95bfb06686 59 }
wuliqunyy 0:be95bfb06686 60 while(busy == true);
wuliqunyy 0:be95bfb06686 61
wuliqunyy 0:be95bfb06686 62 /* We know the read command has finished. Read back the value */
wuliqunyy 0:be95bfb06686 63 ack += this->i2c_word_read_simple(I2C_CMD_INTERPRETER_DATA, &read_value);
wuliqunyy 0:be95bfb06686 64 *return_value = read_value;
wuliqunyy 0:be95bfb06686 65 return (ack == 0) ? 0 : 1;
wuliqunyy 0:be95bfb06686 66 }
wuliqunyy 0:be95bfb06686 67
wuliqunyy 0:be95bfb06686 68
wuliqunyy 0:be95bfb06686 69 bool i2c_mbed_fpga::i2c_check_busy_flag(void){
wuliqunyy 0:be95bfb06686 70 bool retval = true;
wuliqunyy 0:be95bfb06686 71 uint16_t tmp;
wuliqunyy 0:be95bfb06686 72 this->i2c_word_read_simple(I2C_STATUS, &tmp);
wuliqunyy 0:be95bfb06686 73 if((tmp & I2C_STATUS_COMMAND_BUSY_MASK) == 0u) {
wuliqunyy 0:be95bfb06686 74 retval = false;
wuliqunyy 0:be95bfb06686 75 }
wuliqunyy 0:be95bfb06686 76 return retval;
wuliqunyy 0:be95bfb06686 77 }
wuliqunyy 0:be95bfb06686 78
wuliqunyy 0:be95bfb06686 79 /** i2c read from slave DUT
wuliqunyy 0:be95bfb06686 80 * retun 0 on success, otherwise fails
wuliqunyy 0:be95bfb06686 81 *
wuliqunyy 0:be95bfb06686 82 * @param i2c_master specifies the i2c interface
wuliqunyy 0:be95bfb06686 83 * @param word is 4byte, first 2bytes as addr, the rest 2bytes to store data
wuliqunyy 0:be95bfb06686 84 */
wuliqunyy 0:be95bfb06686 85 int i2c_mbed_fpga::i2c_word_read(char *word){
wuliqunyy 0:be95bfb06686 86 int ack = 0;
wuliqunyy 0:be95bfb06686 87 ack = i2c_master.write(I2C_SLAVE_ADDR, word, 1, true); //restart
wuliqunyy 0:be95bfb06686 88 ack += i2c_master.read(I2C_SLAVE_ADDR, word+1, 2, false); //stop bit
wuliqunyy 0:be95bfb06686 89 wait_us(100);
wuliqunyy 0:be95bfb06686 90 return (ack == 0) ? 0 : 1;
wuliqunyy 0:be95bfb06686 91 }
wuliqunyy 0:be95bfb06686 92
wuliqunyy 0:be95bfb06686 93 /** i2c read from slave DUT
wuliqunyy 0:be95bfb06686 94 * retun 0 on success, otherwise fails
wuliqunyy 0:be95bfb06686 95 *
wuliqunyy 0:be95bfb06686 96 * @param i2c_master specifies the i2c interface
wuliqunyy 0:be95bfb06686 97 * @param word is 4byte, first 2bytes as addr, the rest 2bytes to store data
wuliqunyy 0:be95bfb06686 98 */
wuliqunyy 0:be95bfb06686 99 int i2c_mbed_fpga::i2c_word_read_simple(char address, uint16_t* return_value){
wuliqunyy 0:be95bfb06686 100 int ack = 0;
wuliqunyy 0:be95bfb06686 101 char value[2];
wuliqunyy 0:be95bfb06686 102 ack = i2c_master.write(I2C_SLAVE_ADDR, &address, 1, true); //restart
wuliqunyy 0:be95bfb06686 103 ack += i2c_master.read(I2C_SLAVE_ADDR, value, 2, false); //stop bit
wuliqunyy 0:be95bfb06686 104 *return_value = (int)value[1] | ((int)value[0] << 8);
wuliqunyy 0:be95bfb06686 105 wait_us(100);
wuliqunyy 0:be95bfb06686 106 return (ack == 0) ? 0 : 1;
wuliqunyy 0:be95bfb06686 107 }
wuliqunyy 0:be95bfb06686 108
wuliqunyy 0:be95bfb06686 109 /** i2c write to slave DUT
wuliqunyy 0:be95bfb06686 110 * ==> one time write, not read back check
wuliqunyy 0:be95bfb06686 111 *
wuliqunyy 0:be95bfb06686 112 * @param i2c_master specifies the i2c interface
wuliqunyy 0:be95bfb06686 113 * @param word is considered as 4byte char data
wuliqunyy 0:be95bfb06686 114 */
wuliqunyy 0:be95bfb06686 115 int i2c_mbed_fpga::i2c_word_write(char *word){
wuliqunyy 0:be95bfb06686 116 int ack = 0;
wuliqunyy 0:be95bfb06686 117 ack = i2c_master.write(I2C_SLAVE_ADDR, word, 3, false);
wuliqunyy 0:be95bfb06686 118 return ack;
wuliqunyy 0:be95bfb06686 119 }
wuliqunyy 0:be95bfb06686 120
wuliqunyy 0:be95bfb06686 121 /** i2c read from slave DUT
wuliqunyy 0:be95bfb06686 122 * retun 0 on success, otherwise fails
wuliqunyy 0:be95bfb06686 123 *
wuliqunyy 0:be95bfb06686 124 * @param i2c_master specifies the i2c interface
wuliqunyy 0:be95bfb06686 125 * @param word is 4byte, first 2bytes as addr, the rest 2bytes to store data
wuliqunyy 0:be95bfb06686 126 */
wuliqunyy 0:be95bfb06686 127 int i2c_mbed_fpga::i2c_word_write_simple(char address, uint16_t value){
wuliqunyy 0:be95bfb06686 128 int ack = 0;
wuliqunyy 0:be95bfb06686 129 char i2cMessage[3];
wuliqunyy 0:be95bfb06686 130 *(i2cMessage+0) = (char)(address)& 0xff;
wuliqunyy 0:be95bfb06686 131 *(i2cMessage+1) = (char)((value >> 8u) & 0xff);
wuliqunyy 0:be95bfb06686 132 *(i2cMessage+2) = (char)(value & 0xff);
wuliqunyy 0:be95bfb06686 133 ack = i2c_word_write(i2cMessage);
wuliqunyy 0:be95bfb06686 134 wait_us(100);
wuliqunyy 0:be95bfb06686 135 return ack;
wuliqunyy 0:be95bfb06686 136 }
wuliqunyy 0:be95bfb06686 137
wuliqunyy 0:be95bfb06686 138 int i2c_mbed_fpga::i2c_word_write_interpreter(uint16_t address, uint16_t value){
wuliqunyy 0:be95bfb06686 139 uint16_t read_value;
wuliqunyy 0:be95bfb06686 140 int busy;
wuliqunyy 0:be95bfb06686 141 int ack = 0;
wuliqunyy 0:be95bfb06686 142 while(i2c_check_busy_flag()) {
wuliqunyy 0:be95bfb06686 143 /* Wait for the busy flag to clear */
wuliqunyy 0:be95bfb06686 144 }
wuliqunyy 0:be95bfb06686 145 ack += this->i2c_word_write_simple(I2C_CMD_INTERPRETER_DATA, value);
wuliqunyy 0:be95bfb06686 146 ack += this->i2c_word_write_simple(I2C_CMD_INTERPRETER_ADDRESS, (address & 0xFFFE)); /* Write the address with the LSB set to 0 to indicate a write operation */
wuliqunyy 0:be95bfb06686 147 /* Check if the command is finished by polling the LSB of CMD_INTERPRETER_ADDRESS */
wuliqunyy 0:be95bfb06686 148 do {
wuliqunyy 0:be95bfb06686 149 ack += this->i2c_word_read_simple(I2C_CMD_INTERPRETER_ADDRESS, &read_value);
wuliqunyy 0:be95bfb06686 150 if((read_value & 0x1) == 0u) {
wuliqunyy 0:be95bfb06686 151 busy = true;
wuliqunyy 0:be95bfb06686 152 } else {
wuliqunyy 0:be95bfb06686 153 busy = false;
wuliqunyy 0:be95bfb06686 154 }
wuliqunyy 0:be95bfb06686 155 wait_us(100);
wuliqunyy 0:be95bfb06686 156 }
wuliqunyy 0:be95bfb06686 157 while(busy == true);
wuliqunyy 0:be95bfb06686 158 return (ack == 0) ? 0 : 1;
wuliqunyy 0:be95bfb06686 159 }
wuliqunyy 0:be95bfb06686 160
wuliqunyy 0:be95bfb06686 161
wuliqunyy 0:be95bfb06686 162
wuliqunyy 0:be95bfb06686 163 /** i2c enter key to open I2C window (for old releases)
wuliqunyy 0:be95bfb06686 164 */
wuliqunyy 0:be95bfb06686 165 //int i2c_mbed_fpga::i2c_window_open(){
wuliqunyy 0:be95bfb06686 166 // char i2cMessage[3];
wuliqunyy 0:be95bfb06686 167 // *(i2cMessage+0) = (char)(I2C_CUST_ID3)& 0xff;
wuliqunyy 0:be95bfb06686 168 // *(i2cMessage+1) = (char)(0xD0)& 0xff;
wuliqunyy 0:be95bfb06686 169 // *(i2cMessage+2) = (char)(0xD0)& 0xff;
wuliqunyy 0:be95bfb06686 170 // return i2c_word_write(i2cMessage);
wuliqunyy 0:be95bfb06686 171 //}
wuliqunyy 0:be95bfb06686 172
wuliqunyy 0:be95bfb06686 173 /** i2c enter key to Start the motor (for old releases)
wuliqunyy 0:be95bfb06686 174 */
wuliqunyy 0:be95bfb06686 175 //int i2c_mbed_fpga::i2c_motor_start(){
wuliqunyy 0:be95bfb06686 176 // char i2cMessage[3];
wuliqunyy 0:be95bfb06686 177 // *(i2cMessage+0) = (char)(I2C_CUST_ID3)& 0xff;
wuliqunyy 0:be95bfb06686 178 // *(i2cMessage+1) = (char)(0xCA)& 0xff;
wuliqunyy 0:be95bfb06686 179 // *(i2cMessage+2) = (char)(0xFE)& 0xff;
wuliqunyy 0:be95bfb06686 180 // return i2c_word_write(i2cMessage);
wuliqunyy 0:be95bfb06686 181 //}
wuliqunyy 0:be95bfb06686 182
wuliqunyy 0:be95bfb06686 183
wuliqunyy 0:be95bfb06686 184 /** i2c enter key to open I2C configuration mode entry*/
wuliqunyy 0:be95bfb06686 185 int i2c_mbed_fpga::i2c_config_mode_entry(){
wuliqunyy 0:be95bfb06686 186 return i2c_word_write_simple(I2C_COMMAND_CONTROL, 0x1DEA);
wuliqunyy 0:be95bfb06686 187 }
wuliqunyy 0:be95bfb06686 188
wuliqunyy 0:be95bfb06686 189 /** i2c enter MLX key to open I2C MLX configuration mode entry*/
wuliqunyy 0:be95bfb06686 190 int i2c_mbed_fpga::i2c_mlx_mode_entry(){
wuliqunyy 0:be95bfb06686 191 int ack = 0;
wuliqunyy 0:be95bfb06686 192 ack += i2c_word_write_simple(I2C_COMMAND_KEY, 0x65A9);
wuliqunyy 0:be95bfb06686 193 ack += i2c_word_write_simple(I2C_COMMAND_CONTROL, 0x354B);
wuliqunyy 0:be95bfb06686 194 return ack;
wuliqunyy 0:be95bfb06686 195 }
wuliqunyy 0:be95bfb06686 196
wuliqunyy 0:be95bfb06686 197 /** i2c enter key to enter HTOL mode*/
wuliqunyy 0:be95bfb06686 198 int i2c_mbed_fpga::i2c_htol_mode_entry(){
wuliqunyy 0:be95bfb06686 199 int ack = 0;
wuliqunyy 0:be95bfb06686 200 ack += i2c_word_write_simple(I2C_COMMAND_KEY, 0x2BAD);
wuliqunyy 0:be95bfb06686 201 ack += i2c_word_write_simple(I2C_COMMAND_CONTROL, 0xD1E0);
wuliqunyy 0:be95bfb06686 202 return ack;
wuliqunyy 0:be95bfb06686 203 }
wuliqunyy 0:be95bfb06686 204
wuliqunyy 0:be95bfb06686 205 /** i2c ram start up flag set to skip OTP copy */
wuliqunyy 0:be95bfb06686 206 int i2c_mbed_fpga::i2c_skip_app_copy(){
wuliqunyy 0:be95bfb06686 207 return i2c_word_write_simple(I2C_STARTUP_FLAGS_1, 0x0500);
wuliqunyy 0:be95bfb06686 208 }
wuliqunyy 0:be95bfb06686 209
wuliqunyy 0:be95bfb06686 210 /** i2c soft reset */
wuliqunyy 0:be95bfb06686 211 int i2c_mbed_fpga::i2c_soft_reset(){
wuliqunyy 0:be95bfb06686 212 return i2c_word_write_simple(I2C_COMMAND_CONTROL, 0xC1A0);
wuliqunyy 0:be95bfb06686 213 }
wuliqunyy 0:be95bfb06686 214
wuliqunyy 0:be95bfb06686 215 /** i2c to set the 50k PWM*/
wuliqunyy 0:be95bfb06686 216 int i2c_mbed_fpga::i2c_set_50k_pwm(unsigned int pwm50k){
wuliqunyy 0:be95bfb06686 217 nv_gen_ctrl_val &= ~NV_PWM_50K_MASK;
wuliqunyy 0:be95bfb06686 218 nv_gen_ctrl_val |= pwm50k << NV_PWM_50K_OFFSET;
wuliqunyy 0:be95bfb06686 219 return i2c_word_write_simple(I2C_GEN_CTRL, nv_gen_ctrl_val);
wuliqunyy 0:be95bfb06686 220 }
wuliqunyy 0:be95bfb06686 221
wuliqunyy 0:be95bfb06686 222 /** i2c to set the Postion Pulse width*/
wuliqunyy 0:be95bfb06686 223 int i2c_mbed_fpga::i2c_set_position_pulse_width(unsigned int mantisaa_2b, unsigned int exponent_3b){
wuliqunyy 0:be95bfb06686 224 nv_positin_val &= ~NV_POSITION_PULSE_TIME_MASK;
wuliqunyy 0:be95bfb06686 225 nv_positin_val |= ((exponent_3b << 2) | mantisaa_2b) << NV_POSITION_PULSE_TIME_OFFSET;
wuliqunyy 0:be95bfb06686 226 return i2c_word_write_simple(I2C_POSITION, nv_positin_val);
wuliqunyy 0:be95bfb06686 227 }
wuliqunyy 0:be95bfb06686 228
wuliqunyy 0:be95bfb06686 229 /** i2c to set the Postion Flat width */
wuliqunyy 0:be95bfb06686 230 int i2c_mbed_fpga::i2c_set_position_flat(unsigned int mantisaa_2b, unsigned int exponent_3b){
wuliqunyy 0:be95bfb06686 231 nv_positin2_val &= ~NV_POSITION_FLAT_TIME_MASK;
wuliqunyy 0:be95bfb06686 232 nv_positin2_val |= ((exponent_3b << 2) | mantisaa_2b) << NV_POSITION_FLAT_TIME_OFFSET;
wuliqunyy 0:be95bfb06686 233 return i2c_word_write_simple(I2C_POSITION2, nv_positin2_val);
wuliqunyy 0:be95bfb06686 234 }
wuliqunyy 0:be95bfb06686 235
wuliqunyy 0:be95bfb06686 236 /** i2c to set the Postion Pulse duty cycle */
wuliqunyy 0:be95bfb06686 237 int i2c_mbed_fpga::i2c_set_position_duty(unsigned int duty_2b){
wuliqunyy 0:be95bfb06686 238 nv_positin_val &= ~NV_POSITION_DUTY_MASK;
wuliqunyy 0:be95bfb06686 239 nv_positin_val |= duty_2b << NV_POSITION_DUTY_OFFSET;
wuliqunyy 0:be95bfb06686 240 return i2c_word_write_simple(I2C_POSITION, nv_positin_val);
wuliqunyy 0:be95bfb06686 241 }
wuliqunyy 0:be95bfb06686 242
wuliqunyy 0:be95bfb06686 243 /** i2c to enable the Postion Pulse majority volting */
wuliqunyy 0:be95bfb06686 244 int i2c_mbed_fpga::i2c_set_position_maj_vote(unsigned int maj_1b){
wuliqunyy 0:be95bfb06686 245 nv_positin_val &= ~NV_POSI_MAJO_VOTE_MASK;
wuliqunyy 0:be95bfb06686 246 nv_positin_val |= maj_1b << NV_POSI_MAJO_VOTE_OFFSET;
wuliqunyy 0:be95bfb06686 247 return i2c_word_write_simple(I2C_POSITION, nv_positin_val);
wuliqunyy 0:be95bfb06686 248 }
wuliqunyy 0:be95bfb06686 249
wuliqunyy 0:be95bfb06686 250 /** i2c to set the anti-cogging rotation direction */
wuliqunyy 0:be95bfb06686 251 int i2c_mbed_fpga::i2c_set_position_anti_cog(unsigned int cog_1b){
wuliqunyy 0:be95bfb06686 252 nv_positin_val &= ~NV_ANTI_COG_MASK;
wuliqunyy 0:be95bfb06686 253 nv_positin_val |= cog_1b << NV_ANTI_COG_OFFSET;
wuliqunyy 0:be95bfb06686 254 return i2c_word_write_simple(I2C_POSITION, nv_positin_val);
wuliqunyy 0:be95bfb06686 255 }
wuliqunyy 0:be95bfb06686 256
wuliqunyy 0:be95bfb06686 257
wuliqunyy 0:be95bfb06686 258 /** i2c to set the Start Up Pulse width (pulse train) */
wuliqunyy 0:be95bfb06686 259 int i2c_mbed_fpga::i2c_set_start_up_pulse_width(unsigned int mantisaa_3b, unsigned int exponent_3b){
wuliqunyy 0:be95bfb06686 260 nv_start_up_val &= ~NV_START_UP_TIME_MASK;
wuliqunyy 0:be95bfb06686 261 nv_start_up_val |= ((exponent_3b << 3) | mantisaa_3b) << NV_START_UP_TIME_OFFSET;
wuliqunyy 0:be95bfb06686 262 return i2c_word_write_simple(I2C_START_UP, nv_start_up_val);
wuliqunyy 0:be95bfb06686 263 }
wuliqunyy 0:be95bfb06686 264
wuliqunyy 0:be95bfb06686 265 /** i2c to set the Start Up Flat width */
wuliqunyy 0:be95bfb06686 266 int i2c_mbed_fpga::i2c_set_start_up_flat(unsigned int mantisaa_3b, unsigned int exponent_3b){
wuliqunyy 0:be95bfb06686 267 nv_positin2_val &= ~NV_START_UP_FLAT_TIME_MASK;
wuliqunyy 0:be95bfb06686 268 nv_positin2_val |= ((exponent_3b << 3) | mantisaa_3b) << NV_START_UP_FLAT_TIME_OFFSET;
wuliqunyy 0:be95bfb06686 269 return i2c_word_write_simple(I2C_POSITION2, nv_positin2_val);
wuliqunyy 0:be95bfb06686 270 }
wuliqunyy 0:be95bfb06686 271
wuliqunyy 0:be95bfb06686 272 /** i2c to set the Start up Pulse duty cycle (pulse train) */
wuliqunyy 0:be95bfb06686 273 int i2c_mbed_fpga::i2c_set_start_up_duty(unsigned int duty_2b){
wuliqunyy 0:be95bfb06686 274 nv_start_up_val &= ~NV_START_DUTY_MASK;
wuliqunyy 0:be95bfb06686 275 nv_start_up_val |= duty_2b << NV_START_DUTY_OFFSET;
wuliqunyy 0:be95bfb06686 276 return i2c_word_write_simple(I2C_START_UP, nv_start_up_val);
wuliqunyy 0:be95bfb06686 277 }
wuliqunyy 0:be95bfb06686 278
wuliqunyy 0:be95bfb06686 279 /** i2c to set the Start up commutation number of EHPs (pulse train) */
wuliqunyy 0:be95bfb06686 280 int i2c_mbed_fpga::i2c_set_start_up_num_comm(unsigned int comm){
wuliqunyy 0:be95bfb06686 281 nv_start_up_val &= ~NV_COMM_START_NUM_MASK;
wuliqunyy 0:be95bfb06686 282 nv_start_up_val |= comm << NV_COMM_START_NUM_OFFSET;
wuliqunyy 0:be95bfb06686 283 return i2c_word_write_simple(I2C_START_UP, nv_start_up_val);
wuliqunyy 0:be95bfb06686 284 }
wuliqunyy 0:be95bfb06686 285
wuliqunyy 0:be95bfb06686 286 /** i2c to set the Soft Start Up (pulse train) */
wuliqunyy 0:be95bfb06686 287 int i2c_mbed_fpga::i2c_set_soft_start_up(unsigned int enbale, unsigned int mantisaa_3b, unsigned int exponent_3b, unsigned int step_size, unsigned int num_steps){
wuliqunyy 0:be95bfb06686 288 int ack = 0;
wuliqunyy 0:be95bfb06686 289 nv_start_up_val &= ~NV_SOFT_START_MASK;
wuliqunyy 0:be95bfb06686 290 nv_start_up_val |= enbale << NV_SOFT_START_OFFSET;
wuliqunyy 0:be95bfb06686 291 nv_positin_val &= ~NV_FIRST_NON_FLAT_TIME_MASK;
wuliqunyy 0:be95bfb06686 292 nv_positin_val |= ((exponent_3b << 3) | mantisaa_3b) << NV_FIRST_NON_FLAT_TIME_OFFSET;
wuliqunyy 0:be95bfb06686 293 nv_start_up_val &= ~NV_SOFT_STEP_SIZE_MASK;
wuliqunyy 0:be95bfb06686 294 nv_start_up_val |= step_size << NV_SOFT_STEP_SIZE_OFFSET;
wuliqunyy 0:be95bfb06686 295 nv_wind_brake_val &= ~NV_SOFT_NUM_STEP_MASK;
wuliqunyy 0:be95bfb06686 296 nv_wind_brake_val |= num_steps << NV_SOFT_NUM_STEP_OFFSET;
wuliqunyy 0:be95bfb06686 297 ack += i2c_word_write_simple(I2C_POSITION, nv_positin_val);
wuliqunyy 0:be95bfb06686 298 ack += i2c_word_write_simple(I2C_START_UP, nv_start_up_val);
wuliqunyy 0:be95bfb06686 299 ack += i2c_word_write_simple(I2C_WIND_BRAKE, nv_wind_brake_val);
wuliqunyy 0:be95bfb06686 300
wuliqunyy 0:be95bfb06686 301 return ack;
wuliqunyy 0:be95bfb06686 302 }
wuliqunyy 0:be95bfb06686 303
wuliqunyy 0:be95bfb06686 304 /** i2c to set the High Torque Start Up (pulse train */
wuliqunyy 0:be95bfb06686 305 int i2c_mbed_fpga::i2c_set_high_torque_start_up(unsigned int enbale, unsigned int mantisaa_3b, unsigned int exponent_3b){
wuliqunyy 0:be95bfb06686 306 int ack = 0;
wuliqunyy 0:be95bfb06686 307 nv_start_up_val &= ~NV_LONG_START_MASK;
wuliqunyy 0:be95bfb06686 308 nv_start_up_val |= enbale << NV_LONG_START_OFFSET;
wuliqunyy 0:be95bfb06686 309 nv_positin_val &= ~NV_FIRST_NON_FLAT_TIME_MASK;
wuliqunyy 0:be95bfb06686 310 nv_positin_val |= ((exponent_3b << 3) | mantisaa_3b) << NV_FIRST_NON_FLAT_TIME_OFFSET;
wuliqunyy 0:be95bfb06686 311 ack += i2c_word_write_simple(I2C_POSITION, nv_positin_val);
wuliqunyy 0:be95bfb06686 312 ack += i2c_word_write_simple(I2C_START_UP, nv_start_up_val);
wuliqunyy 0:be95bfb06686 313
wuliqunyy 0:be95bfb06686 314 return ack;
wuliqunyy 0:be95bfb06686 315 }
wuliqunyy 0:be95bfb06686 316
wuliqunyy 0:be95bfb06686 317 /** i2c to set the Single Pulse Start Up (pulse train) */
wuliqunyy 0:be95bfb06686 318 int i2c_mbed_fpga::i2c_set_single_pulse_start_up(unsigned int enbale, unsigned int mantisaa_3b, unsigned int exponent_3b){
wuliqunyy 0:be95bfb06686 319 int ack = 0;
wuliqunyy 0:be95bfb06686 320 nv_start_up_val &= ~NV_SINGLE_PULSE_START_MASK;
wuliqunyy 0:be95bfb06686 321 nv_start_up_val |= enbale << NV_SINGLE_PULSE_START_OFFSET;
wuliqunyy 0:be95bfb06686 322 nv_positin_val &= ~NV_FIRST_NON_FLAT_TIME_MASK;
wuliqunyy 0:be95bfb06686 323 nv_positin_val |= ((exponent_3b << 3) | mantisaa_3b) << NV_FIRST_NON_FLAT_TIME_OFFSET;
wuliqunyy 0:be95bfb06686 324 ack += i2c_word_write_simple(I2C_POSITION, nv_positin_val);
wuliqunyy 0:be95bfb06686 325 ack += i2c_word_write_simple(I2C_START_UP, nv_start_up_val);
wuliqunyy 0:be95bfb06686 326
wuliqunyy 0:be95bfb06686 327 return ack;
wuliqunyy 0:be95bfb06686 328 }
wuliqunyy 0:be95bfb06686 329
wuliqunyy 0:be95bfb06686 330 /** i2c to set the rough regulation gain */
wuliqunyy 0:be95bfb06686 331 int i2c_mbed_fpga::i2c_force_rough_reg(unsigned int reg){
wuliqunyy 0:be95bfb06686 332 int ack = 0;
wuliqunyy 0:be95bfb06686 333 nv_gen_ctrl_val &= ~NV_ROUGH_REG_MASK;
wuliqunyy 0:be95bfb06686 334 nv_gen_ctrl_val |= reg << NV_ROUGH_REG_OFFSET;
wuliqunyy 0:be95bfb06686 335 ack += i2c_word_write_simple(I2C_GEN_CTRL, nv_gen_ctrl_val);
wuliqunyy 0:be95bfb06686 336
wuliqunyy 0:be95bfb06686 337 return ack;
wuliqunyy 0:be95bfb06686 338 }
wuliqunyy 0:be95bfb06686 339
wuliqunyy 0:be95bfb06686 340 /** i2c to set the rough regulation gain */
wuliqunyy 0:be95bfb06686 341 int i2c_mbed_fpga::i2c_set_rough_gain(unsigned int rough_gain){
wuliqunyy 0:be95bfb06686 342 int ack = 0;
wuliqunyy 0:be95bfb06686 343 nv_gen_ctrl_val &= ~NV_ROUGH_GAIN_MASK;
wuliqunyy 0:be95bfb06686 344 nv_gen_ctrl_val |= rough_gain << NV_ROUGH_GAIN_OFFSET;
wuliqunyy 0:be95bfb06686 345 ack += i2c_word_write_simple(I2C_GEN_CTRL, nv_gen_ctrl_val);
wuliqunyy 0:be95bfb06686 346
wuliqunyy 0:be95bfb06686 347 return ack;
wuliqunyy 0:be95bfb06686 348 }
wuliqunyy 0:be95bfb06686 349
wuliqunyy 0:be95bfb06686 350 /** i2c to set the ehp regulation gain */
wuliqunyy 0:be95bfb06686 351 int i2c_mbed_fpga::i2c_set_ehp_reg_gain(unsigned int ehp_gain){
wuliqunyy 0:be95bfb06686 352 int ack = 0;
wuliqunyy 0:be95bfb06686 353 nv_gen_ctrl_val &= ~NV_EHP_REG_GAIN_MASK;
wuliqunyy 0:be95bfb06686 354 nv_gen_ctrl_val |= ehp_gain << NV_EHP_REG_GAIN_OFFSET;
wuliqunyy 0:be95bfb06686 355 ack += i2c_word_write_simple(I2C_GEN_CTRL, nv_gen_ctrl_val);
wuliqunyy 0:be95bfb06686 356
wuliqunyy 0:be95bfb06686 357 return ack;
wuliqunyy 0:be95bfb06686 358 }
wuliqunyy 0:be95bfb06686 359
wuliqunyy 0:be95bfb06686 360 /** i2c to set the ehp regulation gain */
wuliqunyy 0:be95bfb06686 361 int i2c_mbed_fpga::i2c_set_fall_time_blank(unsigned int blank_time){
wuliqunyy 0:be95bfb06686 362 int ack = 0;
wuliqunyy 0:be95bfb06686 363 nv_dig_config_val &= ~NV_FLAT_BLANK_MASK;
wuliqunyy 0:be95bfb06686 364 nv_dig_config_val |= blank_time << NV_FLAT_BLANK_OFFSET;
wuliqunyy 0:be95bfb06686 365 ack += i2c_word_write_simple(I2C_DIGITAL_CFG, nv_dig_config_val);
wuliqunyy 0:be95bfb06686 366
wuliqunyy 0:be95bfb06686 367 return ack;
wuliqunyy 0:be95bfb06686 368 }
wuliqunyy 0:be95bfb06686 369
wuliqunyy 0:be95bfb06686 370 /** i2c to set the current threshold for I_didt */
wuliqunyy 0:be95bfb06686 371 int i2c_mbed_fpga::i2c_set_comm_i_thres(unsigned int i_thr_low, unsigned int i_thr_high){
wuliqunyy 0:be95bfb06686 372 int ack = 0;
wuliqunyy 0:be95bfb06686 373 nv_i_zc_th_low_val &= ~NV_I_ZC_TH_LOW_MASK;
wuliqunyy 0:be95bfb06686 374 nv_i_zc_th_low_val |= i_thr_low << NV_I_ZC_TH_LOW_OFFSET;
wuliqunyy 0:be95bfb06686 375 nv_i_zc_th_high_val &= ~NV_I_ZC_TH_HIGH_MASK;
wuliqunyy 0:be95bfb06686 376 nv_i_zc_th_high_val |= i_thr_high << NV_I_ZC_TH_HIGH_OFFSET;
wuliqunyy 0:be95bfb06686 377 ack += i2c_word_write_simple(I2C_I_ZC_TH_LOW_REG, nv_i_zc_th_low_val);
wuliqunyy 0:be95bfb06686 378 ack += i2c_word_write_simple(I2C_I_ZC_TH_HIGH_REG, nv_i_zc_th_high_val);
wuliqunyy 0:be95bfb06686 379 return ack;
wuliqunyy 0:be95bfb06686 380 }
wuliqunyy 0:be95bfb06686 381
wuliqunyy 0:be95bfb06686 382 /** i2c to set the di current threshold for didt */
wuliqunyy 0:be95bfb06686 383 int i2c_mbed_fpga::i2c_set_comm_di_thres(unsigned int di_1st, unsigned int di_2nd){
wuliqunyy 0:be95bfb06686 384 int ack = 0;
wuliqunyy 0:be95bfb06686 385 nv_di_th_1st_val &= ~NV_DI_TH_1ST_MASK;
wuliqunyy 0:be95bfb06686 386 nv_di_th_1st_val |= di_1st << NV_DI_TH_1ST_OFFSET;
wuliqunyy 0:be95bfb06686 387 nv_di_th_2nd_val &= ~NV_DI_TH_2ND_MASK;
wuliqunyy 0:be95bfb06686 388 nv_di_th_2nd_val |= di_2nd << NV_DI_TH_2ND_OFFSET;
wuliqunyy 0:be95bfb06686 389 ack += i2c_word_write_simple(I2C_DI_TH_1ST_REG, nv_di_th_1st_val);
wuliqunyy 0:be95bfb06686 390 ack += i2c_word_write_simple(I2C_DI_TH_2ND_REG, nv_di_th_2nd_val);
wuliqunyy 0:be95bfb06686 391 return ack;
wuliqunyy 0:be95bfb06686 392 }
wuliqunyy 0:be95bfb06686 393
wuliqunyy 0:be95bfb06686 394 /** i2c to clean the I2C controller settins */
wuliqunyy 0:be95bfb06686 395 int i2c_mbed_fpga::i2c_clear_spd_ctrl(){
wuliqunyy 0:be95bfb06686 396 int ack = 0;
wuliqunyy 0:be95bfb06686 397 nv_spd_control_1_val = 0;
wuliqunyy 0:be95bfb06686 398 nv_spd_control_2_val = 0;
wuliqunyy 0:be95bfb06686 399 ack += i2c_word_write_simple(I2C_SPD_CTRL_1, nv_spd_control_1_val);
wuliqunyy 0:be95bfb06686 400 ack += i2c_word_write_simple(I2C_SPD_CTRL_2, nv_spd_control_2_val);
wuliqunyy 0:be95bfb06686 401
wuliqunyy 0:be95bfb06686 402 return ack;
wuliqunyy 0:be95bfb06686 403 }
wuliqunyy 0:be95bfb06686 404
wuliqunyy 0:be95bfb06686 405 /** i2c to set the I2C speed input mode */
wuliqunyy 0:be95bfb06686 406 int i2c_mbed_fpga::i2c_set_input_mode(unsigned int mode){
wuliqunyy 0:be95bfb06686 407 int ack = 0;
wuliqunyy 0:be95bfb06686 408 nv_application_cfg_val &= ~NV_INPUT_MODE_CFG_MASK;
wuliqunyy 0:be95bfb06686 409 nv_application_cfg_val |= mode << NV_INPUT_MODE_CFG_OFFSET;
wuliqunyy 0:be95bfb06686 410 ack += i2c_word_write_simple(I2C_APPLICATION_CFG, nv_application_cfg_val);
wuliqunyy 0:be95bfb06686 411 return ack;
wuliqunyy 0:be95bfb06686 412 }
wuliqunyy 0:be95bfb06686 413
wuliqunyy 0:be95bfb06686 414 /** i2c to set the open loop mode */
wuliqunyy 0:be95bfb06686 415 int i2c_mbed_fpga::i2c_set_loop_mode(unsigned int openloop){
wuliqunyy 0:be95bfb06686 416 int ack = 0;
wuliqunyy 0:be95bfb06686 417 nv_spd_control_1_val &= ~NV_SPD_LOOP_MODE_MASK;
wuliqunyy 0:be95bfb06686 418 nv_spd_control_1_val |= openloop << NV_SPD_LOOP_MODE_OFFSET;
wuliqunyy 0:be95bfb06686 419 ack += i2c_word_write_simple(I2C_SPD_CTRL_1, nv_spd_control_1_val);
wuliqunyy 0:be95bfb06686 420
wuliqunyy 0:be95bfb06686 421 return ack;
wuliqunyy 0:be95bfb06686 422 }
wuliqunyy 0:be95bfb06686 423
wuliqunyy 0:be95bfb06686 424 /** i2c to set the Single Pulse Start Up (pulse train) */
wuliqunyy 0:be95bfb06686 425 int i2c_mbed_fpga::i2c_set_open_loop_duty(unsigned int duty){
wuliqunyy 0:be95bfb06686 426 int ack = 0;
wuliqunyy 0:be95bfb06686 427 ram_open_duty_val = duty;
wuliqunyy 0:be95bfb06686 428 ack += i2c_word_write_simple(I2C_SPEED_DUTY, ram_open_duty_val);
wuliqunyy 0:be95bfb06686 429
wuliqunyy 0:be95bfb06686 430 return ack;
wuliqunyy 0:be95bfb06686 431 }
wuliqunyy 0:be95bfb06686 432
wuliqunyy 0:be95bfb06686 433 /** i2c to set the speed curve type */
wuliqunyy 0:be95bfb06686 434 int i2c_mbed_fpga::i2c_set_curve_type(unsigned int curvetype){
wuliqunyy 0:be95bfb06686 435 int ack = 0;
wuliqunyy 0:be95bfb06686 436 nv_spd_control_1_val &= ~NV_CURVE_MODE_MASK;
wuliqunyy 0:be95bfb06686 437 nv_spd_control_1_val |= curvetype << NV_CURVE_MODE_OFFSET;
wuliqunyy 0:be95bfb06686 438 ack += i2c_word_write_simple(I2C_SPD_CTRL_1, nv_spd_control_1_val);
wuliqunyy 0:be95bfb06686 439
wuliqunyy 0:be95bfb06686 440 return ack;
wuliqunyy 0:be95bfb06686 441 }
wuliqunyy 0:be95bfb06686 442
wuliqunyy 0:be95bfb06686 443 /** i2c to set the open dc ini */
wuliqunyy 0:be95bfb06686 444 int i2c_mbed_fpga::i2c_set_dc_ini(unsigned int ini){
wuliqunyy 0:be95bfb06686 445 int ack = 0;
wuliqunyy 0:be95bfb06686 446 nv_spd_control_2_val &= ~NV_DC_OPENLOOP_INI_MASK;
wuliqunyy 0:be95bfb06686 447 nv_spd_control_2_val |= ini << NV_DC_OPENLOOP_INI_OFFSET;
wuliqunyy 0:be95bfb06686 448 ack += i2c_word_write_simple(I2C_SPD_CTRL_2, nv_spd_control_2_val);
wuliqunyy 0:be95bfb06686 449
wuliqunyy 0:be95bfb06686 450 return ack;
wuliqunyy 0:be95bfb06686 451 }
wuliqunyy 0:be95bfb06686 452
wuliqunyy 0:be95bfb06686 453 /** i2c to set the open dc slew rate */
wuliqunyy 0:be95bfb06686 454 int i2c_mbed_fpga::i2c_set_dc_sr(unsigned int sr){
wuliqunyy 0:be95bfb06686 455 int ack = 0;
wuliqunyy 0:be95bfb06686 456 nv_spd_control_2_val &= ~NV_DC_OPENLOOP_SR_MASK;
wuliqunyy 0:be95bfb06686 457 nv_spd_control_2_val |= sr << NV_DC_OPENLOOP_SR_OFFSET;
wuliqunyy 0:be95bfb06686 458 ack += i2c_word_write_simple(I2C_SPD_CTRL_2, nv_spd_control_2_val);
wuliqunyy 0:be95bfb06686 459
wuliqunyy 0:be95bfb06686 460 return ack;
wuliqunyy 0:be95bfb06686 461 }
wuliqunyy 0:be95bfb06686 462
wuliqunyy 0:be95bfb06686 463 /** i2c to set the target CLIM during start up */
wuliqunyy 0:be95bfb06686 464 int i2c_mbed_fpga::i2c_set_clim_start_up(unsigned int clim){
wuliqunyy 0:be95bfb06686 465 int ack = 0;
wuliqunyy 0:be95bfb06686 466 nv_clim_user_1_val &= ~NV_TARGET_CLIM_USER_PULSES_MASK;
wuliqunyy 0:be95bfb06686 467 nv_clim_user_1_val |= clim << NV_TARGET_CLIM_USER_PULSES_OFFSET;
wuliqunyy 0:be95bfb06686 468 ack += i2c_word_write_simple(I2C_CLIM_USER_1, nv_clim_user_1_val);
wuliqunyy 0:be95bfb06686 469
wuliqunyy 0:be95bfb06686 470 return ack;
wuliqunyy 0:be95bfb06686 471 }
wuliqunyy 0:be95bfb06686 472
wuliqunyy 0:be95bfb06686 473 /** i2c to set the target CLIM during brake */
wuliqunyy 0:be95bfb06686 474 int i2c_mbed_fpga::i2c_set_clim_brake(unsigned int clim){
wuliqunyy 0:be95bfb06686 475 int ack = 0;
wuliqunyy 0:be95bfb06686 476 nv_clim_user_0_val &= ~NV_TARGET_CLIM_USER_BRAKE_MASK;
wuliqunyy 0:be95bfb06686 477 nv_clim_user_0_val |= clim << NV_TARGET_CLIM_USER_BRAKE_OFFSET;
wuliqunyy 0:be95bfb06686 478 ack += i2c_word_write_simple(I2C_CLIM_USER_0, nv_clim_user_0_val);
wuliqunyy 0:be95bfb06686 479
wuliqunyy 0:be95bfb06686 480 return ack;
wuliqunyy 0:be95bfb06686 481 }
wuliqunyy 0:be95bfb06686 482
wuliqunyy 0:be95bfb06686 483 /** i2c to set the target CLIM during run time */
wuliqunyy 0:be95bfb06686 484 int i2c_mbed_fpga::i2c_set_clim_run_time(unsigned int clim){
wuliqunyy 0:be95bfb06686 485 int ack = 0;
wuliqunyy 0:be95bfb06686 486 nv_clim_user_0_val &= ~NV_TARGET_CLIM_USER_MOTOR_MASK;
wuliqunyy 0:be95bfb06686 487 nv_clim_user_0_val |= clim << NV_TARGET_CLIM_USER_MOTOR_OFFSET;
wuliqunyy 0:be95bfb06686 488 ack += i2c_word_write_simple(I2C_CLIM_USER_0, nv_clim_user_0_val);
wuliqunyy 0:be95bfb06686 489
wuliqunyy 0:be95bfb06686 490 return ack;
wuliqunyy 0:be95bfb06686 491 }
wuliqunyy 0:be95bfb06686 492
wuliqunyy 0:be95bfb06686 493
wuliqunyy 0:be95bfb06686 494 /** i2c to enbale test debug mode */
wuliqunyy 0:be95bfb06686 495 int i2c_mbed_fpga::i2c_enable_pules_debug_mode(unsigned int enable){
wuliqunyy 0:be95bfb06686 496 int ack = 0;
wuliqunyy 0:be95bfb06686 497 ram_debug_ctrl_val &= ~0x0001;
wuliqunyy 0:be95bfb06686 498 ram_debug_ctrl_val |= enable;
wuliqunyy 0:be95bfb06686 499 ack += i2c_word_write_simple(0xEA, 1);
wuliqunyy 0:be95bfb06686 500
wuliqunyy 0:be95bfb06686 501 return ack;
wuliqunyy 0:be95bfb06686 502 }
wuliqunyy 0:be95bfb06686 503