Witek Ewert / Mbed 2 deprecated KL46Z-Lab2_lodz

Sensor reporting over USB CDC

Dependencies:   MAG3110 MMA8451Q SLCD- TSI USBDevice mbed

SLCD-/LCDconfig.h@0:7b58cdacf811, 2014-04-16 (annotated)

Committer:
wue
Date:
Wed Apr 16 12:20:12 2014 +0000
Revision:
0:7b58cdacf811
Sensor reporting over USB CDC

Who changed what in which revision?

UserRevisionLine numberNew contents of line
wue 0:7b58cdacf811 1 #include "FRDM-s401.h" // 4x7 segdisplay
wue 0:7b58cdacf811 2
wue 0:7b58cdacf811 3
wue 0:7b58cdacf811 4 #if 1 // VREF to VLL1
wue 0:7b58cdacf811 5 /* Following configuration is used for LCD default initialization */
wue 0:7b58cdacf811 6 #define _LCDRVEN (1) //
wue 0:7b58cdacf811 7 #define _LCDRVTRIM (8) // CPSEL = 1 0 -- 8000 pf 1 -- 6000 pf 2 -- 4000 pf 3 -- 2000 pf
wue 0:7b58cdacf811 8 #define _LCDCPSEL (1) // charge pump select 0 or 1
wue 0:7b58cdacf811 9 #define _LCDLOADADJUST (3) // CPSEL = 1 0 -- 8000 pf 1 -- 6000 pf 2 -- 4000 pf 3 -- 2000 pf
wue 0:7b58cdacf811 10 #define _LCDALTDIV (0) // CPSEL = 1 0 -- 8000 pf 1 -- 6000 pf 2 -- 4000 pf 3 -- 2000 pf
wue 0:7b58cdacf811 11 #define _LCDALRCLKSOURCE (0) // 0 -- External clock 1 -- Alternate clock
wue 0:7b58cdacf811 12
wue 0:7b58cdacf811 13 #define _LCDCLKPSL (0) // Clock divider to generate the LCD Waveforms
wue 0:7b58cdacf811 14 #define _LCDSUPPLY (1)
wue 0:7b58cdacf811 15 #define _LCDHREF (0) // 0 or 1
wue 0:7b58cdacf811 16 #define _LCDCLKSOURCE (1) // 0 -- External clock 1 -- Alternate clock
wue 0:7b58cdacf811 17 #define _LCDLCK (1) //Any number between 0 and 7
wue 0:7b58cdacf811 18 #define _LCDBLINKRATE (3) //Any number between 0 and 7
wue 0:7b58cdacf811 19
wue 0:7b58cdacf811 20
wue 0:7b58cdacf811 21 #else //VLL3 to VDD internally
wue 0:7b58cdacf811 22 /* Following configuration is used for LCD default initialization */
wue 0:7b58cdacf811 23 #define _LCDCLKSOURCE (1) // 0 -- External clock 1 -- Alternate clock
wue 0:7b58cdacf811 24 #define _LCDALRCLKSOURCE (0) // 0 -- External clock 1 -- Alternate clock
wue 0:7b58cdacf811 25 #define _LCDCLKPSL (0) // Clock divider to generate the LCD Waveforms
wue 0:7b58cdacf811 26 #define _LCDSUPPLY (0)
wue 0:7b58cdacf811 27 #define _LCDLOADADJUST (3) // CPSEL = 1 0 -- 8000 pf 1 -- 6000 pf 2 -- 4000 pf 3 -- 2000 pf
wue 0:7b58cdacf811 28 #define _LCDALTDIV (0) // CPSEL = 1 0 -- 8000 pf 1 -- 6000 pf 2 -- 4000 pf 3 -- 2000 pf
wue 0:7b58cdacf811 29 #define _LCDRVTRIM (0) // CPSEL = 1 0 -- 8000 pf 1 -- 6000 pf 2 -- 4000 pf 3 -- 2000 pf
wue 0:7b58cdacf811 30 #define _LCDHREF (0) // 0 or 1
wue 0:7b58cdacf811 31 #define _LCDCPSEL (1) // 0 or 1
wue 0:7b58cdacf811 32 #define _LCDRVEN (0) //
wue 0:7b58cdacf811 33 #define _LCDBLINKRATE (3) // Any number between 0 and 7
wue 0:7b58cdacf811 34 #define _LCDLCK (0) // Any number between 0 and 7
wue 0:7b58cdacf811 35
wue 0:7b58cdacf811 36 #endif
wue 0:7b58cdacf811 37
wue 0:7b58cdacf811 38
wue 0:7b58cdacf811 39
wue 0:7b58cdacf811 40
wue 0:7b58cdacf811 41 /*~|~|~|~|~|~|~|~|~|~|~|~|~|~ LCD Control Register 0 ~|~|~|~|~|~|~|~|~|~|~|~|~*/
wue 0:7b58cdacf811 42 /*~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|*/
wue 0:7b58cdacf811 43 #define _LCDINTENABLE (1)
wue 0:7b58cdacf811 44
wue 0:7b58cdacf811 45 /*~|~|~|~|~|~|~|~|~|~|~|~|~|~ LCD Control Register 1 ~|~|~|~|~|~|~|~|~|~|~|~|~|*/
wue 0:7b58cdacf811 46 /*~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|*/
wue 0:7b58cdacf811 47 #define _LCDFRAMEINTERRUPT (0) //0 Disable Frame Frequency Interrupt
wue 0:7b58cdacf811 48 //1 Enable an LCD interrupt that coincides with the LCD frame frequency
wue 0:7b58cdacf811 49 #define _LCDFULLCPLDIRIVE (0) // 0 GPIO shared with the LCD. Inputs levels and internal pullup reference to VDD
wue 0:7b58cdacf811 50 // 1 If VSUPPLY=11and RVEN=0. Inputs levels and internal pullup reference to VLL3
wue 0:7b58cdacf811 51 #define _LCDWAITMODE (0) // 0 Allows the LCD driver and charge pump to continue running during wait mode
wue 0:7b58cdacf811 52 // 1 Disable the LCD when the MCU goes into wait mode
wue 0:7b58cdacf811 53 #define _LCDSTOPMODE (0) // 0 Allows the LCD driver and charge pump to continue running during stop2 or stop3
wue 0:7b58cdacf811 54 // 1 Disable the LCD when and charge pump when the MCU goes into stop2 or stop3
wue 0:7b58cdacf811 55
wue 0:7b58cdacf811 56 /*~|~|~|~|~|~|~|~|~|~|~|~|~|~ LCD Voltage Supply Register ~|~|~|~|~|~|~|~|~|~|~|~*/
wue 0:7b58cdacf811 57 /*~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|*/
wue 0:7b58cdacf811 58 #define _LCDHIGHREF (0) //0 Divide input VIREG=1.0v
wue 0:7b58cdacf811 59 //1 Do not divide the input VIREG=1.67v
wue 0:7b58cdacf811 60 #define _LCDBBYPASS (0) //Determines whether the internal LCD op amp buffer is bypassed
wue 0:7b58cdacf811 61 //0 Buffered mode
wue 0:7b58cdacf811 62 //1 Unbuffered mode
wue 0:7b58cdacf811 63
wue 0:7b58cdacf811 64 /*~|~|~|~|~|~|~|~|~|~|~|~|~|~ LCD Regulated Voltage Control |~|~|~|~|~|~|~|~|~|~*/
wue 0:7b58cdacf811 65 /*~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|*/
wue 0:7b58cdacf811 66 #define _LCDCONTRAST (1) //Contrast by software 0 -- Disable 1-- Enable
wue 0:7b58cdacf811 67 #define _LVLCONTRAST (0) //Any number between 0 and 15, if the number is bigger the glass gets darker
wue 0:7b58cdacf811 68
wue 0:7b58cdacf811 69 /*~|~|~|~|~|~|~|~|~|~|~|~|~|~ LCD Blink Control Register ~|~|~|~|~|~|~|~|~|~|~|~*/
wue 0:7b58cdacf811 70 /*~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|*/
wue 0:7b58cdacf811 71 #define _LCDBLINKCONTROL (1) //0 Disable blink mode
wue 0:7b58cdacf811 72 //1 Enable blink mode
wue 0:7b58cdacf811 73 #define _LCDALTMODE (0) //0 Normal display
wue 0:7b58cdacf811 74 //1 Alternate display for 4 backplanes or less the LCD backplane sequencer changes to otuput an alternate display
wue 0:7b58cdacf811 75 #define _LCDBLANKDISP (0) //0 Do not blank display
wue 0:7b58cdacf811 76 //1 Blank display if you put it in 0 the text before blank is manteined
wue 0:7b58cdacf811 77 #define _LCDBLINKMODE (0) //0 Display blank during the blink period
wue 0:7b58cdacf811 78 //1 Display alternate displat during blink period (Ignored if duty is 5 or greater)
wue 0:7b58cdacf811 79
wue 0:7b58cdacf811 80
wue 0:7b58cdacf811 81 //Calculated values
wue 0:7b58cdacf811 82 #define _LCDUSEDPINS (_LCDFRONTPLANES + _LCDBACKPLANES)
wue 0:7b58cdacf811 83 #define _LCDDUTY (_LCDBACKPLANES-1) //Any number between 0 and 7
wue 0:7b58cdacf811 84 #define LCD_WF_BASE LCD->WF8B[0]
wue 0:7b58cdacf811 85
wue 0:7b58cdacf811 86 // General definitions used by the LCD library
wue 0:7b58cdacf811 87 #define LCD_WF(x) *((uint8 *)&LCD_WF_BASE + x)
wue 0:7b58cdacf811 88
wue 0:7b58cdacf811 89 /*LCD Fault Detections Consts*/
wue 0:7b58cdacf811 90 #define FP_TYPE 0x00 // pin is a Front Plane
wue 0:7b58cdacf811 91 #define BP_TYPE 0x80 // pin is Back Plane
wue 0:7b58cdacf811 92
wue 0:7b58cdacf811 93 // Fault Detect Preescaler Options
wue 0:7b58cdacf811 94 #define FDPRS_1 0
wue 0:7b58cdacf811 95 #define FDPRS_2 1
wue 0:7b58cdacf811 96 #define FDPRS_4 2
wue 0:7b58cdacf811 97 #define FDPRS_8 3
wue 0:7b58cdacf811 98 #define FDPRS_16 4
wue 0:7b58cdacf811 99 #define FDPRS_32 5
wue 0:7b58cdacf811 100 #define FDPRS_64 6
wue 0:7b58cdacf811 101 #define FDPRS_128 7
wue 0:7b58cdacf811 102
wue 0:7b58cdacf811 103 // Fault Detect Sample Window Width Values
wue 0:7b58cdacf811 104 #define FDSWW_4 0
wue 0:7b58cdacf811 105 #define FDSWW_8 1
wue 0:7b58cdacf811 106 #define FDSWW_16 2
wue 0:7b58cdacf811 107 #define FDSWW_32 3
wue 0:7b58cdacf811 108 #define FDSWW_64 4
wue 0:7b58cdacf811 109 #define FDSWW_128 5
wue 0:7b58cdacf811 110 #define FDSWW_256 6
wue 0:7b58cdacf811 111 #define FDSWW_512 7
wue 0:7b58cdacf811 112
wue 0:7b58cdacf811 113 /*
wue 0:7b58cdacf811 114 Mask Bit definitions used f
wue 0:7b58cdacf811 115 */
wue 0:7b58cdacf811 116 #define mBIT0 1
wue 0:7b58cdacf811 117 #define mBIT1 2
wue 0:7b58cdacf811 118 #define mBIT2 4
wue 0:7b58cdacf811 119 #define mBIT3 8
wue 0:7b58cdacf811 120 #define mBIT4 16
wue 0:7b58cdacf811 121 #define mBIT5 32
wue 0:7b58cdacf811 122 #define mBIT6 64
wue 0:7b58cdacf811 123 #define mBIT7 128
wue 0:7b58cdacf811 124 #define mBIT8 256
wue 0:7b58cdacf811 125 #define mBIT9 512
wue 0:7b58cdacf811 126 #define mBIT10 1024
wue 0:7b58cdacf811 127 #define mBIT11 2048
wue 0:7b58cdacf811 128 #define mBIT12 4096
wue 0:7b58cdacf811 129 #define mBIT13 8192
wue 0:7b58cdacf811 130 #define mBIT14 16384
wue 0:7b58cdacf811 131 #define mBIT15 32768
wue 0:7b58cdacf811 132 #define mBIT16 65536
wue 0:7b58cdacf811 133 #define mBIT17 131072
wue 0:7b58cdacf811 134 #define mBIT18 262144
wue 0:7b58cdacf811 135 #define mBIT19 524288
wue 0:7b58cdacf811 136 #define mBIT20 1048576
wue 0:7b58cdacf811 137 #define mBIT21 2097152
wue 0:7b58cdacf811 138 #define mBIT22 4194304
wue 0:7b58cdacf811 139 #define mBIT23 8388608
wue 0:7b58cdacf811 140 #define mBIT24 16777216
wue 0:7b58cdacf811 141 #define mBIT25 33554432
wue 0:7b58cdacf811 142 #define mBIT26 67108864
wue 0:7b58cdacf811 143 #define mBIT27 134217728
wue 0:7b58cdacf811 144 #define mBIT28 268435456
wue 0:7b58cdacf811 145 #define mBIT29 536870912
wue 0:7b58cdacf811 146 #define mBIT30 1073741824
wue 0:7b58cdacf811 147 #define mBIT31 2147483648
wue 0:7b58cdacf811 148
wue 0:7b58cdacf811 149 #define mBIT32 1
wue 0:7b58cdacf811 150 #define mBIT33 2
wue 0:7b58cdacf811 151 #define mBIT34 4
wue 0:7b58cdacf811 152 #define mBIT35 8
wue 0:7b58cdacf811 153 #define mBIT36 16
wue 0:7b58cdacf811 154 #define mBIT37 32
wue 0:7b58cdacf811 155 #define mBIT38 64
wue 0:7b58cdacf811 156 #define mBIT39 128
wue 0:7b58cdacf811 157 #define mBIT40 256
wue 0:7b58cdacf811 158 #define mBIT41 512
wue 0:7b58cdacf811 159 #define mBIT42 1024
wue 0:7b58cdacf811 160 #define mBIT43 2048
wue 0:7b58cdacf811 161 #define mBIT44 4096
wue 0:7b58cdacf811 162 #define mBIT45 8192
wue 0:7b58cdacf811 163 #define mBIT46 16384
wue 0:7b58cdacf811 164 #define mBIT47 32768
wue 0:7b58cdacf811 165 #define mBIT48 65536
wue 0:7b58cdacf811 166 #define mBIT49 131072
wue 0:7b58cdacf811 167 #define mBIT50 262144
wue 0:7b58cdacf811 168 #define mBIT51 524288
wue 0:7b58cdacf811 169 #define mBIT52 1048576
wue 0:7b58cdacf811 170 #define mBIT53 2097152
wue 0:7b58cdacf811 171 #define mBIT54 4194304
wue 0:7b58cdacf811 172 #define mBIT55 8388608
wue 0:7b58cdacf811 173 #define mBIT56 16777216
wue 0:7b58cdacf811 174 #define mBIT57 33554432
wue 0:7b58cdacf811 175 #define mBIT58 67108864
wue 0:7b58cdacf811 176 #define mBIT59 134217728
wue 0:7b58cdacf811 177 #define mBIT60 268435456
wue 0:7b58cdacf811 178 #define mBIT61 536870912
wue 0:7b58cdacf811 179 #define mBIT62 1073741824
wue 0:7b58cdacf811 180 #define mBIT63 2147483648
wue 0:7b58cdacf811 181
wue 0:7b58cdacf811 182
wue 0:7b58cdacf811 183