wlong xue / SX1276Lib

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Fork of SX1276Lib by Semtech

sx1276/sx1276.cpp@6:e7f02929cd3d, 2014-09-04 (annotated)

Committer:
GregCr
Date:
Thu Sep 04 14:03:20 2014 +0000
Revision:
6:e7f02929cd3d
Parent:
5:11ec8a6ba4f0
Child:
7:2b555111463f
Added support for FHSS

Who changed what in which revision?

UserRevisionLine numberNew contents of line
GregCr 0:e6ceb13d2d05 1 /*
GregCr 0:e6ceb13d2d05 2 / _____) _ | |
GregCr 0:e6ceb13d2d05 3 ( (____ _____ ____ _| |_ _____ ____| |__
GregCr 0:e6ceb13d2d05 4 \____ \| ___ | (_ _) ___ |/ ___) _ \
GregCr 0:e6ceb13d2d05 5 _____) ) ____| | | || |_| ____( (___| | | |
GregCr 0:e6ceb13d2d05 6 (______/|_____)_|_|_| \__)_____)\____)_| |_|
GregCr 0:e6ceb13d2d05 7 ( C )2014 Semtech
GregCr 0:e6ceb13d2d05 8
GregCr 0:e6ceb13d2d05 9 Description: Actual implementation of a SX1276 radio, inherits Radio
GregCr 0:e6ceb13d2d05 10
GregCr 0:e6ceb13d2d05 11 License: Revised BSD License, see LICENSE.TXT file include in the project
GregCr 0:e6ceb13d2d05 12
GregCr 0:e6ceb13d2d05 13 Maintainers: Miguel Luis, Gregory Cristian and Nicolas Huguenin
GregCr 0:e6ceb13d2d05 14 */
GregCr 0:e6ceb13d2d05 15 #include "sx1276.h"
GregCr 0:e6ceb13d2d05 16
GregCr 0:e6ceb13d2d05 17 const FskBandwidth_t SX1276::FskBandwidths[] =
GregCr 0:e6ceb13d2d05 18 {
GregCr 0:e6ceb13d2d05 19 { 2600 , 0x17 },
GregCr 0:e6ceb13d2d05 20 { 3100 , 0x0F },
GregCr 0:e6ceb13d2d05 21 { 3900 , 0x07 },
GregCr 0:e6ceb13d2d05 22 { 5200 , 0x16 },
GregCr 0:e6ceb13d2d05 23 { 6300 , 0x0E },
GregCr 0:e6ceb13d2d05 24 { 7800 , 0x06 },
GregCr 0:e6ceb13d2d05 25 { 10400 , 0x15 },
GregCr 0:e6ceb13d2d05 26 { 12500 , 0x0D },
GregCr 0:e6ceb13d2d05 27 { 15600 , 0x05 },
GregCr 0:e6ceb13d2d05 28 { 20800 , 0x14 },
GregCr 0:e6ceb13d2d05 29 { 25000 , 0x0C },
GregCr 0:e6ceb13d2d05 30 { 31300 , 0x04 },
GregCr 0:e6ceb13d2d05 31 { 41700 , 0x13 },
GregCr 0:e6ceb13d2d05 32 { 50000 , 0x0B },
GregCr 0:e6ceb13d2d05 33 { 62500 , 0x03 },
GregCr 0:e6ceb13d2d05 34 { 83333 , 0x12 },
GregCr 0:e6ceb13d2d05 35 { 100000, 0x0A },
GregCr 0:e6ceb13d2d05 36 { 125000, 0x02 },
GregCr 0:e6ceb13d2d05 37 { 166700, 0x11 },
GregCr 0:e6ceb13d2d05 38 { 200000, 0x09 },
GregCr 0:e6ceb13d2d05 39 { 250000, 0x01 }
GregCr 0:e6ceb13d2d05 40 };
GregCr 0:e6ceb13d2d05 41
GregCr 0:e6ceb13d2d05 42
GregCr 6:e7f02929cd3d 43 SX1276::SX1276( void ( *txDone )( ), void ( *txTimeout ) ( ), void ( *rxDone ) ( uint8_t *payload, uint16_t size, int8_t rssi, int8_t snr ),
GregCr 6:e7f02929cd3d 44 void ( *rxTimeout ) ( ), void ( *rxError ) ( ), void ( *fhssChangeChannel ) ( uint8_t channelIndex ),
GregCr 0:e6ceb13d2d05 45 PinName mosi, PinName miso, PinName sclk, PinName nss, PinName reset,
GregCr 0:e6ceb13d2d05 46 PinName dio0, PinName dio1, PinName dio2, PinName dio3, PinName dio4, PinName dio5 )
GregCr 6:e7f02929cd3d 47 : Radio( txDone, txTimeout, rxDone, rxTimeout, rxError, fhssChangeChannel ),
GregCr 0:e6ceb13d2d05 48 spi( mosi, miso, sclk ),
GregCr 0:e6ceb13d2d05 49 nss( nss ),
GregCr 0:e6ceb13d2d05 50 reset( reset ),
GregCr 0:e6ceb13d2d05 51 dio0( dio0 ), dio1( dio1 ), dio2( dio2 ), dio3( dio3 ), dio4( dio4 ), dio5( dio5 ),
GregCr 0:e6ceb13d2d05 52 isRadioActive( false )
GregCr 0:e6ceb13d2d05 53 {
GregCr 0:e6ceb13d2d05 54 wait_ms( 10 );
GregCr 0:e6ceb13d2d05 55 this->rxTx = 0;
GregCr 0:e6ceb13d2d05 56 this->rxBuffer = new uint8_t[RX_BUFFER_SIZE];
GregCr 0:e6ceb13d2d05 57 previousOpMode = RF_OPMODE_STANDBY;
GregCr 0:e6ceb13d2d05 58
GregCr 0:e6ceb13d2d05 59 this->dioIrq = new DioIrqHandler[6];
GregCr 0:e6ceb13d2d05 60
GregCr 0:e6ceb13d2d05 61 this->dioIrq[0] = &SX1276::OnDio0Irq;
GregCr 0:e6ceb13d2d05 62 this->dioIrq[1] = &SX1276::OnDio1Irq;
GregCr 0:e6ceb13d2d05 63 this->dioIrq[2] = &SX1276::OnDio2Irq;
GregCr 0:e6ceb13d2d05 64 this->dioIrq[3] = &SX1276::OnDio3Irq;
GregCr 0:e6ceb13d2d05 65 this->dioIrq[4] = &SX1276::OnDio4Irq;
GregCr 0:e6ceb13d2d05 66 this->dioIrq[5] = NULL;
GregCr 4:f0ce52e94d3f 67
GregCr 4:f0ce52e94d3f 68 this->settings.State = IDLE;
GregCr 0:e6ceb13d2d05 69 }
GregCr 0:e6ceb13d2d05 70
GregCr 0:e6ceb13d2d05 71 SX1276::~SX1276( )
GregCr 0:e6ceb13d2d05 72 {
GregCr 0:e6ceb13d2d05 73 delete this->rxBuffer;
GregCr 0:e6ceb13d2d05 74 delete this->dioIrq;
GregCr 0:e6ceb13d2d05 75 }
GregCr 0:e6ceb13d2d05 76
GregCr 0:e6ceb13d2d05 77 void SX1276::RxChainCalibration( void )
GregCr 0:e6ceb13d2d05 78 {
GregCr 0:e6ceb13d2d05 79 uint8_t regPaConfigInitVal;
GregCr 0:e6ceb13d2d05 80 uint32_t initialFreq;
GregCr 0:e6ceb13d2d05 81
GregCr 0:e6ceb13d2d05 82 // Save context
GregCr 0:e6ceb13d2d05 83 regPaConfigInitVal = this->Read( REG_PACONFIG );
GregCr 0:e6ceb13d2d05 84 initialFreq = ( double )( ( ( uint32_t )this->Read( REG_FRFMSB ) << 16 ) |
GregCr 0:e6ceb13d2d05 85 ( ( uint32_t )this->Read( REG_FRFMID ) << 8 ) |
GregCr 0:e6ceb13d2d05 86 ( ( uint32_t )this->Read( REG_FRFLSB ) ) ) * ( double )FREQ_STEP;
GregCr 0:e6ceb13d2d05 87
GregCr 0:e6ceb13d2d05 88 // Cut the PA just in case, RFO output, power = -1 dBm
GregCr 0:e6ceb13d2d05 89 this->Write( REG_PACONFIG, 0x00 );
GregCr 0:e6ceb13d2d05 90
GregCr 0:e6ceb13d2d05 91 // Launch Rx chain calibration for LF band
GregCr 0:e6ceb13d2d05 92 Write ( REG_IMAGECAL, ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_MASK ) | RF_IMAGECAL_IMAGECAL_START );
GregCr 0:e6ceb13d2d05 93 while( ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_RUNNING ) == RF_IMAGECAL_IMAGECAL_RUNNING )
GregCr 0:e6ceb13d2d05 94 {
GregCr 0:e6ceb13d2d05 95 }
GregCr 0:e6ceb13d2d05 96
GregCr 0:e6ceb13d2d05 97 // Sets a Frequency in HF band
GregCr 0:e6ceb13d2d05 98 settings.Channel= 868000000 ;
GregCr 0:e6ceb13d2d05 99
GregCr 0:e6ceb13d2d05 100 // Launch Rx chain calibration for HF band
GregCr 0:e6ceb13d2d05 101 Write ( REG_IMAGECAL, ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_MASK ) | RF_IMAGECAL_IMAGECAL_START );
GregCr 0:e6ceb13d2d05 102 while( ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_RUNNING ) == RF_IMAGECAL_IMAGECAL_RUNNING )
GregCr 0:e6ceb13d2d05 103 {
GregCr 0:e6ceb13d2d05 104 }
GregCr 0:e6ceb13d2d05 105
GregCr 0:e6ceb13d2d05 106 // Restore context
GregCr 0:e6ceb13d2d05 107 this->Write( REG_PACONFIG, regPaConfigInitVal );
GregCr 0:e6ceb13d2d05 108 SetChannel( initialFreq );
GregCr 0:e6ceb13d2d05 109 }
GregCr 0:e6ceb13d2d05 110
GregCr 0:e6ceb13d2d05 111 RadioState SX1276::GetState( void )
GregCr 0:e6ceb13d2d05 112 {
GregCr 0:e6ceb13d2d05 113 return this->settings.State;
GregCr 0:e6ceb13d2d05 114 }
GregCr 0:e6ceb13d2d05 115
GregCr 0:e6ceb13d2d05 116 void SX1276::SetChannel( uint32_t freq )
GregCr 0:e6ceb13d2d05 117 {
GregCr 0:e6ceb13d2d05 118 this->settings.Channel = freq;
GregCr 0:e6ceb13d2d05 119 freq = ( uint32_t )( ( double )freq / ( double )FREQ_STEP );
GregCr 0:e6ceb13d2d05 120 Write( REG_FRFMSB, ( uint8_t )( ( freq >> 16 ) & 0xFF ) );
GregCr 0:e6ceb13d2d05 121 Write( REG_FRFMID, ( uint8_t )( ( freq >> 8 ) & 0xFF ) );
GregCr 0:e6ceb13d2d05 122 Write( REG_FRFLSB, ( uint8_t )( freq & 0xFF ) );
GregCr 0:e6ceb13d2d05 123 }
GregCr 0:e6ceb13d2d05 124
GregCr 0:e6ceb13d2d05 125 bool SX1276::IsChannelFree( ModemType modem, uint32_t freq, int8_t rssiThresh )
GregCr 0:e6ceb13d2d05 126 {
GregCr 0:e6ceb13d2d05 127 int8_t rssi = 0;
GregCr 0:e6ceb13d2d05 128
GregCr 0:e6ceb13d2d05 129 SetModem( modem );
GregCr 0:e6ceb13d2d05 130
GregCr 0:e6ceb13d2d05 131 SetChannel( freq );
GregCr 0:e6ceb13d2d05 132
GregCr 0:e6ceb13d2d05 133 SetOpMode( RF_OPMODE_RECEIVER );
GregCr 0:e6ceb13d2d05 134
GregCr 4:f0ce52e94d3f 135 wait_ms( 1 );
GregCr 0:e6ceb13d2d05 136
GregCr 0:e6ceb13d2d05 137 rssi = GetRssi( modem );
GregCr 0:e6ceb13d2d05 138
GregCr 0:e6ceb13d2d05 139 Sleep( );
GregCr 0:e6ceb13d2d05 140
GregCr 0:e6ceb13d2d05 141 if( rssi > rssiThresh )
GregCr 0:e6ceb13d2d05 142 {
GregCr 0:e6ceb13d2d05 143 return false;
GregCr 0:e6ceb13d2d05 144 }
GregCr 0:e6ceb13d2d05 145 return true;
GregCr 0:e6ceb13d2d05 146 }
GregCr 0:e6ceb13d2d05 147
GregCr 0:e6ceb13d2d05 148 uint32_t SX1276::Random( void )
GregCr 0:e6ceb13d2d05 149 {
GregCr 0:e6ceb13d2d05 150 uint8_t i;
GregCr 0:e6ceb13d2d05 151 uint32_t rnd = 0;
GregCr 0:e6ceb13d2d05 152
GregCr 0:e6ceb13d2d05 153 /*
GregCr 0:e6ceb13d2d05 154 * Radio setup for random number generation
GregCr 0:e6ceb13d2d05 155 */
GregCr 0:e6ceb13d2d05 156 // Set LoRa modem ON
GregCr 0:e6ceb13d2d05 157 SetModem( MODEM_LORA );
GregCr 0:e6ceb13d2d05 158
GregCr 0:e6ceb13d2d05 159 // Disable LoRa modem interrupts
GregCr 0:e6ceb13d2d05 160 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
GregCr 0:e6ceb13d2d05 161 RFLR_IRQFLAGS_RXDONE |
GregCr 0:e6ceb13d2d05 162 RFLR_IRQFLAGS_PAYLOADCRCERROR |
GregCr 0:e6ceb13d2d05 163 RFLR_IRQFLAGS_VALIDHEADER |
GregCr 0:e6ceb13d2d05 164 RFLR_IRQFLAGS_TXDONE |
GregCr 0:e6ceb13d2d05 165 RFLR_IRQFLAGS_CADDONE |
GregCr 0:e6ceb13d2d05 166 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
GregCr 0:e6ceb13d2d05 167 RFLR_IRQFLAGS_CADDETECTED );
GregCr 0:e6ceb13d2d05 168
GregCr 0:e6ceb13d2d05 169 // Set radio in continuous reception
GregCr 0:e6ceb13d2d05 170 SetOpMode( RF_OPMODE_RECEIVER );
GregCr 0:e6ceb13d2d05 171
GregCr 0:e6ceb13d2d05 172 for( i = 0; i < 32; i++ )
GregCr 0:e6ceb13d2d05 173 {
GregCr 4:f0ce52e94d3f 174 wait_ms( 1 );
GregCr 0:e6ceb13d2d05 175 // Unfiltered RSSI value reading. Only takes the LSB value
GregCr 0:e6ceb13d2d05 176 rnd |= ( ( uint32_t )Read( REG_LR_RSSIWIDEBAND ) & 0x01 ) << i;
GregCr 0:e6ceb13d2d05 177 }
GregCr 0:e6ceb13d2d05 178
GregCr 0:e6ceb13d2d05 179 Sleep( );
GregCr 0:e6ceb13d2d05 180
GregCr 0:e6ceb13d2d05 181 return rnd;
GregCr 0:e6ceb13d2d05 182 }
GregCr 0:e6ceb13d2d05 183
GregCr 0:e6ceb13d2d05 184 /*!
GregCr 0:e6ceb13d2d05 185 * Returns the known FSK bandwidth registers value
GregCr 0:e6ceb13d2d05 186 *
GregCr 0:e6ceb13d2d05 187 * \param [IN] bandwidth Bandwidth value in Hz
GregCr 0:e6ceb13d2d05 188 * \retval regValue Bandwidth register value.
GregCr 0:e6ceb13d2d05 189 */
GregCr 0:e6ceb13d2d05 190 uint8_t SX1276::GetFskBandwidthRegValue( uint32_t bandwidth )
GregCr 0:e6ceb13d2d05 191 {
GregCr 0:e6ceb13d2d05 192 uint8_t i;
GregCr 0:e6ceb13d2d05 193
GregCr 0:e6ceb13d2d05 194 for( i = 0; i < ( sizeof( FskBandwidths ) / sizeof( FskBandwidth_t ) ) - 1; i++ )
GregCr 0:e6ceb13d2d05 195 {
GregCr 0:e6ceb13d2d05 196 if( ( bandwidth >= FskBandwidths[i].bandwidth ) && ( bandwidth < FskBandwidths[i + 1].bandwidth ) )
GregCr 0:e6ceb13d2d05 197 {
GregCr 0:e6ceb13d2d05 198 return FskBandwidths[i].RegValue;
GregCr 0:e6ceb13d2d05 199 }
GregCr 0:e6ceb13d2d05 200 }
GregCr 0:e6ceb13d2d05 201 // ERROR: Value not found
GregCr 0:e6ceb13d2d05 202 while( 1 );
GregCr 0:e6ceb13d2d05 203 }
GregCr 0:e6ceb13d2d05 204
GregCr 0:e6ceb13d2d05 205 void SX1276::SetRxConfig( ModemType modem, uint32_t bandwidth,
GregCr 0:e6ceb13d2d05 206 uint32_t datarate, uint8_t coderate,
GregCr 0:e6ceb13d2d05 207 uint32_t bandwidthAfc, uint16_t preambleLen,
GregCr 0:e6ceb13d2d05 208 uint16_t symbTimeout, bool fixLen,
GregCr 6:e7f02929cd3d 209 bool crcOn, bool FreqHopOn, uint8_t HopPeriod,
GregCr 6:e7f02929cd3d 210 bool iqInverted, bool rxContinuous )
GregCr 0:e6ceb13d2d05 211 {
GregCr 0:e6ceb13d2d05 212 SetModem( modem );
GregCr 0:e6ceb13d2d05 213
GregCr 0:e6ceb13d2d05 214 switch( modem )
GregCr 0:e6ceb13d2d05 215 {
GregCr 0:e6ceb13d2d05 216 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 217 {
GregCr 0:e6ceb13d2d05 218 this->settings.Fsk.Bandwidth = bandwidth;
GregCr 0:e6ceb13d2d05 219 this->settings.Fsk.Datarate = datarate;
GregCr 0:e6ceb13d2d05 220 this->settings.Fsk.BandwidthAfc = bandwidthAfc;
GregCr 0:e6ceb13d2d05 221 this->settings.Fsk.FixLen = fixLen;
GregCr 0:e6ceb13d2d05 222 this->settings.Fsk.CrcOn = crcOn;
GregCr 0:e6ceb13d2d05 223 this->settings.Fsk.IqInverted = iqInverted;
GregCr 0:e6ceb13d2d05 224 this->settings.Fsk.RxContinuous = rxContinuous;
GregCr 0:e6ceb13d2d05 225 this->settings.Fsk.PreambleLen = preambleLen;
GregCr 0:e6ceb13d2d05 226
GregCr 0:e6ceb13d2d05 227 datarate = ( uint16_t )( ( double )XTAL_FREQ / ( double )datarate );
GregCr 0:e6ceb13d2d05 228 Write( REG_BITRATEMSB, ( uint8_t )( datarate >> 8 ) );
GregCr 0:e6ceb13d2d05 229 Write( REG_BITRATELSB, ( uint8_t )( datarate & 0xFF ) );
GregCr 0:e6ceb13d2d05 230
GregCr 0:e6ceb13d2d05 231 Write( REG_RXBW, GetFskBandwidthRegValue( bandwidth ) );
GregCr 0:e6ceb13d2d05 232 Write( REG_AFCBW, GetFskBandwidthRegValue( bandwidthAfc ) );
GregCr 0:e6ceb13d2d05 233
GregCr 0:e6ceb13d2d05 234 Write( REG_LR_PREAMBLEMSB, ( uint8_t )( ( preambleLen >> 8 ) & 0xFF ) );
GregCr 0:e6ceb13d2d05 235 Write( REG_LR_PREAMBLELSB, ( uint8_t )( preambleLen & 0xFF ) );
GregCr 0:e6ceb13d2d05 236
GregCr 0:e6ceb13d2d05 237 Write( REG_PACKETCONFIG1,
GregCr 0:e6ceb13d2d05 238 ( Read( REG_PACKETCONFIG1 ) &
GregCr 0:e6ceb13d2d05 239 RF_PACKETCONFIG1_CRC_MASK &
GregCr 0:e6ceb13d2d05 240 RF_PACKETCONFIG1_PACKETFORMAT_MASK ) |
GregCr 0:e6ceb13d2d05 241 ( ( fixLen == 1 ) ? RF_PACKETCONFIG1_PACKETFORMAT_FIXED : RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE ) |
GregCr 0:e6ceb13d2d05 242 ( crcOn << 4 ) );
GregCr 0:e6ceb13d2d05 243 }
GregCr 0:e6ceb13d2d05 244 break;
GregCr 0:e6ceb13d2d05 245 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 246 {
GregCr 0:e6ceb13d2d05 247 if( bandwidth > 2 )
GregCr 0:e6ceb13d2d05 248 {
GregCr 0:e6ceb13d2d05 249 // Fatal error: When using LoRa modem only bandwidths 125, 250 and 500 kHz are supported
GregCr 0:e6ceb13d2d05 250 while( 1 );
GregCr 0:e6ceb13d2d05 251 }
GregCr 0:e6ceb13d2d05 252 bandwidth += 7;
GregCr 0:e6ceb13d2d05 253 this->settings.LoRa.Bandwidth = bandwidth;
GregCr 0:e6ceb13d2d05 254 this->settings.LoRa.Datarate = datarate;
GregCr 0:e6ceb13d2d05 255 this->settings.LoRa.Coderate = coderate;
GregCr 0:e6ceb13d2d05 256 this->settings.LoRa.FixLen = fixLen;
GregCr 0:e6ceb13d2d05 257 this->settings.LoRa.CrcOn = crcOn;
GregCr 6:e7f02929cd3d 258 this->settings.LoRa.FreqHopOn = FreqHopOn;
GregCr 6:e7f02929cd3d 259 this->settings.LoRa.HopPeriod = HopPeriod;
GregCr 0:e6ceb13d2d05 260 this->settings.LoRa.IqInverted = iqInverted;
GregCr 0:e6ceb13d2d05 261 this->settings.LoRa.RxContinuous = rxContinuous;
GregCr 0:e6ceb13d2d05 262
GregCr 0:e6ceb13d2d05 263 if( datarate > 12 )
GregCr 0:e6ceb13d2d05 264 {
GregCr 0:e6ceb13d2d05 265 datarate = 12;
GregCr 0:e6ceb13d2d05 266 }
GregCr 0:e6ceb13d2d05 267 else if( datarate < 6 )
GregCr 0:e6ceb13d2d05 268 {
GregCr 0:e6ceb13d2d05 269 datarate = 6;
GregCr 0:e6ceb13d2d05 270 }
GregCr 0:e6ceb13d2d05 271
GregCr 0:e6ceb13d2d05 272 if( ( ( bandwidth == 7 ) && ( ( datarate == 11 ) || ( datarate == 12 ) ) ) ||
GregCr 0:e6ceb13d2d05 273 ( ( bandwidth == 8 ) && ( datarate == 12 ) ) )
GregCr 0:e6ceb13d2d05 274 {
GregCr 0:e6ceb13d2d05 275 this->settings.LoRa.LowDatarateOptimize = 0x01;
GregCr 0:e6ceb13d2d05 276 }
GregCr 0:e6ceb13d2d05 277 else
GregCr 0:e6ceb13d2d05 278 {
GregCr 0:e6ceb13d2d05 279 this->settings.LoRa.LowDatarateOptimize = 0x00;
GregCr 0:e6ceb13d2d05 280 }
GregCr 0:e6ceb13d2d05 281
GregCr 0:e6ceb13d2d05 282 Write( REG_LR_MODEMCONFIG1,
GregCr 0:e6ceb13d2d05 283 ( Read( REG_LR_MODEMCONFIG1 ) &
GregCr 0:e6ceb13d2d05 284 RFLR_MODEMCONFIG1_BW_MASK &
GregCr 0:e6ceb13d2d05 285 RFLR_MODEMCONFIG1_CODINGRATE_MASK &
GregCr 0:e6ceb13d2d05 286 RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK ) |
GregCr 0:e6ceb13d2d05 287 ( bandwidth << 4 ) | ( coderate << 1 ) |
GregCr 0:e6ceb13d2d05 288 fixLen );
GregCr 0:e6ceb13d2d05 289
GregCr 0:e6ceb13d2d05 290 Write( REG_LR_MODEMCONFIG2,
GregCr 0:e6ceb13d2d05 291 ( Read( REG_LR_MODEMCONFIG2 ) &
GregCr 0:e6ceb13d2d05 292 RFLR_MODEMCONFIG2_SF_MASK &
GregCr 0:e6ceb13d2d05 293 RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK &
GregCr 0:e6ceb13d2d05 294 RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ) |
GregCr 0:e6ceb13d2d05 295 ( datarate << 4 ) | ( crcOn << 2 ) |
GregCr 0:e6ceb13d2d05 296 ( ( symbTimeout >> 8 ) & ~RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ) );
GregCr 0:e6ceb13d2d05 297
GregCr 0:e6ceb13d2d05 298 Write( REG_LR_MODEMCONFIG3,
GregCr 0:e6ceb13d2d05 299 ( Read( REG_LR_MODEMCONFIG3 ) &
GregCr 0:e6ceb13d2d05 300 RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 301 ( this->settings.LoRa.LowDatarateOptimize << 3 ) );
GregCr 0:e6ceb13d2d05 302
GregCr 0:e6ceb13d2d05 303 Write( REG_LR_SYMBTIMEOUTLSB, ( uint8_t )( symbTimeout & 0xFF ) );
GregCr 0:e6ceb13d2d05 304
GregCr 0:e6ceb13d2d05 305 Write( REG_LR_PREAMBLEMSB, ( uint8_t )( ( preambleLen >> 8 ) & 0xFF ) );
GregCr 0:e6ceb13d2d05 306 Write( REG_LR_PREAMBLELSB, ( uint8_t )( preambleLen & 0xFF ) );
GregCr 0:e6ceb13d2d05 307
GregCr 6:e7f02929cd3d 308 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 309 {
GregCr 6:e7f02929cd3d 310 Write( REG_LR_PLLHOP, ( Read( REG_LR_PLLHOP ) & RFLR_PLLHOP_FASTHOP_MASK ) | RFLR_PLLHOP_FASTHOP_ON );
GregCr 6:e7f02929cd3d 311 Write( REG_LR_HOPPERIOD, this->settings.LoRa.HopPeriod );
GregCr 6:e7f02929cd3d 312 }
GregCr 6:e7f02929cd3d 313
GregCr 0:e6ceb13d2d05 314 if( datarate == 6 )
GregCr 0:e6ceb13d2d05 315 {
GregCr 0:e6ceb13d2d05 316 Write( REG_LR_DETECTOPTIMIZE,
GregCr 0:e6ceb13d2d05 317 ( Read( REG_LR_DETECTOPTIMIZE ) &
GregCr 0:e6ceb13d2d05 318 RFLR_DETECTIONOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 319 RFLR_DETECTIONOPTIMIZE_SF6 );
GregCr 0:e6ceb13d2d05 320 Write( REG_LR_DETECTIONTHRESHOLD,
GregCr 0:e6ceb13d2d05 321 RFLR_DETECTIONTHRESH_SF6 );
GregCr 0:e6ceb13d2d05 322 }
GregCr 0:e6ceb13d2d05 323 else
GregCr 0:e6ceb13d2d05 324 {
GregCr 0:e6ceb13d2d05 325 Write( REG_LR_DETECTOPTIMIZE,
GregCr 0:e6ceb13d2d05 326 ( Read( REG_LR_DETECTOPTIMIZE ) &
GregCr 0:e6ceb13d2d05 327 RFLR_DETECTIONOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 328 RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 );
GregCr 0:e6ceb13d2d05 329 Write( REG_LR_DETECTIONTHRESHOLD,
GregCr 0:e6ceb13d2d05 330 RFLR_DETECTIONTHRESH_SF7_TO_SF12 );
GregCr 0:e6ceb13d2d05 331 }
GregCr 0:e6ceb13d2d05 332 }
GregCr 0:e6ceb13d2d05 333 break;
GregCr 0:e6ceb13d2d05 334 }
GregCr 0:e6ceb13d2d05 335 }
GregCr 0:e6ceb13d2d05 336
GregCr 0:e6ceb13d2d05 337 void SX1276::SetTxConfig( ModemType modem, int8_t power, uint32_t fdev,
GregCr 0:e6ceb13d2d05 338 uint32_t bandwidth, uint32_t datarate,
GregCr 0:e6ceb13d2d05 339 uint8_t coderate, uint16_t preambleLen,
GregCr 6:e7f02929cd3d 340 bool fixLen, bool crcOn, bool FreqHopOn,
GregCr 6:e7f02929cd3d 341 uint8_t HopPeriod, bool iqInverted, uint32_t timeout )
GregCr 0:e6ceb13d2d05 342 {
GregCr 0:e6ceb13d2d05 343 uint8_t paConfig = 0;
GregCr 0:e6ceb13d2d05 344 uint8_t paDac = 0;
GregCr 0:e6ceb13d2d05 345
GregCr 0:e6ceb13d2d05 346 SetModem( modem );
GregCr 0:e6ceb13d2d05 347
GregCr 0:e6ceb13d2d05 348 paConfig = Read( REG_PACONFIG );
GregCr 0:e6ceb13d2d05 349 paDac = Read( REG_PADAC );
GregCr 0:e6ceb13d2d05 350
GregCr 0:e6ceb13d2d05 351 paConfig = ( paConfig & RF_PACONFIG_PASELECT_MASK ) | GetPaSelect( this->settings.Channel );
GregCr 0:e6ceb13d2d05 352 paConfig = ( paConfig & RF_PACONFIG_MAX_POWER_MASK ) | 0x70;
GregCr 0:e6ceb13d2d05 353
GregCr 0:e6ceb13d2d05 354 if( ( paConfig & RF_PACONFIG_PASELECT_PABOOST ) == RF_PACONFIG_PASELECT_PABOOST )
GregCr 0:e6ceb13d2d05 355 {
GregCr 0:e6ceb13d2d05 356 if( power > 17 )
GregCr 0:e6ceb13d2d05 357 {
GregCr 0:e6ceb13d2d05 358 paDac = ( paDac & RF_PADAC_20DBM_MASK ) | RF_PADAC_20DBM_ON;
GregCr 0:e6ceb13d2d05 359 }
GregCr 0:e6ceb13d2d05 360 else
GregCr 0:e6ceb13d2d05 361 {
GregCr 0:e6ceb13d2d05 362 paDac = ( paDac & RF_PADAC_20DBM_MASK ) | RF_PADAC_20DBM_OFF;
GregCr 0:e6ceb13d2d05 363 }
GregCr 0:e6ceb13d2d05 364 if( ( paDac & RF_PADAC_20DBM_ON ) == RF_PADAC_20DBM_ON )
GregCr 0:e6ceb13d2d05 365 {
GregCr 0:e6ceb13d2d05 366 if( power < 5 )
GregCr 0:e6ceb13d2d05 367 {
GregCr 0:e6ceb13d2d05 368 power = 5;
GregCr 0:e6ceb13d2d05 369 }
GregCr 0:e6ceb13d2d05 370 if( power > 20 )
GregCr 0:e6ceb13d2d05 371 {
GregCr 0:e6ceb13d2d05 372 power = 20;
GregCr 0:e6ceb13d2d05 373 }
GregCr 0:e6ceb13d2d05 374 paConfig = ( paConfig & RF_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power - 5 ) & 0x0F );
GregCr 0:e6ceb13d2d05 375 }
GregCr 0:e6ceb13d2d05 376 else
GregCr 0:e6ceb13d2d05 377 {
GregCr 0:e6ceb13d2d05 378 if( power < 2 )
GregCr 0:e6ceb13d2d05 379 {
GregCr 0:e6ceb13d2d05 380 power = 2;
GregCr 0:e6ceb13d2d05 381 }
GregCr 0:e6ceb13d2d05 382 if( power > 17 )
GregCr 0:e6ceb13d2d05 383 {
GregCr 0:e6ceb13d2d05 384 power = 17;
GregCr 0:e6ceb13d2d05 385 }
GregCr 0:e6ceb13d2d05 386 paConfig = ( paConfig & RF_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power - 2 ) & 0x0F );
GregCr 0:e6ceb13d2d05 387 }
GregCr 0:e6ceb13d2d05 388 }
GregCr 0:e6ceb13d2d05 389 else
GregCr 0:e6ceb13d2d05 390 {
GregCr 0:e6ceb13d2d05 391 if( power < -1 )
GregCr 0:e6ceb13d2d05 392 {
GregCr 0:e6ceb13d2d05 393 power = -1;
GregCr 0:e6ceb13d2d05 394 }
GregCr 0:e6ceb13d2d05 395 if( power > 14 )
GregCr 0:e6ceb13d2d05 396 {
GregCr 0:e6ceb13d2d05 397 power = 14;
GregCr 0:e6ceb13d2d05 398 }
GregCr 0:e6ceb13d2d05 399 paConfig = ( paConfig & RF_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power + 1 ) & 0x0F );
GregCr 0:e6ceb13d2d05 400 }
GregCr 0:e6ceb13d2d05 401 Write( REG_PACONFIG, paConfig );
GregCr 0:e6ceb13d2d05 402 Write( REG_PADAC, paDac );
GregCr 0:e6ceb13d2d05 403
GregCr 0:e6ceb13d2d05 404 switch( modem )
GregCr 0:e6ceb13d2d05 405 {
GregCr 0:e6ceb13d2d05 406 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 407 {
GregCr 0:e6ceb13d2d05 408 this->settings.Fsk.Power = power;
GregCr 0:e6ceb13d2d05 409 this->settings.Fsk.Fdev = fdev;
GregCr 0:e6ceb13d2d05 410 this->settings.Fsk.Bandwidth = bandwidth;
GregCr 0:e6ceb13d2d05 411 this->settings.Fsk.Datarate = datarate;
GregCr 0:e6ceb13d2d05 412 this->settings.Fsk.PreambleLen = preambleLen;
GregCr 0:e6ceb13d2d05 413 this->settings.Fsk.FixLen = fixLen;
GregCr 0:e6ceb13d2d05 414 this->settings.Fsk.CrcOn = crcOn;
GregCr 0:e6ceb13d2d05 415 this->settings.Fsk.IqInverted = iqInverted;
GregCr 0:e6ceb13d2d05 416 this->settings.Fsk.TxTimeout = timeout;
GregCr 0:e6ceb13d2d05 417
GregCr 0:e6ceb13d2d05 418 fdev = ( uint16_t )( ( double )fdev / ( double )FREQ_STEP );
GregCr 0:e6ceb13d2d05 419 Write( REG_FDEVMSB, ( uint8_t )( fdev >> 8 ) );
GregCr 0:e6ceb13d2d05 420 Write( REG_FDEVLSB, ( uint8_t )( fdev & 0xFF ) );
GregCr 0:e6ceb13d2d05 421
GregCr 0:e6ceb13d2d05 422 datarate = ( uint16_t )( ( double )XTAL_FREQ / ( double )datarate );
GregCr 0:e6ceb13d2d05 423 Write( REG_BITRATEMSB, ( uint8_t )( datarate >> 8 ) );
GregCr 0:e6ceb13d2d05 424 Write( REG_BITRATELSB, ( uint8_t )( datarate & 0xFF ) );
GregCr 0:e6ceb13d2d05 425
GregCr 0:e6ceb13d2d05 426 Write( REG_PREAMBLEMSB, ( preambleLen >> 8 ) & 0x00FF );
GregCr 0:e6ceb13d2d05 427 Write( REG_PREAMBLELSB, preambleLen & 0xFF );
GregCr 0:e6ceb13d2d05 428
GregCr 0:e6ceb13d2d05 429 Write( REG_PACKETCONFIG1,
GregCr 0:e6ceb13d2d05 430 ( Read( REG_PACKETCONFIG1 ) &
GregCr 0:e6ceb13d2d05 431 RF_PACKETCONFIG1_CRC_MASK &
GregCr 0:e6ceb13d2d05 432 RF_PACKETCONFIG1_PACKETFORMAT_MASK ) |
GregCr 0:e6ceb13d2d05 433 ( ( fixLen == 1 ) ? RF_PACKETCONFIG1_PACKETFORMAT_FIXED : RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE ) |
GregCr 0:e6ceb13d2d05 434 ( crcOn << 4 ) );
GregCr 0:e6ceb13d2d05 435
GregCr 0:e6ceb13d2d05 436 }
GregCr 0:e6ceb13d2d05 437 break;
GregCr 0:e6ceb13d2d05 438 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 439 {
GregCr 0:e6ceb13d2d05 440 this->settings.LoRa.Power = power;
GregCr 0:e6ceb13d2d05 441 if( bandwidth > 2 )
GregCr 0:e6ceb13d2d05 442 {
GregCr 0:e6ceb13d2d05 443 // Fatal error: When using LoRa modem only bandwidths 125, 250 and 500 kHz are supported
GregCr 0:e6ceb13d2d05 444 while( 1 );
GregCr 0:e6ceb13d2d05 445 }
GregCr 0:e6ceb13d2d05 446 bandwidth += 7;
GregCr 0:e6ceb13d2d05 447 this->settings.LoRa.Bandwidth = bandwidth;
GregCr 0:e6ceb13d2d05 448 this->settings.LoRa.Datarate = datarate;
GregCr 0:e6ceb13d2d05 449 this->settings.LoRa.Coderate = coderate;
GregCr 0:e6ceb13d2d05 450 this->settings.LoRa.PreambleLen = preambleLen;
GregCr 0:e6ceb13d2d05 451 this->settings.LoRa.FixLen = fixLen;
GregCr 0:e6ceb13d2d05 452 this->settings.LoRa.CrcOn = crcOn;
GregCr 6:e7f02929cd3d 453 this->settings.LoRa.FreqHopOn = FreqHopOn;
GregCr 6:e7f02929cd3d 454 this->settings.LoRa.HopPeriod = HopPeriod;
GregCr 0:e6ceb13d2d05 455 this->settings.LoRa.IqInverted = iqInverted;
GregCr 0:e6ceb13d2d05 456 this->settings.LoRa.TxTimeout = timeout;
GregCr 0:e6ceb13d2d05 457
GregCr 0:e6ceb13d2d05 458 if( datarate > 12 )
GregCr 0:e6ceb13d2d05 459 {
GregCr 0:e6ceb13d2d05 460 datarate = 12;
GregCr 0:e6ceb13d2d05 461 }
GregCr 0:e6ceb13d2d05 462 else if( datarate < 6 )
GregCr 0:e6ceb13d2d05 463 {
GregCr 0:e6ceb13d2d05 464 datarate = 6;
GregCr 0:e6ceb13d2d05 465 }
GregCr 0:e6ceb13d2d05 466 if( ( ( bandwidth == 7 ) && ( ( datarate == 11 ) || ( datarate == 12 ) ) ) ||
GregCr 0:e6ceb13d2d05 467 ( ( bandwidth == 8 ) && ( datarate == 12 ) ) )
GregCr 0:e6ceb13d2d05 468 {
GregCr 0:e6ceb13d2d05 469 this->settings.LoRa.LowDatarateOptimize = 0x01;
GregCr 0:e6ceb13d2d05 470 }
GregCr 0:e6ceb13d2d05 471 else
GregCr 0:e6ceb13d2d05 472 {
GregCr 0:e6ceb13d2d05 473 this->settings.LoRa.LowDatarateOptimize = 0x00;
GregCr 0:e6ceb13d2d05 474 }
GregCr 6:e7f02929cd3d 475
GregCr 6:e7f02929cd3d 476 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 477 {
GregCr 6:e7f02929cd3d 478 Write( REG_LR_PLLHOP, ( Read( REG_LR_PLLHOP ) & RFLR_PLLHOP_FASTHOP_MASK ) | RFLR_PLLHOP_FASTHOP_ON );
GregCr 6:e7f02929cd3d 479 Write( REG_LR_HOPPERIOD, this->settings.LoRa.HopPeriod );
GregCr 6:e7f02929cd3d 480 }
GregCr 6:e7f02929cd3d 481
GregCr 0:e6ceb13d2d05 482 Write( REG_LR_MODEMCONFIG1,
GregCr 0:e6ceb13d2d05 483 ( Read( REG_LR_MODEMCONFIG1 ) &
GregCr 0:e6ceb13d2d05 484 RFLR_MODEMCONFIG1_BW_MASK &
GregCr 0:e6ceb13d2d05 485 RFLR_MODEMCONFIG1_CODINGRATE_MASK &
GregCr 0:e6ceb13d2d05 486 RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK ) |
GregCr 0:e6ceb13d2d05 487 ( bandwidth << 4 ) | ( coderate << 1 ) |
GregCr 0:e6ceb13d2d05 488 fixLen );
GregCr 0:e6ceb13d2d05 489
GregCr 0:e6ceb13d2d05 490 Write( REG_LR_MODEMCONFIG2,
GregCr 0:e6ceb13d2d05 491 ( Read( REG_LR_MODEMCONFIG2 ) &
GregCr 0:e6ceb13d2d05 492 RFLR_MODEMCONFIG2_SF_MASK &
GregCr 0:e6ceb13d2d05 493 RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK ) |
GregCr 0:e6ceb13d2d05 494 ( datarate << 4 ) | ( crcOn << 2 ) );
GregCr 0:e6ceb13d2d05 495
GregCr 0:e6ceb13d2d05 496 Write( REG_LR_MODEMCONFIG3,
GregCr 0:e6ceb13d2d05 497 ( Read( REG_LR_MODEMCONFIG3 ) &
GregCr 0:e6ceb13d2d05 498 RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 499 ( this->settings.LoRa.LowDatarateOptimize << 3 ) );
GregCr 0:e6ceb13d2d05 500
GregCr 0:e6ceb13d2d05 501 Write( REG_LR_PREAMBLEMSB, ( preambleLen >> 8 ) & 0x00FF );
GregCr 0:e6ceb13d2d05 502 Write( REG_LR_PREAMBLELSB, preambleLen & 0xFF );
GregCr 0:e6ceb13d2d05 503
GregCr 0:e6ceb13d2d05 504 if( datarate == 6 )
GregCr 0:e6ceb13d2d05 505 {
GregCr 0:e6ceb13d2d05 506 Write( REG_LR_DETECTOPTIMIZE,
GregCr 0:e6ceb13d2d05 507 ( Read( REG_LR_DETECTOPTIMIZE ) &
GregCr 0:e6ceb13d2d05 508 RFLR_DETECTIONOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 509 RFLR_DETECTIONOPTIMIZE_SF6 );
GregCr 0:e6ceb13d2d05 510 Write( REG_LR_DETECTIONTHRESHOLD,
GregCr 0:e6ceb13d2d05 511 RFLR_DETECTIONTHRESH_SF6 );
GregCr 0:e6ceb13d2d05 512 }
GregCr 0:e6ceb13d2d05 513 else
GregCr 0:e6ceb13d2d05 514 {
GregCr 0:e6ceb13d2d05 515 Write( REG_LR_DETECTOPTIMIZE,
GregCr 0:e6ceb13d2d05 516 ( Read( REG_LR_DETECTOPTIMIZE ) &
GregCr 0:e6ceb13d2d05 517 RFLR_DETECTIONOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 518 RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 );
GregCr 0:e6ceb13d2d05 519 Write( REG_LR_DETECTIONTHRESHOLD,
GregCr 0:e6ceb13d2d05 520 RFLR_DETECTIONTHRESH_SF7_TO_SF12 );
GregCr 0:e6ceb13d2d05 521 }
GregCr 0:e6ceb13d2d05 522 }
GregCr 0:e6ceb13d2d05 523 break;
GregCr 0:e6ceb13d2d05 524 }
GregCr 0:e6ceb13d2d05 525 }
GregCr 0:e6ceb13d2d05 526
GregCr 0:e6ceb13d2d05 527 double SX1276::TimeOnAir( ModemType modem, uint8_t pktLen )
GregCr 0:e6ceb13d2d05 528 {
GregCr 0:e6ceb13d2d05 529 double airTime = 0.0;
GregCr 0:e6ceb13d2d05 530
GregCr 0:e6ceb13d2d05 531 switch( modem )
GregCr 0:e6ceb13d2d05 532 {
GregCr 0:e6ceb13d2d05 533 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 534 {
GregCr 4:f0ce52e94d3f 535 airTime = ceil( ( 8 * ( this->settings.Fsk.PreambleLen +
GregCr 0:e6ceb13d2d05 536 ( ( Read( REG_SYNCCONFIG ) & ~RF_SYNCCONFIG_SYNCSIZE_MASK ) + 1 ) +
GregCr 0:e6ceb13d2d05 537 ( ( this->settings.Fsk.FixLen == 0x01 ) ? 0.0 : 1.0 ) +
GregCr 0:e6ceb13d2d05 538 ( ( ( Read( REG_PACKETCONFIG1 ) & ~RF_PACKETCONFIG1_ADDRSFILTERING_MASK ) != 0x00 ) ? 1.0 : 0 ) +
GregCr 0:e6ceb13d2d05 539 pktLen +
GregCr 0:e6ceb13d2d05 540 ( ( this->settings.Fsk.CrcOn == 0x01 ) ? 2.0 : 0 ) ) /
GregCr 0:e6ceb13d2d05 541 this->settings.Fsk.Datarate ) * 1e6 );
GregCr 0:e6ceb13d2d05 542 }
GregCr 0:e6ceb13d2d05 543 break;
GregCr 0:e6ceb13d2d05 544 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 545 {
GregCr 0:e6ceb13d2d05 546 double bw = 0.0;
GregCr 0:e6ceb13d2d05 547 // REMARK: When using LoRa modem only bandwidths 125, 250 and 500 kHz are supported
GregCr 0:e6ceb13d2d05 548 switch( this->settings.LoRa.Bandwidth )
GregCr 0:e6ceb13d2d05 549 {
GregCr 0:e6ceb13d2d05 550 //case 0: // 7.8 kHz
GregCr 0:e6ceb13d2d05 551 // bw = 78e2;
GregCr 0:e6ceb13d2d05 552 // break;
GregCr 0:e6ceb13d2d05 553 //case 1: // 10.4 kHz
GregCr 0:e6ceb13d2d05 554 // bw = 104e2;
GregCr 0:e6ceb13d2d05 555 // break;
GregCr 0:e6ceb13d2d05 556 //case 2: // 15.6 kHz
GregCr 0:e6ceb13d2d05 557 // bw = 156e2;
GregCr 0:e6ceb13d2d05 558 // break;
GregCr 0:e6ceb13d2d05 559 //case 3: // 20.8 kHz
GregCr 0:e6ceb13d2d05 560 // bw = 208e2;
GregCr 0:e6ceb13d2d05 561 // break;
GregCr 0:e6ceb13d2d05 562 //case 4: // 31.2 kHz
GregCr 0:e6ceb13d2d05 563 // bw = 312e2;
GregCr 0:e6ceb13d2d05 564 // break;
GregCr 0:e6ceb13d2d05 565 //case 5: // 41.4 kHz
GregCr 0:e6ceb13d2d05 566 // bw = 414e2;
GregCr 0:e6ceb13d2d05 567 // break;
GregCr 0:e6ceb13d2d05 568 //case 6: // 62.5 kHz
GregCr 0:e6ceb13d2d05 569 // bw = 625e2;
GregCr 0:e6ceb13d2d05 570 // break;
GregCr 0:e6ceb13d2d05 571 case 7: // 125 kHz
GregCr 0:e6ceb13d2d05 572 bw = 125e3;
GregCr 0:e6ceb13d2d05 573 break;
GregCr 0:e6ceb13d2d05 574 case 8: // 250 kHz
GregCr 0:e6ceb13d2d05 575 bw = 250e3;
GregCr 0:e6ceb13d2d05 576 break;
GregCr 0:e6ceb13d2d05 577 case 9: // 500 kHz
GregCr 0:e6ceb13d2d05 578 bw = 500e3;
GregCr 0:e6ceb13d2d05 579 break;
GregCr 0:e6ceb13d2d05 580 }
GregCr 0:e6ceb13d2d05 581
GregCr 0:e6ceb13d2d05 582 // Symbol rate : time for one symbol (secs)
GregCr 0:e6ceb13d2d05 583 double rs = bw / ( 1 << this->settings.LoRa.Datarate );
GregCr 0:e6ceb13d2d05 584 double ts = 1 / rs;
GregCr 0:e6ceb13d2d05 585 // time of preamble
GregCr 0:e6ceb13d2d05 586 double tPreamble = ( this->settings.LoRa.PreambleLen + 4.25 ) * ts;
GregCr 0:e6ceb13d2d05 587 // Symbol length of payload and time
GregCr 0:e6ceb13d2d05 588 double tmp = ceil( ( 8 * pktLen - 4 * this->settings.LoRa.Datarate +
GregCr 0:e6ceb13d2d05 589 28 + 16 * this->settings.LoRa.CrcOn -
GregCr 0:e6ceb13d2d05 590 ( this->settings.LoRa.FixLen ? 20 : 0 ) ) /
GregCr 0:e6ceb13d2d05 591 ( double )( 4 * this->settings.LoRa.Datarate -
GregCr 0:e6ceb13d2d05 592 ( ( this->settings.LoRa.LowDatarateOptimize > 0 ) ? 8 : 0 ) ) ) *
GregCr 0:e6ceb13d2d05 593 ( this->settings.LoRa.Coderate + 4 );
GregCr 0:e6ceb13d2d05 594 double nPayload = 8 + ( ( tmp > 0 ) ? tmp : 0 );
GregCr 0:e6ceb13d2d05 595 double tPayload = nPayload * ts;
GregCr 0:e6ceb13d2d05 596 // Time on air
GregCr 0:e6ceb13d2d05 597 double tOnAir = tPreamble + tPayload;
GregCr 0:e6ceb13d2d05 598 // return us secs
GregCr 0:e6ceb13d2d05 599 airTime = floor( tOnAir * 1e6 + 0.999 );
GregCr 0:e6ceb13d2d05 600 }
GregCr 0:e6ceb13d2d05 601 break;
GregCr 0:e6ceb13d2d05 602 }
GregCr 0:e6ceb13d2d05 603 return airTime;
GregCr 0:e6ceb13d2d05 604 }
GregCr 0:e6ceb13d2d05 605
GregCr 0:e6ceb13d2d05 606 void SX1276::Send( uint8_t *buffer, uint8_t size )
GregCr 0:e6ceb13d2d05 607 {
GregCr 0:e6ceb13d2d05 608 uint32_t txTimeout = 0;
GregCr 0:e6ceb13d2d05 609
GregCr 5:11ec8a6ba4f0 610 this->settings.State = IDLE;
GregCr 5:11ec8a6ba4f0 611
GregCr 0:e6ceb13d2d05 612 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 613 {
GregCr 0:e6ceb13d2d05 614 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 615 {
GregCr 0:e6ceb13d2d05 616 this->settings.FskPacketHandler.NbBytes = 0;
GregCr 0:e6ceb13d2d05 617 this->settings.FskPacketHandler.Size = size;
GregCr 0:e6ceb13d2d05 618
GregCr 0:e6ceb13d2d05 619 if( this->settings.Fsk.FixLen == false )
GregCr 0:e6ceb13d2d05 620 {
GregCr 0:e6ceb13d2d05 621 WriteFifo( ( uint8_t* )&size, 1 );
GregCr 0:e6ceb13d2d05 622 }
GregCr 0:e6ceb13d2d05 623 else
GregCr 0:e6ceb13d2d05 624 {
GregCr 0:e6ceb13d2d05 625 Write( REG_PAYLOADLENGTH, size );
GregCr 0:e6ceb13d2d05 626 }
GregCr 0:e6ceb13d2d05 627
GregCr 0:e6ceb13d2d05 628 if( ( size > 0 ) && ( size <= 64 ) )
GregCr 0:e6ceb13d2d05 629 {
GregCr 0:e6ceb13d2d05 630 this->settings.FskPacketHandler.ChunkSize = size;
GregCr 0:e6ceb13d2d05 631 }
GregCr 0:e6ceb13d2d05 632 else
GregCr 0:e6ceb13d2d05 633 {
GregCr 0:e6ceb13d2d05 634 this->settings.FskPacketHandler.ChunkSize = 32;
GregCr 0:e6ceb13d2d05 635 }
GregCr 0:e6ceb13d2d05 636
GregCr 0:e6ceb13d2d05 637 // Write payload buffer
GregCr 0:e6ceb13d2d05 638 WriteFifo( buffer, this->settings.FskPacketHandler.ChunkSize );
GregCr 0:e6ceb13d2d05 639 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.ChunkSize;
GregCr 0:e6ceb13d2d05 640 txTimeout = this->settings.Fsk.TxTimeout;
GregCr 0:e6ceb13d2d05 641 }
GregCr 0:e6ceb13d2d05 642 break;
GregCr 0:e6ceb13d2d05 643 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 644 {
GregCr 0:e6ceb13d2d05 645 if( this->settings.LoRa.IqInverted == true )
GregCr 0:e6ceb13d2d05 646 {
GregCr 0:e6ceb13d2d05 647 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_ON ) );
GregCr 0:e6ceb13d2d05 648 }
GregCr 0:e6ceb13d2d05 649 else
GregCr 0:e6ceb13d2d05 650 {
GregCr 0:e6ceb13d2d05 651 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_OFF ) );
GregCr 0:e6ceb13d2d05 652 }
GregCr 0:e6ceb13d2d05 653
GregCr 0:e6ceb13d2d05 654 this->settings.LoRaPacketHandler.Size = size;
GregCr 0:e6ceb13d2d05 655
GregCr 0:e6ceb13d2d05 656 // Initializes the payload size
GregCr 0:e6ceb13d2d05 657 Write( REG_LR_PAYLOADLENGTH, size );
GregCr 0:e6ceb13d2d05 658
GregCr 0:e6ceb13d2d05 659 // Full buffer used for Tx
GregCr 0:e6ceb13d2d05 660 Write( REG_LR_FIFOTXBASEADDR, 0 );
GregCr 0:e6ceb13d2d05 661 Write( REG_LR_FIFOADDRPTR, 0 );
GregCr 0:e6ceb13d2d05 662
GregCr 0:e6ceb13d2d05 663 // FIFO operations can not take place in Sleep mode
GregCr 0:e6ceb13d2d05 664 if( ( Read( REG_OPMODE ) & ~RF_OPMODE_MASK ) == RF_OPMODE_SLEEP )
GregCr 0:e6ceb13d2d05 665 {
GregCr 0:e6ceb13d2d05 666 Standby( );
GregCr 4:f0ce52e94d3f 667 wait_ms( 1 );
GregCr 0:e6ceb13d2d05 668 }
GregCr 0:e6ceb13d2d05 669 // Write payload buffer
GregCr 0:e6ceb13d2d05 670 WriteFifo( buffer, size );
GregCr 0:e6ceb13d2d05 671 txTimeout = this->settings.LoRa.TxTimeout;
GregCr 0:e6ceb13d2d05 672 }
GregCr 0:e6ceb13d2d05 673 break;
GregCr 0:e6ceb13d2d05 674 }
GregCr 0:e6ceb13d2d05 675
GregCr 0:e6ceb13d2d05 676 Tx( txTimeout );
GregCr 0:e6ceb13d2d05 677 }
GregCr 0:e6ceb13d2d05 678
GregCr 0:e6ceb13d2d05 679 void SX1276::Sleep( void )
GregCr 0:e6ceb13d2d05 680 {
GregCr 0:e6ceb13d2d05 681 // Initialize driver timeout timers
GregCr 0:e6ceb13d2d05 682 txTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 683 rxTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 684 SetOpMode( RF_OPMODE_SLEEP );
GregCr 0:e6ceb13d2d05 685 }
GregCr 0:e6ceb13d2d05 686
GregCr 0:e6ceb13d2d05 687 void SX1276::Standby( void )
GregCr 0:e6ceb13d2d05 688 {
GregCr 0:e6ceb13d2d05 689 txTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 690 rxTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 691 SetOpMode( RF_OPMODE_STANDBY );
GregCr 0:e6ceb13d2d05 692 }
GregCr 0:e6ceb13d2d05 693
GregCr 0:e6ceb13d2d05 694 void SX1276::Rx( uint32_t timeout )
GregCr 0:e6ceb13d2d05 695 {
GregCr 0:e6ceb13d2d05 696 bool rxContinuous = false;
GregCr 6:e7f02929cd3d 697
GregCr 0:e6ceb13d2d05 698 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 699 {
GregCr 0:e6ceb13d2d05 700 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 701 {
GregCr 0:e6ceb13d2d05 702 rxContinuous = this->settings.Fsk.RxContinuous;
GregCr 0:e6ceb13d2d05 703
GregCr 0:e6ceb13d2d05 704 // DIO0=PayloadReady
GregCr 0:e6ceb13d2d05 705 // DIO1=FifoLevel
GregCr 0:e6ceb13d2d05 706 // DIO2=SyncAddr
GregCr 0:e6ceb13d2d05 707 // DIO3=FifoEmpty
GregCr 0:e6ceb13d2d05 708 // DIO4=Preamble
GregCr 0:e6ceb13d2d05 709 // DIO5=ModeReady
GregCr 5:11ec8a6ba4f0 710 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RF_DIOMAPPING1_DIO0_MASK & RF_DIOMAPPING1_DIO1_MASK &
GregCr 0:e6ceb13d2d05 711 RF_DIOMAPPING1_DIO2_MASK ) |
GregCr 0:e6ceb13d2d05 712 RF_DIOMAPPING1_DIO0_00 |
GregCr 0:e6ceb13d2d05 713 RF_DIOMAPPING1_DIO2_11 );
GregCr 0:e6ceb13d2d05 714
GregCr 0:e6ceb13d2d05 715 Write( REG_DIOMAPPING2, ( Read( REG_DIOMAPPING2 ) & RF_DIOMAPPING2_DIO4_MASK &
GregCr 0:e6ceb13d2d05 716 RF_DIOMAPPING2_MAP_MASK ) |
GregCr 0:e6ceb13d2d05 717 RF_DIOMAPPING2_DIO4_11 |
GregCr 0:e6ceb13d2d05 718 RF_DIOMAPPING2_MAP_PREAMBLEDETECT );
GregCr 0:e6ceb13d2d05 719
GregCr 0:e6ceb13d2d05 720 this->settings.FskPacketHandler.FifoThresh = Read( REG_FIFOTHRESH ) & 0x3F;
GregCr 0:e6ceb13d2d05 721
GregCr 0:e6ceb13d2d05 722 this->settings.FskPacketHandler.PreambleDetected = false;
GregCr 0:e6ceb13d2d05 723 this->settings.FskPacketHandler.SyncWordDetected = false;
GregCr 0:e6ceb13d2d05 724 this->settings.FskPacketHandler.NbBytes = 0;
GregCr 0:e6ceb13d2d05 725 this->settings.FskPacketHandler.Size = 0;
GregCr 0:e6ceb13d2d05 726 }
GregCr 0:e6ceb13d2d05 727 break;
GregCr 0:e6ceb13d2d05 728 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 729 {
GregCr 0:e6ceb13d2d05 730 if( this->settings.LoRa.IqInverted == true )
GregCr 0:e6ceb13d2d05 731 {
GregCr 0:e6ceb13d2d05 732 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_ON | RFLR_INVERTIQ_TX_OFF ) );
GregCr 0:e6ceb13d2d05 733 }
GregCr 0:e6ceb13d2d05 734 else
GregCr 0:e6ceb13d2d05 735 {
GregCr 0:e6ceb13d2d05 736 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_OFF ) );
GregCr 0:e6ceb13d2d05 737 }
GregCr 0:e6ceb13d2d05 738
GregCr 0:e6ceb13d2d05 739 rxContinuous = this->settings.LoRa.RxContinuous;
GregCr 0:e6ceb13d2d05 740
GregCr 6:e7f02929cd3d 741 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 742 {
GregCr 6:e7f02929cd3d 743 Write( REG_LR_IRQFLAGSMASK, //RFLR_IRQFLAGS_RXTIMEOUT |
GregCr 0:e6ceb13d2d05 744 //RFLR_IRQFLAGS_RXDONE |
GregCr 0:e6ceb13d2d05 745 //RFLR_IRQFLAGS_PAYLOADCRCERROR |
GregCr 4:f0ce52e94d3f 746 RFLR_IRQFLAGS_VALIDHEADER |
GregCr 0:e6ceb13d2d05 747 RFLR_IRQFLAGS_TXDONE |
GregCr 0:e6ceb13d2d05 748 RFLR_IRQFLAGS_CADDONE |
GregCr 6:e7f02929cd3d 749 //RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
GregCr 0:e6ceb13d2d05 750 RFLR_IRQFLAGS_CADDETECTED );
GregCr 6:e7f02929cd3d 751
GregCr 6:e7f02929cd3d 752 // DIO0=RxDone
GregCr 6:e7f02929cd3d 753 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_00 );
GregCr 6:e7f02929cd3d 754 // DIO2=FhssChangeChannel
GregCr 6:e7f02929cd3d 755 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO2_MASK ) | RFLR_DIOMAPPING1_DIO2_00 );
GregCr 6:e7f02929cd3d 756 }
GregCr 6:e7f02929cd3d 757 else
GregCr 6:e7f02929cd3d 758 {
GregCr 6:e7f02929cd3d 759 Write( REG_LR_IRQFLAGSMASK, //RFLR_IRQFLAGS_RXTIMEOUT |
GregCr 6:e7f02929cd3d 760 //RFLR_IRQFLAGS_RXDONE |
GregCr 6:e7f02929cd3d 761 //RFLR_IRQFLAGS_PAYLOADCRCERROR |
GregCr 6:e7f02929cd3d 762 RFLR_IRQFLAGS_VALIDHEADER |
GregCr 6:e7f02929cd3d 763 RFLR_IRQFLAGS_TXDONE |
GregCr 6:e7f02929cd3d 764 RFLR_IRQFLAGS_CADDONE |
GregCr 6:e7f02929cd3d 765 //RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
GregCr 6:e7f02929cd3d 766 RFLR_IRQFLAGS_CADDETECTED );
GregCr 6:e7f02929cd3d 767
GregCr 6:e7f02929cd3d 768 // DIO0=RxDone
GregCr 6:e7f02929cd3d 769 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_00 );
GregCr 6:e7f02929cd3d 770 }
GregCr 0:e6ceb13d2d05 771
GregCr 0:e6ceb13d2d05 772 Write( REG_LR_FIFORXBASEADDR, 0 );
GregCr 0:e6ceb13d2d05 773 Write( REG_LR_FIFOADDRPTR, 0 );
GregCr 0:e6ceb13d2d05 774 }
GregCr 0:e6ceb13d2d05 775 break;
GregCr 0:e6ceb13d2d05 776 }
GregCr 0:e6ceb13d2d05 777
GregCr 0:e6ceb13d2d05 778 memset( rxBuffer, 0, ( size_t )RX_BUFFER_SIZE );
GregCr 0:e6ceb13d2d05 779
GregCr 0:e6ceb13d2d05 780 this->settings.State = RX;
GregCr 0:e6ceb13d2d05 781 if( timeout != 0 )
GregCr 0:e6ceb13d2d05 782 {
GregCr 0:e6ceb13d2d05 783 rxTimeoutTimer.attach_us( this, &SX1276::OnTimeoutIrq, timeout );
GregCr 0:e6ceb13d2d05 784 }
GregCr 0:e6ceb13d2d05 785
GregCr 0:e6ceb13d2d05 786 if( this->settings.Modem == MODEM_FSK )
GregCr 0:e6ceb13d2d05 787 {
GregCr 0:e6ceb13d2d05 788 SetOpMode( RF_OPMODE_RECEIVER );
GregCr 0:e6ceb13d2d05 789
GregCr 0:e6ceb13d2d05 790 if( rxContinuous == false )
GregCr 0:e6ceb13d2d05 791 {
GregCr 0:e6ceb13d2d05 792 rxTimeoutSyncWord.attach_us( this, &SX1276::OnTimeoutIrq, ( 8.0 * ( this->settings.Fsk.PreambleLen +
GregCr 0:e6ceb13d2d05 793 ( ( Read( REG_SYNCCONFIG ) &
GregCr 0:e6ceb13d2d05 794 ~RF_SYNCCONFIG_SYNCSIZE_MASK ) +
GregCr 0:e6ceb13d2d05 795 1.0 ) + 1.0 ) /
GregCr 0:e6ceb13d2d05 796 ( double )this->settings.Fsk.Datarate ) * 1e6 ) ;
GregCr 0:e6ceb13d2d05 797 }
GregCr 0:e6ceb13d2d05 798 }
GregCr 0:e6ceb13d2d05 799 else
GregCr 0:e6ceb13d2d05 800 {
GregCr 0:e6ceb13d2d05 801 if( rxContinuous == true )
GregCr 0:e6ceb13d2d05 802 {
GregCr 0:e6ceb13d2d05 803 SetOpMode( RFLR_OPMODE_RECEIVER );
GregCr 0:e6ceb13d2d05 804 }
GregCr 0:e6ceb13d2d05 805 else
GregCr 0:e6ceb13d2d05 806 {
GregCr 0:e6ceb13d2d05 807 SetOpMode( RFLR_OPMODE_RECEIVER_SINGLE );
GregCr 0:e6ceb13d2d05 808 }
GregCr 0:e6ceb13d2d05 809 }
GregCr 0:e6ceb13d2d05 810 }
GregCr 0:e6ceb13d2d05 811
GregCr 0:e6ceb13d2d05 812 void SX1276::Tx( uint32_t timeout )
GregCr 0:e6ceb13d2d05 813 {
GregCr 0:e6ceb13d2d05 814 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 815 {
GregCr 0:e6ceb13d2d05 816 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 817 {
GregCr 0:e6ceb13d2d05 818 // DIO0=PacketSent
GregCr 0:e6ceb13d2d05 819 // DIO1=FifoLevel
GregCr 0:e6ceb13d2d05 820 // DIO2=FifoFull
GregCr 0:e6ceb13d2d05 821 // DIO3=FifoEmpty
GregCr 0:e6ceb13d2d05 822 // DIO4=LowBat
GregCr 0:e6ceb13d2d05 823 // DIO5=ModeReady
GregCr 5:11ec8a6ba4f0 824 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RF_DIOMAPPING1_DIO0_MASK & RF_DIOMAPPING1_DIO1_MASK &
GregCr 0:e6ceb13d2d05 825 RF_DIOMAPPING1_DIO2_MASK ) );
GregCr 0:e6ceb13d2d05 826
GregCr 0:e6ceb13d2d05 827 Write( REG_DIOMAPPING2, ( Read( REG_DIOMAPPING2 ) & RF_DIOMAPPING2_DIO4_MASK &
GregCr 0:e6ceb13d2d05 828 RF_DIOMAPPING2_MAP_MASK ) );
GregCr 0:e6ceb13d2d05 829 this->settings.FskPacketHandler.FifoThresh = Read( REG_FIFOTHRESH ) & 0x3F;
GregCr 0:e6ceb13d2d05 830 }
GregCr 0:e6ceb13d2d05 831 break;
GregCr 0:e6ceb13d2d05 832 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 833 {
GregCr 6:e7f02929cd3d 834
GregCr 6:e7f02929cd3d 835 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 836 {
GregCr 6:e7f02929cd3d 837 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
GregCr 6:e7f02929cd3d 838 RFLR_IRQFLAGS_RXDONE |
GregCr 6:e7f02929cd3d 839 RFLR_IRQFLAGS_PAYLOADCRCERROR |
GregCr 6:e7f02929cd3d 840 RFLR_IRQFLAGS_VALIDHEADER |
GregCr 6:e7f02929cd3d 841 //RFLR_IRQFLAGS_TXDONE |
GregCr 6:e7f02929cd3d 842 RFLR_IRQFLAGS_CADDONE |
GregCr 6:e7f02929cd3d 843 //RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
GregCr 6:e7f02929cd3d 844 RFLR_IRQFLAGS_CADDETECTED );
GregCr 6:e7f02929cd3d 845
GregCr 6:e7f02929cd3d 846 // DIO0=TxDone
GregCr 6:e7f02929cd3d 847 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_00 );
GregCr 6:e7f02929cd3d 848 // DIO2=FhssChangeChannel
GregCr 6:e7f02929cd3d 849 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO2_MASK ) | RFLR_DIOMAPPING1_DIO2_00 );
GregCr 6:e7f02929cd3d 850 }
GregCr 6:e7f02929cd3d 851 else
GregCr 6:e7f02929cd3d 852 {
GregCr 6:e7f02929cd3d 853 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
GregCr 0:e6ceb13d2d05 854 RFLR_IRQFLAGS_RXDONE |
GregCr 0:e6ceb13d2d05 855 RFLR_IRQFLAGS_PAYLOADCRCERROR |
GregCr 0:e6ceb13d2d05 856 RFLR_IRQFLAGS_VALIDHEADER |
GregCr 0:e6ceb13d2d05 857 //RFLR_IRQFLAGS_TXDONE |
GregCr 0:e6ceb13d2d05 858 RFLR_IRQFLAGS_CADDONE |
GregCr 0:e6ceb13d2d05 859 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
GregCr 0:e6ceb13d2d05 860 RFLR_IRQFLAGS_CADDETECTED );
GregCr 6:e7f02929cd3d 861
GregCr 6:e7f02929cd3d 862 // DIO0=TxDone
GregCr 6:e7f02929cd3d 863 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_01 );
GregCr 6:e7f02929cd3d 864 }
GregCr 0:e6ceb13d2d05 865 }
GregCr 0:e6ceb13d2d05 866 break;
GregCr 0:e6ceb13d2d05 867 }
GregCr 0:e6ceb13d2d05 868
GregCr 0:e6ceb13d2d05 869 this->settings.State = TX;
GregCr 0:e6ceb13d2d05 870 txTimeoutTimer.attach_us( this, &SX1276::OnTimeoutIrq, timeout );
GregCr 0:e6ceb13d2d05 871 SetOpMode( RF_OPMODE_TRANSMITTER );
GregCr 0:e6ceb13d2d05 872 }
GregCr 0:e6ceb13d2d05 873
GregCr 0:e6ceb13d2d05 874 int8_t SX1276::GetRssi( ModemType modem )
GregCr 0:e6ceb13d2d05 875 {
GregCr 0:e6ceb13d2d05 876 int8_t rssi = 0;
GregCr 0:e6ceb13d2d05 877
GregCr 0:e6ceb13d2d05 878 switch( modem )
GregCr 0:e6ceb13d2d05 879 {
GregCr 0:e6ceb13d2d05 880 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 881 rssi = -( Read( REG_RSSIVALUE ) >> 1 );
GregCr 0:e6ceb13d2d05 882 break;
GregCr 0:e6ceb13d2d05 883 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 884 if( this->settings.Channel > RF_MID_BAND_THRESH )
GregCr 0:e6ceb13d2d05 885 {
GregCr 0:e6ceb13d2d05 886 rssi = RSSI_OFFSET_HF + Read( REG_LR_RSSIVALUE );
GregCr 0:e6ceb13d2d05 887 }
GregCr 0:e6ceb13d2d05 888 else
GregCr 0:e6ceb13d2d05 889 {
GregCr 0:e6ceb13d2d05 890 rssi = RSSI_OFFSET_LF + Read( REG_LR_RSSIVALUE );
GregCr 0:e6ceb13d2d05 891 }
GregCr 0:e6ceb13d2d05 892 break;
GregCr 0:e6ceb13d2d05 893 default:
GregCr 0:e6ceb13d2d05 894 rssi = -1;
GregCr 0:e6ceb13d2d05 895 break;
GregCr 0:e6ceb13d2d05 896 }
GregCr 0:e6ceb13d2d05 897 return rssi;
GregCr 0:e6ceb13d2d05 898 }
GregCr 0:e6ceb13d2d05 899
GregCr 0:e6ceb13d2d05 900 void SX1276::SetOpMode( uint8_t opMode )
GregCr 0:e6ceb13d2d05 901 {
GregCr 0:e6ceb13d2d05 902 if( opMode != previousOpMode )
GregCr 0:e6ceb13d2d05 903 {
GregCr 0:e6ceb13d2d05 904 previousOpMode = opMode;
GregCr 0:e6ceb13d2d05 905 if( opMode == RF_OPMODE_SLEEP )
GregCr 0:e6ceb13d2d05 906 {
GregCr 0:e6ceb13d2d05 907 SetAntSwLowPower( true );
GregCr 0:e6ceb13d2d05 908 }
GregCr 0:e6ceb13d2d05 909 else
GregCr 0:e6ceb13d2d05 910 {
GregCr 0:e6ceb13d2d05 911 SetAntSwLowPower( false );
GregCr 0:e6ceb13d2d05 912 if( opMode == RF_OPMODE_TRANSMITTER )
GregCr 0:e6ceb13d2d05 913 {
GregCr 0:e6ceb13d2d05 914 SetAntSw( 1 );
GregCr 0:e6ceb13d2d05 915 }
GregCr 0:e6ceb13d2d05 916 else
GregCr 0:e6ceb13d2d05 917 {
GregCr 0:e6ceb13d2d05 918 SetAntSw( 0 );
GregCr 0:e6ceb13d2d05 919 }
GregCr 0:e6ceb13d2d05 920 }
GregCr 0:e6ceb13d2d05 921 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RF_OPMODE_MASK ) | opMode );
GregCr 0:e6ceb13d2d05 922 }
GregCr 0:e6ceb13d2d05 923 }
GregCr 0:e6ceb13d2d05 924
GregCr 0:e6ceb13d2d05 925 void SX1276::SetModem( ModemType modem )
GregCr 0:e6ceb13d2d05 926 {
GregCr 4:f0ce52e94d3f 927 if( this->settings.Modem != modem )
GregCr 0:e6ceb13d2d05 928 {
GregCr 4:f0ce52e94d3f 929 this->settings.Modem = modem;
GregCr 4:f0ce52e94d3f 930 switch( this->settings.Modem )
GregCr 4:f0ce52e94d3f 931 {
GregCr 4:f0ce52e94d3f 932 default:
GregCr 4:f0ce52e94d3f 933 case MODEM_FSK:
GregCr 4:f0ce52e94d3f 934 SetOpMode( RF_OPMODE_SLEEP );
GregCr 4:f0ce52e94d3f 935 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RFLR_OPMODE_LONGRANGEMODE_OFF );
GregCr 4:f0ce52e94d3f 936
GregCr 4:f0ce52e94d3f 937 Write( REG_DIOMAPPING1, 0x00 );
GregCr 4:f0ce52e94d3f 938 Write( REG_DIOMAPPING2, 0x30 ); // DIO5=ModeReady
GregCr 4:f0ce52e94d3f 939 break;
GregCr 4:f0ce52e94d3f 940 case MODEM_LORA:
GregCr 4:f0ce52e94d3f 941 SetOpMode( RF_OPMODE_SLEEP );
GregCr 4:f0ce52e94d3f 942 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RFLR_OPMODE_LONGRANGEMODE_ON );
GregCr 4:f0ce52e94d3f 943
GregCr 4:f0ce52e94d3f 944 Write( REG_DIOMAPPING1, 0x00 );
GregCr 4:f0ce52e94d3f 945 Write( REG_DIOMAPPING2, 0x00 );
GregCr 4:f0ce52e94d3f 946 break;
GregCr 4:f0ce52e94d3f 947 }
GregCr 0:e6ceb13d2d05 948 }
GregCr 0:e6ceb13d2d05 949 }
GregCr 0:e6ceb13d2d05 950
GregCr 0:e6ceb13d2d05 951 void SX1276::OnTimeoutIrq( void )
GregCr 0:e6ceb13d2d05 952 {
GregCr 0:e6ceb13d2d05 953 switch( this->settings.State )
GregCr 0:e6ceb13d2d05 954 {
GregCr 0:e6ceb13d2d05 955 case RX:
GregCr 0:e6ceb13d2d05 956 if( this->settings.Modem == MODEM_FSK )
GregCr 0:e6ceb13d2d05 957 {
GregCr 0:e6ceb13d2d05 958 this->settings.FskPacketHandler.PreambleDetected = false;
GregCr 0:e6ceb13d2d05 959 this->settings.FskPacketHandler.SyncWordDetected = false;
GregCr 0:e6ceb13d2d05 960 this->settings.FskPacketHandler.NbBytes = 0;
GregCr 0:e6ceb13d2d05 961 this->settings.FskPacketHandler.Size = 0;
GregCr 0:e6ceb13d2d05 962
GregCr 0:e6ceb13d2d05 963 // Clear Irqs
GregCr 0:e6ceb13d2d05 964 Write( REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI |
GregCr 0:e6ceb13d2d05 965 RF_IRQFLAGS1_PREAMBLEDETECT |
GregCr 0:e6ceb13d2d05 966 RF_IRQFLAGS1_SYNCADDRESSMATCH );
GregCr 0:e6ceb13d2d05 967 Write( REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN );
GregCr 0:e6ceb13d2d05 968
GregCr 0:e6ceb13d2d05 969 if( this->settings.Fsk.RxContinuous == true )
GregCr 0:e6ceb13d2d05 970 {
GregCr 0:e6ceb13d2d05 971 // Continuous mode restart Rx chain
GregCr 0:e6ceb13d2d05 972 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
GregCr 0:e6ceb13d2d05 973 }
GregCr 0:e6ceb13d2d05 974 else
GregCr 0:e6ceb13d2d05 975 {
GregCr 5:11ec8a6ba4f0 976 this->settings.State = IDLE;
GregCr 5:11ec8a6ba4f0 977 rxTimeoutSyncWord.detach( );
GregCr 0:e6ceb13d2d05 978 }
GregCr 0:e6ceb13d2d05 979 }
GregCr 0:e6ceb13d2d05 980 if( ( rxTimeout != NULL ) )
GregCr 0:e6ceb13d2d05 981 {
GregCr 0:e6ceb13d2d05 982 rxTimeout( );
GregCr 0:e6ceb13d2d05 983 }
GregCr 0:e6ceb13d2d05 984 break;
GregCr 0:e6ceb13d2d05 985 case TX:
GregCr 5:11ec8a6ba4f0 986 this->settings.State = IDLE;
GregCr 0:e6ceb13d2d05 987 if( ( txTimeout != NULL ) )
GregCr 0:e6ceb13d2d05 988 {
GregCr 0:e6ceb13d2d05 989 txTimeout( );
GregCr 0:e6ceb13d2d05 990 }
GregCr 0:e6ceb13d2d05 991 break;
GregCr 0:e6ceb13d2d05 992 default:
GregCr 0:e6ceb13d2d05 993 break;
GregCr 0:e6ceb13d2d05 994 }
GregCr 0:e6ceb13d2d05 995 }
GregCr 0:e6ceb13d2d05 996
GregCr 0:e6ceb13d2d05 997 void SX1276::OnDio0Irq( void )
GregCr 0:e6ceb13d2d05 998 {
GregCr 0:e6ceb13d2d05 999 __IO uint8_t irqFlags = 0;
GregCr 0:e6ceb13d2d05 1000
GregCr 0:e6ceb13d2d05 1001 switch( this->settings.State )
GregCr 0:e6ceb13d2d05 1002 {
GregCr 0:e6ceb13d2d05 1003 case RX:
GregCr 0:e6ceb13d2d05 1004 //TimerStop( &RxTimeoutTimer );
GregCr 0:e6ceb13d2d05 1005 // RxDone interrupt
GregCr 0:e6ceb13d2d05 1006 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1007 {
GregCr 0:e6ceb13d2d05 1008 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1009 irqFlags = Read( REG_IRQFLAGS2 );
GregCr 0:e6ceb13d2d05 1010 if( ( irqFlags & RF_IRQFLAGS2_CRCOK ) != RF_IRQFLAGS2_CRCOK )
GregCr 0:e6ceb13d2d05 1011 {
GregCr 0:e6ceb13d2d05 1012 // Clear Irqs
GregCr 0:e6ceb13d2d05 1013 Write( REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI |
GregCr 0:e6ceb13d2d05 1014 RF_IRQFLAGS1_PREAMBLEDETECT |
GregCr 0:e6ceb13d2d05 1015 RF_IRQFLAGS1_SYNCADDRESSMATCH );
GregCr 0:e6ceb13d2d05 1016 Write( REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN );
GregCr 0:e6ceb13d2d05 1017
GregCr 0:e6ceb13d2d05 1018 if( this->settings.Fsk.RxContinuous == false )
GregCr 0:e6ceb13d2d05 1019 {
GregCr 0:e6ceb13d2d05 1020 this->settings.State = IDLE;
GregCr 0:e6ceb13d2d05 1021 rxTimeoutSyncWord.attach_us( this, &SX1276::OnTimeoutIrq, ( 8.0 * ( this->settings.Fsk.PreambleLen +
GregCr 0:e6ceb13d2d05 1022 ( ( Read( REG_SYNCCONFIG ) &
GregCr 0:e6ceb13d2d05 1023 ~RF_SYNCCONFIG_SYNCSIZE_MASK ) +
GregCr 0:e6ceb13d2d05 1024 1.0 ) + 1.0 ) /
GregCr 0:e6ceb13d2d05 1025 ( double )this->settings.Fsk.Datarate ) * 1e6 ) ;
GregCr 0:e6ceb13d2d05 1026 }
GregCr 0:e6ceb13d2d05 1027 else
GregCr 0:e6ceb13d2d05 1028 {
GregCr 0:e6ceb13d2d05 1029 // Continuous mode restart Rx chain
GregCr 0:e6ceb13d2d05 1030 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
GregCr 0:e6ceb13d2d05 1031 }
GregCr 0:e6ceb13d2d05 1032 rxTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 1033
GregCr 0:e6ceb13d2d05 1034 if( ( rxError != NULL ) )
GregCr 0:e6ceb13d2d05 1035 {
GregCr 0:e6ceb13d2d05 1036 rxError( );
GregCr 0:e6ceb13d2d05 1037 }
GregCr 0:e6ceb13d2d05 1038 this->settings.FskPacketHandler.PreambleDetected = false;
GregCr 0:e6ceb13d2d05 1039 this->settings.FskPacketHandler.SyncWordDetected = false;
GregCr 0:e6ceb13d2d05 1040 this->settings.FskPacketHandler.NbBytes = 0;
GregCr 0:e6ceb13d2d05 1041 this->settings.FskPacketHandler.Size = 0;
GregCr 0:e6ceb13d2d05 1042 break;
GregCr 0:e6ceb13d2d05 1043 }
GregCr 0:e6ceb13d2d05 1044
GregCr 0:e6ceb13d2d05 1045 // Read received packet size
GregCr 0:e6ceb13d2d05 1046 if( ( this->settings.FskPacketHandler.Size == 0 ) && ( this->settings.FskPacketHandler.NbBytes == 0 ) )
GregCr 0:e6ceb13d2d05 1047 {
GregCr 0:e6ceb13d2d05 1048 if( this->settings.Fsk.FixLen == false )
GregCr 0:e6ceb13d2d05 1049 {
GregCr 0:e6ceb13d2d05 1050 ReadFifo( ( uint8_t* )&this->settings.FskPacketHandler.Size, 1 );
GregCr 0:e6ceb13d2d05 1051 }
GregCr 0:e6ceb13d2d05 1052 else
GregCr 0:e6ceb13d2d05 1053 {
GregCr 0:e6ceb13d2d05 1054 this->settings.FskPacketHandler.Size = Read( REG_PAYLOADLENGTH );
GregCr 0:e6ceb13d2d05 1055 }
GregCr 0:e6ceb13d2d05 1056 ReadFifo( rxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1057 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1058 }
GregCr 0:e6ceb13d2d05 1059 else
GregCr 0:e6ceb13d2d05 1060 {
GregCr 0:e6ceb13d2d05 1061 ReadFifo( rxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1062 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1063 }
GregCr 0:e6ceb13d2d05 1064
GregCr 0:e6ceb13d2d05 1065 if( this->settings.Fsk.RxContinuous == false )
GregCr 0:e6ceb13d2d05 1066 {
GregCr 0:e6ceb13d2d05 1067 this->settings.State = IDLE;
GregCr 0:e6ceb13d2d05 1068 rxTimeoutSyncWord.attach_us( this, &SX1276::OnTimeoutIrq, ( 8.0 * ( this->settings.Fsk.PreambleLen +
GregCr 0:e6ceb13d2d05 1069 ( ( Read( REG_SYNCCONFIG ) &
GregCr 0:e6ceb13d2d05 1070 ~RF_SYNCCONFIG_SYNCSIZE_MASK ) +
GregCr 0:e6ceb13d2d05 1071 1.0 ) + 1.0 ) /
GregCr 0:e6ceb13d2d05 1072 ( double )this->settings.Fsk.Datarate ) * 1e6 ) ;
GregCr 0:e6ceb13d2d05 1073 }
GregCr 0:e6ceb13d2d05 1074 else
GregCr 0:e6ceb13d2d05 1075 {
GregCr 0:e6ceb13d2d05 1076 // Continuous mode restart Rx chain
GregCr 0:e6ceb13d2d05 1077 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
GregCr 0:e6ceb13d2d05 1078 }
GregCr 0:e6ceb13d2d05 1079 rxTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 1080
GregCr 0:e6ceb13d2d05 1081 if( (rxDone != NULL ) )
GregCr 0:e6ceb13d2d05 1082 {
GregCr 0:e6ceb13d2d05 1083 rxDone( rxBuffer, this->settings.FskPacketHandler.Size, this->settings.FskPacketHandler.RssiValue, 0 );
GregCr 0:e6ceb13d2d05 1084 }
GregCr 0:e6ceb13d2d05 1085 this->settings.FskPacketHandler.PreambleDetected = false;
GregCr 0:e6ceb13d2d05 1086 this->settings.FskPacketHandler.SyncWordDetected = false;
GregCr 0:e6ceb13d2d05 1087 this->settings.FskPacketHandler.NbBytes = 0;
GregCr 0:e6ceb13d2d05 1088 this->settings.FskPacketHandler.Size = 0;
GregCr 0:e6ceb13d2d05 1089 break;
GregCr 0:e6ceb13d2d05 1090 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1091 {
GregCr 0:e6ceb13d2d05 1092 uint8_t snr = 0;
GregCr 0:e6ceb13d2d05 1093
GregCr 0:e6ceb13d2d05 1094 // Clear Irq
GregCr 0:e6ceb13d2d05 1095 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_RXDONE );
GregCr 0:e6ceb13d2d05 1096
GregCr 0:e6ceb13d2d05 1097 irqFlags = Read( REG_LR_IRQFLAGS );
GregCr 0:e6ceb13d2d05 1098 if( ( irqFlags & RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK ) == RFLR_IRQFLAGS_PAYLOADCRCERROR )
GregCr 0:e6ceb13d2d05 1099 {
GregCr 0:e6ceb13d2d05 1100 // Clear Irq
GregCr 0:e6ceb13d2d05 1101 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_PAYLOADCRCERROR );
GregCr 0:e6ceb13d2d05 1102
GregCr 0:e6ceb13d2d05 1103 if( this->settings.LoRa.RxContinuous == false )
GregCr 0:e6ceb13d2d05 1104 {
GregCr 0:e6ceb13d2d05 1105 this->settings.State = IDLE;
GregCr 0:e6ceb13d2d05 1106 }
GregCr 0:e6ceb13d2d05 1107 rxTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 1108
GregCr 4:f0ce52e94d3f 1109 if( ( rxError != NULL ) )
GregCr 0:e6ceb13d2d05 1110 {
GregCr 0:e6ceb13d2d05 1111 rxError( );
GregCr 0:e6ceb13d2d05 1112 }
GregCr 0:e6ceb13d2d05 1113 break;
GregCr 0:e6ceb13d2d05 1114 }
GregCr 0:e6ceb13d2d05 1115
GregCr 0:e6ceb13d2d05 1116 this->settings.LoRaPacketHandler.SnrValue = Read( REG_LR_PKTSNRVALUE );
GregCr 0:e6ceb13d2d05 1117 if( this->settings.LoRaPacketHandler.SnrValue & 0x80 ) // The SNR sign bit is 1
GregCr 0:e6ceb13d2d05 1118 {
GregCr 0:e6ceb13d2d05 1119 // Invert and divide by 4
GregCr 0:e6ceb13d2d05 1120 snr = ( ( ~this->settings.LoRaPacketHandler.SnrValue + 1 ) & 0xFF ) >> 2;
GregCr 0:e6ceb13d2d05 1121 snr = -snr;
GregCr 0:e6ceb13d2d05 1122 }
GregCr 0:e6ceb13d2d05 1123 else
GregCr 0:e6ceb13d2d05 1124 {
GregCr 0:e6ceb13d2d05 1125 // Divide by 4
GregCr 0:e6ceb13d2d05 1126 snr = ( this->settings.LoRaPacketHandler.SnrValue & 0xFF ) >> 2;
GregCr 0:e6ceb13d2d05 1127 }
GregCr 0:e6ceb13d2d05 1128
GregCr 0:e6ceb13d2d05 1129 int8_t rssi = Read( REG_LR_PKTRSSIVALUE );
GregCr 0:e6ceb13d2d05 1130 if( this->settings.LoRaPacketHandler.SnrValue < 0 )
GregCr 0:e6ceb13d2d05 1131 {
GregCr 0:e6ceb13d2d05 1132 if( this->settings.Channel > RF_MID_BAND_THRESH )
GregCr 0:e6ceb13d2d05 1133 {
GregCr 0:e6ceb13d2d05 1134 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_HF + rssi + ( rssi >> 4 ) +
GregCr 0:e6ceb13d2d05 1135 snr;
GregCr 0:e6ceb13d2d05 1136 }
GregCr 0:e6ceb13d2d05 1137 else
GregCr 0:e6ceb13d2d05 1138 {
GregCr 0:e6ceb13d2d05 1139 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_LF + rssi + ( rssi >> 4 ) +
GregCr 0:e6ceb13d2d05 1140 snr;
GregCr 0:e6ceb13d2d05 1141 }
GregCr 0:e6ceb13d2d05 1142 }
GregCr 0:e6ceb13d2d05 1143 else
GregCr 0:e6ceb13d2d05 1144 {
GregCr 0:e6ceb13d2d05 1145 if( this->settings.Channel > RF_MID_BAND_THRESH )
GregCr 0:e6ceb13d2d05 1146 {
GregCr 0:e6ceb13d2d05 1147 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_HF + rssi + ( rssi >> 4 );
GregCr 0:e6ceb13d2d05 1148 }
GregCr 0:e6ceb13d2d05 1149 else
GregCr 0:e6ceb13d2d05 1150 {
GregCr 0:e6ceb13d2d05 1151 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_LF + rssi + ( rssi >> 4 );
GregCr 0:e6ceb13d2d05 1152 }
GregCr 0:e6ceb13d2d05 1153 }
GregCr 0:e6ceb13d2d05 1154
GregCr 0:e6ceb13d2d05 1155 this->settings.LoRaPacketHandler.Size = Read( REG_LR_RXNBBYTES );
GregCr 0:e6ceb13d2d05 1156 ReadFifo( rxBuffer, this->settings.LoRaPacketHandler.Size );
GregCr 0:e6ceb13d2d05 1157
GregCr 0:e6ceb13d2d05 1158 if( this->settings.LoRa.RxContinuous == false )
GregCr 0:e6ceb13d2d05 1159 {
GregCr 0:e6ceb13d2d05 1160 this->settings.State = IDLE;
GregCr 0:e6ceb13d2d05 1161 }
GregCr 0:e6ceb13d2d05 1162 rxTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 1163
GregCr 0:e6ceb13d2d05 1164 if( ( rxDone != NULL ) )
GregCr 0:e6ceb13d2d05 1165 {
GregCr 0:e6ceb13d2d05 1166 rxDone( rxBuffer, this->settings.LoRaPacketHandler.Size, this->settings.LoRaPacketHandler.RssiValue, this->settings.LoRaPacketHandler.SnrValue );
GregCr 0:e6ceb13d2d05 1167 }
GregCr 0:e6ceb13d2d05 1168 }
GregCr 0:e6ceb13d2d05 1169 break;
GregCr 0:e6ceb13d2d05 1170 default:
GregCr 0:e6ceb13d2d05 1171 break;
GregCr 0:e6ceb13d2d05 1172 }
GregCr 0:e6ceb13d2d05 1173 break;
GregCr 0:e6ceb13d2d05 1174 case TX:
GregCr 0:e6ceb13d2d05 1175 txTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 1176 // TxDone interrupt
GregCr 0:e6ceb13d2d05 1177 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1178 {
GregCr 0:e6ceb13d2d05 1179 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1180 // Clear Irq
GregCr 0:e6ceb13d2d05 1181 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_TXDONE );
GregCr 0:e6ceb13d2d05 1182 // Intentional fall through
GregCr 0:e6ceb13d2d05 1183 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1184 default:
GregCr 0:e6ceb13d2d05 1185 this->settings.State = IDLE;
GregCr 0:e6ceb13d2d05 1186 if( ( txDone != NULL ) )
GregCr 0:e6ceb13d2d05 1187 {
GregCr 0:e6ceb13d2d05 1188 txDone( );
GregCr 0:e6ceb13d2d05 1189 }
GregCr 0:e6ceb13d2d05 1190 break;
GregCr 0:e6ceb13d2d05 1191 }
GregCr 0:e6ceb13d2d05 1192 break;
GregCr 0:e6ceb13d2d05 1193 default:
GregCr 0:e6ceb13d2d05 1194 break;
GregCr 0:e6ceb13d2d05 1195 }
GregCr 0:e6ceb13d2d05 1196 }
GregCr 0:e6ceb13d2d05 1197
GregCr 0:e6ceb13d2d05 1198 void SX1276::OnDio1Irq( void )
GregCr 0:e6ceb13d2d05 1199 {
GregCr 0:e6ceb13d2d05 1200 switch( this->settings.State )
GregCr 0:e6ceb13d2d05 1201 {
GregCr 0:e6ceb13d2d05 1202 case RX:
GregCr 0:e6ceb13d2d05 1203 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1204 {
GregCr 0:e6ceb13d2d05 1205 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1206 // FifoLevel interrupt
GregCr 0:e6ceb13d2d05 1207 // Read received packet size
GregCr 0:e6ceb13d2d05 1208 if( ( this->settings.FskPacketHandler.Size == 0 ) && ( this->settings.FskPacketHandler.NbBytes == 0 ) )
GregCr 0:e6ceb13d2d05 1209 {
GregCr 0:e6ceb13d2d05 1210 if( this->settings.Fsk.FixLen == false )
GregCr 0:e6ceb13d2d05 1211 {
GregCr 0:e6ceb13d2d05 1212 ReadFifo( ( uint8_t* )&this->settings.FskPacketHandler.Size, 1 );
GregCr 0:e6ceb13d2d05 1213 }
GregCr 0:e6ceb13d2d05 1214 else
GregCr 0:e6ceb13d2d05 1215 {
GregCr 0:e6ceb13d2d05 1216 this->settings.FskPacketHandler.Size = Read( REG_PAYLOADLENGTH );
GregCr 0:e6ceb13d2d05 1217 }
GregCr 0:e6ceb13d2d05 1218 }
GregCr 0:e6ceb13d2d05 1219
GregCr 0:e6ceb13d2d05 1220 if( ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ) > this->settings.FskPacketHandler.FifoThresh )
GregCr 0:e6ceb13d2d05 1221 {
GregCr 0:e6ceb13d2d05 1222 ReadFifo( ( rxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.FifoThresh );
GregCr 0:e6ceb13d2d05 1223 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.FifoThresh;
GregCr 0:e6ceb13d2d05 1224 }
GregCr 0:e6ceb13d2d05 1225 else
GregCr 0:e6ceb13d2d05 1226 {
GregCr 0:e6ceb13d2d05 1227 ReadFifo( ( rxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1228 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1229 }
GregCr 0:e6ceb13d2d05 1230 break;
GregCr 0:e6ceb13d2d05 1231 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1232 // Sync time out
GregCr 0:e6ceb13d2d05 1233 rxTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 1234 this->settings.State = IDLE;
GregCr 0:e6ceb13d2d05 1235 if( ( rxTimeout != NULL ) )
GregCr 0:e6ceb13d2d05 1236 {
GregCr 0:e6ceb13d2d05 1237 rxTimeout( );
GregCr 0:e6ceb13d2d05 1238 }
GregCr 0:e6ceb13d2d05 1239 break;
GregCr 0:e6ceb13d2d05 1240 default:
GregCr 0:e6ceb13d2d05 1241 break;
GregCr 0:e6ceb13d2d05 1242 }
GregCr 0:e6ceb13d2d05 1243 break;
GregCr 0:e6ceb13d2d05 1244 case TX:
GregCr 0:e6ceb13d2d05 1245 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1246 {
GregCr 0:e6ceb13d2d05 1247 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1248 // FifoLevel interrupt
GregCr 0:e6ceb13d2d05 1249 if( ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ) > this->settings.FskPacketHandler.ChunkSize )
GregCr 0:e6ceb13d2d05 1250 {
GregCr 0:e6ceb13d2d05 1251 WriteFifo( ( rxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.ChunkSize );
GregCr 0:e6ceb13d2d05 1252 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.ChunkSize;
GregCr 0:e6ceb13d2d05 1253 }
GregCr 0:e6ceb13d2d05 1254 else
GregCr 0:e6ceb13d2d05 1255 {
GregCr 0:e6ceb13d2d05 1256 // Write the last chunk of data
GregCr 0:e6ceb13d2d05 1257 WriteFifo( rxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1258 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes;
GregCr 0:e6ceb13d2d05 1259 }
GregCr 0:e6ceb13d2d05 1260 break;
GregCr 0:e6ceb13d2d05 1261 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1262 break;
GregCr 0:e6ceb13d2d05 1263 default:
GregCr 0:e6ceb13d2d05 1264 break;
GregCr 0:e6ceb13d2d05 1265 }
GregCr 0:e6ceb13d2d05 1266 break;
GregCr 0:e6ceb13d2d05 1267 default:
GregCr 0:e6ceb13d2d05 1268 break;
GregCr 0:e6ceb13d2d05 1269 }
GregCr 0:e6ceb13d2d05 1270 }
GregCr 0:e6ceb13d2d05 1271
GregCr 0:e6ceb13d2d05 1272 void SX1276::OnDio2Irq( void )
GregCr 0:e6ceb13d2d05 1273 {
GregCr 0:e6ceb13d2d05 1274 switch( this->settings.State )
GregCr 0:e6ceb13d2d05 1275 {
GregCr 0:e6ceb13d2d05 1276 case RX:
GregCr 0:e6ceb13d2d05 1277 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1278 {
GregCr 0:e6ceb13d2d05 1279 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1280 if( ( this->settings.FskPacketHandler.PreambleDetected == true ) && ( this->settings.FskPacketHandler.SyncWordDetected == false ) )
GregCr 0:e6ceb13d2d05 1281 {
GregCr 0:e6ceb13d2d05 1282 rxTimeoutSyncWord.detach( );
GregCr 0:e6ceb13d2d05 1283
GregCr 0:e6ceb13d2d05 1284 this->settings.FskPacketHandler.SyncWordDetected = true;
GregCr 0:e6ceb13d2d05 1285
GregCr 0:e6ceb13d2d05 1286 this->settings.FskPacketHandler.RssiValue = -( Read( REG_RSSIVALUE ) >> 1 );
GregCr 0:e6ceb13d2d05 1287
GregCr 0:e6ceb13d2d05 1288 this->settings.FskPacketHandler.AfcValue = ( int32_t )( double )( ( ( uint16_t )Read( REG_AFCMSB ) << 8 ) |
GregCr 0:e6ceb13d2d05 1289 ( uint16_t )Read( REG_AFCLSB ) ) *
GregCr 0:e6ceb13d2d05 1290 ( double )FREQ_STEP;
GregCr 0:e6ceb13d2d05 1291 this->settings.FskPacketHandler.RxGain = ( Read( REG_LNA ) >> 5 ) & 0x07;
GregCr 0:e6ceb13d2d05 1292 }
GregCr 0:e6ceb13d2d05 1293 break;
GregCr 0:e6ceb13d2d05 1294 case MODEM_LORA:
GregCr 6:e7f02929cd3d 1295 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 1296 {
GregCr 6:e7f02929cd3d 1297 // Clear Irq
GregCr 6:e7f02929cd3d 1298 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL );
GregCr 6:e7f02929cd3d 1299
GregCr 6:e7f02929cd3d 1300 if( ( fhssChangeChannel != NULL ) )
GregCr 6:e7f02929cd3d 1301 {
GregCr 6:e7f02929cd3d 1302 fhssChangeChannel( ( Read( REG_LR_HOPCHANNEL ) & RFLR_HOPCHANNEL_CHANNEL_MASK ) );
GregCr 6:e7f02929cd3d 1303 }
GregCr 6:e7f02929cd3d 1304 }
GregCr 0:e6ceb13d2d05 1305 break;
GregCr 0:e6ceb13d2d05 1306 default:
GregCr 0:e6ceb13d2d05 1307 break;
GregCr 0:e6ceb13d2d05 1308 }
GregCr 0:e6ceb13d2d05 1309 break;
GregCr 0:e6ceb13d2d05 1310 case TX:
GregCr 0:e6ceb13d2d05 1311 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1312 {
GregCr 0:e6ceb13d2d05 1313 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1314 break;
GregCr 0:e6ceb13d2d05 1315 case MODEM_LORA:
GregCr 6:e7f02929cd3d 1316 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 1317 {
GregCr 6:e7f02929cd3d 1318 // Clear Irq
GregCr 6:e7f02929cd3d 1319 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL );
GregCr 6:e7f02929cd3d 1320
GregCr 6:e7f02929cd3d 1321 if( ( fhssChangeChannel != NULL ) )
GregCr 6:e7f02929cd3d 1322 {
GregCr 6:e7f02929cd3d 1323 fhssChangeChannel( ( Read( REG_LR_HOPCHANNEL ) & RFLR_HOPCHANNEL_CHANNEL_MASK ) );
GregCr 6:e7f02929cd3d 1324 }
GregCr 6:e7f02929cd3d 1325 }
GregCr 0:e6ceb13d2d05 1326 break;
GregCr 0:e6ceb13d2d05 1327 default:
GregCr 0:e6ceb13d2d05 1328 break;
GregCr 0:e6ceb13d2d05 1329 }
GregCr 0:e6ceb13d2d05 1330 break;
GregCr 0:e6ceb13d2d05 1331 default:
GregCr 0:e6ceb13d2d05 1332 break;
GregCr 0:e6ceb13d2d05 1333 }
GregCr 0:e6ceb13d2d05 1334 }
GregCr 0:e6ceb13d2d05 1335
GregCr 0:e6ceb13d2d05 1336 void SX1276::OnDio3Irq( void )
GregCr 0:e6ceb13d2d05 1337 {
GregCr 0:e6ceb13d2d05 1338 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1339 {
GregCr 0:e6ceb13d2d05 1340 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1341 break;
GregCr 0:e6ceb13d2d05 1342 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1343 break;
GregCr 0:e6ceb13d2d05 1344 default:
GregCr 0:e6ceb13d2d05 1345 break;
GregCr 0:e6ceb13d2d05 1346 }
GregCr 0:e6ceb13d2d05 1347 }
GregCr 0:e6ceb13d2d05 1348
GregCr 0:e6ceb13d2d05 1349 void SX1276::OnDio4Irq( void )
GregCr 0:e6ceb13d2d05 1350 {
GregCr 0:e6ceb13d2d05 1351 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1352 {
GregCr 0:e6ceb13d2d05 1353 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1354 {
GregCr 0:e6ceb13d2d05 1355 if( this->settings.FskPacketHandler.PreambleDetected == false )
GregCr 0:e6ceb13d2d05 1356 {
GregCr 0:e6ceb13d2d05 1357 this->settings.FskPacketHandler.PreambleDetected = true;
GregCr 0:e6ceb13d2d05 1358 }
GregCr 0:e6ceb13d2d05 1359 }
GregCr 0:e6ceb13d2d05 1360 break;
GregCr 0:e6ceb13d2d05 1361 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1362 break;
GregCr 0:e6ceb13d2d05 1363 default:
GregCr 0:e6ceb13d2d05 1364 break;
GregCr 0:e6ceb13d2d05 1365 }
GregCr 0:e6ceb13d2d05 1366 }
GregCr 0:e6ceb13d2d05 1367
GregCr 0:e6ceb13d2d05 1368 void SX1276::OnDio5Irq( void )
GregCr 0:e6ceb13d2d05 1369 {
GregCr 0:e6ceb13d2d05 1370 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1371 {
GregCr 0:e6ceb13d2d05 1372 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1373 break;
GregCr 0:e6ceb13d2d05 1374 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1375 break;
GregCr 0:e6ceb13d2d05 1376 default:
GregCr 0:e6ceb13d2d05 1377 break;
GregCr 0:e6ceb13d2d05 1378 }
GregCr 0:e6ceb13d2d05 1379 }