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rtx/TARGET_CORTEX_A/rt_HAL_CA.h@49:77c8e4604045, 2014-11-06 (annotated)

Committer:
mbed_official
Date:
Thu Nov 06 13:00:11 2014 +0000
Revision:
49:77c8e4604045
Parent:
rtx_ca/rt_HAL_CA.h@48:e9a2c7cb57a4
Child:
51:318e02f48146
Synchronized with git revision 7b90c2ba137baaf9769219e0e8a7b8e8d1299c4f



Full URL: https://github.com/mbedmicro/mbed/commit/7b90c2ba137baaf9769219e0e8a7b8e8d1299c4f/



This target is not yet tested, so it can't be released as part of the official

SDK build for now.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 48:e9a2c7cb57a4 1 /*----------------------------------------------------------------------------
mbed_official 48:e9a2c7cb57a4 2 * RL-ARM - RTX
mbed_official 48:e9a2c7cb57a4 3 *----------------------------------------------------------------------------
mbed_official 48:e9a2c7cb57a4 4 * Name: RT_HAL_CM.H
mbed_official 48:e9a2c7cb57a4 5 * Purpose: Hardware Abstraction Layer for Cortex-A definitions
mbed_official 48:e9a2c7cb57a4 6 * Rev.: 21 Aug 2013
mbed_official 48:e9a2c7cb57a4 7 *----------------------------------------------------------------------------
mbed_official 48:e9a2c7cb57a4 8 *
mbed_official 48:e9a2c7cb57a4 9 * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
mbed_official 48:e9a2c7cb57a4 10 * All rights reserved.
mbed_official 48:e9a2c7cb57a4 11 * Redistribution and use in source and binary forms, with or without
mbed_official 48:e9a2c7cb57a4 12 * modification, are permitted provided that the following conditions are met:
mbed_official 48:e9a2c7cb57a4 13 * - Redistributions of source code must retain the above copyright
mbed_official 48:e9a2c7cb57a4 14 * notice, this list of conditions and the following disclaimer.
mbed_official 48:e9a2c7cb57a4 15 * - Redistributions in binary form must reproduce the above copyright
mbed_official 48:e9a2c7cb57a4 16 * notice, this list of conditions and the following disclaimer in the
mbed_official 48:e9a2c7cb57a4 17 * documentation and/or other materials provided with the distribution.
mbed_official 48:e9a2c7cb57a4 18 * - Neither the name of ARM nor the names of its contributors may be used
mbed_official 48:e9a2c7cb57a4 19 * to endorse or promote products derived from this software without
mbed_official 48:e9a2c7cb57a4 20 * specific prior written permission.
mbed_official 48:e9a2c7cb57a4 21 *
mbed_official 48:e9a2c7cb57a4 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 48:e9a2c7cb57a4 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 48:e9a2c7cb57a4 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
mbed_official 48:e9a2c7cb57a4 25 * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
mbed_official 48:e9a2c7cb57a4 26 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
mbed_official 48:e9a2c7cb57a4 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
mbed_official 48:e9a2c7cb57a4 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
mbed_official 48:e9a2c7cb57a4 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
mbed_official 48:e9a2c7cb57a4 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
mbed_official 48:e9a2c7cb57a4 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
mbed_official 48:e9a2c7cb57a4 32 * POSSIBILITY OF SUCH DAMAGE.
mbed_official 48:e9a2c7cb57a4 33 *---------------------------------------------------------------------------*/
mbed_official 48:e9a2c7cb57a4 34
mbed_official 48:e9a2c7cb57a4 35 /* Definitions */
mbed_official 48:e9a2c7cb57a4 36 #define INIT_CPSR_SYS 0x4000001F
mbed_official 48:e9a2c7cb57a4 37 #define INIT_CPSR_USER 0x40000010
mbed_official 48:e9a2c7cb57a4 38
mbed_official 48:e9a2c7cb57a4 39 #define CPSR_T_BIT 0x20
mbed_official 48:e9a2c7cb57a4 40 #define CPSR_I_BIT 0x80
mbed_official 48:e9a2c7cb57a4 41 #define CPSR_F_BIT 0x40
mbed_official 48:e9a2c7cb57a4 42
mbed_official 48:e9a2c7cb57a4 43 #define MODE_USR 0x10
mbed_official 48:e9a2c7cb57a4 44 #define MODE_FIQ 0x11
mbed_official 48:e9a2c7cb57a4 45 #define MODE_IRQ 0x12
mbed_official 48:e9a2c7cb57a4 46 #define MODE_SVC 0x13
mbed_official 48:e9a2c7cb57a4 47 #define MODE_ABT 0x17
mbed_official 48:e9a2c7cb57a4 48 #define MODE_UND 0x1B
mbed_official 48:e9a2c7cb57a4 49 #define MODE_SYS 0x1F
mbed_official 48:e9a2c7cb57a4 50
mbed_official 48:e9a2c7cb57a4 51 #define MAGIC_WORD 0xE25A2EA5
mbed_official 48:e9a2c7cb57a4 52
mbed_official 48:e9a2c7cb57a4 53 #include "core_ca9.h"
mbed_official 48:e9a2c7cb57a4 54
mbed_official 48:e9a2c7cb57a4 55 #if defined (__CC_ARM) /* ARM Compiler */
mbed_official 48:e9a2c7cb57a4 56
mbed_official 48:e9a2c7cb57a4 57 #if ((__TARGET_ARCH_7_M || __TARGET_ARCH_7E_M || __TARGET_ARCH_7_A) && !NO_EXCLUSIVE_ACCESS)
mbed_official 48:e9a2c7cb57a4 58 #define __USE_EXCLUSIVE_ACCESS
mbed_official 48:e9a2c7cb57a4 59 #else
mbed_official 48:e9a2c7cb57a4 60 #undef __USE_EXCLUSIVE_ACCESS
mbed_official 48:e9a2c7cb57a4 61 #endif
mbed_official 48:e9a2c7cb57a4 62
mbed_official 48:e9a2c7cb57a4 63 #elif defined (__GNUC__) /* GNU Compiler */
mbed_official 48:e9a2c7cb57a4 64
mbed_official 48:e9a2c7cb57a4 65 #error GNU Compiler support not implemented for Cortex-A
mbed_official 48:e9a2c7cb57a4 66
mbed_official 48:e9a2c7cb57a4 67 #elif defined (__ICCARM__) /* IAR Compiler */
mbed_official 48:e9a2c7cb57a4 68
mbed_official 48:e9a2c7cb57a4 69 #error IAR Compiler support not implemented for Cortex-A
mbed_official 48:e9a2c7cb57a4 70
mbed_official 48:e9a2c7cb57a4 71 #endif
mbed_official 48:e9a2c7cb57a4 72
mbed_official 48:e9a2c7cb57a4 73 static U8 priority = 0xff;
mbed_official 48:e9a2c7cb57a4 74
mbed_official 48:e9a2c7cb57a4 75 extern const U32 GICDistributor_BASE;
mbed_official 48:e9a2c7cb57a4 76 extern const U32 GICInterface_BASE;
mbed_official 48:e9a2c7cb57a4 77
mbed_official 48:e9a2c7cb57a4 78 /* GIC registers - Distributor */
mbed_official 48:e9a2c7cb57a4 79 #define GICD_ICDICER0 (*((volatile U32 *)(GICDistributor_BASE + 0x180))) /* - RW - Interrupt Clear-Enable Registers */
mbed_official 48:e9a2c7cb57a4 80 #define GICD_ICDISER0 (*((volatile U32 *)(GICDistributor_BASE + 0x100))) /* - RW - Interrupt Set-Enable Registers */
mbed_official 48:e9a2c7cb57a4 81 #define GICD_ICDIPR0 (*((volatile U32 *)(GICDistributor_BASE + 0x400))) /* - RW - Interrupt Priority Registers */
mbed_official 48:e9a2c7cb57a4 82 #define GICD_ICDSGIR (*((volatile U32 *)(GICDistributor_BASE + 0xf00))) /* - RW - Interrupt Software Interrupt Register */
mbed_official 48:e9a2c7cb57a4 83 #define GICD_ICDICERx(irq) *(volatile U32 *)(&GICD_ICDICER0 + irq/32)
mbed_official 48:e9a2c7cb57a4 84 #define GICD_ICDISERx(irq) *(volatile U32 *)(&GICD_ICDISER0 + irq/32)
mbed_official 48:e9a2c7cb57a4 85
mbed_official 48:e9a2c7cb57a4 86 /* GIC register - CPU Interface */
mbed_official 48:e9a2c7cb57a4 87 #define GICI_ICCPMR (*((volatile U32 *)(GICInterface_BASE + 0x004))) /* - RW - Interrupt Priority Mask Register */
mbed_official 48:e9a2c7cb57a4 88
mbed_official 48:e9a2c7cb57a4 89 #define SGI_PENDSV 0 /* SGI0 */
mbed_official 48:e9a2c7cb57a4 90 #define SGI_PENDSV_BIT ((U32)(1 << (SGI_PENDSV & 0xf)))
mbed_official 48:e9a2c7cb57a4 91
mbed_official 48:e9a2c7cb57a4 92 //Increase priority filter to prevent timer and PendSV interrupts signaling. Guarantees that interrupts will not be forwarded.
mbed_official 48:e9a2c7cb57a4 93 #define OS_LOCK() int irq_dis = __disable_irq();\
mbed_official 48:e9a2c7cb57a4 94 priority = GICI_ICCPMR; \
mbed_official 48:e9a2c7cb57a4 95 GICI_ICCPMR = 0xff; \
mbed_official 48:e9a2c7cb57a4 96 GICI_ICCPMR = GICI_ICCPMR - 1; \
mbed_official 48:e9a2c7cb57a4 97 while(GICI_ICCPMR > priority);\
mbed_official 48:e9a2c7cb57a4 98 __DSB();\
mbed_official 48:e9a2c7cb57a4 99 if(!irq_dis) __enable_irq(); \
mbed_official 48:e9a2c7cb57a4 100
mbed_official 48:e9a2c7cb57a4 101 //Restore priority filter. Re-enable timer and PendSV signaling
mbed_official 48:e9a2c7cb57a4 102 #define OS_UNLOCK() __DSB(); \
mbed_official 48:e9a2c7cb57a4 103 GICI_ICCPMR = priority; \
mbed_official 48:e9a2c7cb57a4 104
mbed_official 48:e9a2c7cb57a4 105 #define OS_PEND_IRQ() GICD_ICDSGIR = 0x0010000 | SGI_PENDSV
mbed_official 48:e9a2c7cb57a4 106 #define OS_PEND(fl,p) if(p) OS_PEND_IRQ();
mbed_official 48:e9a2c7cb57a4 107 #define OS_UNPEND(fl)
mbed_official 48:e9a2c7cb57a4 108
mbed_official 48:e9a2c7cb57a4 109 /* HW initialization needs to be done in os_tick_init (void) -RTX_Conf_CM.c-
mbed_official 48:e9a2c7cb57a4 110 * OS_X_INIT enables the IRQ n in the GIC */
mbed_official 48:e9a2c7cb57a4 111 #define OS_X_INIT(n) char *reg; \
mbed_official 48:e9a2c7cb57a4 112 reg = (char *)(&GICD_ICDIPR0 + n / 4); \
mbed_official 48:e9a2c7cb57a4 113 reg += n % 4; \
mbed_official 48:e9a2c7cb57a4 114 *reg = (char)0xff; \
mbed_official 48:e9a2c7cb57a4 115 *reg = *reg - 1; \
mbed_official 48:e9a2c7cb57a4 116 GICD_ICDISERx(n) = (U32)(1 << n % 32);
mbed_official 48:e9a2c7cb57a4 117 #define OS_X_LOCK(n) OS_LOCK()
mbed_official 48:e9a2c7cb57a4 118 #define OS_X_UNLOCK(n) OS_UNLOCK()
mbed_official 48:e9a2c7cb57a4 119 #define OS_X_PEND_IRQ() OS_PEND_IRQ()
mbed_official 48:e9a2c7cb57a4 120 #define OS_X_PEND(fl,p) if(p) OS_X_PEND_IRQ();
mbed_official 48:e9a2c7cb57a4 121 #define OS_X_UNPEND(fl)
mbed_official 48:e9a2c7cb57a4 122
mbed_official 48:e9a2c7cb57a4 123
mbed_official 48:e9a2c7cb57a4 124 /* Functions */
mbed_official 48:e9a2c7cb57a4 125 #ifdef __USE_EXCLUSIVE_ACCESS
mbed_official 48:e9a2c7cb57a4 126 #define rt_inc(p) while(__strex((__ldrex(p)+1),p))
mbed_official 48:e9a2c7cb57a4 127 #define rt_dec(p) while(__strex((__ldrex(p)-1),p))
mbed_official 48:e9a2c7cb57a4 128 #else
mbed_official 48:e9a2c7cb57a4 129 #define rt_inc(p) { int irq_dis = __disable_irq();(*p)++;if(!irq_dis) __enable_irq(); }
mbed_official 48:e9a2c7cb57a4 130 #define rt_dec(p) { int irq_dis = __disable_irq();(*p)--;if(!irq_dis) __enable_irq(); }
mbed_official 48:e9a2c7cb57a4 131 #endif
mbed_official 48:e9a2c7cb57a4 132
mbed_official 48:e9a2c7cb57a4 133 __inline static U32 rt_inc_qi (U32 size, U8 *count, U8 *first) {
mbed_official 48:e9a2c7cb57a4 134 U32 cnt,c2;
mbed_official 48:e9a2c7cb57a4 135 #ifdef __USE_EXCLUSIVE_ACCESS
mbed_official 48:e9a2c7cb57a4 136 do {
mbed_official 48:e9a2c7cb57a4 137 if ((cnt = __ldrex(count)) == size) {
mbed_official 48:e9a2c7cb57a4 138 __clrex();
mbed_official 48:e9a2c7cb57a4 139 return (cnt); }
mbed_official 48:e9a2c7cb57a4 140 } while (__strex(cnt+1, count));
mbed_official 48:e9a2c7cb57a4 141 do {
mbed_official 48:e9a2c7cb57a4 142 c2 = (cnt = __ldrex(first)) + 1;
mbed_official 48:e9a2c7cb57a4 143 if (c2 == size) c2 = 0;
mbed_official 48:e9a2c7cb57a4 144 } while (__strex(c2, first));
mbed_official 48:e9a2c7cb57a4 145 #else
mbed_official 48:e9a2c7cb57a4 146 int irq_dis;
mbed_official 48:e9a2c7cb57a4 147 irq_dis = __disable_irq();
mbed_official 48:e9a2c7cb57a4 148 if ((cnt = *count) < size) {
mbed_official 48:e9a2c7cb57a4 149 *count = cnt+1;
mbed_official 48:e9a2c7cb57a4 150 c2 = (cnt = *first) + 1;
mbed_official 48:e9a2c7cb57a4 151 if (c2 == size) c2 = 0;
mbed_official 48:e9a2c7cb57a4 152 *first = c2;
mbed_official 48:e9a2c7cb57a4 153 }
mbed_official 48:e9a2c7cb57a4 154 if(!irq_dis) __enable_irq ();
mbed_official 48:e9a2c7cb57a4 155 #endif
mbed_official 48:e9a2c7cb57a4 156 return (cnt);
mbed_official 48:e9a2c7cb57a4 157 }
mbed_official 48:e9a2c7cb57a4 158
mbed_official 48:e9a2c7cb57a4 159 __inline static void rt_systick_init (void) {
mbed_official 48:e9a2c7cb57a4 160 /* Cortex-A doesn't have a Systick. User needs to provide an alternative timer using RTX_Conf_CM configuration */
mbed_official 48:e9a2c7cb57a4 161 /* HW initialization needs to be done in os_tick_init (void) -RTX_Conf_CM.c- */
mbed_official 48:e9a2c7cb57a4 162 }
mbed_official 48:e9a2c7cb57a4 163
mbed_official 48:e9a2c7cb57a4 164 __inline static void rt_svc_init (void) {
mbed_official 48:e9a2c7cb57a4 165 /* Register pendSV - through SGI */
mbed_official 48:e9a2c7cb57a4 166 char *reg;
mbed_official 48:e9a2c7cb57a4 167
mbed_official 48:e9a2c7cb57a4 168 reg = (char *)(&GICD_ICDIPR0 + SGI_PENDSV/4);
mbed_official 48:e9a2c7cb57a4 169 reg += SGI_PENDSV % 4;
mbed_official 48:e9a2c7cb57a4 170 /* Write 0xff to read priority level */
mbed_official 48:e9a2c7cb57a4 171 *reg = (char)0xff;
mbed_official 48:e9a2c7cb57a4 172 /* Read priority level and set the lowest possible*/
mbed_official 48:e9a2c7cb57a4 173 *reg = *reg - 1;
mbed_official 48:e9a2c7cb57a4 174
mbed_official 48:e9a2c7cb57a4 175 GICD_ICDISERx(SGI_PENDSV) = (U32)SGI_PENDSV_BIT;
mbed_official 48:e9a2c7cb57a4 176 }
mbed_official 48:e9a2c7cb57a4 177
mbed_official 48:e9a2c7cb57a4 178 extern void rt_set_PSP (U32 stack);
mbed_official 48:e9a2c7cb57a4 179 extern U32 rt_get_PSP (void);
mbed_official 48:e9a2c7cb57a4 180 extern void os_set_env (P_TCB p_TCB);
mbed_official 48:e9a2c7cb57a4 181 extern void *_alloc_box (void *box_mem);
mbed_official 48:e9a2c7cb57a4 182 extern int _free_box (void *box_mem, void *box);
mbed_official 48:e9a2c7cb57a4 183
mbed_official 48:e9a2c7cb57a4 184 extern void rt_init_stack (P_TCB p_TCB, FUNCP task_body);
mbed_official 48:e9a2c7cb57a4 185 extern void rt_ret_val (P_TCB p_TCB, U32 v0);
mbed_official 48:e9a2c7cb57a4 186 extern void rt_ret_val2 (P_TCB p_TCB, U32 v0, U32 v1);
mbed_official 48:e9a2c7cb57a4 187
mbed_official 48:e9a2c7cb57a4 188 extern void dbg_init (void);
mbed_official 48:e9a2c7cb57a4 189 extern void dbg_task_notify (P_TCB p_tcb, BOOL create);
mbed_official 48:e9a2c7cb57a4 190 extern void dbg_task_switch (U32 task_id);
mbed_official 48:e9a2c7cb57a4 191
mbed_official 48:e9a2c7cb57a4 192 #define DBG_INIT()
mbed_official 48:e9a2c7cb57a4 193 #define DBG_TASK_NOTIFY(p_tcb,create)
mbed_official 48:e9a2c7cb57a4 194 #define DBG_TASK_SWITCH(task_id)
mbed_official 48:e9a2c7cb57a4 195
mbed_official 48:e9a2c7cb57a4 196 /*----------------------------------------------------------------------------
mbed_official 48:e9a2c7cb57a4 197 * end of file
mbed_official 48:e9a2c7cb57a4 198 *---------------------------------------------------------------------------*/
mbed_official 48:e9a2c7cb57a4 199