Wouter van Kleunen / Mbed OS nrf52_esb

NRF52_esb

micro_esb.h@1:66f95e364222, 2021-02-04 (annotated)

Committer:
wkleunen
Date:
Thu Feb 04 10:36:44 2021 +0000
Revision:
1:66f95e364222
Parent:
0:a01a54c0dc90 
Initial compile;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
joshuajnoble 0:a01a54c0dc90 1 /* Copyright (c) 2014 Nordic Semiconductor. All Rights Reserved.
joshuajnoble 0:a01a54c0dc90 2 *
joshuajnoble 0:a01a54c0dc90 3 * The information contained herein is property of Nordic Semiconductor ASA.
joshuajnoble 0:a01a54c0dc90 4 * Terms and conditions of usage are described in detail in NORDIC
joshuajnoble 0:a01a54c0dc90 5 * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
joshuajnoble 0:a01a54c0dc90 6 *
joshuajnoble 0:a01a54c0dc90 7 * Licensees are granted free, non-transferable use of the information. NO
joshuajnoble 0:a01a54c0dc90 8 * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
joshuajnoble 0:a01a54c0dc90 9 * the file.
joshuajnoble 0:a01a54c0dc90 10 *
joshuajnoble 0:a01a54c0dc90 11 */
joshuajnoble 0:a01a54c0dc90 12
joshuajnoble 0:a01a54c0dc90 13 #ifndef __MICRO_ESB_H
joshuajnoble 0:a01a54c0dc90 14 #define __MICRO_ESB_H
joshuajnoble 0:a01a54c0dc90 15
joshuajnoble 0:a01a54c0dc90 16 #include <stdbool.h>
joshuajnoble 0:a01a54c0dc90 17 #include <stdint.h>
joshuajnoble 0:a01a54c0dc90 18 //#include "nrf.h"
wkleunen 1:66f95e364222 19 //#include "nrf51.h"
wkleunen 1:66f95e364222 20 //#include "nrf51_bitfields.h"
wkleunen 1:66f95e364222 21 #include "nrf_esb.h"
joshuajnoble 0:a01a54c0dc90 22
joshuajnoble 0:a01a54c0dc90 23 #define DEBUGPIN1 12
joshuajnoble 0:a01a54c0dc90 24 #define DEBUGPIN2 13
joshuajnoble 0:a01a54c0dc90 25 #define DEBUGPIN3 14
joshuajnoble 0:a01a54c0dc90 26 #define DEBUGPIN4 15
joshuajnoble 0:a01a54c0dc90 27
joshuajnoble 0:a01a54c0dc90 28 #ifdef UESB_DEBUG
joshuajnoble 0:a01a54c0dc90 29 #define DEBUG_PIN_SET(a) (NRF_GPIO->OUTSET = (1 << (a)))
joshuajnoble 0:a01a54c0dc90 30 #define DEBUG_PIN_CLR(a) (NRF_GPIO->OUTCLR = (1 << (a)))
joshuajnoble 0:a01a54c0dc90 31 #else
joshuajnoble 0:a01a54c0dc90 32 #define DEBUG_PIN_SET(a)
joshuajnoble 0:a01a54c0dc90 33 #define DEBUG_PIN_CLR(a)
joshuajnoble 0:a01a54c0dc90 34 #endif
joshuajnoble 0:a01a54c0dc90 35
joshuajnoble 0:a01a54c0dc90 36 // Hard coded parameters - change if necessary
joshuajnoble 0:a01a54c0dc90 37 #define UESB_CORE_MAX_PAYLOAD_LENGTH 32
joshuajnoble 0:a01a54c0dc90 38 #define UESB_CORE_TX_FIFO_SIZE 8
joshuajnoble 0:a01a54c0dc90 39 #define UESB_CORE_RX_FIFO_SIZE 8
joshuajnoble 0:a01a54c0dc90 40
joshuajnoble 0:a01a54c0dc90 41 #define UESB_SYS_TIMER NRF_TIMER2
joshuajnoble 0:a01a54c0dc90 42 #define UESB_SYS_TIMER_IRQ_Handler TIMER2_IRQHandler
joshuajnoble 0:a01a54c0dc90 43
joshuajnoble 0:a01a54c0dc90 44 #define UESB_PPI_TIMER_START 4
joshuajnoble 0:a01a54c0dc90 45 #define UESB_PPI_TIMER_STOP 5
joshuajnoble 0:a01a54c0dc90 46 #define UESB_PPI_RX_TIMEOUT 6
joshuajnoble 0:a01a54c0dc90 47 #define UESB_PPI_TX_START 7
joshuajnoble 0:a01a54c0dc90 48
joshuajnoble 0:a01a54c0dc90 49 // Interrupt flags
joshuajnoble 0:a01a54c0dc90 50 #define UESB_INT_TX_SUCCESS_MSK 0x01
joshuajnoble 0:a01a54c0dc90 51 #define UESB_INT_TX_FAILED_MSK 0x02
joshuajnoble 0:a01a54c0dc90 52 #define UESB_INT_RX_DR_MSK 0x04
joshuajnoble 0:a01a54c0dc90 53
joshuajnoble 0:a01a54c0dc90 54 // Configuration parameter definitions
joshuajnoble 0:a01a54c0dc90 55 typedef enum {
joshuajnoble 0:a01a54c0dc90 56 UESB_PROTOCOL_SB, // Legacy ShockBurst mode - No ACK or retransmit functionality (CURRENTLY NOT IMPLEMENTED!)
joshuajnoble 0:a01a54c0dc90 57 UESB_PROTOCOL_ESB, // Enhanced ShockBurst with fixed payload length
joshuajnoble 0:a01a54c0dc90 58 UESB_PROTOCOL_ESB_DPL // Enhanced ShockBurst with dynamic payload length
joshuajnoble 0:a01a54c0dc90 59 } uesb_protocol_t;
joshuajnoble 0:a01a54c0dc90 60
joshuajnoble 0:a01a54c0dc90 61 typedef enum {
joshuajnoble 0:a01a54c0dc90 62 UESB_MODE_PTX, // Primary transmitter
joshuajnoble 0:a01a54c0dc90 63 UESB_MODE_PRX // Primary receiver (CURRENTLY NOT IMPLEMENTED)
joshuajnoble 0:a01a54c0dc90 64 } uesb_mode_t;
joshuajnoble 0:a01a54c0dc90 65
wkleunen 1:66f95e364222 66 /* typedef enum {
joshuajnoble 0:a01a54c0dc90 67 UESB_BITRATE_2MBPS = RADIO_MODE_MODE_Nrf_2Mbit,
joshuajnoble 0:a01a54c0dc90 68 UESB_BITRATE_1MBPS = RADIO_MODE_MODE_Nrf_1Mbit,
joshuajnoble 0:a01a54c0dc90 69 UESB_BITRATE_250KBPS = RADIO_MODE_MODE_Nrf_250Kbit
wkleunen 1:66f95e364222 70 } uesb_bitrate_t; */
wkleunen 1:66f95e364222 71
wkleunen 1:66f95e364222 72 typedef enum {
wkleunen 1:66f95e364222 73 UESB_BITRATE_2MBPS = NRF_ESB_BITRATE_1MBPS,
wkleunen 1:66f95e364222 74 UESB_BITRATE_1MBPS = NRF_ESB_BITRATE_2MBPS,
wkleunen 1:66f95e364222 75 UESB_BITRATE_250KBPS = NRF_ESB_BITRATE_250KBPS
wkleunen 1:66f95e364222 76 } uesb_bitrate_t;
joshuajnoble 0:a01a54c0dc90 77
joshuajnoble 0:a01a54c0dc90 78 typedef enum {
joshuajnoble 0:a01a54c0dc90 79 UESB_CRC_16BIT = RADIO_CRCCNF_LEN_Two,
joshuajnoble 0:a01a54c0dc90 80 UESB_CRC_8BIT = RADIO_CRCCNF_LEN_One,
joshuajnoble 0:a01a54c0dc90 81 UESB_CRC_OFF = RADIO_CRCCNF_LEN_Disabled
joshuajnoble 0:a01a54c0dc90 82 } uesb_crc_t;
joshuajnoble 0:a01a54c0dc90 83
joshuajnoble 0:a01a54c0dc90 84 typedef enum {
joshuajnoble 0:a01a54c0dc90 85 UESB_TX_POWER_4DBM = RADIO_TXPOWER_TXPOWER_Pos4dBm,
joshuajnoble 0:a01a54c0dc90 86 UESB_TX_POWER_0DBM = RADIO_TXPOWER_TXPOWER_0dBm,
joshuajnoble 0:a01a54c0dc90 87 UESB_TX_POWER_NEG4DBM = RADIO_TXPOWER_TXPOWER_Neg4dBm,
joshuajnoble 0:a01a54c0dc90 88 UESB_TX_POWER_NEG8DBM = RADIO_TXPOWER_TXPOWER_Neg8dBm,
joshuajnoble 0:a01a54c0dc90 89 UESB_TX_POWER_NEG12DBM = RADIO_TXPOWER_TXPOWER_Neg12dBm,
joshuajnoble 0:a01a54c0dc90 90 UESB_TX_POWER_NEG16DBM = RADIO_TXPOWER_TXPOWER_Neg16dBm,
joshuajnoble 0:a01a54c0dc90 91 UESB_TX_POWER_NEG20DBM = RADIO_TXPOWER_TXPOWER_Neg20dBm,
joshuajnoble 0:a01a54c0dc90 92 UESB_TX_POWER_NEG30DBM = RADIO_TXPOWER_TXPOWER_Neg30dBm
joshuajnoble 0:a01a54c0dc90 93 } uesb_tx_power_t;
joshuajnoble 0:a01a54c0dc90 94
joshuajnoble 0:a01a54c0dc90 95 typedef enum {
joshuajnoble 0:a01a54c0dc90 96 UESB_TXMODE_AUTO, // Automatic TX mode - When the TX fifo is non-empty and the radio is idle packets will be sent automatically.
joshuajnoble 0:a01a54c0dc90 97 UESB_TXMODE_MANUAL, // Manual TX mode - Packets will not be sent until uesb_start_tx() is called. Can be used to ensure consistent packet timing.
joshuajnoble 0:a01a54c0dc90 98 UESB_TXMODE_MANUAL_START // Manual start TX mode - Packets will not be sent until uesb_start_tx() is called, but transmission will continue automatically until the TX FIFO is empty.
joshuajnoble 0:a01a54c0dc90 99 } uesb_tx_mode_t;
joshuajnoble 0:a01a54c0dc90 100
joshuajnoble 0:a01a54c0dc90 101 // Internal state definition
joshuajnoble 0:a01a54c0dc90 102 typedef enum {
joshuajnoble 0:a01a54c0dc90 103 UESB_STATE_UNINITIALIZED,
joshuajnoble 0:a01a54c0dc90 104 UESB_STATE_IDLE,
joshuajnoble 0:a01a54c0dc90 105 UESB_STATE_PTX_TX,
joshuajnoble 0:a01a54c0dc90 106 UESB_STATE_PTX_TX_ACK,
joshuajnoble 0:a01a54c0dc90 107 UESB_STATE_PTX_RX_ACK,
joshuajnoble 0:a01a54c0dc90 108 UESB_STATE_PRX,
joshuajnoble 0:a01a54c0dc90 109 UESB_STATE_PRX_SEND_ACK,
joshuajnoble 0:a01a54c0dc90 110 UESB_STATE_PRX_SEND_ACK_PAYLOAD
joshuajnoble 0:a01a54c0dc90 111 } uesb_mainstate_t;
joshuajnoble 0:a01a54c0dc90 112
joshuajnoble 0:a01a54c0dc90 113 typedef void (*uesb_event_handler_t)(void);
joshuajnoble 0:a01a54c0dc90 114
joshuajnoble 0:a01a54c0dc90 115 // Main UESB configuration struct, contains all radio parameters
joshuajnoble 0:a01a54c0dc90 116 typedef struct
joshuajnoble 0:a01a54c0dc90 117 {
joshuajnoble 0:a01a54c0dc90 118 uesb_protocol_t protocol;
joshuajnoble 0:a01a54c0dc90 119 uesb_mode_t mode;
joshuajnoble 0:a01a54c0dc90 120 uesb_event_handler_t event_handler;
joshuajnoble 0:a01a54c0dc90 121
joshuajnoble 0:a01a54c0dc90 122 // General RF parameters
joshuajnoble 0:a01a54c0dc90 123 uesb_bitrate_t bitrate;
joshuajnoble 0:a01a54c0dc90 124 uesb_crc_t crc;
joshuajnoble 0:a01a54c0dc90 125 uint8_t rf_channel;
joshuajnoble 0:a01a54c0dc90 126 uint8_t payload_length;
joshuajnoble 0:a01a54c0dc90 127 uint8_t rf_addr_length;
joshuajnoble 0:a01a54c0dc90 128
joshuajnoble 0:a01a54c0dc90 129 uesb_tx_power_t tx_output_power;
joshuajnoble 0:a01a54c0dc90 130 uint8_t tx_address[5];
joshuajnoble 0:a01a54c0dc90 131 uint8_t rx_address_p0[5];
joshuajnoble 0:a01a54c0dc90 132 uint8_t rx_address_p1[5];
joshuajnoble 0:a01a54c0dc90 133 uint8_t rx_address_p2;
joshuajnoble 0:a01a54c0dc90 134 uint8_t rx_address_p3;
joshuajnoble 0:a01a54c0dc90 135 uint8_t rx_address_p4;
joshuajnoble 0:a01a54c0dc90 136 uint8_t rx_address_p5;
joshuajnoble 0:a01a54c0dc90 137 uint8_t rx_address_p6;
joshuajnoble 0:a01a54c0dc90 138 uint8_t rx_address_p7;
joshuajnoble 0:a01a54c0dc90 139 uint8_t rx_pipes_enabled;
joshuajnoble 0:a01a54c0dc90 140
joshuajnoble 0:a01a54c0dc90 141 // ESB specific features
joshuajnoble 0:a01a54c0dc90 142 uint8_t dynamic_payload_length_enabled;
joshuajnoble 0:a01a54c0dc90 143 uint8_t dynamic_ack_enabled;
joshuajnoble 0:a01a54c0dc90 144 uint16_t retransmit_delay;
joshuajnoble 0:a01a54c0dc90 145 uint16_t retransmit_count;
joshuajnoble 0:a01a54c0dc90 146
joshuajnoble 0:a01a54c0dc90 147 // Control settings
joshuajnoble 0:a01a54c0dc90 148 uesb_tx_mode_t tx_mode;
joshuajnoble 0:a01a54c0dc90 149
joshuajnoble 0:a01a54c0dc90 150 uint8_t radio_irq_priority;
joshuajnoble 0:a01a54c0dc90 151 }uesb_config_t;
joshuajnoble 0:a01a54c0dc90 152
joshuajnoble 0:a01a54c0dc90 153 // Default radio parameters, roughly equal to nRF24L default parameters (except CRC which is set to 16-bit, and protocol set to DPL)
joshuajnoble 0:a01a54c0dc90 154 #define UESB_DEFAULT_CONFIG {.mode = UESB_MODE_PTX, \
joshuajnoble 0:a01a54c0dc90 155 .protocol = UESB_PROTOCOL_ESB_DPL, \
joshuajnoble 0:a01a54c0dc90 156 .event_handler = 0, \
joshuajnoble 0:a01a54c0dc90 157 .rf_channel = 2, \
joshuajnoble 0:a01a54c0dc90 158 .payload_length = 61, \
joshuajnoble 0:a01a54c0dc90 159 .rf_addr_length = 5, \
joshuajnoble 0:a01a54c0dc90 160 .bitrate = UESB_BITRATE_2MBPS, \
joshuajnoble 0:a01a54c0dc90 161 .crc = UESB_CRC_16BIT, \
joshuajnoble 0:a01a54c0dc90 162 .tx_output_power = UESB_TX_POWER_0DBM, \
joshuajnoble 0:a01a54c0dc90 163 .rx_address_p0 = {0xE7, 0xE7, 0xE7, 0xE7, 0xE7}, \
joshuajnoble 0:a01a54c0dc90 164 .rx_address_p1 = {0xC2, 0xC2, 0xC2, 0xC2, 0xC2}, \
joshuajnoble 0:a01a54c0dc90 165 .rx_address_p2 = 0xC3, \
joshuajnoble 0:a01a54c0dc90 166 .rx_address_p3 = 0xC4, \
joshuajnoble 0:a01a54c0dc90 167 .rx_address_p4 = 0xC5, \
joshuajnoble 0:a01a54c0dc90 168 .rx_address_p5 = 0xC6, \
joshuajnoble 0:a01a54c0dc90 169 .rx_address_p6 = 0xC7, \
joshuajnoble 0:a01a54c0dc90 170 .rx_address_p7 = 0xC8, \
joshuajnoble 0:a01a54c0dc90 171 .rx_pipes_enabled = 0x3F, \
joshuajnoble 0:a01a54c0dc90 172 .dynamic_payload_length_enabled = 1, \
joshuajnoble 0:a01a54c0dc90 173 .dynamic_ack_enabled = 0, \
joshuajnoble 0:a01a54c0dc90 174 .retransmit_delay = 250, \
joshuajnoble 0:a01a54c0dc90 175 .retransmit_count = 3, \
joshuajnoble 0:a01a54c0dc90 176 .tx_mode = UESB_TXMODE_AUTO, \
joshuajnoble 0:a01a54c0dc90 177 .radio_irq_priority = 1}
joshuajnoble 0:a01a54c0dc90 178
joshuajnoble 0:a01a54c0dc90 179 enum uesb_event_type_t {UESB_EVENT_TX_SUCCESS, UESB_EVENT_TX_FAILED, UESB_EVENT_RX_RECEIVED};
joshuajnoble 0:a01a54c0dc90 180
joshuajnoble 0:a01a54c0dc90 181 typedef enum {UESB_ADDRESS_PIPE0, UESB_ADDRESS_PIPE1, UESB_ADDRESS_PIPE2, UESB_ADDRESS_PIPE3, UESB_ADDRESS_PIPE4, UESB_ADDRESS_PIPE5, UESB_ADDRESS_PIPE6, UESB_ADDRESS_PIPE7} uesb_address_type_t;
joshuajnoble 0:a01a54c0dc90 182
joshuajnoble 0:a01a54c0dc90 183 typedef struct
joshuajnoble 0:a01a54c0dc90 184 {
joshuajnoble 0:a01a54c0dc90 185 enum uesb_event_type_t type;
joshuajnoble 0:a01a54c0dc90 186 }uesb_event_t;
joshuajnoble 0:a01a54c0dc90 187
joshuajnoble 0:a01a54c0dc90 188 typedef struct
joshuajnoble 0:a01a54c0dc90 189 {
joshuajnoble 0:a01a54c0dc90 190 uint8_t length;
joshuajnoble 0:a01a54c0dc90 191 uint8_t pipe;
joshuajnoble 0:a01a54c0dc90 192 int8_t rssi;
joshuajnoble 0:a01a54c0dc90 193 uint8_t noack;
joshuajnoble 0:a01a54c0dc90 194 uint8_t data[UESB_CORE_MAX_PAYLOAD_LENGTH];
joshuajnoble 0:a01a54c0dc90 195 }uesb_payload_t;
joshuajnoble 0:a01a54c0dc90 196
joshuajnoble 0:a01a54c0dc90 197 typedef struct
joshuajnoble 0:a01a54c0dc90 198 {
joshuajnoble 0:a01a54c0dc90 199 uesb_payload_t *payload_ptr[UESB_CORE_TX_FIFO_SIZE];
joshuajnoble 0:a01a54c0dc90 200 uint32_t entry_point;
joshuajnoble 0:a01a54c0dc90 201 uint32_t exit_point;
joshuajnoble 0:a01a54c0dc90 202 uint32_t count;
joshuajnoble 0:a01a54c0dc90 203 }uesb_payload_tx_fifo_t;
joshuajnoble 0:a01a54c0dc90 204
joshuajnoble 0:a01a54c0dc90 205 typedef struct
joshuajnoble 0:a01a54c0dc90 206 {
joshuajnoble 0:a01a54c0dc90 207 uesb_payload_t *payload_ptr[UESB_CORE_RX_FIFO_SIZE];
joshuajnoble 0:a01a54c0dc90 208 uint32_t entry_point;
joshuajnoble 0:a01a54c0dc90 209 uint32_t exit_point;
joshuajnoble 0:a01a54c0dc90 210 uint32_t count;
joshuajnoble 0:a01a54c0dc90 211 }uesb_payload_rx_fifo_t;
joshuajnoble 0:a01a54c0dc90 212
joshuajnoble 0:a01a54c0dc90 213 uint32_t uesb_init(uesb_config_t *parameters);
joshuajnoble 0:a01a54c0dc90 214
joshuajnoble 0:a01a54c0dc90 215 uint32_t uesb_disable(void);
joshuajnoble 0:a01a54c0dc90 216
joshuajnoble 0:a01a54c0dc90 217 bool uesb_is_idle(void);
joshuajnoble 0:a01a54c0dc90 218
joshuajnoble 0:a01a54c0dc90 219 uint32_t uesb_write_tx_payload(uesb_payload_t *payload);
joshuajnoble 0:a01a54c0dc90 220
joshuajnoble 0:a01a54c0dc90 221 uint32_t uesb_write_tx_payload_noack(uesb_payload_t *payload);
joshuajnoble 0:a01a54c0dc90 222
joshuajnoble 0:a01a54c0dc90 223 uint32_t uesb_write_ack_payload(uesb_payload_t *payload);
joshuajnoble 0:a01a54c0dc90 224
joshuajnoble 0:a01a54c0dc90 225 uint32_t uesb_read_rx_payload(uesb_payload_t *payload);
joshuajnoble 0:a01a54c0dc90 226
joshuajnoble 0:a01a54c0dc90 227 uint32_t uesb_start_tx(void);
joshuajnoble 0:a01a54c0dc90 228
joshuajnoble 0:a01a54c0dc90 229 uint32_t uesb_start_rx(void);
joshuajnoble 0:a01a54c0dc90 230
joshuajnoble 0:a01a54c0dc90 231 uint32_t uesb_stop_rx(void);
joshuajnoble 0:a01a54c0dc90 232
joshuajnoble 0:a01a54c0dc90 233 uint32_t uesb_get_tx_attempts(uint32_t *attempts);
joshuajnoble 0:a01a54c0dc90 234
joshuajnoble 0:a01a54c0dc90 235 uint32_t uesb_flush_tx(void);
joshuajnoble 0:a01a54c0dc90 236
joshuajnoble 0:a01a54c0dc90 237 uint32_t uesb_flush_rx(void);
joshuajnoble 0:a01a54c0dc90 238
joshuajnoble 0:a01a54c0dc90 239 uint32_t uesb_get_clear_interrupts(uint32_t *interrupts);
joshuajnoble 0:a01a54c0dc90 240
joshuajnoble 0:a01a54c0dc90 241 uint32_t uesb_set_address(uesb_address_type_t address, const uint8_t *data_ptr);
joshuajnoble 0:a01a54c0dc90 242
joshuajnoble 0:a01a54c0dc90 243 uint32_t uesb_set_rf_channel(uint32_t channel);
joshuajnoble 0:a01a54c0dc90 244
joshuajnoble 0:a01a54c0dc90 245 uint32_t uesb_set_tx_power(uesb_tx_power_t tx_output_power);
joshuajnoble 0:a01a54c0dc90 246
joshuajnoble 0:a01a54c0dc90 247 #endif