Wim Huiskamp
SPI or I2C to UART Bridge
Dependents: SC16IS750_Test mbed_SC16IS750 Xadow_SC16IS750_Test Xadow_MPU9150AHRS
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SC16IS750.h
00001 /* SC16IS750 I2C or SPI to UART bridge 00002 * v0.1 WH, Nov 2013, Sparkfun WiFly Shield code library alpha 0 used as example, Added I2C I/F and many more methods. 00003 * https://forum.sparkfun.com/viewtopic.php?f=13&t=21846 00004 * v0.2 WH, Feb 2014, Added Doxygen Documentation, Added Hardware Reset pin methods. 00005 * v0.3 WH, Dec 2014, Added support for SC16IS752 dual UART. 00006 * v0.4 WH, Dec 2014, Added Repeated Start for I2C readRegister(). Set I2C clock at 100kb/s. Fixed and added some comments. 00007 * 00008 * Permission is hereby granted, free of charge, to any person obtaining a copy of this software 00009 * and associated documentation files (the "Software"), to deal in the Software without restriction, 00010 * including without limitation the rights to use, copy, modify, merge, publish, distribute, 00011 * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is 00012 * furnished to do so, subject to the following conditions: 00013 * 00014 * The above copyright notice and this permission notice shall be included in all copies or 00015 * substantial portions of the Software. 00016 * 00017 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING 00018 * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 00019 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, 00020 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 00021 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 00022 */ 00023 #ifndef _SC16IS750_H 00024 #define _SC16IS750_H 00025 00026 00027 #include "Stream.h" 00028 //#include <SerialBase.h> 00029 00030 //I2C Slaveaddresses A1 A0 00031 #define SC16IS750_SA0 0x90 /* VDD VDD */ 00032 #define SC16IS750_SA1 0x92 /* VDD VSS */ 00033 #define SC16IS750_SA2 0x94 /* VDD SCL */ 00034 #define SC16IS750_SA3 0x95 /* VDD SDA */ 00035 #define SC16IS750_SA4 0x98 /* VSS VDD */ 00036 #define SC16IS750_SA5 0x9A /* VSS VSS */ 00037 #define SC16IS750_SA6 0x9C /* VSS SCL */ 00038 #define SC16IS750_SA7 0x9E /* VSS SDA */ 00039 #define SC16IS750_SA8 0xA0 /* SCL VDD */ 00040 #define SC16IS750_SA9 0xA2 /* SCL VSS */ 00041 #define SC16IS750_SA10 0xA4 /* SCL SCL */ 00042 #define SC16IS750_SA11 0xA6 /* SCL SDA */ 00043 #define SC16IS750_SA12 0xA8 /* SDA VDD */ 00044 #define SC16IS750_SA13 0xAA /* SDA VSS */ 00045 #define SC16IS750_SA14 0xAC /* SDA SCL */ 00046 #define SC16IS750_SA15 0xAE /* SDA SDA */ 00047 00048 //Default I2C Slaveaddress 00049 #define SC16IS750_DEFAULT_ADDR SC16IS750_SA0 00050 00051 00052 /** See datasheet section 7.8 for configuring the 00053 * "Programmable baud rate generator" 00054 */ 00055 #define SC16IS750_XTAL_FREQ 14745600UL /* On-board crystal (New mid-2010 Version) */ 00056 #define SC16IS750_PRESCALER_1 1 /* Default prescaler after reset */ 00057 #define SC16IS750_PRESCALER_4 4 /* Selectable by setting MCR[7] */ 00058 #define SC16IS750_PRESCALER SC16IS750_PRESCALER_1 00059 #define SC16IS750_BAUDRATE_DIVISOR(baud) ((SC16IS750_XTAL_FREQ/SC16IS750_PRESCALER)/(baud*16UL)) 00060 00061 //Default baudrate 00062 #define SC16IS750_DEFAULT_BAUDRATE 9600 00063 00064 00065 /** See section 8.3 of the datasheet for definitions 00066 * of bits in the FIFO Control Register (FCR) 00067 */ 00068 #define FCR_RX_IRQ_60 (3 << 6) 00069 #define FCR_RX_IRQ_56 (2 << 6) 00070 #define FCR_RX_IRQ_16 (1 << 6) 00071 #define FCR_RX_IRQ_8 (0 << 6) 00072 //TX Level only accessible when EFR[4] is set 00073 #define FCR_TX_IRQ_56 (3 << 4) 00074 #define FCR_TX_IRQ_32 (2 << 4) 00075 #define FCR_TX_IRQ_16 (1 << 4) 00076 #define FCR_TX_IRQ_8 (0 << 4) 00077 //#define FCR_RESERVED (1 << 3) 00078 #define FCR_TX_FIFO_RST (1 << 2) 00079 #define FCR_RX_FIFO_RST (1 << 1) 00080 #define FCR_ENABLE_FIFO (1 << 0) 00081 00082 //FIFO size 00083 #define SC16IS750_FIFO_RX 64 00084 #define SC16IS750_FIFO_TX 64 00085 00086 00087 /** See section 8.4 of the datasheet for definitions 00088 * of bits in the Line Control Register (LCR) 00089 */ 00090 #define LCR_BITS5 0x00 00091 #define LCR_BITS6 0x01 00092 #define LCR_BITS7 0x02 00093 #define LCR_BITS8 0x03 00094 00095 #define LCR_BITS1 0x00 00096 #define LCR_BITS2 0x04 00097 00098 #define LCR_NONE 0x00 00099 #define LCR_ODD 0x08 00100 #define LCR_EVEN 0x18 00101 #define LCR_FORCED1 0x28 00102 #define LCR_FORCED0 0x38 00103 00104 #define LCR_BRK_ENA 0x40 00105 #define LCR_BRK_DIS 0x00 00106 00107 #define LCR_ENABLE_DIV 0x80 00108 #define LCR_DISABLE_DIV 0x00 00109 00110 #define LCR_ENABLE_ENHANCED_FUNCTIONS (0xBF) 00111 00112 00113 /** See section 8.5 of the datasheet for definitions 00114 * of bits in the Line status register (LSR) 00115 */ 00116 #define LSR_DR (0x01) /* Data ready in RX FIFO */ 00117 #define LSR_OE (0x02) /* Overrun error */ 00118 #define LSR_PE (0x04) /* Parity error */ 00119 #define LSR_FE (0x08) /* Framing error */ 00120 #define LSR_BI (0x10) /* Break interrupt */ 00121 #define LSR_THRE (0x20) /* Transmitter holding register (FIFO empty) */ 00122 #define LSR_TEMT (0x40) /* Transmitter empty (FIFO and TSR both empty) */ 00123 #define LSR_FFE (0x80) /* At least one PE, FE or BI in FIFO */ 00124 00125 00126 /** See section 8.6 of the datasheet for definitions 00127 * of bits in the Modem control register (MCR) 00128 */ 00129 #define MCR_MDTR (1 << 0) /* Data Terminal Ready pin control. */ 00130 #define MCR_MRTS (1 << 1) /* Request to Send pin control when not in Auto RTS mode.*/ 00131 //MCR[2] only accessible when EFR[4] is set 00132 #define MCR_ENABLE_TCR_TLR (1 << 2) 00133 #define MCR_ENABLE_LOOPBACK (1 << 4) 00134 //MCR[7:5] only accessible when EFR[4] is set 00135 #define MCR_ENABLE_XON_ANY_CHAR (1 << 5) 00136 #define MCR_ENABLE_IRDA (1 << 6) 00137 #define MCR_PRESCALE_1 (0 << 7) 00138 #define MCR_PRESCALE_4 (1 << 7) 00139 00140 00141 /** See section 8.7 of the datasheet for definitions 00142 * of bits in the Modem status register (MSR) 00143 */ 00144 #define MSR_DCTS (1 << 0) /* Delta CTS - CTS Changed State */ 00145 #define MSR_DDSR (1 << 1) /* Delta DSR - DSR Changed State */ 00146 #define MSR_DDI (1 << 2) /* Delta DI - DI Changed State */ 00147 #define MSR_DCD (1 << 3) /* Delta CD - CD Changed State */ 00148 #define MSR_CTS (1 << 4) /* CTS State - Complement of NCTS pin */ 00149 //MSR[7:5] only accessible when GPIO[7:4] are set as modem pin 00150 #define MSR_DSR (1 << 5) /* DSR State - Complement of NDSR pin */ 00151 #define MSR_RI (1 << 6) /* RI State - Complement of NRI pin */ 00152 #define MSR_CD (1 << 7) /* CD State - Complement of NCD pin */ 00153 00154 00155 /** See section 8.8 of the datasheet for definitions 00156 * of bits in the Interrupt enable register (IER) 00157 */ 00158 #define IER_ERHRI (0x01) /* Enable received data available interrupt */ 00159 #define IER_ETHRI (0x02) /* Enable transmitter holding register empty interrupt */ 00160 #define IER_ELSI (0x04) /* Enable receiver line status interrupt */ 00161 #define IER_EMSI (0x08) /* Enable modem status interrupt */ 00162 //IER[7:5] only accessible when EFR[4] is set 00163 #define IER_SLEEP (0x10) /* Enable sleep mode */ 00164 #define IER_XOFFI (0x20) /* Enable XOFF interrupt */ 00165 #define IER_RTSI (0x40) /* Enable RTS interrupt */ 00166 #define IER_CTSI (0x80) /* Enable CTS interrupt */ 00167 00168 00169 /** See section 8.9 of the datasheet for definitions 00170 * of bits in the Interrupt identification register (IIR) 00171 * Bit 0 is set to 0 if an IRQ is pending. 00172 * Bits 1..5 are used to identify the IRQ source. 00173 */ 00174 #define IIR_IRQ_NOT_PENDING (0x01) /* IRQ Not Pending */ 00175 #define IIR_TX_EMPTY (0x02) /* THR Interrupt */ 00176 #define IIR_RX_DATA (0x04) /* RHR Interrupt */ 00177 #define IIR_RX_ERROR (0x06) /* Line Status Error Interrupt */ 00178 #define IIR_RX_TIMEOUT (0x0B) /* RX Timeout Interrupt */ 00179 #define IIR_RX_XOFF (0x10) /* RX XOff Interrupt */ 00180 #define IIR_DCTS_DRTS (0x20) /* Delta CTS or RTS Interrupt */ 00181 #define IIR_DIO (0x30) /* Delta GPIO pin Interrupt */ 00182 00183 #define IIR_BITS_USED (0x07) 00184 00185 00186 /** See section 8.10 of the datasheet for definitions 00187 * of bits in the Enhanced Features Register (EFR) 00188 */ 00189 #define EFR_ENABLE_CTS (1 << 7) 00190 #define EFR_ENABLE_RTS (1 << 6) 00191 #define EFR_ENABLE_XOFF2_CHAR_DETECT (1 << 5) 00192 #define EFR_ENABLE_ENHANCED_FUNCTIONS (1 << 4) 00193 // EFR[3:0] are used to define Software Flow Control mode 00194 // See section 7.3 00195 #define EFR_DISABLE_TX_FLOW_CTRL (0x0 << 2) 00196 #define EFR_TX_XON2_XOFF2 (0x1 << 2) 00197 #define EFR_TX_XON1_XOFF1 (0x2 << 2) 00198 #define EFR_TX_XON2_1_XOFF2_1 (0x3 << 2) 00199 00200 #define EFR_DISABLE_RX_FLOW_CTRL (0x0 << 0) 00201 #define EFR_RX_XON2_XOFF2 (0x1 << 0) 00202 #define EFR_RX_XON1_XOFF1 (0x2 << 0) 00203 #define EFR_RX_XON2_1_XOFF2_1 (0x3 << 0) 00204 00205 #define EFR_TX_XON2_XOFF2_RX_FLOW (0x1 << 2) | (0x3 << 0) 00206 #define EFR_TX_XON1_XOFF1_RX_FLOW (0x2 << 2) | (0x3 << 0) 00207 #define EFR_TX_XON2_1_XOFF2_1_RX_FLOW (0x3 << 2) | (0x3 << 0) 00208 00209 00210 00211 /** See section 8.12 of the datasheet for definitions 00212 * of bits in the Transmission Control Register (TCR) 00213 * These levels control when RTS is asserted or de-asserted and auto RTS is enabled. Note that XON/XOFF is not supported in this lib. 00214 * Trigger level to halt transmission to the device : 0..15 (meaning 0-60 with a granularity of 4) 00215 * RTS is de-asserted when RX FIFO is above the set trigger level (i.e. buffer is getting full) 00216 * Trigger level to resume transmission to the device : 0..15 (meaning 0-60 with a granularity of 4) 00217 * RTS is asserted again when RX FIFO drops below the set trigger level (i.e. buffer has room again) 00218 */ 00219 #define TCR_HALT_DEFAULT (0x0E) 00220 #define TCR_RESUME_DEFAULT (0x08) 00221 00222 /** See section 8.12 of the datasheet for definitions 00223 * Note: The device will stop transmissions from the TX FIFO when CTS is de-asserted by external receiver and 00224 * auto CTS is enabled. Note that XON/XOFF is not supported in this lib. 00225 */ 00226 00227 00228 /** See section 7.5 and 8.13 of the datasheet for definitions 00229 * of bits in the Trigger Level Register (TLR) control when an IRQ is generated. 00230 * Trigger level for TX interrupt: 0..15 (meaning 0-60 with a granularity of 4) 00231 * IRQ when TX FIFO is above the set trigger level (i.e. buffer is getting full) 00232 * Trigger level for RX interrupt: 0..15 (meaning 0-60 with a granularity of 4) 00233 * IRQ when RX FIFO is above the set trigger level (i.e. data is waiting to be read) 00234 */ 00235 #define TLR_TX_DEFAULT (0x0E) 00236 #define TLR_RX_DEFAULT (0x04) 00237 00238 00239 /** 00240 * See section 8.16, 8.17, 8.18 of the datasheet for definitions 00241 * of bits in the IO Direction (IODIR), IO State (IOSTATE) and IO Interrupt Enable register (IOINTENA) 00242 * 00243 * Basically a direct mapping of register bits to GPIO pin. 00244 */ 00245 00246 00247 /** 00248 * See section 8.19 of the datasheet for definitions 00249 * of bits in the IO Control register (IOC) 00250 * 00251 * Bit 0 is set to 0 to enable latch of IO inputs. 00252 * Bit 1 is set to enable GPIO[7-4] as /RI, /CD, /DTR, /DST. 00253 * Bit 2 is set to enable software reset. 00254 */ 00255 #define IOC_ENA_LATCH (0x01) 00256 #define IOC_ENA_MODEM (0x02) /* Set GPIO[7:4] pins to modem functions */ 00257 #define IOC_SW_RST (0x04) 00258 00259 00260 /** 00261 * See section 8.20 of the datasheet for definitions 00262 * of bits in the Extra Features Control register (EFCR) 00263 * 00264 */ 00265 #define EFCR_ENA_RS485 (0x01) 00266 #define EFCR_DIS_RX (0x02) 00267 #define EFCR_DIS_TX (0x04) 00268 #define EFCR_ENA_TX_RTS (0x10) 00269 #define EFCR_INV_RTS_RS485 (0x20) 00270 #define EFCR_ENA_IRDA (0x80) 00271 00272 // See Chapter 11 of datasheet 00273 #define SPI_READ_MODE_FLAG (0x80) 00274 00275 00276 /** Abstract class SC16IS750 for a bridge between either SPI or I2C and a Serial port 00277 * 00278 * Supports both SPI and I2C interfaces through derived classes 00279 * 00280 * @code 00281 * 00282 * @endcode 00283 */ 00284 //class SC16IS750 { 00285 //class SC16IS750 : public SerialBase, public Stream { // Wrong, Serialbase can not be constructed for NC,NC 00286 class SC16IS750 : public Stream { 00287 public: 00288 00289 // SC16IS750 Register definitions (shifted to align) 00290 enum RegisterName { 00291 /* 00292 * 16750 addresses. Registers accessed when LCR[7] = 0. 00293 */ 00294 RHR = 0x00 << 3, /* Rx buffer register - Read access */ 00295 THR = 0x00 << 3, /* Tx holding register - Write access */ 00296 IER = 0x01 << 3, /* Interrupt enable reg - RD/WR access */ 00297 00298 /* 00299 * 16750 addresses. Registers accessed when LCR[7] = 1. 00300 */ 00301 DLL = 0x00 << 3, /* Divisor latch (LSB) - RD/WR access */ 00302 DLH = 0x01 << 3, /* Divisor latch (MSB) - RD/WR access */ 00303 00304 /* 00305 * 16750 addresses. IIR/FCR is accessed when LCR[7:0] <> 0xBF. 00306 * Bit 5 of the FCR register is accessed when LCR[7] = 1. 00307 */ 00308 IIR = 0x02 << 3, /* Interrupt id. register - Read only */ 00309 FCR = 0x02 << 3, /* FIFO control register - Write only */ 00310 /* 00311 * 16750 addresses. EFR is accessed when LCR[7:0] = 0xBF. 00312 */ 00313 EFR = 0x02 << 3, /* Enhanced features reg - RD/WR access */ 00314 00315 /* 00316 * 16750 addresses. 00317 */ 00318 LCR = 0x03 << 3, /* Line control register - RD/WR access */ 00319 /* 00320 * 16750 addresses. MCR/LSR is accessed when LCR[7:0] <> 0xBF. 00321 * Bit 7 of the MCR register is accessed when EFR[4] = 1. 00322 */ 00323 MCR = 0x04 << 3, /* Modem control register - RD/WR access */ 00324 LSR = 0x05 << 3, /* Line status register - Read only */ 00325 00326 /* 00327 * 16750 addresses. MSR/SPR is accessed when LCR[7:0] <> 0xBF. 00328 * MSR, SPR register is accessed when EFR[1]=0 and MCR[2]=0. 00329 */ 00330 MSR = 0x06 << 3, /* Modem status register - Read only */ 00331 SPR = 0x07 << 3, /* Scratchpad register - RD/WR access */ 00332 /* 00333 * 16750 addresses. TCR/TLR is accessed when LCR[7:0] <> 0xBF. 00334 * TCR, TLR register is accessed when EFR[1]=1 and MCR[2]=1. 00335 */ 00336 TCR = 0x06 << 3, /* Transmission control register - RD/WR access */ 00337 TLR = 0x07 << 3, /* Trigger level register - RD/WR access */ 00338 00339 /* 00340 * 16750 addresses. XON, XOFF is accessed when LCR[7:0] = 0xBF. 00341 */ 00342 XON1 = 0x04 << 3, /* XON1 register - RD/WR access */ 00343 XON2 = 0x05 << 3, /* XON2 register - RD/WR access */ 00344 XOFF1 = 0x06 << 3, /* XOFF1 register - RD/WR access */ 00345 XOFF2 = 0x07 << 3, /* XOFF2 register - RD/WR access */ 00346 00347 /* 00348 * 16750 addresses. 00349 */ 00350 TXLVL = 0x08 << 3, /* TX FIFO Level register - Read only */ 00351 RXLVL = 0x09 << 3, /* RX FIFO Level register - Read only */ 00352 IODIR = 0x0A << 3, /* IO Pin Direction reg - RD/WR access */ 00353 IOSTATE = 0x0B << 3, /* IO Pin State reg - RD/WR access */ 00354 IOINTENA = 0x0C << 3, /* IO Interrupt Enable - RD/WR access */ 00355 // reserved = 0x0D << 3, 00356 IOCTRL = 0x0E << 3, /* IO Control register - RD/WR access */ 00357 EFCR = 0x0F << 3, /* Extra features reg - RD/WR access */ 00358 00359 } ; 00360 00361 00362 // This enum used to be part of SerialBase class (access via SerialBase.h). 00363 // It seems not be supported anymore. The enums for Parity have moved to Serial now.. 00364 enum Flow { 00365 Disabled = 0, 00366 RTS, 00367 CTS, 00368 RTSCTS 00369 }; 00370 00371 // SC16IS752 Channel definitions (shifted to align) 00372 enum ChannelName { 00373 Channel_A = 0x00 << 1, 00374 Channel_B = 0x01 << 1 00375 }; 00376 00377 // SC16IS750 configuration register values 00378 // Several configuration registers are write-only. Need to save values to allow restoring. 00379 struct SC16IS750_cfg { 00380 char baudrate; 00381 char dataformat; 00382 char flowctrl; 00383 char fifoformat; 00384 bool fifoenable; 00385 }; 00386 00387 00388 /** Determine if there is a character available to read. 00389 * This is data that's already arrived and stored in the receive 00390 * buffer (which holds 64 chars). 00391 * 00392 * @return 1 if there is a character available to read, 0 otherwise 00393 */ 00394 int readable(); 00395 00396 /** Determine how many characters are available to read. 00397 * This is data that's already arrived and stored in the receive 00398 * buffer (which holds 64 chars). 00399 * 00400 * @return int Characters available to read 00401 */ 00402 int readableCount(); 00403 00404 /** Determine if there is space available to write a character. 00405 * @return 1 if there is a space for a character to write, 0 otherwise 00406 */ 00407 int writable(); 00408 00409 00410 /** Determine how much space available for writing characters. 00411 * This considers data that's already stored in the transmit 00412 * buffer (which holds 64 chars). 00413 * 00414 * @return int character space available to write 00415 */ 00416 int writableCount(); 00417 00418 /** 00419 * Read char from UART Bridge. 00420 * Acts in the same manner as 'Serial.read()'. 00421 * @param none 00422 * @return char read or -1 if no data available. 00423 */ 00424 int getc(); 00425 00426 /** 00427 * Write char to UART Bridge. Blocking when no free space in FIFO 00428 * @param value char to be written 00429 * @return value written 00430 */ 00431 int putc(int c); 00432 00433 00434 #if DOXYGEN_ONLY 00435 /** Write a formatted string to the UART Bridge. Blocking when no free space in FIFO 00436 * 00437 * @param format A printf-style format string, followed by the 00438 * variables to use in formatting the string. 00439 */ 00440 int printf(const char* format, ...); 00441 #endif 00442 00443 00444 /** 00445 * Write char string to UART Bridge. Blocking when no free space in FIFO 00446 * @param *str char string to be written 00447 * @return none 00448 */ 00449 void writeString(const char *str); 00450 00451 00452 /** 00453 * Write byte array to UART Bridge. Blocking when no free space in FIFO 00454 * @param *data byte array to be written 00455 * @param len number of bytes to write 00456 * @return none 00457 */ 00458 void writeBytes(const char *data, int len); 00459 00460 /** Set baudrate of the serial port. 00461 * @param baud integer baudrate (4800, 9600 etc) 00462 * @return none 00463 */ 00464 void baud(int baudrate = SC16IS750_DEFAULT_BAUDRATE); 00465 00466 /** Set the transmission format used by the serial port. 00467 * @param bits The number of bits in a word (5-8; default = 8) 00468 * @param parity The parity used (Serial::None, Serial::Odd, Serial::Even, Serial::Forced1, Serial::Forced0; default = Serial::None) 00469 * @param stop_bits The number of stop bits (1 or 2; default = 1) 00470 * @return none 00471 */ 00472 void format(int bits=8, Serial::Parity parity=Serial::None, int stop_bits=1); 00473 00474 #if(0) 00475 /** Attach a function to call whenever a serial interrupt is generated 00476 * 00477 * @param fptr A pointer to a void function, or 0 to set as none 00478 * @param type Which serial interrupt to attach the member function to (Seriall::RxIrq for receive, TxIrq for transmit buffer empty) 00479 */ 00480 void attach(void (*fptr)(void), IrqType type=RxIrq); 00481 00482 /** Attach a member function to call whenever a serial interrupt is generated 00483 * 00484 * @param tptr pointer to the object to call the member function on 00485 * @param mptr pointer to the member function to be called 00486 * @param type Which serial interrupt to attach the member function to (Seriall::RxIrq for receive, TxIrq for transmit buffer empty) 00487 * @return none 00488 */ 00489 template<typename T> 00490 void attach(T* tptr, void (T::*mptr)(void), IrqType type=RxIrq) { 00491 if((mptr != NULL) && (tptr != NULL)) { 00492 _irq[type].attach(tptr, mptr); 00493 serial_irq_set(&_serial, (SerialIrq)type, 1); 00494 } 00495 } 00496 #endif 00497 00498 /** Generate a break condition on the serial line 00499 * @param none 00500 * @return none 00501 */ 00502 void send_break(); 00503 00504 00505 /** Set a break condition on the serial line 00506 * @param enable break condition 00507 * @return none 00508 */ 00509 void set_break(bool enable=false); 00510 00511 00512 /** Set the flow control type on the serial port 00513 * Added for compatibility with Serial Class. 00514 * SC16IS750 supports only Flow, Pins can not be selected. 00515 * This method sets hardware flow control levels. SC16IS750 supports XON/XOFF, but this is not implemented. 00516 * 00517 * @param type the flow control type (Disabled, RTS, CTS, RTSCTS) 00518 * @param flow1 the first flow control pin (RTS for RTS or RTSCTS, CTS for CTS) 00519 * @param flow2 the second flow control pin (CTS for RTSCTS) 00520 * @return none 00521 */ 00522 void set_flow_control(Flow type=Disabled, PinName flow1=NC, PinName flow2=NC); 00523 00524 00525 /** Set the RX FIFO flow control levels 00526 * This method sets hardware flow control levels. SC16IS750 supports XON/XOFF, but this is not implemented. 00527 * Should be called BEFORE Auto RTS is enabled. 00528 * 00529 * @param resume trigger level to resume transmission (0..15, meaning 0-60 with a granularity of 4) 00530 * @param halt trigger level to resume transmission (0..15, meaning 0-60 with granularity of 4) 00531 * @return none 00532 */ 00533 void set_flow_triggers(int resume = TCR_RESUME_DEFAULT, int halt = TCR_HALT_DEFAULT); 00534 00535 00536 /** Set the Modem Control register 00537 * This method sets prescaler, enables TCR and TLR 00538 * 00539 * @param none 00540 * @return none 00541 */ 00542 void set_modem_control(); 00543 00544 00545 /** 00546 * Check that UART is connected and operational. 00547 * @param none 00548 * @return bool true when connected, false otherwise 00549 */ 00550 bool connected(); 00551 00552 00553 00554 /** FIFO control, sets TX and RX IRQ trigger levels and enables FIFO and save in _config 00555 * Note FCR[5:4] (=TX_IRQ_LVL) only accessible when EFR[4] is set (enhanced functions enable) 00556 * Note TLR only accessible when EFR[4] is set (enhanced functions enable) and MCR[2] is set 00557 * @param none 00558 * @return none 00559 */ 00560 void set_fifo_control(); 00561 00562 00563 /** Flush the UART FIFOs while maintaining current FIFO mode. 00564 * @param none 00565 * @return none 00566 */ 00567 void flush(); 00568 00569 00570 /** Set direction of I/O port pins. 00571 * This method is specific to the SPI-I2C UART and not found on the 16750 00572 * Note: The SC16IS752 does not have separate GPIOs for Channel_A and Channel_B. 00573 * @param bits Bitpattern for I/O (1=output, 0=input) 00574 * @return none 00575 */ 00576 void ioSetDirection(unsigned char bits); 00577 00578 /** Set bits of I/O port pins. 00579 * This method is specific to the SPI-I2C UART and not found on the 16750 00580 * Note: The SC16IS752 does not have separate GPIOs for Channel_A and Channel_B. 00581 * @param bits Bitpattern for I/O (1= set output bit, 0 = clear output bit) 00582 * @return none 00583 */ 00584 void ioSetState(unsigned char bits); 00585 00586 /** Get bits of I/O port pins. 00587 * This method is specific to the SPI-I2C UART and not found on the 16750 00588 * Note: The SC16IS752 does not have separate GPIOs for Channel_A and Channel_B. 00589 * @param none 00590 * @return bits Bitpattern for I/O (1= bit set, 0 = bit cleared) 00591 */ 00592 unsigned char ioGetState(); 00593 00594 00595 /** Software Reset SC16IS750 device. 00596 * This method is specific to the SPI-I2C UART and not found on the 16750 00597 * Note: The SC16IS752 does not have separate Reset for Channel_A and Channel_B. 00598 * @param none 00599 * @return none 00600 */ 00601 void swReset(); 00602 00603 00604 /** Hardware Reset SC16IS750 device. 00605 * Pure virtual, must be declared in derived class. 00606 * This method is only functional when the Reset pin has been declared and is also connected 00607 * @param none 00608 * @return none 00609 */ 00610 virtual void hwReset() =0; 00611 00612 /** Write value to internal register. 00613 * Pure virtual, must be declared in derived class. 00614 * @param registerAddress The address of the Register (enum RegisterName) 00615 * @param data The 8bit value to write 00616 * @return none 00617 */ 00618 virtual void writeRegister (RegisterName register_address, char data ) =0; 00619 00620 /** Read value from internal register. 00621 * Pure virtual, must be declared in derived class. 00622 * @param registerAddress The address of the Register (enum RegisterName) 00623 * @return char The 8bit value read from the register 00624 */ 00625 virtual char readRegister (RegisterName register_address ) =0; 00626 00627 /** Write multiple datavalues to Transmitregister. 00628 * More Efficient implementation than writing individual bytes 00629 * Pure virtual, must be declared in derived class. 00630 * @param char* databytes The pointer to the block of data 00631 * @param len The number of bytes to write 00632 * @return none 00633 */ 00634 virtual void writeDataBlock (const char *data, int len ) =0; 00635 00636 00637 /** Initialise internal registers 00638 * Should be in protection section. Public for testing purposes 00639 * If initialisation fails this method does not return. 00640 * @param none 00641 * @return none 00642 */ 00643 void _init(); 00644 00645 protected: 00646 //protected is accessible to derived classes, but not to external users 00647 00648 00649 /** Constructor is protected for this abstract Class 00650 * 00651 */ 00652 SC16IS750(); 00653 00654 /** Needed to implement Stream 00655 * 00656 * Read char from UART Bridge. 00657 * Acts in the same manner as 'Serial.read()'. 00658 * @param none 00659 * @return char read or -1 if no data available. 00660 */ 00661 virtual int _getc() { 00662 return getc(); 00663 } 00664 00665 00666 /** Needed to implement Stream 00667 * 00668 * Write char to UART Bridge. Blocking when no free space in FIFO 00669 * @param value char to be written 00670 * @return value written 00671 */ 00672 virtual int _putc(int c) { 00673 return putc(c); 00674 } 00675 00676 /** Needed to implement Stream 00677 * 00678 */ 00679 virtual int peek() {return 0;}; 00680 00681 00682 // Save config settings 00683 SC16IS750_cfg _config; 00684 00685 private: 00686 //private is not accessible to derived classes, nor external users 00687 00688 }; 00689 00690 00691 00692 /** Class SC16IS750_SPI for a bridge between SPI and a Serial port 00693 * 00694 * @code 00695 * #include "mbed.h" 00696 * #include "SC16IS750.h" 00697 * 00698 * SPI spi(PTD2, PTD3, PTD1); //MOSI, MISO, SCK 00699 * SC16IS750_SPI serial_spi(&spi, PTD0); 00700 * 00701 * Serial pc(USBTX,USBRX); 00702 * 00703 * int main() { 00704 * pc.printf("\nHello World!\n"); 00705 * 00706 * while(1) { 00707 * serial_spi.ioSetState(0x00); 00708 * wait(0.5); 00709 * serial_spi.ioSetState(0xFF); 00710 * wait(0.5); 00711 * serial_spi.putc('*'); 00712 * pc.putc('*'); 00713 * } 00714 * } 00715 * 00716 * @endcode 00717 */ 00718 class SC16IS750_SPI : public SC16IS750 { 00719 public: 00720 00721 /** Create an SC16IS750_SPI object using a specified SPI bus and CS 00722 * 00723 * @param SPI &spi the SPI port to connect to 00724 * @param cs Pinname of the CS pin (active low) 00725 * @param rst Pinname for Reset pin (active low) Optional, Default = NC 00726 */ 00727 SC16IS750_SPI(SPI *spi, PinName cs, PinName rst = NC); 00728 00729 /** Destruct SC16IS750_SPI bridge object 00730 * 00731 * @param none 00732 * @return none 00733 */ 00734 virtual ~SC16IS750_SPI(); 00735 00736 00737 /** Write value to internal register. 00738 * @param registerAddress The address of the Register (enum RegisterName) 00739 * @param data The 8bit value to write 00740 * @return none 00741 */ 00742 virtual void writeRegister(SC16IS750::RegisterName registerAddress, char data); 00743 00744 /** Read value from internal register. 00745 * @param registerAddress The address of the Register (enum RegisterName) 00746 * @return char The 8bit value read from the register 00747 */ 00748 virtual char readRegister(SC16IS750::RegisterName registerAddress); 00749 00750 /** Write multiple datavalues to Transmitregister. 00751 * More Efficient implementation than writing individual bytes 00752 * Assume that previous check confirmed that the FIFO has sufficient free space to store the data 00753 * 00754 * @param char* databytes The pointer to the block of data 00755 * @param len The number of bytes to write 00756 * @return none 00757 */ 00758 virtual void writeDataBlock (const char *data, int len ); 00759 00760 /** Hardware Reset SC16IS750 device. 00761 * This method is only functional when the Reset pin has been declared and is also connected 00762 * @param none 00763 * @return none 00764 */ 00765 virtual void hwReset(); 00766 00767 00768 protected: 00769 //protected is accessible to derived classes, but not to external users 00770 00771 00772 private: 00773 SPI *_spi; //SPI bus reference 00774 DigitalOut _cs; //CS of SPI device (active low) 00775 00776 /** Optional Hardware Reset pin for the bridge device (active low) 00777 * Default PinName value is NC 00778 */ 00779 DigitalOut* _reset; //Reset the Bridge device (active low) 00780 00781 }; 00782 00783 00784 00785 /** Class SC16IS750_I2C for a bridge between I2C and a Serial port 00786 * 00787 * @code 00788 * #include "mbed.h" 00789 * #include "SC16IS750.h" 00790 * 00791 * I2C i2c(PTE0, PTE1); //SDA, SCL 00792 * SC16IS750_I2C serial_i2c(&i2c, SC16IS750_DEFAULT_ADDR); 00793 * 00794 * Serial pc(USBTX,USBRX); 00795 * 00796 * int main() { 00797 * pc.printf("\nHello World!\n"); 00798 * 00799 * while(1) { 00800 * serial_i2c.ioSetState(0x00); 00801 * wait(0.5); 00802 * serial_i2c.ioSetState(0xFF); 00803 * wait(0.5); 00804 * serial_i2c.putc('*'); 00805 * pc.putc('*'); 00806 * } 00807 * } 00808 * 00809 * @endcode 00810 */ 00811 class SC16IS750_I2C : public SC16IS750 { 00812 public: 00813 00814 /** Create an SC16IS750_I2C object using a specified I2C bus and slaveaddress 00815 * 00816 * @param I2C &i2c the I2C port to connect to 00817 * @param char deviceAddress the address of the SC16IS750 00818 * @param rst Pinname for Reset pin (active low) Optional, Default = NC 00819 */ 00820 SC16IS750_I2C(I2C *i2c, uint8_t deviceAddress = SC16IS750_DEFAULT_ADDR, PinName rst = NC); 00821 00822 00823 /** Destruct SC16IS750_I2C bridge object 00824 * 00825 * @param none 00826 * @return none 00827 */ 00828 virtual ~SC16IS750_I2C(); 00829 00830 00831 /** Write value to internal register. 00832 * @param registerAddress The address of the Register (enum RegisterName) 00833 * @param data The 8bit value to write 00834 * @return none 00835 */ 00836 virtual void writeRegister(SC16IS750::RegisterName register_address, char data ); 00837 00838 /** Read value from internal register. 00839 * @param registerAddress The address of the Register (enum RegisterName) 00840 * @return char The 8bit value read from the register 00841 */ 00842 virtual char readRegister(SC16IS750::RegisterName register_address ); 00843 00844 00845 /** Write multiple datavalues to Transmitregister. 00846 * More Efficient implementation than writing individual bytes 00847 * Assume that previous check confirmed that the FIFO has sufficient free space to store the data 00848 * Pure virtual, must be declared in derived class. 00849 * @param char* databytes The pointer to the block of data 00850 * @param len The number of bytes to write 00851 * @return none 00852 */ 00853 virtual void writeDataBlock (const char *data, int len ); 00854 00855 00856 /** Hardware Reset SC16IS750 device. 00857 * This method is only functional when the Reset pin has been declared and is also connected 00858 * @param none 00859 * @return none 00860 */ 00861 virtual void hwReset(); 00862 00863 00864 protected: 00865 //protected is accessible to derived classes, but not to external users 00866 00867 00868 private: 00869 I2C *_i2c; //I2C bus reference 00870 uint8_t _slaveAddress; //I2C Slave address of device 00871 00872 /** Optional Hardware Reset pin for the bridge device (active low) 00873 * Default PinName value is NC 00874 */ 00875 DigitalOut* _reset; //Reset the Bridge device (active low) 00876 00877 }; 00878 00879 00880 00881 /** Class SC16IS752_SPI for a bridge between SPI and a Serial port 00882 * 00883 * @code 00884 * #include "mbed.h" 00885 * #include "SC16IS750.h" 00886 * 00887 * SPI spi(PTD2, PTD3, PTD1); //MOSI, MISO, SCK 00888 * SC16IS750_SPI serial_spi(&spi, PTD0, NC, SC16IS750::Channel_B); 00889 * 00890 * Serial pc(USBTX,USBRX); 00891 * 00892 * int main() { 00893 * pc.printf("\nHello World!\n"); 00894 * 00895 * while(1) { 00896 * serial_spi.ioSetState(0x00); 00897 * wait(0.5); 00898 * serial_spi.ioSetState(0xFF); 00899 * wait(0.5); 00900 * serial_spi.putc('*'); 00901 * pc.putc('*'); 00902 * } 00903 * } 00904 * 00905 * @endcode 00906 */ 00907 class SC16IS752_SPI : public SC16IS750 { 00908 public: 00909 00910 /** Create an SC16IS752_SPI object using a specified SPI bus and CS 00911 * Note: The SC16IS752 does not have separate GPIOs for Channel_A and Channel_B. 00912 * Note: The SC16IS752 does not have separate Reset for Channel_A and Channel_B. 00913 * 00914 * @param SPI &spi the SPI port to connect to 00915 * @param cs Pinname of the CS pin (active low) 00916 * @param rst Pinname for Reset pin (active low) Optional, Default = NC 00917 * @param channel UART ChannelName, Default = Channel_A 00918 */ 00919 SC16IS752_SPI(SPI *spi, PinName cs, PinName rst = NC, ChannelName channel = SC16IS750::Channel_A ); 00920 00921 /** Destruct SC16IS752_SPI bridge object 00922 * 00923 * @param none 00924 * @return none 00925 */ 00926 virtual ~SC16IS752_SPI(); 00927 00928 00929 /** Write value to internal register. 00930 * @param registerAddress The address of the Register (enum RegisterName) 00931 * @param data The 8bit value to write 00932 * @return none 00933 */ 00934 virtual void writeRegister(SC16IS750::RegisterName registerAddress, char data); 00935 00936 /** Read value from internal register. 00937 * @param registerAddress The address of the Register (enum RegisterName) 00938 * @return char The 8bit value read from the register 00939 */ 00940 virtual char readRegister(SC16IS750::RegisterName registerAddress); 00941 00942 /** Write multiple datavalues to Transmitregister. 00943 * More Efficient implementation than writing individual bytes 00944 * Assume that previous check confirmed that the FIFO has sufficient free space to store the data 00945 * 00946 * @param char* databytes The pointer to the block of data 00947 * @param len The number of bytes to write 00948 * @return none 00949 */ 00950 virtual void writeDataBlock (const char *data, int len ); 00951 00952 /** Hardware Reset SC16IS750 device. 00953 * This method is only functional when the Reset pin has been declared and is also connected 00954 * @param none 00955 * @return none 00956 */ 00957 virtual void hwReset(); 00958 00959 00960 protected: 00961 //protected is accessible to derived classes, but not to external users 00962 00963 00964 private: 00965 SPI *_spi; //SPI bus reference 00966 DigitalOut _cs; //CS of SPI device (active low) 00967 00968 /** Optional Hardware Reset pin for the bridge device (active low) 00969 * Default PinName value is NC 00970 */ 00971 DigitalOut* _reset; //Reset the Bridge device (active low) 00972 00973 // Save Channel setting 00974 ChannelName _channel; 00975 }; 00976 00977 00978 00979 /** Class SC16IS752_I2C for a bridge between I2C and a Serial port 00980 * 00981 * @code 00982 * #include "mbed.h" 00983 * #include "SC16IS750.h" 00984 * 00985 * I2C i2c(PTE0, PTE1); //SDA, SCL 00986 * SC16IS752_I2C serial_i2c(&i2c, SC16IS750_DEFAULT_ADDR, NC, SC16IS750::Channel_A); 00987 * 00988 * Serial pc(USBTX,USBRX); 00989 * 00990 * int main() { 00991 * pc.printf("\nHello World!\n"); 00992 * 00993 * while(1) { 00994 * serial_i2c.ioSetState(0x00); 00995 * wait(0.5); 00996 * serial_i2c.ioSetState(0xFF); 00997 * wait(0.5); 00998 * serial_i2c.putc('*'); 00999 * pc.putc('*'); 01000 * } 01001 * } 01002 * 01003 * @endcode 01004 */ 01005 class SC16IS752_I2C : public SC16IS750 { 01006 public: 01007 01008 /** Create an SC16IS752_I2C object using a specified I2C bus, slaveaddress and Channel 01009 * Note: The SC16IS752 does not have separate GPIOs for Channel_A and Channel_B. 01010 * Note: The SC16IS752 does not have separate Reset for Channel_A and Channel_B. 01011 * 01012 * @param I2C &i2c the I2C port to connect to 01013 * @param char deviceAddress the address of the SC16IS750 01014 * @param rst Pinname for Reset pin (active low) Optional, Default = NC 01015 * @param channel UART ChannelName, Default = Channel_A 01016 */ 01017 SC16IS752_I2C(I2C *i2c, uint8_t deviceAddress = SC16IS750_DEFAULT_ADDR, PinName rst = NC, ChannelName channel = SC16IS750::Channel_A); 01018 01019 01020 /** Destruct SC16IS752_I2C bridge object 01021 * 01022 * @param none 01023 * @return none 01024 */ 01025 virtual ~SC16IS752_I2C(); 01026 01027 01028 /** Write value to internal register. 01029 * @param registerAddress The address of the Register (enum RegisterName) 01030 * @param data The 8bit value to write 01031 * @return none 01032 */ 01033 virtual void writeRegister(SC16IS750::RegisterName register_address, char data ); 01034 01035 /** Read value from internal register. 01036 * @param registerAddress The address of the Register (enum RegisterName) 01037 * @return char The 8bit value read from the register 01038 */ 01039 virtual char readRegister(SC16IS750::RegisterName register_address ); 01040 01041 01042 /** Write multiple datavalues to Transmitregister. 01043 * More Efficient implementation than writing individual bytes 01044 * Assume that previous check confirmed that the FIFO has sufficient free space to store the data 01045 * Pure virtual, must be declared in derived class. 01046 * @param char* databytes The pointer to the block of data 01047 * @param len The number of bytes to write 01048 * @return none 01049 */ 01050 virtual void writeDataBlock (const char *data, int len ); 01051 01052 01053 /** Hardware Reset SC16IS752 device. 01054 * This method is only functional when the Reset pin has been declared and is also connected 01055 * @param none 01056 * @return none 01057 */ 01058 virtual void hwReset(); 01059 01060 01061 protected: 01062 //protected is accessible to derived classes, but not to external users 01063 01064 01065 private: 01066 I2C *_i2c; //I2C bus reference 01067 uint8_t _slaveAddress; //I2C Slave address of device 01068 01069 /** Optional Hardware Reset pin for the bridge device (active low) 01070 * Default PinName value is NC 01071 */ 01072 DigitalOut* _reset; //Reset the Bridge device (active low) 01073 01074 // Save Channel setting 01075 ChannelName _channel; 01076 01077 }; 01078 01079 01080 #endif // _SC16IS750_H
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SC16IS750 and SC16IS752 I2C or SPI to UART bridge