Wim Huiskamp / MCP23017

Added support for banked registers

Dependents:   Component_Test_Interface FalconWing MX_Spoile_Test Simple_Power_Distribution ... more

MCP23017.h@4:868db61f5f4e, 2012-02-13 (annotated)

Committer:
wim
Date:
Mon Feb 13 21:54:29 2012 +0000
Revision:
4:868db61f5f4e
Parent:
3:72da9cd002bd
Child:
5:5696b886a895
v05

Who changed what in which revision?

UserRevisionLine numberNew contents of line
wim 0:1a9288cc0630 1 /* MCP23017 - drive the Microchip MCP23017 16-bit Port Extender using I2C
wim 0:1a9288cc0630 2 * Copyright (c) 2010 Wim Huiskamp, Romilly Cocking (original version for SPI)
wim 0:1a9288cc0630 3 *
wim 0:1a9288cc0630 4 * Released under the MIT License: http://mbed.org/license/mit
wim 0:1a9288cc0630 5 *
wim 1:e2edbd61f4d0 6 * version 0.2 Initial Release
wim 1:e2edbd61f4d0 7 * version 0.3 Cleaned up
wim 3:72da9cd002bd 8 * version 0.4 Fixed problem with _read method
wim 4:868db61f5f4e 9 * version 0.5 Added support for 'Banked' access to registers
wim 0:1a9288cc0630 10 */
wim 0:1a9288cc0630 11 #include "mbed.h"
wim 0:1a9288cc0630 12
wim 0:1a9288cc0630 13 #ifndef MCP23017_H
wim 0:1a9288cc0630 14 #define MCP23017_H
wim 0:1a9288cc0630 15
wim 0:1a9288cc0630 16 // All register addresses assume IOCON.BANK = 0 (POR default)
wim 0:1a9288cc0630 17 #define IODIRA 0x00
wim 0:1a9288cc0630 18 #define IODIRB 0x01
wim 4:868db61f5f4e 19 #define IPOLA 0x02
wim 4:868db61f5f4e 20 #define IPOLB 0x03
wim 0:1a9288cc0630 21 #define GPINTENA 0x04
wim 0:1a9288cc0630 22 #define GPINTENB 0x05
wim 0:1a9288cc0630 23 #define DEFVALA 0x06
wim 0:1a9288cc0630 24 #define DEFVALB 0x07
wim 0:1a9288cc0630 25 #define INTCONA 0x08
wim 0:1a9288cc0630 26 #define INTCONB 0x09
wim 4:868db61f5f4e 27 #define IOCONA 0x0A
wim 4:868db61f5f4e 28 #define IOCONB 0x0B
wim 0:1a9288cc0630 29 #define GPPUA 0x0C
wim 0:1a9288cc0630 30 #define GPPUB 0x0D
wim 0:1a9288cc0630 31 #define INTFA 0x0E
wim 0:1a9288cc0630 32 #define INTFB 0x0F
wim 0:1a9288cc0630 33 #define INTCAPA 0x10
wim 0:1a9288cc0630 34 #define INTCAPB 0x11
wim 0:1a9288cc0630 35 #define GPIOA 0x12
wim 0:1a9288cc0630 36 #define GPIOB 0x13
wim 0:1a9288cc0630 37 #define OLATA 0x14
wim 0:1a9288cc0630 38 #define OLATB 0x15
wim 0:1a9288cc0630 39
wim 4:868db61f5f4e 40 // The following register addresses assume IOCON.BANK = 1
wim 4:868db61f5f4e 41 #define IODIRA_BNK 0x00
wim 4:868db61f5f4e 42 #define IPOLA_BNK 0x01
wim 4:868db61f5f4e 43 #define GPINTENA_BNK 0x02
wim 4:868db61f5f4e 44 #define DEFVALA_BNK 0x03
wim 4:868db61f5f4e 45 #define INTCONA_BNK 0x04
wim 4:868db61f5f4e 46 #define GPPUA_BNK 0x05
wim 4:868db61f5f4e 47 #define INTFA_BNK 0x06
wim 4:868db61f5f4e 48 #define IOCONA_BNK 0x07
wim 4:868db61f5f4e 49 #define INTCAPA_BNK 0x08
wim 4:868db61f5f4e 50 #define GPIOA_BNK 0x09
wim 4:868db61f5f4e 51 #define OLATA_BNK 0x0A
wim 4:868db61f5f4e 52
wim 4:868db61f5f4e 53 #define IODIRB_BNK 0x10
wim 4:868db61f5f4e 54 #define IPOLB_BNK 0x11
wim 4:868db61f5f4e 55 #define GPINTENB_BNK 0x12
wim 4:868db61f5f4e 56 #define DEFVALB_BNK 0x13
wim 4:868db61f5f4e 57 #define INTCONB_BNK 0x14
wim 4:868db61f5f4e 58 #define IOCONB_BNK 0x15
wim 4:868db61f5f4e 59 #define GPPUB_BNK 0x16
wim 4:868db61f5f4e 60 #define INTFB_BNK 0x17
wim 4:868db61f5f4e 61 #define INTCAPB_BNK 0x18
wim 4:868db61f5f4e 62 #define GPIOB_BNK 0x19
wim 4:868db61f5f4e 63 #define OLATB_BNK 0x1A
wim 4:868db61f5f4e 64
wim 4:868db61f5f4e 65 // This array allows structured access to Port_A and Port_B registers for both bankModes
wim 4:868db61f5f4e 66 const int IODIR_AB[2][2] = {{IODIRA, IODIRB}, {IODIRA_BNK, IODIRB_BNK}};
wim 4:868db61f5f4e 67 const int IPOL_AB[2][2] = {{IPOLA, IPOLB}, {IPOLA_BNK, IPOLB_BNK}};
wim 4:868db61f5f4e 68 const int GPINTEN_AB[2][2] = {{GPINTENA, GPINTENB}, {GPINTENA_BNK, GPINTENB_BNK}};
wim 4:868db61f5f4e 69 const int DEFVAL_AB[2][2] = {{DEFVALA, DEFVALB}, {DEFVALA_BNK, DEFVALB_BNK}};
wim 4:868db61f5f4e 70 const int INTCON_AB[2][2] = {{INTCONA, INTCONB}, {INTCONA_BNK, INTCONB_BNK}};
wim 4:868db61f5f4e 71 const int IOCON_AB[2][2] = {{IOCONA, IOCONB}, {IOCONA_BNK, IOCONB_BNK}};
wim 4:868db61f5f4e 72 const int GPPU_AB[2][2] = {{GPPUA, GPPUB}, {GPPUA_BNK, GPPUB_BNK}};
wim 4:868db61f5f4e 73 const int INTF_AB[2][2] = {{INTFA, INTFB}, {INTFA_BNK, INTFB_BNK}};
wim 4:868db61f5f4e 74 const int INTCAP_AB[2][2] = {{INTCAPA, INTCAPB}, {INTCAPA_BNK, INTCAPB_BNK}};
wim 4:868db61f5f4e 75 const int GPIO_AB[2][2] = {{GPIOA, GPIOB}, {GPIOA_BNK, GPIOB_BNK}};
wim 4:868db61f5f4e 76 const int OLAT_AB[2][2] = {{OLATA, OLATB}, {OLATA_BNK, OLATB_BNK}};
wim 4:868db61f5f4e 77
wim 4:868db61f5f4e 78
wim 0:1a9288cc0630 79 // Control settings
wim 0:1a9288cc0630 80 #define IOCON_BANK 0x80 // Banked registers for Port A and B
wim 0:1a9288cc0630 81 #define IOCON_BYTE_MODE 0x20 // Disables sequential operation, Address Ptr does not increment
wim 0:1a9288cc0630 82 // If Disabled and Bank = 0, operations toggle between Port A and B registers
wim 4:868db61f5f4e 83 // If Disabled and Bank = 1, operations do not increment registeraddress
wim 0:1a9288cc0630 84 #define IOCON_HAEN 0x08 // Hardware address enable
wim 0:1a9288cc0630 85
wim 0:1a9288cc0630 86 #define INTERRUPT_POLARITY_BIT 0x02
wim 0:1a9288cc0630 87 #define INTERRUPT_MIRROR_BIT 0x40
wim 0:1a9288cc0630 88
wim 0:1a9288cc0630 89 #define PORT_DIR_OUT 0x00
wim 0:1a9288cc0630 90 #define PORT_DIR_IN 0xFF
wim 0:1a9288cc0630 91
wim 0:1a9288cc0630 92 enum Polarity { ACTIVE_LOW , ACTIVE_HIGH };
wim 4:868db61f5f4e 93 enum Port { PORT_A=0, PORT_B=1 };
wim 4:868db61f5f4e 94 enum Bank { NOT_BNK=0, BNK=1 };
wim 0:1a9288cc0630 95
wim 0:1a9288cc0630 96 class MCP23017 {
wim 0:1a9288cc0630 97 public:
wim 2:2d4ee919e8a7 98 /** Create an MCP23017 object connected to the specified I2C object and using the specified deviceAddress
wim 2:2d4ee919e8a7 99 *
wim 2:2d4ee919e8a7 100 * @param I2C &i2c the I2C port to connect to
wim 3:72da9cd002bd 101 * @param char deviceAddress the address of the MCP23017
wim 2:2d4ee919e8a7 102 */
wim 0:1a9288cc0630 103 MCP23017(I2C &i2c, char deviceAddress);
wim 2:2d4ee919e8a7 104
wim 2:2d4ee919e8a7 105 /** Set I/O direction of specified MCP23017 Port
wim 2:2d4ee919e8a7 106 *
wim 2:2d4ee919e8a7 107 * @param Port Port address (Port_A or Port_B)
wim 2:2d4ee919e8a7 108 * @param char direction pin direction (0 = output, 1 = input)
wim 2:2d4ee919e8a7 109 */
wim 0:1a9288cc0630 110 void direction(Port port, char direction);
wim 2:2d4ee919e8a7 111
wim 2:2d4ee919e8a7 112 /** Set Pull-Up Resistors on specified MCP23017 Port
wim 2:2d4ee919e8a7 113 *
wim 2:2d4ee919e8a7 114 * @param Port Port address (Port_A or Port_B)
wim 2:2d4ee919e8a7 115 * @param char offOrOn per pin (0 = off, 1 = on)
wim 2:2d4ee919e8a7 116 */
wim 0:1a9288cc0630 117 void configurePullUps(Port port, char offOrOn);
wim 2:2d4ee919e8a7 118
wim 4:868db61f5f4e 119 void configureBanked(Bank bankmode);
wim 0:1a9288cc0630 120 void interruptEnable(Port port, char interruptsEnabledMask);
wim 0:1a9288cc0630 121 void interruptPolarity(Polarity polarity);
wim 0:1a9288cc0630 122 void mirrorInterrupts(bool mirror);
wim 0:1a9288cc0630 123 void defaultValue(Port port, char valuesToCompare);
wim 0:1a9288cc0630 124 void interruptControl(Port port, char interruptControlBits);
wim 2:2d4ee919e8a7 125
wim 2:2d4ee919e8a7 126 /** Read from specified MCP23017 Port
wim 2:2d4ee919e8a7 127 *
wim 2:2d4ee919e8a7 128 * @param Port Port address (Port_A or Port_B)
wim 2:2d4ee919e8a7 129 * @returns data from Port
wim 2:2d4ee919e8a7 130 */
wim 0:1a9288cc0630 131 char read(Port port);
wim 2:2d4ee919e8a7 132
wim 2:2d4ee919e8a7 133 /** Write to specified MCP23017 Port
wim 2:2d4ee919e8a7 134 *
wim 2:2d4ee919e8a7 135 * @param Port Port address (Port_A or Port_B)
wim 2:2d4ee919e8a7 136 * @param char byte data to write
wim 2:2d4ee919e8a7 137 */
wim 0:1a9288cc0630 138 void write(Port port, char byte);
wim 1:e2edbd61f4d0 139
wim 0:1a9288cc0630 140 protected:
wim 0:1a9288cc0630 141 I2C &_i2c;
wim 0:1a9288cc0630 142 char _readOpcode;
wim 0:1a9288cc0630 143 char _writeOpcode;
wim 4:868db61f5f4e 144 Bank _bankMode;
wim 2:2d4ee919e8a7 145
wim 2:2d4ee919e8a7 146 /** Init MCP23017
wim 2:2d4ee919e8a7 147 *
wim 2:2d4ee919e8a7 148 * @param
wim 2:2d4ee919e8a7 149 * @returns
wim 2:2d4ee919e8a7 150 */
wim 2:2d4ee919e8a7 151 void _init();
wim 2:2d4ee919e8a7 152
wim 2:2d4ee919e8a7 153 /** Write to specified MCP23017 register
wim 2:2d4ee919e8a7 154 *
wim 3:72da9cd002bd 155 * @param char address the internal registeraddress of the MCP23017
wim 2:2d4ee919e8a7 156 */
wim 2:2d4ee919e8a7 157 void _write(char address, char byte);
wim 2:2d4ee919e8a7 158
wim 2:2d4ee919e8a7 159 /** Read from specified MCP23017 register
wim 2:2d4ee919e8a7 160 *
wim 3:72da9cd002bd 161 * @param char address the internal registeraddress of the MCP23017
wim 2:2d4ee919e8a7 162 * @returns data from register
wim 2:2d4ee919e8a7 163 */
wim 2:2d4ee919e8a7 164 char _read(char address);
wim 0:1a9288cc0630 165 };
wim 0:1a9288cc0630 166
wim 0:1a9288cc0630 167 #endif