Wim Huiskamp / MCP23017

Added support for banked registers

Dependents:   Component_Test_Interface FalconWing MX_Spoile_Test Simple_Power_Distribution ... more

MCP23017.h@1:e2edbd61f4d0, 2010-12-20 (annotated)

Committer:
wim
Date:
Mon Dec 20 15:53:38 2010 +0000
Revision:
1:e2edbd61f4d0
Parent:
0:1a9288cc0630
Child:
2:2d4ee919e8a7
Cleaned up and added documentation

Who changed what in which revision?

UserRevisionLine numberNew contents of line
wim 0:1a9288cc0630 1 /* MCP23017 - drive the Microchip MCP23017 16-bit Port Extender using I2C
wim 0:1a9288cc0630 2 * Copyright (c) 2010 Wim Huiskamp, Romilly Cocking (original version for SPI)
wim 0:1a9288cc0630 3 *
wim 0:1a9288cc0630 4 * Released under the MIT License: http://mbed.org/license/mit
wim 0:1a9288cc0630 5 *
wim 1:e2edbd61f4d0 6 * version 0.2 Initial Release
wim 1:e2edbd61f4d0 7 * version 0.3 Cleaned up
wim 0:1a9288cc0630 8 */
wim 0:1a9288cc0630 9 #include "mbed.h"
wim 0:1a9288cc0630 10
wim 0:1a9288cc0630 11 #ifndef MCP23017_H
wim 0:1a9288cc0630 12 #define MCP23017_H
wim 0:1a9288cc0630 13
wim 0:1a9288cc0630 14 // All register addresses assume IOCON.BANK = 0 (POR default)
wim 0:1a9288cc0630 15 #define IODIRA 0x00
wim 0:1a9288cc0630 16 #define IODIRB 0x01
wim 0:1a9288cc0630 17 #define GPINTENA 0x04
wim 0:1a9288cc0630 18 #define GPINTENB 0x05
wim 0:1a9288cc0630 19 #define DEFVALA 0x06
wim 0:1a9288cc0630 20 #define DEFVALB 0x07
wim 0:1a9288cc0630 21 #define INTCONA 0x08
wim 0:1a9288cc0630 22 #define INTCONB 0x09
wim 0:1a9288cc0630 23 #define IOCON 0x0A
wim 0:1a9288cc0630 24 //#define IOCON 0x0B
wim 0:1a9288cc0630 25 #define GPPUA 0x0C
wim 0:1a9288cc0630 26 #define GPPUB 0x0D
wim 0:1a9288cc0630 27 #define INTFA 0x0E
wim 0:1a9288cc0630 28 #define INTFB 0x0F
wim 0:1a9288cc0630 29 #define INTCAPA 0x10
wim 0:1a9288cc0630 30 #define INTCAPB 0x11
wim 0:1a9288cc0630 31 #define GPIOA 0x12
wim 0:1a9288cc0630 32 #define GPIOB 0x13
wim 0:1a9288cc0630 33 #define OLATA 0x14
wim 0:1a9288cc0630 34 #define OLATB 0x15
wim 0:1a9288cc0630 35
wim 0:1a9288cc0630 36 // Control settings
wim 0:1a9288cc0630 37 #define IOCON_BANK 0x80 // Banked registers for Port A and B
wim 0:1a9288cc0630 38 #define IOCON_BYTE_MODE 0x20 // Disables sequential operation, Address Ptr does not increment
wim 0:1a9288cc0630 39 // If Disabled and Bank = 0, operations toggle between Port A and B registers
wim 0:1a9288cc0630 40 #define IOCON_HAEN 0x08 // Hardware address enable
wim 0:1a9288cc0630 41
wim 0:1a9288cc0630 42 #define INTERRUPT_POLARITY_BIT 0x02
wim 0:1a9288cc0630 43 #define INTERRUPT_MIRROR_BIT 0x40
wim 0:1a9288cc0630 44
wim 0:1a9288cc0630 45 #define PORT_DIR_OUT 0x00
wim 0:1a9288cc0630 46 #define PORT_DIR_IN 0xFF
wim 0:1a9288cc0630 47
wim 0:1a9288cc0630 48 enum Polarity { ACTIVE_LOW , ACTIVE_HIGH };
wim 0:1a9288cc0630 49 enum Port { PORT_A, PORT_B };
wim 0:1a9288cc0630 50
wim 0:1a9288cc0630 51 class MCP23017 {
wim 0:1a9288cc0630 52 public:
wim 0:1a9288cc0630 53 MCP23017(I2C &i2c, char deviceAddress);
wim 0:1a9288cc0630 54 void direction(Port port, char direction);
wim 0:1a9288cc0630 55 void configurePullUps(Port port, char offOrOn);
wim 0:1a9288cc0630 56 void interruptEnable(Port port, char interruptsEnabledMask);
wim 0:1a9288cc0630 57 void interruptPolarity(Polarity polarity);
wim 0:1a9288cc0630 58 void mirrorInterrupts(bool mirror);
wim 0:1a9288cc0630 59 void defaultValue(Port port, char valuesToCompare);
wim 0:1a9288cc0630 60 void interruptControl(Port port, char interruptControlBits);
wim 0:1a9288cc0630 61 char read(Port port);
wim 0:1a9288cc0630 62 void write(Port port, char byte);
wim 1:e2edbd61f4d0 63
wim 0:1a9288cc0630 64 protected:
wim 0:1a9288cc0630 65 I2C &_i2c;
wim 0:1a9288cc0630 66 void _init();
wim 0:1a9288cc0630 67 void _write(char address, char byte);
wim 0:1a9288cc0630 68 char _read(char address);
wim 0:1a9288cc0630 69 char _readOpcode;
wim 0:1a9288cc0630 70 char _writeOpcode;
wim 0:1a9288cc0630 71 };
wim 0:1a9288cc0630 72
wim 0:1a9288cc0630 73 #endif