Diff: MAX11043/MAX11043.h

Revision:

90:d6ed8a8c5f26

Parent:

89:20fd6ce5e4dd

Child:

93:6b22269935a6

--- a/MAX11043/MAX11043.h	Fri Feb 28 07:59:58 2020 +0000
+++ b/MAX11043/MAX11043.h	Fri Feb 28 23:46:49 2020 +0000
@@ -406,8 +406,7 @@
 
 // CODE GENERATOR: TypedefEnum MAX11043_STATUS_enum_t
     //----------------------------------------
-    /// CMD_0001_1110_d8_Rd_Status
-    /// regAddr=07h
+    /// CMD_0001_1110_d8_Rd07_Status regAddr=07h
     /// Status: x x FlashBusy BOOT OFLGA OFLGB OFLGC OFLGD
     typedef enum MAX11043_STATUS_enum_t {
         STATUS_xxxx_xxx1_OverflowFlagOFLGD = 0x01, //!< 8'b00000001
@@ -422,8 +421,7 @@
 
 // CODE GENERATOR: TypedefEnum MAX11043_CONFIG_enum_t
     //----------------------------------------
-    /// CMD_0010_0000_d16_Wr_Configuration
-    /// regAddr=08h
+    /// CMD_0010_0000_d16_Wr08_Configuration regAddr=08h
     /// Config: EXTCLK CLKDIV1 CLKDIV0 PD PDA PDB PDC PDD PDDAC PDOSC 24BIT SCHANA SCHANB SCHANC SCHAND DECSEL
     typedef enum MAX11043_CONFIG_enum_t {
         CONFIG_xxxx_xxxx_xxxx_xxx1_DECSEL12 = 0x0001, //!< 16'b0000000000000001
@@ -446,14 +444,10 @@
 
 // CODE GENERATOR: TypedefEnum MAX11043_CONFIGABCD_enum_t
     //----------------------------------------
-    /// CMD_0011_0000_d16_Wr_CONFIGa
-    /// CMD_0011_0100_d16_Wr_CONFIGb
-    /// CMD_0011_1000_d16_Wr_CONFIGc
-    /// CMD_0011_1100_d16_Wr_CONFIGd
-    /// regAddr=0Ch
-    /// regAddr=0Dh
-    /// regAddr=0Eh
-    /// regAddr=0Fh
+    /// CMD_0011_0000_d16_Wr0C_ConfigA regAddr=0Ch
+    /// CMD_0011_0100_d16_Wr0D_ConfigB regAddr=0Dh
+    /// CMD_0011_1000_d16_Wr0E_ConfigC regAddr=0Eh
+    /// CMD_0011_1100_d16_Wr0F_ConfigD regAddr=0Fh
     /// ConfigABCD: x x x BDAC[3:0] DIFF EQ MODG[1:0] PDPGA FILT PGAG ENBIASP ENBIASN
     typedef enum MAX11043_CONFIGABCD_enum_t {
         CONFIGABCD_xxxx_xxxx_xxxx_xxx1_ENBIASN = 0x0001, //!< 16'b0000000000000001
@@ -476,19 +470,16 @@
 
 // CODE GENERATOR: TypedefEnum MAX11043_BDAC_enum_t
     //----------------------------------------
-    /// CMD_0011_0000_d16_Wr_CONFIGa
-    /// CMD_0011_0100_d16_Wr_CONFIGb
-    /// CMD_0011_1000_d16_Wr_CONFIGc
-    /// CMD_0011_1100_d16_Wr_CONFIGd
+    /// CMD_0011_0000_d16_Wr0C_ConfigA regAddr=0Ch
+    /// CMD_0011_0100_d16_Wr0D_ConfigB regAddr=0Dh
+    /// CMD_0011_1000_d16_Wr0E_ConfigC regAddr=0Eh
+    /// CMD_0011_1100_d16_Wr0F_ConfigD regAddr=0Fh
+    ///
     /// CONFIGABCD_xxx1_xxxx_xxxx_xxxx_BDAC3
     /// CONFIGABCD_xxxx_1xxx_xxxx_xxxx_BDAC2
     /// CONFIGABCD_xxxx_x1xx_xxxx_xxxx_BDAC1
     /// CONFIGABCD_xxxx_xx1x_xxxx_xxxx_BDAC0
     /// Sets the input bias voltage for AC-coupled signals when ENBIAS_ is set to 1.
-    /// regAddr=0Ch
-    /// regAddr=0Dh
-    /// regAddr=0Eh
-    /// regAddr=0Fh
     /// ConfigABCD: x x x BDAC[3:0] DIFF EQ MODG[1:0] PDPGA FILT PGAG ENBIASP ENBIASN
     typedef enum MAX11043_BDAC_enum_t {
         BDAC_0000_033pctAVDD = 0x00, //!< 8'b00000000
@@ -511,8 +502,7 @@
 
 // CODE GENERATOR: TypedefEnum MAX11043_REFERENCE_enum_t
     //----------------------------------------
-    /// CMD_0100_0000_d16_Wr_Reference
-    /// regAddr=10h
+    /// CMD_0100_0000_d16_Wr10_Reference regAddr=10h
     /// ReferenceDelay: 0 0 0 PURGE[4:0] EXTREF EXBUFA EXBUFB EXBUFC EXBUFD EXBUFDAC EXBUFDACH EXBUFDACL
     typedef enum MAX11043_REFERENCE_enum_t {
         REFERENCE_xxxx_xxxx_xxxx_xxx1_EXBUFDACL = 0x0001, //!< 16'b0000000000000001
@@ -627,19 +617,19 @@
     uint16_t config;
 
     /// shadow of register status CMD_0001_1110_d8_Rd07_Status
-    uint32_t status;
+    uint8_t status;
 
     /// shadow of register ADCa CMD_0000_0010_d16o8_Rd00_ADCa
-    uint32_t adca;
+    int adca;
 
     /// shadow of register ADCb CMD_0000_0110_d16o8_Rd01_ADCb
-    uint32_t adcb;
+    int adcb;
 
     /// shadow of register ADCc CMD_0000_1010_d16o8_Rd02_ADCc
-    uint32_t adcc;
+    int adcc;
 
     /// shadow of register ADCd CMD_0000_1110_d16o8_Rd03_ADCd
-    uint32_t adcd;
+    int adcd;
 
 // CODE GENERATOR: omit global g_MAX11043_device