Fabian Wenger / Mbed 2 deprecated Rainbow

Grundfunktionen für Micromouse

Dependencies:   AutomationElements mbed

MotorDriver/EncoderCounter.cpp@1:4808f55970e8, 2018-04-22 (annotated)

Committer:
wengefa1
Date:
Sun Apr 22 09:55:40 2018 +0000
Revision:
1:4808f55970e8
Parent:
0:e38b500d6e74 
Grundfunktionen funktionieren

Who changed what in which revision?

UserRevisionLine numberNew contents of line
wengefa1 0:e38b500d6e74 1 /*
wengefa1 0:e38b500d6e74 2 * EncoderCounter.cpp
wengefa1 0:e38b500d6e74 3 * Copyright (c) 2018, ZHAW
wengefa1 0:e38b500d6e74 4 * All rights reserved.
wengefa1 0:e38b500d6e74 5 */
wengefa1 0:e38b500d6e74 6
wengefa1 0:e38b500d6e74 7 #include "EncoderCounter.h"
wengefa1 0:e38b500d6e74 8
wengefa1 0:e38b500d6e74 9 using namespace std;
wengefa1 0:e38b500d6e74 10
wengefa1 0:e38b500d6e74 11 /**
wengefa1 0:e38b500d6e74 12 * Creates and initializes the driver to read the quadrature
wengefa1 0:e38b500d6e74 13 * encoder counter of the STM32 microcontroller.
wengefa1 0:e38b500d6e74 14 * @param a the input pin for the channel A.
wengefa1 0:e38b500d6e74 15 * @param b the input pin for the channel B.
wengefa1 0:e38b500d6e74 16 */
wengefa1 0:e38b500d6e74 17 EncoderCounter::EncoderCounter(PinName a, PinName b) {
wengefa1 0:e38b500d6e74 18
wengefa1 0:e38b500d6e74 19 // check pins
wengefa1 0:e38b500d6e74 20
wengefa1 0:e38b500d6e74 21 if ((a == PA_0) && (b == PA_1)) {
wengefa1 0:e38b500d6e74 22
wengefa1 0:e38b500d6e74 23 // pinmap OK for TIM2 CH1 and CH2
wengefa1 0:e38b500d6e74 24
wengefa1 0:e38b500d6e74 25 TIM = TIM2;
wengefa1 0:e38b500d6e74 26
wengefa1 0:e38b500d6e74 27 // configure general purpose I/O registers
wengefa1 0:e38b500d6e74 28
wengefa1 0:e38b500d6e74 29 GPIOA->MODER &= ~GPIO_MODER_MODER0; // reset port A0
wengefa1 0:e38b500d6e74 30 GPIOA->MODER |= GPIO_MODER_MODER0_1; // set alternate mode of port A0
wengefa1 0:e38b500d6e74 31 GPIOA->PUPDR &= ~GPIO_PUPDR_PUPDR0; // reset pull-up/pull-down on port A0
wengefa1 0:e38b500d6e74 32 GPIOA->PUPDR |= GPIO_PUPDR_PUPDR0_1; // set input as pull-down
wengefa1 0:e38b500d6e74 33 GPIOA->AFR[0] &= ~(0xF << 4*0); // reset alternate function of port A0
wengefa1 0:e38b500d6e74 34 GPIOA->AFR[0] |= 1 << 4*0; // set alternate funtion 1 of port A0
wengefa1 0:e38b500d6e74 35
wengefa1 0:e38b500d6e74 36 GPIOA->MODER &= ~GPIO_MODER_MODER1; // reset port A1
wengefa1 0:e38b500d6e74 37 GPIOA->MODER |= GPIO_MODER_MODER1_1; // set alternate mode of port A1
wengefa1 0:e38b500d6e74 38 GPIOA->PUPDR &= ~GPIO_PUPDR_PUPDR1; // reset pull-up/pull-down on port A1
wengefa1 0:e38b500d6e74 39 GPIOA->PUPDR |= GPIO_PUPDR_PUPDR1_1; // set input as pull-down
wengefa1 0:e38b500d6e74 40 GPIOA->AFR[0] &= ~(0xF << 4*1); // reset alternate function of port A1
wengefa1 0:e38b500d6e74 41 GPIOA->AFR[0] |= 1 << 4*1; // set alternate funtion 1 of port A1
wengefa1 0:e38b500d6e74 42
wengefa1 0:e38b500d6e74 43 // configure reset and clock control registers
wengefa1 0:e38b500d6e74 44
wengefa1 0:e38b500d6e74 45 RCC->APB1RSTR |= RCC_APB1RSTR_TIM2RST; //reset TIM2 controller
wengefa1 0:e38b500d6e74 46 RCC->APB1RSTR &= ~RCC_APB1RSTR_TIM2RST;
wengefa1 0:e38b500d6e74 47
wengefa1 0:e38b500d6e74 48 RCC->APB1ENR |= RCC_APB1ENR_TIM2EN; // TIM2 clock enable
wengefa1 0:e38b500d6e74 49
wengefa1 0:e38b500d6e74 50 } else if ((a == PA_6) && (b == PC_7)) {
wengefa1 0:e38b500d6e74 51
wengefa1 0:e38b500d6e74 52 // pinmap OK for TIM3 CH1 and CH2
wengefa1 0:e38b500d6e74 53
wengefa1 0:e38b500d6e74 54 TIM = TIM3;
wengefa1 0:e38b500d6e74 55
wengefa1 0:e38b500d6e74 56 // configure reset and clock control registers
wengefa1 0:e38b500d6e74 57
wengefa1 0:e38b500d6e74 58 RCC->AHB1ENR |= RCC_AHB1ENR_GPIOCEN; // manually enable port C (port A enabled by mbed library)
wengefa1 0:e38b500d6e74 59
wengefa1 0:e38b500d6e74 60 // configure general purpose I/O registers
wengefa1 0:e38b500d6e74 61
wengefa1 0:e38b500d6e74 62 GPIOA->MODER &= ~GPIO_MODER_MODER6; // reset port A6
wengefa1 0:e38b500d6e74 63 GPIOA->MODER |= GPIO_MODER_MODER6_1; // set alternate mode of port A6
wengefa1 0:e38b500d6e74 64 GPIOA->PUPDR &= ~GPIO_PUPDR_PUPDR6; // reset pull-up/pull-down on port A6
wengefa1 0:e38b500d6e74 65 GPIOA->PUPDR |= GPIO_PUPDR_PUPDR6_1; // set input as pull-down
wengefa1 0:e38b500d6e74 66 GPIOA->AFR[0] &= ~(0xF << 4*6); // reset alternate function of port A6
wengefa1 0:e38b500d6e74 67 GPIOA->AFR[0] |= 2 << 4*6; // set alternate funtion 2 of port A6
wengefa1 0:e38b500d6e74 68
wengefa1 0:e38b500d6e74 69 GPIOC->MODER &= ~GPIO_MODER_MODER7; // reset port C7
wengefa1 0:e38b500d6e74 70 GPIOC->MODER |= GPIO_MODER_MODER7_1; // set alternate mode of port C7
wengefa1 0:e38b500d6e74 71 GPIOC->PUPDR &= ~GPIO_PUPDR_PUPDR7; // reset pull-up/pull-down on port C7
wengefa1 0:e38b500d6e74 72 GPIOC->PUPDR |= GPIO_PUPDR_PUPDR7_1; // set input as pull-down
wengefa1 0:e38b500d6e74 73 GPIOC->AFR[0] &= ~0xF0000000; // reset alternate function of port C7
wengefa1 0:e38b500d6e74 74 GPIOC->AFR[0] |= 2 << 4*7; // set alternate funtion 2 of port C7
wengefa1 0:e38b500d6e74 75
wengefa1 0:e38b500d6e74 76 // configure reset and clock control registers
wengefa1 0:e38b500d6e74 77
wengefa1 0:e38b500d6e74 78 RCC->APB1RSTR |= RCC_APB1RSTR_TIM3RST; //reset TIM3 controller
wengefa1 0:e38b500d6e74 79 RCC->APB1RSTR &= ~RCC_APB1RSTR_TIM3RST;
wengefa1 0:e38b500d6e74 80
wengefa1 0:e38b500d6e74 81 RCC->APB1ENR |= RCC_APB1ENR_TIM3EN; // TIM3 clock enable
wengefa1 0:e38b500d6e74 82
wengefa1 0:e38b500d6e74 83 } else if ((a == PB_6) && (b == PB_7)) {
wengefa1 0:e38b500d6e74 84
wengefa1 0:e38b500d6e74 85 // pinmap OK for TIM4 CH1 and CH2
wengefa1 0:e38b500d6e74 86
wengefa1 0:e38b500d6e74 87 TIM = TIM4;
wengefa1 0:e38b500d6e74 88
wengefa1 0:e38b500d6e74 89 // configure reset and clock control registers
wengefa1 0:e38b500d6e74 90
wengefa1 0:e38b500d6e74 91 RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN; // manually enable port B (port A enabled by mbed library)
wengefa1 0:e38b500d6e74 92
wengefa1 0:e38b500d6e74 93 // configure general purpose I/O registers
wengefa1 0:e38b500d6e74 94
wengefa1 0:e38b500d6e74 95 GPIOB->MODER &= ~GPIO_MODER_MODER6; // reset port B6
wengefa1 0:e38b500d6e74 96 GPIOB->MODER |= GPIO_MODER_MODER6_1; // set alternate mode of port B6
wengefa1 0:e38b500d6e74 97 GPIOB->PUPDR &= ~GPIO_PUPDR_PUPDR6; // reset pull-up/pull-down on port B6
wengefa1 0:e38b500d6e74 98 GPIOB->PUPDR |= GPIO_PUPDR_PUPDR6_1; // set input as pull-down
wengefa1 0:e38b500d6e74 99 GPIOB->AFR[0] &= ~(0xF << 4*6); // reset alternate function of port B6
wengefa1 0:e38b500d6e74 100 GPIOB->AFR[0] |= 2 << 4*6; // set alternate funtion 2 of port B6
wengefa1 0:e38b500d6e74 101
wengefa1 0:e38b500d6e74 102 GPIOB->MODER &= ~GPIO_MODER_MODER7; // reset port B7
wengefa1 0:e38b500d6e74 103 GPIOB->MODER |= GPIO_MODER_MODER7_1; // set alternate mode of port B7
wengefa1 0:e38b500d6e74 104 GPIOB->PUPDR &= ~GPIO_PUPDR_PUPDR7; // reset pull-up/pull-down on port B7
wengefa1 0:e38b500d6e74 105 GPIOB->PUPDR |= GPIO_PUPDR_PUPDR7_1; // set input as pull-down
wengefa1 0:e38b500d6e74 106 GPIOB->AFR[0] &= ~0xF0000000; // reset alternate function of port B7
wengefa1 0:e38b500d6e74 107 GPIOB->AFR[0] |= 2 << 4*7; // set alternate funtion 2 of port B7
wengefa1 0:e38b500d6e74 108
wengefa1 0:e38b500d6e74 109 // configure reset and clock control registers
wengefa1 0:e38b500d6e74 110
wengefa1 0:e38b500d6e74 111 RCC->APB1RSTR |= RCC_APB1RSTR_TIM4RST; //reset TIM4 controller
wengefa1 0:e38b500d6e74 112 RCC->APB1RSTR &= ~RCC_APB1RSTR_TIM4RST;
wengefa1 0:e38b500d6e74 113
wengefa1 0:e38b500d6e74 114 RCC->APB1ENR |= RCC_APB1ENR_TIM4EN; // TIM4 clock enable
wengefa1 0:e38b500d6e74 115
wengefa1 0:e38b500d6e74 116 } else {
wengefa1 0:e38b500d6e74 117
wengefa1 0:e38b500d6e74 118 printf("pinmap not found for peripheral\n");
wengefa1 0:e38b500d6e74 119 }
wengefa1 0:e38b500d6e74 120
wengefa1 0:e38b500d6e74 121 // configure general purpose timer 3 or 4
wengefa1 0:e38b500d6e74 122
wengefa1 0:e38b500d6e74 123 TIM->CR1 = 0x0000; // counter disable
wengefa1 0:e38b500d6e74 124 TIM->CR2 = 0x0000; // reset master mode selection
wengefa1 0:e38b500d6e74 125 TIM->SMCR = TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0; // counting on both TI1 & TI2 edges
wengefa1 0:e38b500d6e74 126 TIM->CCMR1 = TIM_CCMR1_CC2S_0 | TIM_CCMR1_CC1S_0;
wengefa1 0:e38b500d6e74 127 TIM->CCMR2 = 0x0000; // reset capture mode register 2
wengefa1 0:e38b500d6e74 128 TIM->CCER = TIM_CCER_CC2E | TIM_CCER_CC1E;
wengefa1 0:e38b500d6e74 129 TIM->CNT = 0x0000; // reset counter value
wengefa1 0:e38b500d6e74 130 TIM->ARR = 0xFFFF; // auto reload register
wengefa1 0:e38b500d6e74 131 TIM->CR1 = TIM_CR1_CEN; // counter enable
wengefa1 0:e38b500d6e74 132 }
wengefa1 0:e38b500d6e74 133
wengefa1 0:e38b500d6e74 134 EncoderCounter::~EncoderCounter() {}
wengefa1 0:e38b500d6e74 135
wengefa1 0:e38b500d6e74 136 /**
wengefa1 0:e38b500d6e74 137 * Resets the counter value to zero.
wengefa1 0:e38b500d6e74 138 */
wengefa1 0:e38b500d6e74 139 void EncoderCounter::reset() {
wengefa1 0:e38b500d6e74 140
wengefa1 0:e38b500d6e74 141 TIM->CNT = 0x0000;
wengefa1 0:e38b500d6e74 142 }
wengefa1 0:e38b500d6e74 143
wengefa1 0:e38b500d6e74 144 /**
wengefa1 0:e38b500d6e74 145 * Resets the counter value to a given offset value.
wengefa1 0:e38b500d6e74 146 * @param offset the offset value to reset the counter to.
wengefa1 0:e38b500d6e74 147 */
wengefa1 0:e38b500d6e74 148 void EncoderCounter::reset(short offset) {
wengefa1 0:e38b500d6e74 149
wengefa1 0:e38b500d6e74 150 TIM->CNT = -offset;
wengefa1 0:e38b500d6e74 151 }
wengefa1 0:e38b500d6e74 152
wengefa1 0:e38b500d6e74 153 /**
wengefa1 0:e38b500d6e74 154 * Reads the quadrature encoder counter value.
wengefa1 0:e38b500d6e74 155 * @return the quadrature encoder counter as a signed 16-bit integer value.
wengefa1 0:e38b500d6e74 156 */
wengefa1 0:e38b500d6e74 157 short EncoderCounter::read() {
wengefa1 0:e38b500d6e74 158
wengefa1 0:e38b500d6e74 159 return (short)(-TIM->CNT);
wengefa1 0:e38b500d6e74 160 }
wengefa1 0:e38b500d6e74 161
wengefa1 0:e38b500d6e74 162 /**
wengefa1 0:e38b500d6e74 163 * The empty operator is a shorthand notation of the <code>read()</code> method.
wengefa1 0:e38b500d6e74 164 */
wengefa1 0:e38b500d6e74 165 EncoderCounter::operator short() {
wengefa1 0:e38b500d6e74 166
wengefa1 0:e38b500d6e74 167 return read();
wengefa1 0:e38b500d6e74 168 }
wengefa1 0:e38b500d6e74 169
wengefa1 0:e38b500d6e74 170