wimbeaumont Project / AD5384

control for DAC AD5384 for the SOLID SM1 Slow Control

Dependents:   SPItest sscm

AD5384.h@3:7ca85ed310e0, 2014-10-08 (annotated)

Committer:
wbeaumont
Date:
Wed Oct 08 10:43:18 2014 +0000
Revision:
3:7ca85ed310e0
Parent:
1:d2d6341d3e97
Child:
4:bc9ab300ab26
added hw reset

Who changed what in which revision?

UserRevisionLine numberNew contents of line
wbeaumont 0:33bb5081488a 1 #ifndef AD5384_H
wbeaumont 0:33bb5081488a 2 #define AD5384_H
wbeaumont 0:33bb5081488a 3
wbeaumont 0:33bb5081488a 4 #include "solid_sctrl_def.h"
wbeaumont 0:33bb5081488a 5 #include "SWSPI.h"
wbeaumont 1:d2d6341d3e97 6 #include "getVersion.h"
wbeaumont 0:33bb5081488a 7
wbeaumont 3:7ca85ed310e0 8 #define VERSION_AD5384_HDR "1.20"
wbeaumont 0:33bb5081488a 9
wbeaumont 0:33bb5081488a 10
wbeaumont 0:33bb5081488a 11 /*
wbeaumont 0:33bb5081488a 12 * class to set and readback the AD5384
wbeaumont 0:33bb5081488a 13 * to minimize the access to the device there is a shadow of the DAC, GAIN and OFFSET values
wbeaumont 0:33bb5081488a 14
wbeaumont 1:d2d6341d3e97 15 * v0.10 initial development to see if reading / writing is possible
wbeaumont 1:d2d6341d3e97 16 * v1.10 initial release versioni
wbeaumont 1:d2d6341d3e97 17 * v1.11 added init1 init2
wbeaumont 3:7ca85ed310e0 18 * v1.20 added rst pin
wbeaumont 0:33bb5081488a 19 */
wbeaumont 0:33bb5081488a 20 class SWSPI;
wbeaumont 0:33bb5081488a 21 #include "mbed.h"
wbeaumont 0:33bb5081488a 22 //class DigitalOut;
wbeaumont 0:33bb5081488a 23
wbeaumont 1:d2d6341d3e97 24 class AD5384 : public getVersion {
wbeaumont 0:33bb5081488a 25 SWSPI *spi ;
wbeaumont 0:33bb5081488a 26 DigitalOut* cs;
wbeaumont 3:7ca85ed310e0 27 DigitalOut* rst;
wbeaumont 0:33bb5081488a 28 float vref;
wbeaumont 0:33bb5081488a 29
wbeaumont 0:33bb5081488a 30 void set_spi_mode();
wbeaumont 0:33bb5081488a 31 u16 calculate_dac_setting(u8 nr, float vout );
wbeaumont 0:33bb5081488a 32 u32 format_word(u8 mode,u8 ch,u8 rw,u16 data) ;
wbeaumont 0:33bb5081488a 33 u16 get_reg(u8 mode, u8 ch );
wbeaumont 0:33bb5081488a 34 u32 set_reg(u8 mode,u8 ch, u16 value );
wbeaumont 0:33bb5081488a 35 public:
wbeaumont 3:7ca85ed310e0 36 AD5384(SWSPI *spiinterface ,DigitalOut* chipselect,DigitalOut* reset );
wbeaumont 0:33bb5081488a 37
wbeaumont 0:33bb5081488a 38 u16 dac[40];
wbeaumont 0:33bb5081488a 39 u16 gain[40];
wbeaumont 0:33bb5081488a 40 u16 offset[40];
wbeaumont 0:33bb5081488a 41 float volt[40];
wbeaumont 0:33bb5081488a 42 u16 get_dac(u8 ch);
wbeaumont 0:33bb5081488a 43 u16 set_dac( u8 ch, u16 dac);
wbeaumont 0:33bb5081488a 44 u16 get_ch_out_reg(u8 ch) ;
wbeaumont 0:33bb5081488a 45 u16 set_volt(u8 nr, float vout );
wbeaumont 0:33bb5081488a 46 u16 set_gain(u8 ch, u16 gain );
wbeaumont 0:33bb5081488a 47 u16 get_gain(u8 ch );
wbeaumont 0:33bb5081488a 48 u16 set_offset(u8 ch, u16 gain);
wbeaumont 0:33bb5081488a 49 u16 get_offset(u8 ch );
wbeaumont 3:7ca85ed310e0 50 void hw_rst();
wbeaumont 0:33bb5081488a 51 // ctnrls
wbeaumont 0:33bb5081488a 52 u32 get_ctrl();
wbeaumont 0:33bb5081488a 53 u32 soft_clr();
wbeaumont 0:33bb5081488a 54 u32 soft_rst();
wbeaumont 0:33bb5081488a 55 u32 clear_code();
wbeaumont 1:d2d6341d3e97 56 void init1();
wbeaumont 1:d2d6341d3e97 57 void init2();
wbeaumont 1:d2d6341d3e97 58
wbeaumont 1:d2d6341d3e97 59
wbeaumont 0:33bb5081488a 60
wbeaumont 0:33bb5081488a 61 };
wbeaumont 0:33bb5081488a 62
wbeaumont 0:33bb5081488a 63 #endif