Code for Technion Formula car sensors reader
Dependencies: mbed Buffer FATFileSystem
Fork of SX1272PingPong by
This is code is part of a Technion course project in advanced IoT, implementing a device to read and transmit sensors data from a Formula racing car built by students at Technion - Israel Institute of Technology.
How to install
- Create an account on Mbed: https://os.mbed.com/account/signup/
- Import project into Compiler
- In the Program Workspace select "Formula_Nucleo_Reader"
- Select a Platform like so:
- Click button at top-left
- Add Board
- Search "NUCLEO F103RB" and then "Add to your Mbed Compiler"
- Finally click "Compile", if the build was successful, the binary would download automatically
- To install it on device simply plug it in to a PC, open device drive and drag then drop binary file in it
SX1272Lib/sx1272/sx1272.cpp@15:2e0d977dbb31, 2018-05-17 (annotated)
- Committer:
- wardm
- Date:
- Thu May 17 20:37:41 2018 +0000
- Revision:
- 15:2e0d977dbb31
V1.0.0
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
wardm | 15:2e0d977dbb31 | 1 | /* |
wardm | 15:2e0d977dbb31 | 2 | / _____) _ | | |
wardm | 15:2e0d977dbb31 | 3 | ( (____ _____ ____ _| |_ _____ ____| |__ |
wardm | 15:2e0d977dbb31 | 4 | \____ \| ___ | (_ _) ___ |/ ___) _ \ |
wardm | 15:2e0d977dbb31 | 5 | _____) ) ____| | | || |_| ____( (___| | | | |
wardm | 15:2e0d977dbb31 | 6 | (______/|_____)_|_|_| \__)_____)\____)_| |_| |
wardm | 15:2e0d977dbb31 | 7 | (C) 2015 Semtech |
wardm | 15:2e0d977dbb31 | 8 | |
wardm | 15:2e0d977dbb31 | 9 | Description: Actual implementation of a SX1272 radio, inherits Radio |
wardm | 15:2e0d977dbb31 | 10 | |
wardm | 15:2e0d977dbb31 | 11 | License: Revised BSD License, see LICENSE.TXT file include in the project |
wardm | 15:2e0d977dbb31 | 12 | |
wardm | 15:2e0d977dbb31 | 13 | Maintainers: Miguel Luis, Gregory Cristian and Nicolas Huguenin |
wardm | 15:2e0d977dbb31 | 14 | */ |
wardm | 15:2e0d977dbb31 | 15 | #include "sx1272.h" |
wardm | 15:2e0d977dbb31 | 16 | |
wardm | 15:2e0d977dbb31 | 17 | const FskBandwidth_t SX1272::FskBandwidths[] = |
wardm | 15:2e0d977dbb31 | 18 | { |
wardm | 15:2e0d977dbb31 | 19 | { 2600 , 0x17 }, |
wardm | 15:2e0d977dbb31 | 20 | { 3100 , 0x0F }, |
wardm | 15:2e0d977dbb31 | 21 | { 3900 , 0x07 }, |
wardm | 15:2e0d977dbb31 | 22 | { 5200 , 0x16 }, |
wardm | 15:2e0d977dbb31 | 23 | { 6300 , 0x0E }, |
wardm | 15:2e0d977dbb31 | 24 | { 7800 , 0x06 }, |
wardm | 15:2e0d977dbb31 | 25 | { 10400 , 0x15 }, |
wardm | 15:2e0d977dbb31 | 26 | { 12500 , 0x0D }, |
wardm | 15:2e0d977dbb31 | 27 | { 15600 , 0x05 }, |
wardm | 15:2e0d977dbb31 | 28 | { 20800 , 0x14 }, |
wardm | 15:2e0d977dbb31 | 29 | { 25000 , 0x0C }, |
wardm | 15:2e0d977dbb31 | 30 | { 31300 , 0x04 }, |
wardm | 15:2e0d977dbb31 | 31 | { 41700 , 0x13 }, |
wardm | 15:2e0d977dbb31 | 32 | { 50000 , 0x0B }, |
wardm | 15:2e0d977dbb31 | 33 | { 62500 , 0x03 }, |
wardm | 15:2e0d977dbb31 | 34 | { 83333 , 0x12 }, |
wardm | 15:2e0d977dbb31 | 35 | { 100000, 0x0A }, |
wardm | 15:2e0d977dbb31 | 36 | { 125000, 0x02 }, |
wardm | 15:2e0d977dbb31 | 37 | { 166700, 0x11 }, |
wardm | 15:2e0d977dbb31 | 38 | { 200000, 0x09 }, |
wardm | 15:2e0d977dbb31 | 39 | { 250000, 0x01 }, |
wardm | 15:2e0d977dbb31 | 40 | { 300000, 0x00 }, // Invalid Bandwidth |
wardm | 15:2e0d977dbb31 | 41 | }; |
wardm | 15:2e0d977dbb31 | 42 | |
wardm | 15:2e0d977dbb31 | 43 | |
wardm | 15:2e0d977dbb31 | 44 | SX1272::SX1272( RadioEvents_t *events, |
wardm | 15:2e0d977dbb31 | 45 | PinName mosi, PinName miso, PinName sclk, PinName nss, PinName reset, |
wardm | 15:2e0d977dbb31 | 46 | PinName dio0, PinName dio1, PinName dio2, PinName dio3, PinName dio4, PinName dio5 ) |
wardm | 15:2e0d977dbb31 | 47 | : Radio( events ), |
wardm | 15:2e0d977dbb31 | 48 | spi( mosi, miso, sclk ), |
wardm | 15:2e0d977dbb31 | 49 | nss( nss ), |
wardm | 15:2e0d977dbb31 | 50 | reset( reset ), |
wardm | 15:2e0d977dbb31 | 51 | dio0( dio0 ), dio1( dio1 ), dio2( dio2 ), dio3( dio3 ), dio4( dio4 ), dio5( dio5 ), |
wardm | 15:2e0d977dbb31 | 52 | isRadioActive( false ) |
wardm | 15:2e0d977dbb31 | 53 | { |
wardm | 15:2e0d977dbb31 | 54 | wait_ms( 10 ); |
wardm | 15:2e0d977dbb31 | 55 | this->rxtxBuffer = new uint8_t[RX_BUFFER_SIZE]; |
wardm | 15:2e0d977dbb31 | 56 | |
wardm | 15:2e0d977dbb31 | 57 | this->RadioEvents = events; |
wardm | 15:2e0d977dbb31 | 58 | |
wardm | 15:2e0d977dbb31 | 59 | this->dioIrq = new DioIrqHandler[6]; |
wardm | 15:2e0d977dbb31 | 60 | |
wardm | 15:2e0d977dbb31 | 61 | this->dioIrq[0] = &SX1272::OnDio0Irq; |
wardm | 15:2e0d977dbb31 | 62 | this->dioIrq[1] = &SX1272::OnDio1Irq; |
wardm | 15:2e0d977dbb31 | 63 | this->dioIrq[2] = &SX1272::OnDio2Irq; |
wardm | 15:2e0d977dbb31 | 64 | this->dioIrq[3] = &SX1272::OnDio3Irq; |
wardm | 15:2e0d977dbb31 | 65 | this->dioIrq[4] = &SX1272::OnDio4Irq; |
wardm | 15:2e0d977dbb31 | 66 | this->dioIrq[5] = NULL; |
wardm | 15:2e0d977dbb31 | 67 | |
wardm | 15:2e0d977dbb31 | 68 | this->settings.State = RF_IDLE; |
wardm | 15:2e0d977dbb31 | 69 | } |
wardm | 15:2e0d977dbb31 | 70 | |
wardm | 15:2e0d977dbb31 | 71 | SX1272::~SX1272( ) |
wardm | 15:2e0d977dbb31 | 72 | { |
wardm | 15:2e0d977dbb31 | 73 | delete this->rxtxBuffer; |
wardm | 15:2e0d977dbb31 | 74 | delete this->dioIrq; |
wardm | 15:2e0d977dbb31 | 75 | } |
wardm | 15:2e0d977dbb31 | 76 | |
wardm | 15:2e0d977dbb31 | 77 | void SX1272::Init( RadioEvents_t *events ) |
wardm | 15:2e0d977dbb31 | 78 | { |
wardm | 15:2e0d977dbb31 | 79 | this->RadioEvents = events; |
wardm | 15:2e0d977dbb31 | 80 | } |
wardm | 15:2e0d977dbb31 | 81 | |
wardm | 15:2e0d977dbb31 | 82 | RadioState SX1272::GetStatus( void ) |
wardm | 15:2e0d977dbb31 | 83 | { |
wardm | 15:2e0d977dbb31 | 84 | return this->settings.State; |
wardm | 15:2e0d977dbb31 | 85 | } |
wardm | 15:2e0d977dbb31 | 86 | |
wardm | 15:2e0d977dbb31 | 87 | void SX1272::SetChannel( uint32_t freq ) |
wardm | 15:2e0d977dbb31 | 88 | { |
wardm | 15:2e0d977dbb31 | 89 | this->settings.Channel = freq; |
wardm | 15:2e0d977dbb31 | 90 | freq = ( uint32_t )( ( double )freq / ( double )FREQ_STEP ); |
wardm | 15:2e0d977dbb31 | 91 | Write( REG_FRFMSB, ( uint8_t )( ( freq >> 16 ) & 0xFF ) ); |
wardm | 15:2e0d977dbb31 | 92 | Write( REG_FRFMID, ( uint8_t )( ( freq >> 8 ) & 0xFF ) ); |
wardm | 15:2e0d977dbb31 | 93 | Write( REG_FRFLSB, ( uint8_t )( freq & 0xFF ) ); |
wardm | 15:2e0d977dbb31 | 94 | } |
wardm | 15:2e0d977dbb31 | 95 | |
wardm | 15:2e0d977dbb31 | 96 | bool SX1272::IsChannelFree( RadioModems_t modem, uint32_t freq, int16_t rssiThresh ) |
wardm | 15:2e0d977dbb31 | 97 | { |
wardm | 15:2e0d977dbb31 | 98 | int16_t rssi = 0; |
wardm | 15:2e0d977dbb31 | 99 | |
wardm | 15:2e0d977dbb31 | 100 | SetModem( modem ); |
wardm | 15:2e0d977dbb31 | 101 | |
wardm | 15:2e0d977dbb31 | 102 | SetChannel( freq ); |
wardm | 15:2e0d977dbb31 | 103 | |
wardm | 15:2e0d977dbb31 | 104 | SetOpMode( RF_OPMODE_RECEIVER ); |
wardm | 15:2e0d977dbb31 | 105 | |
wardm | 15:2e0d977dbb31 | 106 | wait_ms( 1 ); |
wardm | 15:2e0d977dbb31 | 107 | |
wardm | 15:2e0d977dbb31 | 108 | rssi = GetRssi( modem ); |
wardm | 15:2e0d977dbb31 | 109 | |
wardm | 15:2e0d977dbb31 | 110 | Sleep( ); |
wardm | 15:2e0d977dbb31 | 111 | |
wardm | 15:2e0d977dbb31 | 112 | if( rssi > rssiThresh ) |
wardm | 15:2e0d977dbb31 | 113 | { |
wardm | 15:2e0d977dbb31 | 114 | return false; |
wardm | 15:2e0d977dbb31 | 115 | } |
wardm | 15:2e0d977dbb31 | 116 | return true; |
wardm | 15:2e0d977dbb31 | 117 | } |
wardm | 15:2e0d977dbb31 | 118 | |
wardm | 15:2e0d977dbb31 | 119 | uint32_t SX1272::Random( void ) |
wardm | 15:2e0d977dbb31 | 120 | { |
wardm | 15:2e0d977dbb31 | 121 | uint8_t i; |
wardm | 15:2e0d977dbb31 | 122 | uint32_t rnd = 0; |
wardm | 15:2e0d977dbb31 | 123 | |
wardm | 15:2e0d977dbb31 | 124 | /* |
wardm | 15:2e0d977dbb31 | 125 | * Radio setup for random number generation |
wardm | 15:2e0d977dbb31 | 126 | */ |
wardm | 15:2e0d977dbb31 | 127 | // Set LoRa modem ON |
wardm | 15:2e0d977dbb31 | 128 | SetModem( MODEM_LORA ); |
wardm | 15:2e0d977dbb31 | 129 | |
wardm | 15:2e0d977dbb31 | 130 | // Disable LoRa modem interrupts |
wardm | 15:2e0d977dbb31 | 131 | Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT | |
wardm | 15:2e0d977dbb31 | 132 | RFLR_IRQFLAGS_RXDONE | |
wardm | 15:2e0d977dbb31 | 133 | RFLR_IRQFLAGS_PAYLOADCRCERROR | |
wardm | 15:2e0d977dbb31 | 134 | RFLR_IRQFLAGS_VALIDHEADER | |
wardm | 15:2e0d977dbb31 | 135 | RFLR_IRQFLAGS_TXDONE | |
wardm | 15:2e0d977dbb31 | 136 | RFLR_IRQFLAGS_CADDONE | |
wardm | 15:2e0d977dbb31 | 137 | RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL | |
wardm | 15:2e0d977dbb31 | 138 | RFLR_IRQFLAGS_CADDETECTED ); |
wardm | 15:2e0d977dbb31 | 139 | |
wardm | 15:2e0d977dbb31 | 140 | // Set radio in continuous reception |
wardm | 15:2e0d977dbb31 | 141 | SetOpMode( RF_OPMODE_RECEIVER ); |
wardm | 15:2e0d977dbb31 | 142 | |
wardm | 15:2e0d977dbb31 | 143 | for( i = 0; i < 32; i++ ) |
wardm | 15:2e0d977dbb31 | 144 | { |
wardm | 15:2e0d977dbb31 | 145 | wait_ms( 1 ); |
wardm | 15:2e0d977dbb31 | 146 | // Unfiltered RSSI value reading. Only takes the LSB value |
wardm | 15:2e0d977dbb31 | 147 | rnd |= ( ( uint32_t )Read( REG_LR_RSSIWIDEBAND ) & 0x01 ) << i; |
wardm | 15:2e0d977dbb31 | 148 | } |
wardm | 15:2e0d977dbb31 | 149 | |
wardm | 15:2e0d977dbb31 | 150 | Sleep( ); |
wardm | 15:2e0d977dbb31 | 151 | |
wardm | 15:2e0d977dbb31 | 152 | return rnd; |
wardm | 15:2e0d977dbb31 | 153 | } |
wardm | 15:2e0d977dbb31 | 154 | |
wardm | 15:2e0d977dbb31 | 155 | /*! |
wardm | 15:2e0d977dbb31 | 156 | * Returns the known FSK bandwidth registers value |
wardm | 15:2e0d977dbb31 | 157 | * |
wardm | 15:2e0d977dbb31 | 158 | * \param [IN] bandwidth Bandwidth value in Hz |
wardm | 15:2e0d977dbb31 | 159 | * \retval regValue Bandwidth register value. |
wardm | 15:2e0d977dbb31 | 160 | */ |
wardm | 15:2e0d977dbb31 | 161 | uint8_t SX1272::GetFskBandwidthRegValue( uint32_t bandwidth ) |
wardm | 15:2e0d977dbb31 | 162 | { |
wardm | 15:2e0d977dbb31 | 163 | uint8_t i; |
wardm | 15:2e0d977dbb31 | 164 | |
wardm | 15:2e0d977dbb31 | 165 | for( i = 0; i < ( sizeof( FskBandwidths ) / sizeof( FskBandwidth_t ) ) - 1; i++ ) |
wardm | 15:2e0d977dbb31 | 166 | { |
wardm | 15:2e0d977dbb31 | 167 | if( ( bandwidth >= FskBandwidths[i].bandwidth ) && ( bandwidth < FskBandwidths[i + 1].bandwidth ) ) |
wardm | 15:2e0d977dbb31 | 168 | { |
wardm | 15:2e0d977dbb31 | 169 | return FskBandwidths[i].RegValue; |
wardm | 15:2e0d977dbb31 | 170 | } |
wardm | 15:2e0d977dbb31 | 171 | } |
wardm | 15:2e0d977dbb31 | 172 | // ERROR: Value not found |
wardm | 15:2e0d977dbb31 | 173 | while( 1 ); |
wardm | 15:2e0d977dbb31 | 174 | } |
wardm | 15:2e0d977dbb31 | 175 | |
wardm | 15:2e0d977dbb31 | 176 | void SX1272::SetRxConfig( RadioModems_t modem, uint32_t bandwidth, |
wardm | 15:2e0d977dbb31 | 177 | uint32_t datarate, uint8_t coderate, |
wardm | 15:2e0d977dbb31 | 178 | uint32_t bandwidthAfc, uint16_t preambleLen, |
wardm | 15:2e0d977dbb31 | 179 | uint16_t symbTimeout, bool fixLen, |
wardm | 15:2e0d977dbb31 | 180 | uint8_t payloadLen, |
wardm | 15:2e0d977dbb31 | 181 | bool crcOn, bool freqHopOn, uint8_t hopPeriod, |
wardm | 15:2e0d977dbb31 | 182 | bool iqInverted, bool rxContinuous ) |
wardm | 15:2e0d977dbb31 | 183 | { |
wardm | 15:2e0d977dbb31 | 184 | SetModem( modem ); |
wardm | 15:2e0d977dbb31 | 185 | |
wardm | 15:2e0d977dbb31 | 186 | switch( modem ) |
wardm | 15:2e0d977dbb31 | 187 | { |
wardm | 15:2e0d977dbb31 | 188 | case MODEM_FSK: |
wardm | 15:2e0d977dbb31 | 189 | { |
wardm | 15:2e0d977dbb31 | 190 | this->settings.Fsk.Bandwidth = bandwidth; |
wardm | 15:2e0d977dbb31 | 191 | this->settings.Fsk.Datarate = datarate; |
wardm | 15:2e0d977dbb31 | 192 | this->settings.Fsk.BandwidthAfc = bandwidthAfc; |
wardm | 15:2e0d977dbb31 | 193 | this->settings.Fsk.FixLen = fixLen; |
wardm | 15:2e0d977dbb31 | 194 | this->settings.Fsk.PayloadLen = payloadLen; |
wardm | 15:2e0d977dbb31 | 195 | this->settings.Fsk.CrcOn = crcOn; |
wardm | 15:2e0d977dbb31 | 196 | this->settings.Fsk.IqInverted = iqInverted; |
wardm | 15:2e0d977dbb31 | 197 | this->settings.Fsk.RxContinuous = rxContinuous; |
wardm | 15:2e0d977dbb31 | 198 | this->settings.Fsk.PreambleLen = preambleLen; |
wardm | 15:2e0d977dbb31 | 199 | this->settings.Fsk.RxSingleTimeout = symbTimeout * ( ( 1.0 / ( double )datarate ) * 8.0 ) * 1e3; |
wardm | 15:2e0d977dbb31 | 200 | |
wardm | 15:2e0d977dbb31 | 201 | datarate = ( uint16_t )( ( double )XTAL_FREQ / ( double )datarate ); |
wardm | 15:2e0d977dbb31 | 202 | Write( REG_BITRATEMSB, ( uint8_t )( datarate >> 8 ) ); |
wardm | 15:2e0d977dbb31 | 203 | Write( REG_BITRATELSB, ( uint8_t )( datarate & 0xFF ) ); |
wardm | 15:2e0d977dbb31 | 204 | |
wardm | 15:2e0d977dbb31 | 205 | Write( REG_RXBW, GetFskBandwidthRegValue( bandwidth ) ); |
wardm | 15:2e0d977dbb31 | 206 | Write( REG_AFCBW, GetFskBandwidthRegValue( bandwidthAfc ) ); |
wardm | 15:2e0d977dbb31 | 207 | |
wardm | 15:2e0d977dbb31 | 208 | Write( REG_PREAMBLEMSB, ( uint8_t )( ( preambleLen >> 8 ) & 0xFF ) ); |
wardm | 15:2e0d977dbb31 | 209 | Write( REG_PREAMBLELSB, ( uint8_t )( preambleLen & 0xFF ) ); |
wardm | 15:2e0d977dbb31 | 210 | |
wardm | 15:2e0d977dbb31 | 211 | if( fixLen == 1 ) |
wardm | 15:2e0d977dbb31 | 212 | { |
wardm | 15:2e0d977dbb31 | 213 | Write( REG_PAYLOADLENGTH, payloadLen ); |
wardm | 15:2e0d977dbb31 | 214 | } |
wardm | 15:2e0d977dbb31 | 215 | else |
wardm | 15:2e0d977dbb31 | 216 | { |
wardm | 15:2e0d977dbb31 | 217 | Write( REG_PAYLOADLENGTH, 0xFF ); // Set payload length to the maximum |
wardm | 15:2e0d977dbb31 | 218 | } |
wardm | 15:2e0d977dbb31 | 219 | |
wardm | 15:2e0d977dbb31 | 220 | Write( REG_PACKETCONFIG1, |
wardm | 15:2e0d977dbb31 | 221 | ( Read( REG_PACKETCONFIG1 ) & |
wardm | 15:2e0d977dbb31 | 222 | RF_PACKETCONFIG1_CRC_MASK & |
wardm | 15:2e0d977dbb31 | 223 | RF_PACKETCONFIG1_PACKETFORMAT_MASK ) | |
wardm | 15:2e0d977dbb31 | 224 | ( ( fixLen == 1 ) ? RF_PACKETCONFIG1_PACKETFORMAT_FIXED : RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE ) | |
wardm | 15:2e0d977dbb31 | 225 | ( crcOn << 4 ) ); |
wardm | 15:2e0d977dbb31 | 226 | Write( REG_PACKETCONFIG2, ( Read( REG_PACKETCONFIG2 ) | RF_PACKETCONFIG2_DATAMODE_PACKET ) ); |
wardm | 15:2e0d977dbb31 | 227 | } |
wardm | 15:2e0d977dbb31 | 228 | break; |
wardm | 15:2e0d977dbb31 | 229 | case MODEM_LORA: |
wardm | 15:2e0d977dbb31 | 230 | { |
wardm | 15:2e0d977dbb31 | 231 | this->settings.LoRa.Bandwidth = bandwidth; |
wardm | 15:2e0d977dbb31 | 232 | this->settings.LoRa.Datarate = datarate; |
wardm | 15:2e0d977dbb31 | 233 | this->settings.LoRa.Coderate = coderate; |
wardm | 15:2e0d977dbb31 | 234 | this->settings.LoRa.PreambleLen = preambleLen; |
wardm | 15:2e0d977dbb31 | 235 | this->settings.LoRa.FixLen = fixLen; |
wardm | 15:2e0d977dbb31 | 236 | this->settings.LoRa.PayloadLen = payloadLen; |
wardm | 15:2e0d977dbb31 | 237 | this->settings.LoRa.CrcOn = crcOn; |
wardm | 15:2e0d977dbb31 | 238 | this->settings.LoRa.FreqHopOn = freqHopOn; |
wardm | 15:2e0d977dbb31 | 239 | this->settings.LoRa.HopPeriod = hopPeriod; |
wardm | 15:2e0d977dbb31 | 240 | this->settings.LoRa.IqInverted = iqInverted; |
wardm | 15:2e0d977dbb31 | 241 | this->settings.LoRa.RxContinuous = rxContinuous; |
wardm | 15:2e0d977dbb31 | 242 | |
wardm | 15:2e0d977dbb31 | 243 | if( datarate > 12 ) |
wardm | 15:2e0d977dbb31 | 244 | { |
wardm | 15:2e0d977dbb31 | 245 | datarate = 12; |
wardm | 15:2e0d977dbb31 | 246 | } |
wardm | 15:2e0d977dbb31 | 247 | else if( datarate < 6 ) |
wardm | 15:2e0d977dbb31 | 248 | { |
wardm | 15:2e0d977dbb31 | 249 | datarate = 6; |
wardm | 15:2e0d977dbb31 | 250 | } |
wardm | 15:2e0d977dbb31 | 251 | |
wardm | 15:2e0d977dbb31 | 252 | if( ( ( bandwidth == 0 ) && ( ( datarate == 11 ) || ( datarate == 12 ) ) ) || |
wardm | 15:2e0d977dbb31 | 253 | ( ( bandwidth == 1 ) && ( datarate == 12 ) ) ) |
wardm | 15:2e0d977dbb31 | 254 | { |
wardm | 15:2e0d977dbb31 | 255 | this->settings.LoRa.LowDatarateOptimize = 0x01; |
wardm | 15:2e0d977dbb31 | 256 | } |
wardm | 15:2e0d977dbb31 | 257 | else |
wardm | 15:2e0d977dbb31 | 258 | { |
wardm | 15:2e0d977dbb31 | 259 | this->settings.LoRa.LowDatarateOptimize = 0x00; |
wardm | 15:2e0d977dbb31 | 260 | } |
wardm | 15:2e0d977dbb31 | 261 | |
wardm | 15:2e0d977dbb31 | 262 | Write( REG_LR_MODEMCONFIG1, |
wardm | 15:2e0d977dbb31 | 263 | ( Read( REG_LR_MODEMCONFIG1 ) & |
wardm | 15:2e0d977dbb31 | 264 | RFLR_MODEMCONFIG1_BW_MASK & |
wardm | 15:2e0d977dbb31 | 265 | RFLR_MODEMCONFIG1_CODINGRATE_MASK & |
wardm | 15:2e0d977dbb31 | 266 | RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK & |
wardm | 15:2e0d977dbb31 | 267 | RFLR_MODEMCONFIG1_RXPAYLOADCRC_MASK & |
wardm | 15:2e0d977dbb31 | 268 | RFLR_MODEMCONFIG1_LOWDATARATEOPTIMIZE_MASK ) | |
wardm | 15:2e0d977dbb31 | 269 | ( bandwidth << 6 ) | ( coderate << 3 ) | |
wardm | 15:2e0d977dbb31 | 270 | ( fixLen << 2 ) | ( crcOn << 1 ) | |
wardm | 15:2e0d977dbb31 | 271 | this->settings.LoRa.LowDatarateOptimize ); |
wardm | 15:2e0d977dbb31 | 272 | |
wardm | 15:2e0d977dbb31 | 273 | Write( REG_LR_MODEMCONFIG2, |
wardm | 15:2e0d977dbb31 | 274 | ( Read( REG_LR_MODEMCONFIG2 ) & |
wardm | 15:2e0d977dbb31 | 275 | RFLR_MODEMCONFIG2_SF_MASK & |
wardm | 15:2e0d977dbb31 | 276 | RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ) | |
wardm | 15:2e0d977dbb31 | 277 | ( datarate << 4 ) | |
wardm | 15:2e0d977dbb31 | 278 | ( ( symbTimeout >> 8 ) & ~RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ) ); |
wardm | 15:2e0d977dbb31 | 279 | |
wardm | 15:2e0d977dbb31 | 280 | Write( REG_LR_SYMBTIMEOUTLSB, ( uint8_t )( symbTimeout & 0xFF ) ); |
wardm | 15:2e0d977dbb31 | 281 | |
wardm | 15:2e0d977dbb31 | 282 | Write( REG_LR_PREAMBLEMSB, ( uint8_t )( ( preambleLen >> 8 ) & 0xFF ) ); |
wardm | 15:2e0d977dbb31 | 283 | Write( REG_LR_PREAMBLELSB, ( uint8_t )( preambleLen & 0xFF ) ); |
wardm | 15:2e0d977dbb31 | 284 | |
wardm | 15:2e0d977dbb31 | 285 | if( fixLen == 1 ) |
wardm | 15:2e0d977dbb31 | 286 | { |
wardm | 15:2e0d977dbb31 | 287 | Write( REG_LR_PAYLOADLENGTH, payloadLen ); |
wardm | 15:2e0d977dbb31 | 288 | } |
wardm | 15:2e0d977dbb31 | 289 | |
wardm | 15:2e0d977dbb31 | 290 | if( this->settings.LoRa.FreqHopOn == true ) |
wardm | 15:2e0d977dbb31 | 291 | { |
wardm | 15:2e0d977dbb31 | 292 | Write( REG_LR_PLLHOP, ( Read( REG_LR_PLLHOP ) & RFLR_PLLHOP_FASTHOP_MASK ) | RFLR_PLLHOP_FASTHOP_ON ); |
wardm | 15:2e0d977dbb31 | 293 | Write( REG_LR_HOPPERIOD, this->settings.LoRa.HopPeriod ); |
wardm | 15:2e0d977dbb31 | 294 | } |
wardm | 15:2e0d977dbb31 | 295 | |
wardm | 15:2e0d977dbb31 | 296 | if( datarate == 6 ) |
wardm | 15:2e0d977dbb31 | 297 | { |
wardm | 15:2e0d977dbb31 | 298 | Write( REG_LR_DETECTOPTIMIZE, |
wardm | 15:2e0d977dbb31 | 299 | ( Read( REG_LR_DETECTOPTIMIZE ) & |
wardm | 15:2e0d977dbb31 | 300 | RFLR_DETECTIONOPTIMIZE_MASK ) | |
wardm | 15:2e0d977dbb31 | 301 | RFLR_DETECTIONOPTIMIZE_SF6 ); |
wardm | 15:2e0d977dbb31 | 302 | Write( REG_LR_DETECTIONTHRESHOLD, |
wardm | 15:2e0d977dbb31 | 303 | RFLR_DETECTIONTHRESH_SF6 ); |
wardm | 15:2e0d977dbb31 | 304 | } |
wardm | 15:2e0d977dbb31 | 305 | else |
wardm | 15:2e0d977dbb31 | 306 | { |
wardm | 15:2e0d977dbb31 | 307 | Write( REG_LR_DETECTOPTIMIZE, |
wardm | 15:2e0d977dbb31 | 308 | ( Read( REG_LR_DETECTOPTIMIZE ) & |
wardm | 15:2e0d977dbb31 | 309 | RFLR_DETECTIONOPTIMIZE_MASK ) | |
wardm | 15:2e0d977dbb31 | 310 | RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 ); |
wardm | 15:2e0d977dbb31 | 311 | Write( REG_LR_DETECTIONTHRESHOLD, |
wardm | 15:2e0d977dbb31 | 312 | RFLR_DETECTIONTHRESH_SF7_TO_SF12 ); |
wardm | 15:2e0d977dbb31 | 313 | } |
wardm | 15:2e0d977dbb31 | 314 | } |
wardm | 15:2e0d977dbb31 | 315 | break; |
wardm | 15:2e0d977dbb31 | 316 | } |
wardm | 15:2e0d977dbb31 | 317 | } |
wardm | 15:2e0d977dbb31 | 318 | |
wardm | 15:2e0d977dbb31 | 319 | void SX1272::SetTxConfig( RadioModems_t modem, int8_t power, uint32_t fdev, |
wardm | 15:2e0d977dbb31 | 320 | uint32_t bandwidth, uint32_t datarate, |
wardm | 15:2e0d977dbb31 | 321 | uint8_t coderate, uint16_t preambleLen, |
wardm | 15:2e0d977dbb31 | 322 | bool fixLen, bool crcOn, bool freqHopOn, |
wardm | 15:2e0d977dbb31 | 323 | uint8_t hopPeriod, bool iqInverted, uint32_t timeout ) |
wardm | 15:2e0d977dbb31 | 324 | { |
wardm | 15:2e0d977dbb31 | 325 | SetModem( modem ); |
wardm | 15:2e0d977dbb31 | 326 | |
wardm | 15:2e0d977dbb31 | 327 | SetRfTxPower( power ); |
wardm | 15:2e0d977dbb31 | 328 | |
wardm | 15:2e0d977dbb31 | 329 | switch( modem ) |
wardm | 15:2e0d977dbb31 | 330 | { |
wardm | 15:2e0d977dbb31 | 331 | case MODEM_FSK: |
wardm | 15:2e0d977dbb31 | 332 | { |
wardm | 15:2e0d977dbb31 | 333 | this->settings.Fsk.Power = power; |
wardm | 15:2e0d977dbb31 | 334 | this->settings.Fsk.Fdev = fdev; |
wardm | 15:2e0d977dbb31 | 335 | this->settings.Fsk.Bandwidth = bandwidth; |
wardm | 15:2e0d977dbb31 | 336 | this->settings.Fsk.Datarate = datarate; |
wardm | 15:2e0d977dbb31 | 337 | this->settings.Fsk.PreambleLen = preambleLen; |
wardm | 15:2e0d977dbb31 | 338 | this->settings.Fsk.FixLen = fixLen; |
wardm | 15:2e0d977dbb31 | 339 | this->settings.Fsk.CrcOn = crcOn; |
wardm | 15:2e0d977dbb31 | 340 | this->settings.Fsk.IqInverted = iqInverted; |
wardm | 15:2e0d977dbb31 | 341 | this->settings.Fsk.TxTimeout = timeout; |
wardm | 15:2e0d977dbb31 | 342 | |
wardm | 15:2e0d977dbb31 | 343 | fdev = ( uint16_t )( ( double )fdev / ( double )FREQ_STEP ); |
wardm | 15:2e0d977dbb31 | 344 | Write( REG_FDEVMSB, ( uint8_t )( fdev >> 8 ) ); |
wardm | 15:2e0d977dbb31 | 345 | Write( REG_FDEVLSB, ( uint8_t )( fdev & 0xFF ) ); |
wardm | 15:2e0d977dbb31 | 346 | |
wardm | 15:2e0d977dbb31 | 347 | datarate = ( uint16_t )( ( double )XTAL_FREQ / ( double )datarate ); |
wardm | 15:2e0d977dbb31 | 348 | Write( REG_BITRATEMSB, ( uint8_t )( datarate >> 8 ) ); |
wardm | 15:2e0d977dbb31 | 349 | Write( REG_BITRATELSB, ( uint8_t )( datarate & 0xFF ) ); |
wardm | 15:2e0d977dbb31 | 350 | |
wardm | 15:2e0d977dbb31 | 351 | Write( REG_PREAMBLEMSB, ( preambleLen >> 8 ) & 0x00FF ); |
wardm | 15:2e0d977dbb31 | 352 | Write( REG_PREAMBLELSB, preambleLen & 0xFF ); |
wardm | 15:2e0d977dbb31 | 353 | |
wardm | 15:2e0d977dbb31 | 354 | Write( REG_PACKETCONFIG1, |
wardm | 15:2e0d977dbb31 | 355 | ( Read( REG_PACKETCONFIG1 ) & |
wardm | 15:2e0d977dbb31 | 356 | RF_PACKETCONFIG1_CRC_MASK & |
wardm | 15:2e0d977dbb31 | 357 | RF_PACKETCONFIG1_PACKETFORMAT_MASK ) | |
wardm | 15:2e0d977dbb31 | 358 | ( ( fixLen == 1 ) ? RF_PACKETCONFIG1_PACKETFORMAT_FIXED : RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE ) | |
wardm | 15:2e0d977dbb31 | 359 | ( crcOn << 4 ) ); |
wardm | 15:2e0d977dbb31 | 360 | Write( REG_PACKETCONFIG2, ( Read( REG_PACKETCONFIG2 ) | RF_PACKETCONFIG2_DATAMODE_PACKET ) ); |
wardm | 15:2e0d977dbb31 | 361 | } |
wardm | 15:2e0d977dbb31 | 362 | break; |
wardm | 15:2e0d977dbb31 | 363 | case MODEM_LORA: |
wardm | 15:2e0d977dbb31 | 364 | { |
wardm | 15:2e0d977dbb31 | 365 | this->settings.LoRa.Power = power; |
wardm | 15:2e0d977dbb31 | 366 | this->settings.LoRa.Bandwidth = bandwidth; |
wardm | 15:2e0d977dbb31 | 367 | this->settings.LoRa.Datarate = datarate; |
wardm | 15:2e0d977dbb31 | 368 | this->settings.LoRa.Coderate = coderate; |
wardm | 15:2e0d977dbb31 | 369 | this->settings.LoRa.PreambleLen = preambleLen; |
wardm | 15:2e0d977dbb31 | 370 | this->settings.LoRa.FixLen = fixLen; |
wardm | 15:2e0d977dbb31 | 371 | this->settings.LoRa.FreqHopOn = freqHopOn; |
wardm | 15:2e0d977dbb31 | 372 | this->settings.LoRa.HopPeriod = hopPeriod; |
wardm | 15:2e0d977dbb31 | 373 | this->settings.LoRa.CrcOn = crcOn; |
wardm | 15:2e0d977dbb31 | 374 | this->settings.LoRa.IqInverted = iqInverted; |
wardm | 15:2e0d977dbb31 | 375 | this->settings.LoRa.TxTimeout = timeout; |
wardm | 15:2e0d977dbb31 | 376 | |
wardm | 15:2e0d977dbb31 | 377 | if( datarate > 12 ) |
wardm | 15:2e0d977dbb31 | 378 | { |
wardm | 15:2e0d977dbb31 | 379 | datarate = 12; |
wardm | 15:2e0d977dbb31 | 380 | } |
wardm | 15:2e0d977dbb31 | 381 | else if( datarate < 6 ) |
wardm | 15:2e0d977dbb31 | 382 | { |
wardm | 15:2e0d977dbb31 | 383 | datarate = 6; |
wardm | 15:2e0d977dbb31 | 384 | } |
wardm | 15:2e0d977dbb31 | 385 | if( ( ( bandwidth == 0 ) && ( ( datarate == 11 ) || ( datarate == 12 ) ) ) || |
wardm | 15:2e0d977dbb31 | 386 | ( ( bandwidth == 1 ) && ( datarate == 12 ) ) ) |
wardm | 15:2e0d977dbb31 | 387 | { |
wardm | 15:2e0d977dbb31 | 388 | this->settings.LoRa.LowDatarateOptimize = 0x01; |
wardm | 15:2e0d977dbb31 | 389 | } |
wardm | 15:2e0d977dbb31 | 390 | else |
wardm | 15:2e0d977dbb31 | 391 | { |
wardm | 15:2e0d977dbb31 | 392 | this->settings.LoRa.LowDatarateOptimize = 0x00; |
wardm | 15:2e0d977dbb31 | 393 | } |
wardm | 15:2e0d977dbb31 | 394 | |
wardm | 15:2e0d977dbb31 | 395 | if( this->settings.LoRa.FreqHopOn == true ) |
wardm | 15:2e0d977dbb31 | 396 | { |
wardm | 15:2e0d977dbb31 | 397 | Write( REG_LR_PLLHOP, ( Read( REG_LR_PLLHOP ) & RFLR_PLLHOP_FASTHOP_MASK ) | RFLR_PLLHOP_FASTHOP_ON ); |
wardm | 15:2e0d977dbb31 | 398 | Write( REG_LR_HOPPERIOD, this->settings.LoRa.HopPeriod ); |
wardm | 15:2e0d977dbb31 | 399 | } |
wardm | 15:2e0d977dbb31 | 400 | |
wardm | 15:2e0d977dbb31 | 401 | Write( REG_LR_MODEMCONFIG1, |
wardm | 15:2e0d977dbb31 | 402 | ( Read( REG_LR_MODEMCONFIG1 ) & |
wardm | 15:2e0d977dbb31 | 403 | RFLR_MODEMCONFIG1_BW_MASK & |
wardm | 15:2e0d977dbb31 | 404 | RFLR_MODEMCONFIG1_CODINGRATE_MASK & |
wardm | 15:2e0d977dbb31 | 405 | RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK & |
wardm | 15:2e0d977dbb31 | 406 | RFLR_MODEMCONFIG1_RXPAYLOADCRC_MASK & |
wardm | 15:2e0d977dbb31 | 407 | RFLR_MODEMCONFIG1_LOWDATARATEOPTIMIZE_MASK ) | |
wardm | 15:2e0d977dbb31 | 408 | ( bandwidth << 6 ) | ( coderate << 3 ) | |
wardm | 15:2e0d977dbb31 | 409 | ( fixLen << 2 ) | ( crcOn << 1 ) | |
wardm | 15:2e0d977dbb31 | 410 | this->settings.LoRa.LowDatarateOptimize ); |
wardm | 15:2e0d977dbb31 | 411 | |
wardm | 15:2e0d977dbb31 | 412 | Write( REG_LR_MODEMCONFIG2, |
wardm | 15:2e0d977dbb31 | 413 | ( Read( REG_LR_MODEMCONFIG2 ) & |
wardm | 15:2e0d977dbb31 | 414 | RFLR_MODEMCONFIG2_SF_MASK ) | |
wardm | 15:2e0d977dbb31 | 415 | ( datarate << 4 ) ); |
wardm | 15:2e0d977dbb31 | 416 | |
wardm | 15:2e0d977dbb31 | 417 | |
wardm | 15:2e0d977dbb31 | 418 | Write( REG_LR_PREAMBLEMSB, ( preambleLen >> 8 ) & 0x00FF ); |
wardm | 15:2e0d977dbb31 | 419 | Write( REG_LR_PREAMBLELSB, preambleLen & 0xFF ); |
wardm | 15:2e0d977dbb31 | 420 | |
wardm | 15:2e0d977dbb31 | 421 | if( datarate == 6 ) |
wardm | 15:2e0d977dbb31 | 422 | { |
wardm | 15:2e0d977dbb31 | 423 | Write( REG_LR_DETECTOPTIMIZE, |
wardm | 15:2e0d977dbb31 | 424 | ( Read( REG_LR_DETECTOPTIMIZE ) & |
wardm | 15:2e0d977dbb31 | 425 | RFLR_DETECTIONOPTIMIZE_MASK ) | |
wardm | 15:2e0d977dbb31 | 426 | RFLR_DETECTIONOPTIMIZE_SF6 ); |
wardm | 15:2e0d977dbb31 | 427 | Write( REG_LR_DETECTIONTHRESHOLD, |
wardm | 15:2e0d977dbb31 | 428 | RFLR_DETECTIONTHRESH_SF6 ); |
wardm | 15:2e0d977dbb31 | 429 | } |
wardm | 15:2e0d977dbb31 | 430 | else |
wardm | 15:2e0d977dbb31 | 431 | { |
wardm | 15:2e0d977dbb31 | 432 | Write( REG_LR_DETECTOPTIMIZE, |
wardm | 15:2e0d977dbb31 | 433 | ( Read( REG_LR_DETECTOPTIMIZE ) & |
wardm | 15:2e0d977dbb31 | 434 | RFLR_DETECTIONOPTIMIZE_MASK ) | |
wardm | 15:2e0d977dbb31 | 435 | RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 ); |
wardm | 15:2e0d977dbb31 | 436 | Write( REG_LR_DETECTIONTHRESHOLD, |
wardm | 15:2e0d977dbb31 | 437 | RFLR_DETECTIONTHRESH_SF7_TO_SF12 ); |
wardm | 15:2e0d977dbb31 | 438 | } |
wardm | 15:2e0d977dbb31 | 439 | } |
wardm | 15:2e0d977dbb31 | 440 | break; |
wardm | 15:2e0d977dbb31 | 441 | } |
wardm | 15:2e0d977dbb31 | 442 | } |
wardm | 15:2e0d977dbb31 | 443 | |
wardm | 15:2e0d977dbb31 | 444 | uint32_t SX1272::TimeOnAir( RadioModems_t modem, uint8_t pktLen ) |
wardm | 15:2e0d977dbb31 | 445 | { |
wardm | 15:2e0d977dbb31 | 446 | uint32_t airTime = 0; |
wardm | 15:2e0d977dbb31 | 447 | |
wardm | 15:2e0d977dbb31 | 448 | switch( modem ) |
wardm | 15:2e0d977dbb31 | 449 | { |
wardm | 15:2e0d977dbb31 | 450 | case MODEM_FSK: |
wardm | 15:2e0d977dbb31 | 451 | { |
wardm | 15:2e0d977dbb31 | 452 | airTime = rint( ( 8 * ( this->settings.Fsk.PreambleLen + |
wardm | 15:2e0d977dbb31 | 453 | ( ( Read( REG_SYNCCONFIG ) & ~RF_SYNCCONFIG_SYNCSIZE_MASK ) + 1 ) + |
wardm | 15:2e0d977dbb31 | 454 | ( ( this->settings.Fsk.FixLen == 0x01 ) ? 0.0 : 1.0 ) + |
wardm | 15:2e0d977dbb31 | 455 | ( ( ( Read( REG_PACKETCONFIG1 ) & ~RF_PACKETCONFIG1_ADDRSFILTERING_MASK ) != 0x00 ) ? 1.0 : 0 ) + |
wardm | 15:2e0d977dbb31 | 456 | pktLen + |
wardm | 15:2e0d977dbb31 | 457 | ( ( this->settings.Fsk.CrcOn == 0x01 ) ? 2.0 : 0 ) ) / |
wardm | 15:2e0d977dbb31 | 458 | this->settings.Fsk.Datarate ) * 1e3 ); |
wardm | 15:2e0d977dbb31 | 459 | } |
wardm | 15:2e0d977dbb31 | 460 | break; |
wardm | 15:2e0d977dbb31 | 461 | case MODEM_LORA: |
wardm | 15:2e0d977dbb31 | 462 | { |
wardm | 15:2e0d977dbb31 | 463 | double bw = 0.0; |
wardm | 15:2e0d977dbb31 | 464 | switch( this->settings.LoRa.Bandwidth ) |
wardm | 15:2e0d977dbb31 | 465 | { |
wardm | 15:2e0d977dbb31 | 466 | case 0: // 125 kHz |
wardm | 15:2e0d977dbb31 | 467 | bw = 125e3; |
wardm | 15:2e0d977dbb31 | 468 | break; |
wardm | 15:2e0d977dbb31 | 469 | case 1: // 250 kHz |
wardm | 15:2e0d977dbb31 | 470 | bw = 250e3; |
wardm | 15:2e0d977dbb31 | 471 | break; |
wardm | 15:2e0d977dbb31 | 472 | case 2: // 500 kHz |
wardm | 15:2e0d977dbb31 | 473 | bw = 500e3; |
wardm | 15:2e0d977dbb31 | 474 | break; |
wardm | 15:2e0d977dbb31 | 475 | } |
wardm | 15:2e0d977dbb31 | 476 | |
wardm | 15:2e0d977dbb31 | 477 | // Symbol rate : time for one symbol (secs) |
wardm | 15:2e0d977dbb31 | 478 | double rs = bw / ( 1 << this->settings.LoRa.Datarate ); |
wardm | 15:2e0d977dbb31 | 479 | double ts = 1 / rs; |
wardm | 15:2e0d977dbb31 | 480 | // time of preamble |
wardm | 15:2e0d977dbb31 | 481 | double tPreamble = ( this->settings.LoRa.PreambleLen + 4.25 ) * ts; |
wardm | 15:2e0d977dbb31 | 482 | // Symbol length of payload and time |
wardm | 15:2e0d977dbb31 | 483 | double tmp = ceil( ( 8 * pktLen - 4 * this->settings.LoRa.Datarate + |
wardm | 15:2e0d977dbb31 | 484 | 28 + 16 * this->settings.LoRa.CrcOn - |
wardm | 15:2e0d977dbb31 | 485 | ( this->settings.LoRa.FixLen ? 20 : 0 ) ) / |
wardm | 15:2e0d977dbb31 | 486 | ( double )( 4 * ( this->settings.LoRa.Datarate - |
wardm | 15:2e0d977dbb31 | 487 | ( ( this->settings.LoRa.LowDatarateOptimize > 0 ) ? 2 : 0 ) ) ) ) * |
wardm | 15:2e0d977dbb31 | 488 | ( this->settings.LoRa.Coderate + 4 ); |
wardm | 15:2e0d977dbb31 | 489 | double nPayload = 8 + ( ( tmp > 0 ) ? tmp : 0 ); |
wardm | 15:2e0d977dbb31 | 490 | double tPayload = nPayload * ts; |
wardm | 15:2e0d977dbb31 | 491 | // Time on air |
wardm | 15:2e0d977dbb31 | 492 | double tOnAir = tPreamble + tPayload; |
wardm | 15:2e0d977dbb31 | 493 | // return ms secs |
wardm | 15:2e0d977dbb31 | 494 | airTime = floor( tOnAir * 1e3 + 0.999 ); |
wardm | 15:2e0d977dbb31 | 495 | } |
wardm | 15:2e0d977dbb31 | 496 | break; |
wardm | 15:2e0d977dbb31 | 497 | } |
wardm | 15:2e0d977dbb31 | 498 | return airTime; |
wardm | 15:2e0d977dbb31 | 499 | } |
wardm | 15:2e0d977dbb31 | 500 | |
wardm | 15:2e0d977dbb31 | 501 | void SX1272::Send( uint8_t *buffer, uint8_t size ) |
wardm | 15:2e0d977dbb31 | 502 | { |
wardm | 15:2e0d977dbb31 | 503 | uint32_t txTimeout = 0; |
wardm | 15:2e0d977dbb31 | 504 | |
wardm | 15:2e0d977dbb31 | 505 | switch( this->settings.Modem ) |
wardm | 15:2e0d977dbb31 | 506 | { |
wardm | 15:2e0d977dbb31 | 507 | case MODEM_FSK: |
wardm | 15:2e0d977dbb31 | 508 | { |
wardm | 15:2e0d977dbb31 | 509 | this->settings.FskPacketHandler.NbBytes = 0; |
wardm | 15:2e0d977dbb31 | 510 | this->settings.FskPacketHandler.Size = size; |
wardm | 15:2e0d977dbb31 | 511 | |
wardm | 15:2e0d977dbb31 | 512 | if( this->settings.Fsk.FixLen == false ) |
wardm | 15:2e0d977dbb31 | 513 | { |
wardm | 15:2e0d977dbb31 | 514 | WriteFifo( ( uint8_t* )&size, 1 ); |
wardm | 15:2e0d977dbb31 | 515 | } |
wardm | 15:2e0d977dbb31 | 516 | else |
wardm | 15:2e0d977dbb31 | 517 | { |
wardm | 15:2e0d977dbb31 | 518 | Write( REG_PAYLOADLENGTH, size ); |
wardm | 15:2e0d977dbb31 | 519 | } |
wardm | 15:2e0d977dbb31 | 520 | |
wardm | 15:2e0d977dbb31 | 521 | if( ( size > 0 ) && ( size <= 64 ) ) |
wardm | 15:2e0d977dbb31 | 522 | { |
wardm | 15:2e0d977dbb31 | 523 | this->settings.FskPacketHandler.ChunkSize = size; |
wardm | 15:2e0d977dbb31 | 524 | } |
wardm | 15:2e0d977dbb31 | 525 | else |
wardm | 15:2e0d977dbb31 | 526 | { |
wardm | 15:2e0d977dbb31 | 527 | memcpy( rxtxBuffer, buffer, size ); |
wardm | 15:2e0d977dbb31 | 528 | this->settings.FskPacketHandler.ChunkSize = 32; |
wardm | 15:2e0d977dbb31 | 529 | } |
wardm | 15:2e0d977dbb31 | 530 | |
wardm | 15:2e0d977dbb31 | 531 | // Write payload buffer |
wardm | 15:2e0d977dbb31 | 532 | WriteFifo( buffer, this->settings.FskPacketHandler.ChunkSize ); |
wardm | 15:2e0d977dbb31 | 533 | this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.ChunkSize; |
wardm | 15:2e0d977dbb31 | 534 | txTimeout = this->settings.Fsk.TxTimeout; |
wardm | 15:2e0d977dbb31 | 535 | } |
wardm | 15:2e0d977dbb31 | 536 | break; |
wardm | 15:2e0d977dbb31 | 537 | case MODEM_LORA: |
wardm | 15:2e0d977dbb31 | 538 | { |
wardm | 15:2e0d977dbb31 | 539 | if( this->settings.LoRa.IqInverted == true ) |
wardm | 15:2e0d977dbb31 | 540 | { |
wardm | 15:2e0d977dbb31 | 541 | Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_ON ) ); |
wardm | 15:2e0d977dbb31 | 542 | Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_ON ); |
wardm | 15:2e0d977dbb31 | 543 | } |
wardm | 15:2e0d977dbb31 | 544 | else |
wardm | 15:2e0d977dbb31 | 545 | { |
wardm | 15:2e0d977dbb31 | 546 | Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_OFF ) ); |
wardm | 15:2e0d977dbb31 | 547 | Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_OFF ); |
wardm | 15:2e0d977dbb31 | 548 | } |
wardm | 15:2e0d977dbb31 | 549 | |
wardm | 15:2e0d977dbb31 | 550 | this->settings.LoRaPacketHandler.Size = size; |
wardm | 15:2e0d977dbb31 | 551 | |
wardm | 15:2e0d977dbb31 | 552 | // Initializes the payload size |
wardm | 15:2e0d977dbb31 | 553 | Write( REG_LR_PAYLOADLENGTH, size ); |
wardm | 15:2e0d977dbb31 | 554 | |
wardm | 15:2e0d977dbb31 | 555 | // Full buffer used for Tx |
wardm | 15:2e0d977dbb31 | 556 | Write( REG_LR_FIFOTXBASEADDR, 0 ); |
wardm | 15:2e0d977dbb31 | 557 | Write( REG_LR_FIFOADDRPTR, 0 ); |
wardm | 15:2e0d977dbb31 | 558 | |
wardm | 15:2e0d977dbb31 | 559 | // FIFO operations can not take place in Sleep mode |
wardm | 15:2e0d977dbb31 | 560 | if( ( Read( REG_OPMODE ) & ~RF_OPMODE_MASK ) == RF_OPMODE_SLEEP ) |
wardm | 15:2e0d977dbb31 | 561 | { |
wardm | 15:2e0d977dbb31 | 562 | Standby( ); |
wardm | 15:2e0d977dbb31 | 563 | wait_ms( 1 ); |
wardm | 15:2e0d977dbb31 | 564 | } |
wardm | 15:2e0d977dbb31 | 565 | // Write payload buffer |
wardm | 15:2e0d977dbb31 | 566 | WriteFifo( buffer, size ); |
wardm | 15:2e0d977dbb31 | 567 | txTimeout = this->settings.LoRa.TxTimeout; |
wardm | 15:2e0d977dbb31 | 568 | } |
wardm | 15:2e0d977dbb31 | 569 | break; |
wardm | 15:2e0d977dbb31 | 570 | } |
wardm | 15:2e0d977dbb31 | 571 | |
wardm | 15:2e0d977dbb31 | 572 | Tx( txTimeout ); |
wardm | 15:2e0d977dbb31 | 573 | } |
wardm | 15:2e0d977dbb31 | 574 | |
wardm | 15:2e0d977dbb31 | 575 | void SX1272::Sleep( void ) |
wardm | 15:2e0d977dbb31 | 576 | { |
wardm | 15:2e0d977dbb31 | 577 | txTimeoutTimer.detach( ); |
wardm | 15:2e0d977dbb31 | 578 | rxTimeoutTimer.detach( ); |
wardm | 15:2e0d977dbb31 | 579 | |
wardm | 15:2e0d977dbb31 | 580 | SetOpMode( RF_OPMODE_SLEEP ); |
wardm | 15:2e0d977dbb31 | 581 | this->settings.State = RF_IDLE; |
wardm | 15:2e0d977dbb31 | 582 | } |
wardm | 15:2e0d977dbb31 | 583 | |
wardm | 15:2e0d977dbb31 | 584 | void SX1272::Standby( void ) |
wardm | 15:2e0d977dbb31 | 585 | { |
wardm | 15:2e0d977dbb31 | 586 | txTimeoutTimer.detach( ); |
wardm | 15:2e0d977dbb31 | 587 | rxTimeoutTimer.detach( ); |
wardm | 15:2e0d977dbb31 | 588 | |
wardm | 15:2e0d977dbb31 | 589 | SetOpMode( RF_OPMODE_STANDBY ); |
wardm | 15:2e0d977dbb31 | 590 | this->settings.State = RF_IDLE; |
wardm | 15:2e0d977dbb31 | 591 | } |
wardm | 15:2e0d977dbb31 | 592 | |
wardm | 15:2e0d977dbb31 | 593 | void SX1272::Rx( uint32_t timeout ) |
wardm | 15:2e0d977dbb31 | 594 | { |
wardm | 15:2e0d977dbb31 | 595 | bool rxContinuous = false; |
wardm | 15:2e0d977dbb31 | 596 | |
wardm | 15:2e0d977dbb31 | 597 | switch( this->settings.Modem ) |
wardm | 15:2e0d977dbb31 | 598 | { |
wardm | 15:2e0d977dbb31 | 599 | case MODEM_FSK: |
wardm | 15:2e0d977dbb31 | 600 | { |
wardm | 15:2e0d977dbb31 | 601 | rxContinuous = this->settings.Fsk.RxContinuous; |
wardm | 15:2e0d977dbb31 | 602 | |
wardm | 15:2e0d977dbb31 | 603 | // DIO0=PayloadReady |
wardm | 15:2e0d977dbb31 | 604 | // DIO1=FifoLevel |
wardm | 15:2e0d977dbb31 | 605 | // DIO2=SyncAddr |
wardm | 15:2e0d977dbb31 | 606 | // DIO3=FifoEmpty |
wardm | 15:2e0d977dbb31 | 607 | // DIO4=Preamble |
wardm | 15:2e0d977dbb31 | 608 | // DIO5=ModeReady |
wardm | 15:2e0d977dbb31 | 609 | Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RF_DIOMAPPING1_DIO0_MASK & |
wardm | 15:2e0d977dbb31 | 610 | RF_DIOMAPPING1_DIO1_MASK & |
wardm | 15:2e0d977dbb31 | 611 | RF_DIOMAPPING1_DIO2_MASK ) | |
wardm | 15:2e0d977dbb31 | 612 | RF_DIOMAPPING1_DIO0_00 | |
wardm | 15:2e0d977dbb31 | 613 | RF_DIOMAPPING1_DIO1_00 | |
wardm | 15:2e0d977dbb31 | 614 | RF_DIOMAPPING1_DIO2_11 ); |
wardm | 15:2e0d977dbb31 | 615 | |
wardm | 15:2e0d977dbb31 | 616 | Write( REG_DIOMAPPING2, ( Read( REG_DIOMAPPING2 ) & RF_DIOMAPPING2_DIO4_MASK & |
wardm | 15:2e0d977dbb31 | 617 | RF_DIOMAPPING2_MAP_MASK ) | |
wardm | 15:2e0d977dbb31 | 618 | RF_DIOMAPPING2_DIO4_11 | |
wardm | 15:2e0d977dbb31 | 619 | RF_DIOMAPPING2_MAP_PREAMBLEDETECT ); |
wardm | 15:2e0d977dbb31 | 620 | |
wardm | 15:2e0d977dbb31 | 621 | this->settings.FskPacketHandler.FifoThresh = Read( REG_FIFOTHRESH ) & 0x3F; |
wardm | 15:2e0d977dbb31 | 622 | |
wardm | 15:2e0d977dbb31 | 623 | Write( REG_RXCONFIG, RF_RXCONFIG_AFCAUTO_ON | RF_RXCONFIG_AGCAUTO_ON | RF_RXCONFIG_RXTRIGER_PREAMBLEDETECT ); |
wardm | 15:2e0d977dbb31 | 624 | |
wardm | 15:2e0d977dbb31 | 625 | this->settings.FskPacketHandler.PreambleDetected = false; |
wardm | 15:2e0d977dbb31 | 626 | this->settings.FskPacketHandler.SyncWordDetected = false; |
wardm | 15:2e0d977dbb31 | 627 | this->settings.FskPacketHandler.NbBytes = 0; |
wardm | 15:2e0d977dbb31 | 628 | this->settings.FskPacketHandler.Size = 0; |
wardm | 15:2e0d977dbb31 | 629 | } |
wardm | 15:2e0d977dbb31 | 630 | break; |
wardm | 15:2e0d977dbb31 | 631 | case MODEM_LORA: |
wardm | 15:2e0d977dbb31 | 632 | { |
wardm | 15:2e0d977dbb31 | 633 | if( this->settings.LoRa.IqInverted == true ) |
wardm | 15:2e0d977dbb31 | 634 | { |
wardm | 15:2e0d977dbb31 | 635 | Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_ON | RFLR_INVERTIQ_TX_OFF ) ); |
wardm | 15:2e0d977dbb31 | 636 | Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_ON ); |
wardm | 15:2e0d977dbb31 | 637 | } |
wardm | 15:2e0d977dbb31 | 638 | else |
wardm | 15:2e0d977dbb31 | 639 | { |
wardm | 15:2e0d977dbb31 | 640 | Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_OFF ) ); |
wardm | 15:2e0d977dbb31 | 641 | Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_OFF ); |
wardm | 15:2e0d977dbb31 | 642 | } |
wardm | 15:2e0d977dbb31 | 643 | |
wardm | 15:2e0d977dbb31 | 644 | rxContinuous = this->settings.LoRa.RxContinuous; |
wardm | 15:2e0d977dbb31 | 645 | |
wardm | 15:2e0d977dbb31 | 646 | if( this->settings.LoRa.FreqHopOn == true ) |
wardm | 15:2e0d977dbb31 | 647 | { |
wardm | 15:2e0d977dbb31 | 648 | Write( REG_LR_IRQFLAGSMASK, //RFLR_IRQFLAGS_RXTIMEOUT | |
wardm | 15:2e0d977dbb31 | 649 | //RFLR_IRQFLAGS_RXDONE | |
wardm | 15:2e0d977dbb31 | 650 | //RFLR_IRQFLAGS_PAYLOADCRCERROR | |
wardm | 15:2e0d977dbb31 | 651 | RFLR_IRQFLAGS_VALIDHEADER | |
wardm | 15:2e0d977dbb31 | 652 | RFLR_IRQFLAGS_TXDONE | |
wardm | 15:2e0d977dbb31 | 653 | RFLR_IRQFLAGS_CADDONE | |
wardm | 15:2e0d977dbb31 | 654 | //RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL | |
wardm | 15:2e0d977dbb31 | 655 | RFLR_IRQFLAGS_CADDETECTED ); |
wardm | 15:2e0d977dbb31 | 656 | |
wardm | 15:2e0d977dbb31 | 657 | // DIO0=RxDone, DIO2=FhssChangeChannel |
wardm | 15:2e0d977dbb31 | 658 | Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK & RFLR_DIOMAPPING1_DIO2_MASK ) | RFLR_DIOMAPPING1_DIO0_00 | RFLR_DIOMAPPING1_DIO2_00 ); |
wardm | 15:2e0d977dbb31 | 659 | } |
wardm | 15:2e0d977dbb31 | 660 | else |
wardm | 15:2e0d977dbb31 | 661 | { |
wardm | 15:2e0d977dbb31 | 662 | Write( REG_LR_IRQFLAGSMASK, //RFLR_IRQFLAGS_RXTIMEOUT | |
wardm | 15:2e0d977dbb31 | 663 | //RFLR_IRQFLAGS_RXDONE | |
wardm | 15:2e0d977dbb31 | 664 | //RFLR_IRQFLAGS_PAYLOADCRCERROR | |
wardm | 15:2e0d977dbb31 | 665 | RFLR_IRQFLAGS_VALIDHEADER | |
wardm | 15:2e0d977dbb31 | 666 | RFLR_IRQFLAGS_TXDONE | |
wardm | 15:2e0d977dbb31 | 667 | RFLR_IRQFLAGS_CADDONE | |
wardm | 15:2e0d977dbb31 | 668 | RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL | |
wardm | 15:2e0d977dbb31 | 669 | RFLR_IRQFLAGS_CADDETECTED ); |
wardm | 15:2e0d977dbb31 | 670 | |
wardm | 15:2e0d977dbb31 | 671 | // DIO0=RxDone |
wardm | 15:2e0d977dbb31 | 672 | Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_00 ); |
wardm | 15:2e0d977dbb31 | 673 | } |
wardm | 15:2e0d977dbb31 | 674 | Write( REG_LR_FIFORXBASEADDR, 0 ); |
wardm | 15:2e0d977dbb31 | 675 | Write( REG_LR_FIFOADDRPTR, 0 ); |
wardm | 15:2e0d977dbb31 | 676 | } |
wardm | 15:2e0d977dbb31 | 677 | break; |
wardm | 15:2e0d977dbb31 | 678 | } |
wardm | 15:2e0d977dbb31 | 679 | |
wardm | 15:2e0d977dbb31 | 680 | memset( rxtxBuffer, 0, ( size_t )RX_BUFFER_SIZE ); |
wardm | 15:2e0d977dbb31 | 681 | |
wardm | 15:2e0d977dbb31 | 682 | this->settings.State = RF_RX_RUNNING; |
wardm | 15:2e0d977dbb31 | 683 | if( timeout != 0 ) |
wardm | 15:2e0d977dbb31 | 684 | { |
wardm | 15:2e0d977dbb31 | 685 | rxTimeoutTimer.attach_us( mbed::callback( this, &SX1272::OnTimeoutIrq ), timeout * 1e3 ); |
wardm | 15:2e0d977dbb31 | 686 | } |
wardm | 15:2e0d977dbb31 | 687 | |
wardm | 15:2e0d977dbb31 | 688 | if( this->settings.Modem == MODEM_FSK ) |
wardm | 15:2e0d977dbb31 | 689 | { |
wardm | 15:2e0d977dbb31 | 690 | SetOpMode( RF_OPMODE_RECEIVER ); |
wardm | 15:2e0d977dbb31 | 691 | |
wardm | 15:2e0d977dbb31 | 692 | if( rxContinuous == false ) |
wardm | 15:2e0d977dbb31 | 693 | { |
wardm | 15:2e0d977dbb31 | 694 | rxTimeoutSyncWord.attach_us( mbed::callback( this, &SX1272::OnTimeoutIrq ), |
wardm | 15:2e0d977dbb31 | 695 | this->settings.Fsk.RxSingleTimeout * 1e3 ); |
wardm | 15:2e0d977dbb31 | 696 | } |
wardm | 15:2e0d977dbb31 | 697 | } |
wardm | 15:2e0d977dbb31 | 698 | else |
wardm | 15:2e0d977dbb31 | 699 | { |
wardm | 15:2e0d977dbb31 | 700 | if( rxContinuous == true ) |
wardm | 15:2e0d977dbb31 | 701 | { |
wardm | 15:2e0d977dbb31 | 702 | SetOpMode( RFLR_OPMODE_RECEIVER ); |
wardm | 15:2e0d977dbb31 | 703 | } |
wardm | 15:2e0d977dbb31 | 704 | else |
wardm | 15:2e0d977dbb31 | 705 | { |
wardm | 15:2e0d977dbb31 | 706 | SetOpMode( RFLR_OPMODE_RECEIVER_SINGLE ); |
wardm | 15:2e0d977dbb31 | 707 | } |
wardm | 15:2e0d977dbb31 | 708 | } |
wardm | 15:2e0d977dbb31 | 709 | } |
wardm | 15:2e0d977dbb31 | 710 | |
wardm | 15:2e0d977dbb31 | 711 | void SX1272::Tx( uint32_t timeout ) |
wardm | 15:2e0d977dbb31 | 712 | { |
wardm | 15:2e0d977dbb31 | 713 | |
wardm | 15:2e0d977dbb31 | 714 | switch( this->settings.Modem ) |
wardm | 15:2e0d977dbb31 | 715 | { |
wardm | 15:2e0d977dbb31 | 716 | case MODEM_FSK: |
wardm | 15:2e0d977dbb31 | 717 | { |
wardm | 15:2e0d977dbb31 | 718 | // DIO0=PacketSent |
wardm | 15:2e0d977dbb31 | 719 | // DIO1=FifoEmpty |
wardm | 15:2e0d977dbb31 | 720 | // DIO2=FifoFull |
wardm | 15:2e0d977dbb31 | 721 | // DIO3=FifoEmpty |
wardm | 15:2e0d977dbb31 | 722 | // DIO4=LowBat |
wardm | 15:2e0d977dbb31 | 723 | // DIO5=ModeReady |
wardm | 15:2e0d977dbb31 | 724 | Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RF_DIOMAPPING1_DIO0_MASK & |
wardm | 15:2e0d977dbb31 | 725 | RF_DIOMAPPING1_DIO1_MASK & |
wardm | 15:2e0d977dbb31 | 726 | RF_DIOMAPPING1_DIO2_MASK ) | |
wardm | 15:2e0d977dbb31 | 727 | RF_DIOMAPPING1_DIO1_01 ); |
wardm | 15:2e0d977dbb31 | 728 | |
wardm | 15:2e0d977dbb31 | 729 | Write( REG_DIOMAPPING2, ( Read( REG_DIOMAPPING2 ) & RF_DIOMAPPING2_DIO4_MASK & |
wardm | 15:2e0d977dbb31 | 730 | RF_DIOMAPPING2_MAP_MASK ) ); |
wardm | 15:2e0d977dbb31 | 731 | this->settings.FskPacketHandler.FifoThresh = Read( REG_FIFOTHRESH ) & 0x3F; |
wardm | 15:2e0d977dbb31 | 732 | } |
wardm | 15:2e0d977dbb31 | 733 | break; |
wardm | 15:2e0d977dbb31 | 734 | case MODEM_LORA: |
wardm | 15:2e0d977dbb31 | 735 | { |
wardm | 15:2e0d977dbb31 | 736 | if( this->settings.LoRa.FreqHopOn == true ) |
wardm | 15:2e0d977dbb31 | 737 | { |
wardm | 15:2e0d977dbb31 | 738 | Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT | |
wardm | 15:2e0d977dbb31 | 739 | RFLR_IRQFLAGS_RXDONE | |
wardm | 15:2e0d977dbb31 | 740 | RFLR_IRQFLAGS_PAYLOADCRCERROR | |
wardm | 15:2e0d977dbb31 | 741 | RFLR_IRQFLAGS_VALIDHEADER | |
wardm | 15:2e0d977dbb31 | 742 | //RFLR_IRQFLAGS_TXDONE | |
wardm | 15:2e0d977dbb31 | 743 | RFLR_IRQFLAGS_CADDONE | |
wardm | 15:2e0d977dbb31 | 744 | //RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL | |
wardm | 15:2e0d977dbb31 | 745 | RFLR_IRQFLAGS_CADDETECTED ); |
wardm | 15:2e0d977dbb31 | 746 | |
wardm | 15:2e0d977dbb31 | 747 | // DIO0=TxDone, DIO2=FhssChangeChannel |
wardm | 15:2e0d977dbb31 | 748 | Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK & RFLR_DIOMAPPING1_DIO2_MASK ) | RFLR_DIOMAPPING1_DIO0_01 | RFLR_DIOMAPPING1_DIO2_00 ); |
wardm | 15:2e0d977dbb31 | 749 | } |
wardm | 15:2e0d977dbb31 | 750 | else |
wardm | 15:2e0d977dbb31 | 751 | { |
wardm | 15:2e0d977dbb31 | 752 | Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT | |
wardm | 15:2e0d977dbb31 | 753 | RFLR_IRQFLAGS_RXDONE | |
wardm | 15:2e0d977dbb31 | 754 | RFLR_IRQFLAGS_PAYLOADCRCERROR | |
wardm | 15:2e0d977dbb31 | 755 | RFLR_IRQFLAGS_VALIDHEADER | |
wardm | 15:2e0d977dbb31 | 756 | //RFLR_IRQFLAGS_TXDONE | |
wardm | 15:2e0d977dbb31 | 757 | RFLR_IRQFLAGS_CADDONE | |
wardm | 15:2e0d977dbb31 | 758 | RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL | |
wardm | 15:2e0d977dbb31 | 759 | RFLR_IRQFLAGS_CADDETECTED ); |
wardm | 15:2e0d977dbb31 | 760 | |
wardm | 15:2e0d977dbb31 | 761 | // DIO0=TxDone |
wardm | 15:2e0d977dbb31 | 762 | Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_01 ); |
wardm | 15:2e0d977dbb31 | 763 | } |
wardm | 15:2e0d977dbb31 | 764 | } |
wardm | 15:2e0d977dbb31 | 765 | break; |
wardm | 15:2e0d977dbb31 | 766 | } |
wardm | 15:2e0d977dbb31 | 767 | |
wardm | 15:2e0d977dbb31 | 768 | this->settings.State = RF_TX_RUNNING; |
wardm | 15:2e0d977dbb31 | 769 | txTimeoutTimer.attach_us( mbed::callback( this, &SX1272::OnTimeoutIrq ), timeout * 1e3 ); |
wardm | 15:2e0d977dbb31 | 770 | SetOpMode( RF_OPMODE_TRANSMITTER ); |
wardm | 15:2e0d977dbb31 | 771 | } |
wardm | 15:2e0d977dbb31 | 772 | |
wardm | 15:2e0d977dbb31 | 773 | void SX1272::StartCad( void ) |
wardm | 15:2e0d977dbb31 | 774 | { |
wardm | 15:2e0d977dbb31 | 775 | switch( this->settings.Modem ) |
wardm | 15:2e0d977dbb31 | 776 | { |
wardm | 15:2e0d977dbb31 | 777 | case MODEM_FSK: |
wardm | 15:2e0d977dbb31 | 778 | { |
wardm | 15:2e0d977dbb31 | 779 | |
wardm | 15:2e0d977dbb31 | 780 | } |
wardm | 15:2e0d977dbb31 | 781 | break; |
wardm | 15:2e0d977dbb31 | 782 | case MODEM_LORA: |
wardm | 15:2e0d977dbb31 | 783 | { |
wardm | 15:2e0d977dbb31 | 784 | Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT | |
wardm | 15:2e0d977dbb31 | 785 | RFLR_IRQFLAGS_RXDONE | |
wardm | 15:2e0d977dbb31 | 786 | RFLR_IRQFLAGS_PAYLOADCRCERROR | |
wardm | 15:2e0d977dbb31 | 787 | RFLR_IRQFLAGS_VALIDHEADER | |
wardm | 15:2e0d977dbb31 | 788 | RFLR_IRQFLAGS_TXDONE | |
wardm | 15:2e0d977dbb31 | 789 | //RFLR_IRQFLAGS_CADDONE | |
wardm | 15:2e0d977dbb31 | 790 | RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL // | |
wardm | 15:2e0d977dbb31 | 791 | //RFLR_IRQFLAGS_CADDETECTED |
wardm | 15:2e0d977dbb31 | 792 | ); |
wardm | 15:2e0d977dbb31 | 793 | |
wardm | 15:2e0d977dbb31 | 794 | // DIO3=CADDone |
wardm | 15:2e0d977dbb31 | 795 | Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO3_MASK ) | RFLR_DIOMAPPING1_DIO3_00 ); |
wardm | 15:2e0d977dbb31 | 796 | |
wardm | 15:2e0d977dbb31 | 797 | this->settings.State = RF_CAD; |
wardm | 15:2e0d977dbb31 | 798 | SetOpMode( RFLR_OPMODE_CAD ); |
wardm | 15:2e0d977dbb31 | 799 | } |
wardm | 15:2e0d977dbb31 | 800 | break; |
wardm | 15:2e0d977dbb31 | 801 | default: |
wardm | 15:2e0d977dbb31 | 802 | break; |
wardm | 15:2e0d977dbb31 | 803 | } |
wardm | 15:2e0d977dbb31 | 804 | } |
wardm | 15:2e0d977dbb31 | 805 | |
wardm | 15:2e0d977dbb31 | 806 | void SX1272::SetTxContinuousWave( uint32_t freq, int8_t power, uint16_t time ) |
wardm | 15:2e0d977dbb31 | 807 | { |
wardm | 15:2e0d977dbb31 | 808 | uint32_t timeout = ( uint32_t )( time * 1e6 ); |
wardm | 15:2e0d977dbb31 | 809 | |
wardm | 15:2e0d977dbb31 | 810 | SetChannel( freq ); |
wardm | 15:2e0d977dbb31 | 811 | |
wardm | 15:2e0d977dbb31 | 812 | SetTxConfig( MODEM_FSK, power, 0, 0, 4800, 0, 5, false, false, 0, 0, 0, timeout ); |
wardm | 15:2e0d977dbb31 | 813 | |
wardm | 15:2e0d977dbb31 | 814 | Write( REG_PACKETCONFIG2, ( Read( REG_PACKETCONFIG2 ) & RF_PACKETCONFIG2_DATAMODE_MASK ) ); |
wardm | 15:2e0d977dbb31 | 815 | // Disable radio interrupts |
wardm | 15:2e0d977dbb31 | 816 | Write( REG_DIOMAPPING1, RF_DIOMAPPING1_DIO0_11 | RF_DIOMAPPING1_DIO1_11 ); |
wardm | 15:2e0d977dbb31 | 817 | Write( REG_DIOMAPPING2, RF_DIOMAPPING2_DIO4_10 | RF_DIOMAPPING2_DIO5_10 ); |
wardm | 15:2e0d977dbb31 | 818 | |
wardm | 15:2e0d977dbb31 | 819 | this->settings.State = RF_TX_RUNNING; |
wardm | 15:2e0d977dbb31 | 820 | txTimeoutTimer.attach_us( mbed::callback( this, &SX1272::OnTimeoutIrq ), timeout ); |
wardm | 15:2e0d977dbb31 | 821 | SetOpMode( RF_OPMODE_TRANSMITTER ); |
wardm | 15:2e0d977dbb31 | 822 | } |
wardm | 15:2e0d977dbb31 | 823 | |
wardm | 15:2e0d977dbb31 | 824 | int16_t SX1272::GetRssi( RadioModems_t modem ) |
wardm | 15:2e0d977dbb31 | 825 | { |
wardm | 15:2e0d977dbb31 | 826 | int16_t rssi = 0; |
wardm | 15:2e0d977dbb31 | 827 | |
wardm | 15:2e0d977dbb31 | 828 | switch( modem ) |
wardm | 15:2e0d977dbb31 | 829 | { |
wardm | 15:2e0d977dbb31 | 830 | case MODEM_FSK: |
wardm | 15:2e0d977dbb31 | 831 | rssi = -( Read( REG_RSSIVALUE ) >> 1 ); |
wardm | 15:2e0d977dbb31 | 832 | break; |
wardm | 15:2e0d977dbb31 | 833 | case MODEM_LORA: |
wardm | 15:2e0d977dbb31 | 834 | rssi = RSSI_OFFSET + Read( REG_LR_RSSIVALUE ); |
wardm | 15:2e0d977dbb31 | 835 | break; |
wardm | 15:2e0d977dbb31 | 836 | default: |
wardm | 15:2e0d977dbb31 | 837 | rssi = -1; |
wardm | 15:2e0d977dbb31 | 838 | break; |
wardm | 15:2e0d977dbb31 | 839 | } |
wardm | 15:2e0d977dbb31 | 840 | return rssi; |
wardm | 15:2e0d977dbb31 | 841 | } |
wardm | 15:2e0d977dbb31 | 842 | |
wardm | 15:2e0d977dbb31 | 843 | void SX1272::SetOpMode( uint8_t opMode ) |
wardm | 15:2e0d977dbb31 | 844 | { |
wardm | 15:2e0d977dbb31 | 845 | if( opMode == RF_OPMODE_SLEEP ) |
wardm | 15:2e0d977dbb31 | 846 | { |
wardm | 15:2e0d977dbb31 | 847 | SetAntSwLowPower( true ); |
wardm | 15:2e0d977dbb31 | 848 | } |
wardm | 15:2e0d977dbb31 | 849 | else |
wardm | 15:2e0d977dbb31 | 850 | { |
wardm | 15:2e0d977dbb31 | 851 | SetAntSwLowPower( false ); |
wardm | 15:2e0d977dbb31 | 852 | SetAntSw( opMode ); |
wardm | 15:2e0d977dbb31 | 853 | } |
wardm | 15:2e0d977dbb31 | 854 | Write( REG_OPMODE, ( Read( REG_OPMODE ) & RF_OPMODE_MASK ) | opMode ); |
wardm | 15:2e0d977dbb31 | 855 | } |
wardm | 15:2e0d977dbb31 | 856 | |
wardm | 15:2e0d977dbb31 | 857 | void SX1272::SetModem( RadioModems_t modem ) |
wardm | 15:2e0d977dbb31 | 858 | { |
wardm | 15:2e0d977dbb31 | 859 | if( ( Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_ON ) != 0 ) |
wardm | 15:2e0d977dbb31 | 860 | { |
wardm | 15:2e0d977dbb31 | 861 | this->settings.Modem = MODEM_LORA; |
wardm | 15:2e0d977dbb31 | 862 | } |
wardm | 15:2e0d977dbb31 | 863 | else |
wardm | 15:2e0d977dbb31 | 864 | { |
wardm | 15:2e0d977dbb31 | 865 | this->settings.Modem = MODEM_FSK; |
wardm | 15:2e0d977dbb31 | 866 | } |
wardm | 15:2e0d977dbb31 | 867 | |
wardm | 15:2e0d977dbb31 | 868 | if( this->settings.Modem == modem ) |
wardm | 15:2e0d977dbb31 | 869 | { |
wardm | 15:2e0d977dbb31 | 870 | return; |
wardm | 15:2e0d977dbb31 | 871 | } |
wardm | 15:2e0d977dbb31 | 872 | |
wardm | 15:2e0d977dbb31 | 873 | this->settings.Modem = modem; |
wardm | 15:2e0d977dbb31 | 874 | switch( this->settings.Modem ) |
wardm | 15:2e0d977dbb31 | 875 | { |
wardm | 15:2e0d977dbb31 | 876 | default: |
wardm | 15:2e0d977dbb31 | 877 | case MODEM_FSK: |
wardm | 15:2e0d977dbb31 | 878 | Sleep( ); |
wardm | 15:2e0d977dbb31 | 879 | Write( REG_OPMODE, ( Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RFLR_OPMODE_LONGRANGEMODE_OFF ); |
wardm | 15:2e0d977dbb31 | 880 | |
wardm | 15:2e0d977dbb31 | 881 | Write( REG_DIOMAPPING1, 0x00 ); |
wardm | 15:2e0d977dbb31 | 882 | Write( REG_DIOMAPPING2, 0x30 ); // DIO5=ModeReady |
wardm | 15:2e0d977dbb31 | 883 | break; |
wardm | 15:2e0d977dbb31 | 884 | case MODEM_LORA: |
wardm | 15:2e0d977dbb31 | 885 | Sleep( ); |
wardm | 15:2e0d977dbb31 | 886 | Write( REG_OPMODE, ( Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RFLR_OPMODE_LONGRANGEMODE_ON ); |
wardm | 15:2e0d977dbb31 | 887 | |
wardm | 15:2e0d977dbb31 | 888 | Write( REG_DIOMAPPING1, 0x00 ); |
wardm | 15:2e0d977dbb31 | 889 | Write( REG_DIOMAPPING2, 0x00 ); |
wardm | 15:2e0d977dbb31 | 890 | break; |
wardm | 15:2e0d977dbb31 | 891 | } |
wardm | 15:2e0d977dbb31 | 892 | } |
wardm | 15:2e0d977dbb31 | 893 | |
wardm | 15:2e0d977dbb31 | 894 | void SX1272::SetMaxPayloadLength( RadioModems_t modem, uint8_t max ) |
wardm | 15:2e0d977dbb31 | 895 | { |
wardm | 15:2e0d977dbb31 | 896 | this->SetModem( modem ); |
wardm | 15:2e0d977dbb31 | 897 | |
wardm | 15:2e0d977dbb31 | 898 | switch( modem ) |
wardm | 15:2e0d977dbb31 | 899 | { |
wardm | 15:2e0d977dbb31 | 900 | case MODEM_FSK: |
wardm | 15:2e0d977dbb31 | 901 | if( this->settings.Fsk.FixLen == false ) |
wardm | 15:2e0d977dbb31 | 902 | { |
wardm | 15:2e0d977dbb31 | 903 | this->Write( REG_PAYLOADLENGTH, max ); |
wardm | 15:2e0d977dbb31 | 904 | } |
wardm | 15:2e0d977dbb31 | 905 | break; |
wardm | 15:2e0d977dbb31 | 906 | case MODEM_LORA: |
wardm | 15:2e0d977dbb31 | 907 | this->Write( REG_LR_PAYLOADMAXLENGTH, max ); |
wardm | 15:2e0d977dbb31 | 908 | break; |
wardm | 15:2e0d977dbb31 | 909 | } |
wardm | 15:2e0d977dbb31 | 910 | } |
wardm | 15:2e0d977dbb31 | 911 | |
wardm | 15:2e0d977dbb31 | 912 | void SX1272::SetPublicNetwork( bool enable ) |
wardm | 15:2e0d977dbb31 | 913 | { |
wardm | 15:2e0d977dbb31 | 914 | SetModem( MODEM_LORA ); |
wardm | 15:2e0d977dbb31 | 915 | this->settings.LoRa.PublicNetwork = enable; |
wardm | 15:2e0d977dbb31 | 916 | if( enable == true ) |
wardm | 15:2e0d977dbb31 | 917 | { |
wardm | 15:2e0d977dbb31 | 918 | // Change LoRa modem SyncWord |
wardm | 15:2e0d977dbb31 | 919 | Write( REG_LR_SYNCWORD, LORA_MAC_PUBLIC_SYNCWORD ); |
wardm | 15:2e0d977dbb31 | 920 | } |
wardm | 15:2e0d977dbb31 | 921 | else |
wardm | 15:2e0d977dbb31 | 922 | { |
wardm | 15:2e0d977dbb31 | 923 | // Change LoRa modem SyncWord |
wardm | 15:2e0d977dbb31 | 924 | Write( REG_LR_SYNCWORD, LORA_MAC_PRIVATE_SYNCWORD ); |
wardm | 15:2e0d977dbb31 | 925 | } |
wardm | 15:2e0d977dbb31 | 926 | } |
wardm | 15:2e0d977dbb31 | 927 | |
wardm | 15:2e0d977dbb31 | 928 | void SX1272::OnTimeoutIrq( void ) |
wardm | 15:2e0d977dbb31 | 929 | { |
wardm | 15:2e0d977dbb31 | 930 | switch( this->settings.State ) |
wardm | 15:2e0d977dbb31 | 931 | { |
wardm | 15:2e0d977dbb31 | 932 | case RF_RX_RUNNING: |
wardm | 15:2e0d977dbb31 | 933 | if( this->settings.Modem == MODEM_FSK ) |
wardm | 15:2e0d977dbb31 | 934 | { |
wardm | 15:2e0d977dbb31 | 935 | this->settings.FskPacketHandler.PreambleDetected = false; |
wardm | 15:2e0d977dbb31 | 936 | this->settings.FskPacketHandler.SyncWordDetected = false; |
wardm | 15:2e0d977dbb31 | 937 | this->settings.FskPacketHandler.NbBytes = 0; |
wardm | 15:2e0d977dbb31 | 938 | this->settings.FskPacketHandler.Size = 0; |
wardm | 15:2e0d977dbb31 | 939 | |
wardm | 15:2e0d977dbb31 | 940 | // Clear Irqs |
wardm | 15:2e0d977dbb31 | 941 | Write( REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI | |
wardm | 15:2e0d977dbb31 | 942 | RF_IRQFLAGS1_PREAMBLEDETECT | |
wardm | 15:2e0d977dbb31 | 943 | RF_IRQFLAGS1_SYNCADDRESSMATCH ); |
wardm | 15:2e0d977dbb31 | 944 | Write( REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN ); |
wardm | 15:2e0d977dbb31 | 945 | |
wardm | 15:2e0d977dbb31 | 946 | if( this->settings.Fsk.RxContinuous == true ) |
wardm | 15:2e0d977dbb31 | 947 | { |
wardm | 15:2e0d977dbb31 | 948 | // Continuous mode restart Rx chain |
wardm | 15:2e0d977dbb31 | 949 | Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK ); |
wardm | 15:2e0d977dbb31 | 950 | rxTimeoutSyncWord.attach_us( mbed::callback( this, &SX1272::OnTimeoutIrq ), |
wardm | 15:2e0d977dbb31 | 951 | this->settings.Fsk.RxSingleTimeout * 1e3 ); |
wardm | 15:2e0d977dbb31 | 952 | } |
wardm | 15:2e0d977dbb31 | 953 | else |
wardm | 15:2e0d977dbb31 | 954 | { |
wardm | 15:2e0d977dbb31 | 955 | this->settings.State = RF_IDLE; |
wardm | 15:2e0d977dbb31 | 956 | rxTimeoutSyncWord.detach( ); |
wardm | 15:2e0d977dbb31 | 957 | } |
wardm | 15:2e0d977dbb31 | 958 | } |
wardm | 15:2e0d977dbb31 | 959 | if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxTimeout != NULL ) ) |
wardm | 15:2e0d977dbb31 | 960 | { |
wardm | 15:2e0d977dbb31 | 961 | this->RadioEvents->RxTimeout( ); |
wardm | 15:2e0d977dbb31 | 962 | } |
wardm | 15:2e0d977dbb31 | 963 | break; |
wardm | 15:2e0d977dbb31 | 964 | case RF_TX_RUNNING: |
wardm | 15:2e0d977dbb31 | 965 | // Tx timeout shouldn't happen. |
wardm | 15:2e0d977dbb31 | 966 | // But it has been observed that when it happens it is a result of a corrupted SPI transfer |
wardm | 15:2e0d977dbb31 | 967 | // it depends on the platform design. |
wardm | 15:2e0d977dbb31 | 968 | // |
wardm | 15:2e0d977dbb31 | 969 | // The workaround is to put the radio in a known state. Thus, we re-initialize it. |
wardm | 15:2e0d977dbb31 | 970 | |
wardm | 15:2e0d977dbb31 | 971 | // BEGIN WORKAROUND |
wardm | 15:2e0d977dbb31 | 972 | |
wardm | 15:2e0d977dbb31 | 973 | // Reset the radio |
wardm | 15:2e0d977dbb31 | 974 | Reset( ); |
wardm | 15:2e0d977dbb31 | 975 | |
wardm | 15:2e0d977dbb31 | 976 | // Initialize radio default values |
wardm | 15:2e0d977dbb31 | 977 | SetOpMode( RF_OPMODE_SLEEP ); |
wardm | 15:2e0d977dbb31 | 978 | |
wardm | 15:2e0d977dbb31 | 979 | RadioRegistersInit( ); |
wardm | 15:2e0d977dbb31 | 980 | |
wardm | 15:2e0d977dbb31 | 981 | SetModem( MODEM_FSK ); |
wardm | 15:2e0d977dbb31 | 982 | |
wardm | 15:2e0d977dbb31 | 983 | // Restore previous network type setting. |
wardm | 15:2e0d977dbb31 | 984 | SetPublicNetwork( this->settings.LoRa.PublicNetwork ); |
wardm | 15:2e0d977dbb31 | 985 | // END WORKAROUND |
wardm | 15:2e0d977dbb31 | 986 | |
wardm | 15:2e0d977dbb31 | 987 | this->settings.State = RF_IDLE; |
wardm | 15:2e0d977dbb31 | 988 | if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->TxTimeout != NULL ) ) |
wardm | 15:2e0d977dbb31 | 989 | { |
wardm | 15:2e0d977dbb31 | 990 | this->RadioEvents->TxTimeout( ); |
wardm | 15:2e0d977dbb31 | 991 | } |
wardm | 15:2e0d977dbb31 | 992 | break; |
wardm | 15:2e0d977dbb31 | 993 | default: |
wardm | 15:2e0d977dbb31 | 994 | break; |
wardm | 15:2e0d977dbb31 | 995 | } |
wardm | 15:2e0d977dbb31 | 996 | } |
wardm | 15:2e0d977dbb31 | 997 | |
wardm | 15:2e0d977dbb31 | 998 | void SX1272::OnDio0Irq( void ) |
wardm | 15:2e0d977dbb31 | 999 | { |
wardm | 15:2e0d977dbb31 | 1000 | volatile uint8_t irqFlags = 0; |
wardm | 15:2e0d977dbb31 | 1001 | |
wardm | 15:2e0d977dbb31 | 1002 | switch( this->settings.State ) |
wardm | 15:2e0d977dbb31 | 1003 | { |
wardm | 15:2e0d977dbb31 | 1004 | case RF_RX_RUNNING: |
wardm | 15:2e0d977dbb31 | 1005 | //TimerStop( &RxTimeoutTimer ); |
wardm | 15:2e0d977dbb31 | 1006 | // RxDone interrupt |
wardm | 15:2e0d977dbb31 | 1007 | switch( this->settings.Modem ) |
wardm | 15:2e0d977dbb31 | 1008 | { |
wardm | 15:2e0d977dbb31 | 1009 | case MODEM_FSK: |
wardm | 15:2e0d977dbb31 | 1010 | if( this->settings.Fsk.CrcOn == true ) |
wardm | 15:2e0d977dbb31 | 1011 | { |
wardm | 15:2e0d977dbb31 | 1012 | irqFlags = Read( REG_IRQFLAGS2 ); |
wardm | 15:2e0d977dbb31 | 1013 | if( ( irqFlags & RF_IRQFLAGS2_CRCOK ) != RF_IRQFLAGS2_CRCOK ) |
wardm | 15:2e0d977dbb31 | 1014 | { |
wardm | 15:2e0d977dbb31 | 1015 | // Clear Irqs |
wardm | 15:2e0d977dbb31 | 1016 | Write( REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI | |
wardm | 15:2e0d977dbb31 | 1017 | RF_IRQFLAGS1_PREAMBLEDETECT | |
wardm | 15:2e0d977dbb31 | 1018 | RF_IRQFLAGS1_SYNCADDRESSMATCH ); |
wardm | 15:2e0d977dbb31 | 1019 | Write( REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN ); |
wardm | 15:2e0d977dbb31 | 1020 | |
wardm | 15:2e0d977dbb31 | 1021 | rxTimeoutTimer.detach( ); |
wardm | 15:2e0d977dbb31 | 1022 | |
wardm | 15:2e0d977dbb31 | 1023 | if( this->settings.Fsk.RxContinuous == false ) |
wardm | 15:2e0d977dbb31 | 1024 | { |
wardm | 15:2e0d977dbb31 | 1025 | rxTimeoutSyncWord.detach( ); |
wardm | 15:2e0d977dbb31 | 1026 | this->settings.State = RF_IDLE; |
wardm | 15:2e0d977dbb31 | 1027 | } |
wardm | 15:2e0d977dbb31 | 1028 | else |
wardm | 15:2e0d977dbb31 | 1029 | { |
wardm | 15:2e0d977dbb31 | 1030 | // Continuous mode restart Rx chain |
wardm | 15:2e0d977dbb31 | 1031 | Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK ); |
wardm | 15:2e0d977dbb31 | 1032 | rxTimeoutSyncWord.attach_us( mbed::callback( this, &SX1272::OnTimeoutIrq ), |
wardm | 15:2e0d977dbb31 | 1033 | this->settings.Fsk.RxSingleTimeout * 1e3 ); |
wardm | 15:2e0d977dbb31 | 1034 | } |
wardm | 15:2e0d977dbb31 | 1035 | |
wardm | 15:2e0d977dbb31 | 1036 | if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxError != NULL ) ) |
wardm | 15:2e0d977dbb31 | 1037 | { |
wardm | 15:2e0d977dbb31 | 1038 | this->RadioEvents->RxError( ); |
wardm | 15:2e0d977dbb31 | 1039 | } |
wardm | 15:2e0d977dbb31 | 1040 | this->settings.FskPacketHandler.PreambleDetected = false; |
wardm | 15:2e0d977dbb31 | 1041 | this->settings.FskPacketHandler.SyncWordDetected = false; |
wardm | 15:2e0d977dbb31 | 1042 | this->settings.FskPacketHandler.NbBytes = 0; |
wardm | 15:2e0d977dbb31 | 1043 | this->settings.FskPacketHandler.Size = 0; |
wardm | 15:2e0d977dbb31 | 1044 | break; |
wardm | 15:2e0d977dbb31 | 1045 | } |
wardm | 15:2e0d977dbb31 | 1046 | } |
wardm | 15:2e0d977dbb31 | 1047 | |
wardm | 15:2e0d977dbb31 | 1048 | // Read received packet size |
wardm | 15:2e0d977dbb31 | 1049 | if( ( this->settings.FskPacketHandler.Size == 0 ) && ( this->settings.FskPacketHandler.NbBytes == 0 ) ) |
wardm | 15:2e0d977dbb31 | 1050 | { |
wardm | 15:2e0d977dbb31 | 1051 | if( this->settings.Fsk.FixLen == false ) |
wardm | 15:2e0d977dbb31 | 1052 | { |
wardm | 15:2e0d977dbb31 | 1053 | ReadFifo( ( uint8_t* )&this->settings.FskPacketHandler.Size, 1 ); |
wardm | 15:2e0d977dbb31 | 1054 | } |
wardm | 15:2e0d977dbb31 | 1055 | else |
wardm | 15:2e0d977dbb31 | 1056 | { |
wardm | 15:2e0d977dbb31 | 1057 | this->settings.FskPacketHandler.Size = Read( REG_PAYLOADLENGTH ); |
wardm | 15:2e0d977dbb31 | 1058 | } |
wardm | 15:2e0d977dbb31 | 1059 | ReadFifo( rxtxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ); |
wardm | 15:2e0d977dbb31 | 1060 | this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ); |
wardm | 15:2e0d977dbb31 | 1061 | } |
wardm | 15:2e0d977dbb31 | 1062 | else |
wardm | 15:2e0d977dbb31 | 1063 | { |
wardm | 15:2e0d977dbb31 | 1064 | ReadFifo( rxtxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ); |
wardm | 15:2e0d977dbb31 | 1065 | this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ); |
wardm | 15:2e0d977dbb31 | 1066 | } |
wardm | 15:2e0d977dbb31 | 1067 | |
wardm | 15:2e0d977dbb31 | 1068 | rxTimeoutTimer.detach( ); |
wardm | 15:2e0d977dbb31 | 1069 | |
wardm | 15:2e0d977dbb31 | 1070 | if( this->settings.Fsk.RxContinuous == false ) |
wardm | 15:2e0d977dbb31 | 1071 | { |
wardm | 15:2e0d977dbb31 | 1072 | this->settings.State = RF_IDLE; |
wardm | 15:2e0d977dbb31 | 1073 | rxTimeoutSyncWord.detach( ); |
wardm | 15:2e0d977dbb31 | 1074 | } |
wardm | 15:2e0d977dbb31 | 1075 | else |
wardm | 15:2e0d977dbb31 | 1076 | { |
wardm | 15:2e0d977dbb31 | 1077 | // Continuous mode restart Rx chain |
wardm | 15:2e0d977dbb31 | 1078 | Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK ); |
wardm | 15:2e0d977dbb31 | 1079 | rxTimeoutSyncWord.attach_us( mbed::callback( this, &SX1272::OnTimeoutIrq ), |
wardm | 15:2e0d977dbb31 | 1080 | this->settings.Fsk.RxSingleTimeout * 1e3 ); |
wardm | 15:2e0d977dbb31 | 1081 | } |
wardm | 15:2e0d977dbb31 | 1082 | |
wardm | 15:2e0d977dbb31 | 1083 | if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxDone != NULL ) ) |
wardm | 15:2e0d977dbb31 | 1084 | { |
wardm | 15:2e0d977dbb31 | 1085 | this->RadioEvents->RxDone( rxtxBuffer, this->settings.FskPacketHandler.Size, this->settings.FskPacketHandler.RssiValue, 0 ); |
wardm | 15:2e0d977dbb31 | 1086 | } |
wardm | 15:2e0d977dbb31 | 1087 | this->settings.FskPacketHandler.PreambleDetected = false; |
wardm | 15:2e0d977dbb31 | 1088 | this->settings.FskPacketHandler.SyncWordDetected = false; |
wardm | 15:2e0d977dbb31 | 1089 | this->settings.FskPacketHandler.NbBytes = 0; |
wardm | 15:2e0d977dbb31 | 1090 | this->settings.FskPacketHandler.Size = 0; |
wardm | 15:2e0d977dbb31 | 1091 | break; |
wardm | 15:2e0d977dbb31 | 1092 | case MODEM_LORA: |
wardm | 15:2e0d977dbb31 | 1093 | { |
wardm | 15:2e0d977dbb31 | 1094 | int8_t snr = 0; |
wardm | 15:2e0d977dbb31 | 1095 | |
wardm | 15:2e0d977dbb31 | 1096 | // Clear Irq |
wardm | 15:2e0d977dbb31 | 1097 | Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_RXDONE ); |
wardm | 15:2e0d977dbb31 | 1098 | |
wardm | 15:2e0d977dbb31 | 1099 | irqFlags = Read( REG_LR_IRQFLAGS ); |
wardm | 15:2e0d977dbb31 | 1100 | if( ( irqFlags & RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK ) == RFLR_IRQFLAGS_PAYLOADCRCERROR ) |
wardm | 15:2e0d977dbb31 | 1101 | { |
wardm | 15:2e0d977dbb31 | 1102 | // Clear Irq |
wardm | 15:2e0d977dbb31 | 1103 | Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_PAYLOADCRCERROR ); |
wardm | 15:2e0d977dbb31 | 1104 | |
wardm | 15:2e0d977dbb31 | 1105 | if( this->settings.LoRa.RxContinuous == false ) |
wardm | 15:2e0d977dbb31 | 1106 | { |
wardm | 15:2e0d977dbb31 | 1107 | this->settings.State = RF_IDLE; |
wardm | 15:2e0d977dbb31 | 1108 | } |
wardm | 15:2e0d977dbb31 | 1109 | rxTimeoutTimer.detach( ); |
wardm | 15:2e0d977dbb31 | 1110 | |
wardm | 15:2e0d977dbb31 | 1111 | if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxError != NULL ) ) |
wardm | 15:2e0d977dbb31 | 1112 | { |
wardm | 15:2e0d977dbb31 | 1113 | this->RadioEvents->RxError( ); |
wardm | 15:2e0d977dbb31 | 1114 | } |
wardm | 15:2e0d977dbb31 | 1115 | break; |
wardm | 15:2e0d977dbb31 | 1116 | } |
wardm | 15:2e0d977dbb31 | 1117 | |
wardm | 15:2e0d977dbb31 | 1118 | this->settings.LoRaPacketHandler.SnrValue = Read( REG_LR_PKTSNRVALUE ); |
wardm | 15:2e0d977dbb31 | 1119 | if( this->settings.LoRaPacketHandler.SnrValue & 0x80 ) // The SNR sign bit is 1 |
wardm | 15:2e0d977dbb31 | 1120 | { |
wardm | 15:2e0d977dbb31 | 1121 | // Invert and divide by 4 |
wardm | 15:2e0d977dbb31 | 1122 | snr = ( ( ~this->settings.LoRaPacketHandler.SnrValue + 1 ) & 0xFF ) >> 2; |
wardm | 15:2e0d977dbb31 | 1123 | snr = -snr; |
wardm | 15:2e0d977dbb31 | 1124 | } |
wardm | 15:2e0d977dbb31 | 1125 | else |
wardm | 15:2e0d977dbb31 | 1126 | { |
wardm | 15:2e0d977dbb31 | 1127 | // Divide by 4 |
wardm | 15:2e0d977dbb31 | 1128 | snr = ( this->settings.LoRaPacketHandler.SnrValue & 0xFF ) >> 2; |
wardm | 15:2e0d977dbb31 | 1129 | } |
wardm | 15:2e0d977dbb31 | 1130 | |
wardm | 15:2e0d977dbb31 | 1131 | int16_t rssi = Read( REG_LR_PKTRSSIVALUE ); |
wardm | 15:2e0d977dbb31 | 1132 | if( snr < 0 ) |
wardm | 15:2e0d977dbb31 | 1133 | { |
wardm | 15:2e0d977dbb31 | 1134 | this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET + rssi + ( rssi >> 4 ) + |
wardm | 15:2e0d977dbb31 | 1135 | snr; |
wardm | 15:2e0d977dbb31 | 1136 | } |
wardm | 15:2e0d977dbb31 | 1137 | else |
wardm | 15:2e0d977dbb31 | 1138 | { |
wardm | 15:2e0d977dbb31 | 1139 | this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET + rssi + ( rssi >> 4 ); |
wardm | 15:2e0d977dbb31 | 1140 | } |
wardm | 15:2e0d977dbb31 | 1141 | |
wardm | 15:2e0d977dbb31 | 1142 | this->settings.LoRaPacketHandler.Size = Read( REG_LR_RXNBBYTES ); |
wardm | 15:2e0d977dbb31 | 1143 | ReadFifo( rxtxBuffer, this->settings.LoRaPacketHandler.Size ); |
wardm | 15:2e0d977dbb31 | 1144 | |
wardm | 15:2e0d977dbb31 | 1145 | if( this->settings.LoRa.RxContinuous == false ) |
wardm | 15:2e0d977dbb31 | 1146 | { |
wardm | 15:2e0d977dbb31 | 1147 | this->settings.State = RF_IDLE; |
wardm | 15:2e0d977dbb31 | 1148 | } |
wardm | 15:2e0d977dbb31 | 1149 | rxTimeoutTimer.detach( ); |
wardm | 15:2e0d977dbb31 | 1150 | |
wardm | 15:2e0d977dbb31 | 1151 | if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxDone != NULL ) ) |
wardm | 15:2e0d977dbb31 | 1152 | { |
wardm | 15:2e0d977dbb31 | 1153 | this->RadioEvents->RxDone( rxtxBuffer, this->settings.LoRaPacketHandler.Size, this->settings.LoRaPacketHandler.RssiValue, this->settings.LoRaPacketHandler.SnrValue ); |
wardm | 15:2e0d977dbb31 | 1154 | } |
wardm | 15:2e0d977dbb31 | 1155 | } |
wardm | 15:2e0d977dbb31 | 1156 | break; |
wardm | 15:2e0d977dbb31 | 1157 | default: |
wardm | 15:2e0d977dbb31 | 1158 | break; |
wardm | 15:2e0d977dbb31 | 1159 | } |
wardm | 15:2e0d977dbb31 | 1160 | break; |
wardm | 15:2e0d977dbb31 | 1161 | case RF_TX_RUNNING: |
wardm | 15:2e0d977dbb31 | 1162 | txTimeoutTimer.detach( ); |
wardm | 15:2e0d977dbb31 | 1163 | // TxDone interrupt |
wardm | 15:2e0d977dbb31 | 1164 | switch( this->settings.Modem ) |
wardm | 15:2e0d977dbb31 | 1165 | { |
wardm | 15:2e0d977dbb31 | 1166 | case MODEM_LORA: |
wardm | 15:2e0d977dbb31 | 1167 | // Clear Irq |
wardm | 15:2e0d977dbb31 | 1168 | Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_TXDONE ); |
wardm | 15:2e0d977dbb31 | 1169 | // Intentional fall through |
wardm | 15:2e0d977dbb31 | 1170 | case MODEM_FSK: |
wardm | 15:2e0d977dbb31 | 1171 | default: |
wardm | 15:2e0d977dbb31 | 1172 | this->settings.State = RF_IDLE; |
wardm | 15:2e0d977dbb31 | 1173 | if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->TxDone != NULL ) ) |
wardm | 15:2e0d977dbb31 | 1174 | { |
wardm | 15:2e0d977dbb31 | 1175 | this->RadioEvents->TxDone( ); |
wardm | 15:2e0d977dbb31 | 1176 | } |
wardm | 15:2e0d977dbb31 | 1177 | break; |
wardm | 15:2e0d977dbb31 | 1178 | } |
wardm | 15:2e0d977dbb31 | 1179 | break; |
wardm | 15:2e0d977dbb31 | 1180 | default: |
wardm | 15:2e0d977dbb31 | 1181 | break; |
wardm | 15:2e0d977dbb31 | 1182 | } |
wardm | 15:2e0d977dbb31 | 1183 | } |
wardm | 15:2e0d977dbb31 | 1184 | |
wardm | 15:2e0d977dbb31 | 1185 | void SX1272::OnDio1Irq( void ) |
wardm | 15:2e0d977dbb31 | 1186 | { |
wardm | 15:2e0d977dbb31 | 1187 | switch( this->settings.State ) |
wardm | 15:2e0d977dbb31 | 1188 | { |
wardm | 15:2e0d977dbb31 | 1189 | case RF_RX_RUNNING: |
wardm | 15:2e0d977dbb31 | 1190 | switch( this->settings.Modem ) |
wardm | 15:2e0d977dbb31 | 1191 | { |
wardm | 15:2e0d977dbb31 | 1192 | case MODEM_FSK: |
wardm | 15:2e0d977dbb31 | 1193 | // FifoLevel interrupt |
wardm | 15:2e0d977dbb31 | 1194 | // Read received packet size |
wardm | 15:2e0d977dbb31 | 1195 | if( ( this->settings.FskPacketHandler.Size == 0 ) && ( this->settings.FskPacketHandler.NbBytes == 0 ) ) |
wardm | 15:2e0d977dbb31 | 1196 | { |
wardm | 15:2e0d977dbb31 | 1197 | if( this->settings.Fsk.FixLen == false ) |
wardm | 15:2e0d977dbb31 | 1198 | { |
wardm | 15:2e0d977dbb31 | 1199 | ReadFifo( ( uint8_t* )&this->settings.FskPacketHandler.Size, 1 ); |
wardm | 15:2e0d977dbb31 | 1200 | } |
wardm | 15:2e0d977dbb31 | 1201 | else |
wardm | 15:2e0d977dbb31 | 1202 | { |
wardm | 15:2e0d977dbb31 | 1203 | this->settings.FskPacketHandler.Size = Read( REG_PAYLOADLENGTH ); |
wardm | 15:2e0d977dbb31 | 1204 | } |
wardm | 15:2e0d977dbb31 | 1205 | } |
wardm | 15:2e0d977dbb31 | 1206 | |
wardm | 15:2e0d977dbb31 | 1207 | if( ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ) > this->settings.FskPacketHandler.FifoThresh ) |
wardm | 15:2e0d977dbb31 | 1208 | { |
wardm | 15:2e0d977dbb31 | 1209 | ReadFifo( ( rxtxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.FifoThresh ); |
wardm | 15:2e0d977dbb31 | 1210 | this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.FifoThresh; |
wardm | 15:2e0d977dbb31 | 1211 | } |
wardm | 15:2e0d977dbb31 | 1212 | else |
wardm | 15:2e0d977dbb31 | 1213 | { |
wardm | 15:2e0d977dbb31 | 1214 | ReadFifo( ( rxtxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ); |
wardm | 15:2e0d977dbb31 | 1215 | this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ); |
wardm | 15:2e0d977dbb31 | 1216 | } |
wardm | 15:2e0d977dbb31 | 1217 | break; |
wardm | 15:2e0d977dbb31 | 1218 | case MODEM_LORA: |
wardm | 15:2e0d977dbb31 | 1219 | // Sync time out |
wardm | 15:2e0d977dbb31 | 1220 | rxTimeoutTimer.detach( ); |
wardm | 15:2e0d977dbb31 | 1221 | // Clear Irq |
wardm | 15:2e0d977dbb31 | 1222 | Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_RXTIMEOUT ); |
wardm | 15:2e0d977dbb31 | 1223 | |
wardm | 15:2e0d977dbb31 | 1224 | this->settings.State = RF_IDLE; |
wardm | 15:2e0d977dbb31 | 1225 | if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxTimeout != NULL ) ) |
wardm | 15:2e0d977dbb31 | 1226 | { |
wardm | 15:2e0d977dbb31 | 1227 | this->RadioEvents->RxTimeout( ); |
wardm | 15:2e0d977dbb31 | 1228 | } |
wardm | 15:2e0d977dbb31 | 1229 | break; |
wardm | 15:2e0d977dbb31 | 1230 | default: |
wardm | 15:2e0d977dbb31 | 1231 | break; |
wardm | 15:2e0d977dbb31 | 1232 | } |
wardm | 15:2e0d977dbb31 | 1233 | break; |
wardm | 15:2e0d977dbb31 | 1234 | case RF_TX_RUNNING: |
wardm | 15:2e0d977dbb31 | 1235 | switch( this->settings.Modem ) |
wardm | 15:2e0d977dbb31 | 1236 | { |
wardm | 15:2e0d977dbb31 | 1237 | case MODEM_FSK: |
wardm | 15:2e0d977dbb31 | 1238 | // FifoEmpty interrupt |
wardm | 15:2e0d977dbb31 | 1239 | if( ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ) > this->settings.FskPacketHandler.ChunkSize ) |
wardm | 15:2e0d977dbb31 | 1240 | { |
wardm | 15:2e0d977dbb31 | 1241 | WriteFifo( ( rxtxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.ChunkSize ); |
wardm | 15:2e0d977dbb31 | 1242 | this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.ChunkSize; |
wardm | 15:2e0d977dbb31 | 1243 | } |
wardm | 15:2e0d977dbb31 | 1244 | else |
wardm | 15:2e0d977dbb31 | 1245 | { |
wardm | 15:2e0d977dbb31 | 1246 | // Write the last chunk of data |
wardm | 15:2e0d977dbb31 | 1247 | WriteFifo( rxtxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ); |
wardm | 15:2e0d977dbb31 | 1248 | this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes; |
wardm | 15:2e0d977dbb31 | 1249 | } |
wardm | 15:2e0d977dbb31 | 1250 | break; |
wardm | 15:2e0d977dbb31 | 1251 | case MODEM_LORA: |
wardm | 15:2e0d977dbb31 | 1252 | break; |
wardm | 15:2e0d977dbb31 | 1253 | default: |
wardm | 15:2e0d977dbb31 | 1254 | break; |
wardm | 15:2e0d977dbb31 | 1255 | } |
wardm | 15:2e0d977dbb31 | 1256 | break; |
wardm | 15:2e0d977dbb31 | 1257 | default: |
wardm | 15:2e0d977dbb31 | 1258 | break; |
wardm | 15:2e0d977dbb31 | 1259 | } |
wardm | 15:2e0d977dbb31 | 1260 | } |
wardm | 15:2e0d977dbb31 | 1261 | |
wardm | 15:2e0d977dbb31 | 1262 | void SX1272::OnDio2Irq( void ) |
wardm | 15:2e0d977dbb31 | 1263 | { |
wardm | 15:2e0d977dbb31 | 1264 | switch( this->settings.State ) |
wardm | 15:2e0d977dbb31 | 1265 | { |
wardm | 15:2e0d977dbb31 | 1266 | case RF_RX_RUNNING: |
wardm | 15:2e0d977dbb31 | 1267 | switch( this->settings.Modem ) |
wardm | 15:2e0d977dbb31 | 1268 | { |
wardm | 15:2e0d977dbb31 | 1269 | case MODEM_FSK: |
wardm | 15:2e0d977dbb31 | 1270 | // Checks if DIO4 is connected. If it is not PreambleDtected is set to true. |
wardm | 15:2e0d977dbb31 | 1271 | if( this->dioIrq[4] == NULL ) |
wardm | 15:2e0d977dbb31 | 1272 | { |
wardm | 15:2e0d977dbb31 | 1273 | this->settings.FskPacketHandler.PreambleDetected = true; |
wardm | 15:2e0d977dbb31 | 1274 | } |
wardm | 15:2e0d977dbb31 | 1275 | |
wardm | 15:2e0d977dbb31 | 1276 | if( ( this->settings.FskPacketHandler.PreambleDetected == true ) && ( this->settings.FskPacketHandler.SyncWordDetected == false ) ) |
wardm | 15:2e0d977dbb31 | 1277 | { |
wardm | 15:2e0d977dbb31 | 1278 | rxTimeoutSyncWord.detach( ); |
wardm | 15:2e0d977dbb31 | 1279 | |
wardm | 15:2e0d977dbb31 | 1280 | this->settings.FskPacketHandler.SyncWordDetected = true; |
wardm | 15:2e0d977dbb31 | 1281 | |
wardm | 15:2e0d977dbb31 | 1282 | this->settings.FskPacketHandler.RssiValue = -( Read( REG_RSSIVALUE ) >> 1 ); |
wardm | 15:2e0d977dbb31 | 1283 | |
wardm | 15:2e0d977dbb31 | 1284 | this->settings.FskPacketHandler.AfcValue = ( int32_t )( double )( ( ( uint16_t )Read( REG_AFCMSB ) << 8 ) | |
wardm | 15:2e0d977dbb31 | 1285 | ( uint16_t )Read( REG_AFCLSB ) ) * |
wardm | 15:2e0d977dbb31 | 1286 | ( double )FREQ_STEP; |
wardm | 15:2e0d977dbb31 | 1287 | this->settings.FskPacketHandler.RxGain = ( Read( REG_LNA ) >> 5 ) & 0x07; |
wardm | 15:2e0d977dbb31 | 1288 | } |
wardm | 15:2e0d977dbb31 | 1289 | break; |
wardm | 15:2e0d977dbb31 | 1290 | case MODEM_LORA: |
wardm | 15:2e0d977dbb31 | 1291 | if( this->settings.LoRa.FreqHopOn == true ) |
wardm | 15:2e0d977dbb31 | 1292 | { |
wardm | 15:2e0d977dbb31 | 1293 | // Clear Irq |
wardm | 15:2e0d977dbb31 | 1294 | Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL ); |
wardm | 15:2e0d977dbb31 | 1295 | |
wardm | 15:2e0d977dbb31 | 1296 | if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->FhssChangeChannel != NULL ) ) |
wardm | 15:2e0d977dbb31 | 1297 | { |
wardm | 15:2e0d977dbb31 | 1298 | this->RadioEvents->FhssChangeChannel( ( Read( REG_LR_HOPCHANNEL ) & RFLR_HOPCHANNEL_CHANNEL_MASK ) ); |
wardm | 15:2e0d977dbb31 | 1299 | } |
wardm | 15:2e0d977dbb31 | 1300 | } |
wardm | 15:2e0d977dbb31 | 1301 | break; |
wardm | 15:2e0d977dbb31 | 1302 | default: |
wardm | 15:2e0d977dbb31 | 1303 | break; |
wardm | 15:2e0d977dbb31 | 1304 | } |
wardm | 15:2e0d977dbb31 | 1305 | break; |
wardm | 15:2e0d977dbb31 | 1306 | case RF_TX_RUNNING: |
wardm | 15:2e0d977dbb31 | 1307 | switch( this->settings.Modem ) |
wardm | 15:2e0d977dbb31 | 1308 | { |
wardm | 15:2e0d977dbb31 | 1309 | case MODEM_FSK: |
wardm | 15:2e0d977dbb31 | 1310 | break; |
wardm | 15:2e0d977dbb31 | 1311 | case MODEM_LORA: |
wardm | 15:2e0d977dbb31 | 1312 | if( this->settings.LoRa.FreqHopOn == true ) |
wardm | 15:2e0d977dbb31 | 1313 | { |
wardm | 15:2e0d977dbb31 | 1314 | // Clear Irq |
wardm | 15:2e0d977dbb31 | 1315 | Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL ); |
wardm | 15:2e0d977dbb31 | 1316 | |
wardm | 15:2e0d977dbb31 | 1317 | if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->FhssChangeChannel != NULL ) ) |
wardm | 15:2e0d977dbb31 | 1318 | { |
wardm | 15:2e0d977dbb31 | 1319 | this->RadioEvents->FhssChangeChannel( ( Read( REG_LR_HOPCHANNEL ) & RFLR_HOPCHANNEL_CHANNEL_MASK ) ); |
wardm | 15:2e0d977dbb31 | 1320 | } |
wardm | 15:2e0d977dbb31 | 1321 | } |
wardm | 15:2e0d977dbb31 | 1322 | break; |
wardm | 15:2e0d977dbb31 | 1323 | default: |
wardm | 15:2e0d977dbb31 | 1324 | break; |
wardm | 15:2e0d977dbb31 | 1325 | } |
wardm | 15:2e0d977dbb31 | 1326 | break; |
wardm | 15:2e0d977dbb31 | 1327 | default: |
wardm | 15:2e0d977dbb31 | 1328 | break; |
wardm | 15:2e0d977dbb31 | 1329 | } |
wardm | 15:2e0d977dbb31 | 1330 | } |
wardm | 15:2e0d977dbb31 | 1331 | |
wardm | 15:2e0d977dbb31 | 1332 | void SX1272::OnDio3Irq( void ) |
wardm | 15:2e0d977dbb31 | 1333 | { |
wardm | 15:2e0d977dbb31 | 1334 | switch( this->settings.Modem ) |
wardm | 15:2e0d977dbb31 | 1335 | { |
wardm | 15:2e0d977dbb31 | 1336 | case MODEM_FSK: |
wardm | 15:2e0d977dbb31 | 1337 | break; |
wardm | 15:2e0d977dbb31 | 1338 | case MODEM_LORA: |
wardm | 15:2e0d977dbb31 | 1339 | if( ( Read( REG_LR_IRQFLAGS ) & RFLR_IRQFLAGS_CADDETECTED ) == RFLR_IRQFLAGS_CADDETECTED ) |
wardm | 15:2e0d977dbb31 | 1340 | { |
wardm | 15:2e0d977dbb31 | 1341 | // Clear Irq |
wardm | 15:2e0d977dbb31 | 1342 | Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDETECTED | RFLR_IRQFLAGS_CADDONE ); |
wardm | 15:2e0d977dbb31 | 1343 | if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->CadDone != NULL ) ) |
wardm | 15:2e0d977dbb31 | 1344 | { |
wardm | 15:2e0d977dbb31 | 1345 | this->RadioEvents->CadDone( true ); |
wardm | 15:2e0d977dbb31 | 1346 | } |
wardm | 15:2e0d977dbb31 | 1347 | } |
wardm | 15:2e0d977dbb31 | 1348 | else |
wardm | 15:2e0d977dbb31 | 1349 | { |
wardm | 15:2e0d977dbb31 | 1350 | // Clear Irq |
wardm | 15:2e0d977dbb31 | 1351 | Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDONE ); |
wardm | 15:2e0d977dbb31 | 1352 | if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->CadDone != NULL ) ) |
wardm | 15:2e0d977dbb31 | 1353 | { |
wardm | 15:2e0d977dbb31 | 1354 | this->RadioEvents->CadDone( false ); |
wardm | 15:2e0d977dbb31 | 1355 | } |
wardm | 15:2e0d977dbb31 | 1356 | } |
wardm | 15:2e0d977dbb31 | 1357 | break; |
wardm | 15:2e0d977dbb31 | 1358 | default: |
wardm | 15:2e0d977dbb31 | 1359 | break; |
wardm | 15:2e0d977dbb31 | 1360 | } |
wardm | 15:2e0d977dbb31 | 1361 | } |
wardm | 15:2e0d977dbb31 | 1362 | |
wardm | 15:2e0d977dbb31 | 1363 | void SX1272::OnDio4Irq( void ) |
wardm | 15:2e0d977dbb31 | 1364 | { |
wardm | 15:2e0d977dbb31 | 1365 | switch( this->settings.Modem ) |
wardm | 15:2e0d977dbb31 | 1366 | { |
wardm | 15:2e0d977dbb31 | 1367 | case MODEM_FSK: |
wardm | 15:2e0d977dbb31 | 1368 | { |
wardm | 15:2e0d977dbb31 | 1369 | if( this->settings.FskPacketHandler.PreambleDetected == false ) |
wardm | 15:2e0d977dbb31 | 1370 | { |
wardm | 15:2e0d977dbb31 | 1371 | this->settings.FskPacketHandler.PreambleDetected = true; |
wardm | 15:2e0d977dbb31 | 1372 | } |
wardm | 15:2e0d977dbb31 | 1373 | } |
wardm | 15:2e0d977dbb31 | 1374 | break; |
wardm | 15:2e0d977dbb31 | 1375 | case MODEM_LORA: |
wardm | 15:2e0d977dbb31 | 1376 | break; |
wardm | 15:2e0d977dbb31 | 1377 | default: |
wardm | 15:2e0d977dbb31 | 1378 | break; |
wardm | 15:2e0d977dbb31 | 1379 | } |
wardm | 15:2e0d977dbb31 | 1380 | } |
wardm | 15:2e0d977dbb31 | 1381 | |
wardm | 15:2e0d977dbb31 | 1382 | void SX1272::OnDio5Irq( void ) |
wardm | 15:2e0d977dbb31 | 1383 | { |
wardm | 15:2e0d977dbb31 | 1384 | switch( this->settings.Modem ) |
wardm | 15:2e0d977dbb31 | 1385 | { |
wardm | 15:2e0d977dbb31 | 1386 | case MODEM_FSK: |
wardm | 15:2e0d977dbb31 | 1387 | break; |
wardm | 15:2e0d977dbb31 | 1388 | case MODEM_LORA: |
wardm | 15:2e0d977dbb31 | 1389 | break; |
wardm | 15:2e0d977dbb31 | 1390 | default: |
wardm | 15:2e0d977dbb31 | 1391 | break; |
wardm | 15:2e0d977dbb31 | 1392 | } |
wardm | 15:2e0d977dbb31 | 1393 | } |