stephen mathenge / Mbed OS Level_estimation_Maesurement

Level measurement using range finder and lora technology

Dependencies:   Cayenne-LPP SDBlockDevice

mbed-lora-radio-drv/SX1272/registers/sx1272Regs-LoRa.h@0:f930f0440fd5, 2019-06-26 (annotated)

Committer:
wamae
Date:
Wed Jun 26 10:35:50 2019 +0000
Revision:
0:f930f0440fd5
better copy

Who changed what in which revision?

UserRevisionLine numberNew contents of line
wamae 0:f930f0440fd5 1 /**
wamae 0:f930f0440fd5 2 / _____) _ | |
wamae 0:f930f0440fd5 3 ( (____ _____ ____ _| |_ _____ ____| |__
wamae 0:f930f0440fd5 4 \____ \| ___ | (_ _) ___ |/ ___) _ \
wamae 0:f930f0440fd5 5 _____) ) ____| | | || |_| ____( (___| | | |
wamae 0:f930f0440fd5 6 (______/|_____)_|_|_| \__)_____)\____)_| |_|
wamae 0:f930f0440fd5 7 (C) 2015 Semtech
wamae 0:f930f0440fd5 8
wamae 0:f930f0440fd5 9 Description: SX1272 LoRa modem registers and bits definitions
wamae 0:f930f0440fd5 10
wamae 0:f930f0440fd5 11 License: Revised BSD License, see LICENSE.TXT file include in the project
wamae 0:f930f0440fd5 12
wamae 0:f930f0440fd5 13 Maintainer: Miguel Luis and Gregory Cristian
wamae 0:f930f0440fd5 14
wamae 0:f930f0440fd5 15 Copyright (c) 2017, Arm Limited and affiliates.
wamae 0:f930f0440fd5 16
wamae 0:f930f0440fd5 17 SPDX-License-Identifier: BSD-3-Clause
wamae 0:f930f0440fd5 18 */
wamae 0:f930f0440fd5 19 #ifndef __SX1272_REGS_LORA_H__
wamae 0:f930f0440fd5 20 #define __SX1272_REGS_LORA_H__
wamae 0:f930f0440fd5 21
wamae 0:f930f0440fd5 22 /*!
wamae 0:f930f0440fd5 23 * ============================================================================
wamae 0:f930f0440fd5 24 * SX1272 Internal registers Address
wamae 0:f930f0440fd5 25 * ============================================================================
wamae 0:f930f0440fd5 26 */
wamae 0:f930f0440fd5 27 #define REG_LR_FIFO 0x00
wamae 0:f930f0440fd5 28 // Common settings
wamae 0:f930f0440fd5 29 #define REG_LR_OPMODE 0x01
wamae 0:f930f0440fd5 30 #define REG_LR_FRFMSB 0x06
wamae 0:f930f0440fd5 31 #define REG_LR_FRFMID 0x07
wamae 0:f930f0440fd5 32 #define REG_LR_FRFLSB 0x08
wamae 0:f930f0440fd5 33 // Tx settings
wamae 0:f930f0440fd5 34 #define REG_LR_PACONFIG 0x09
wamae 0:f930f0440fd5 35 #define REG_LR_PARAMP 0x0A
wamae 0:f930f0440fd5 36 #define REG_LR_OCP 0x0B
wamae 0:f930f0440fd5 37 // Rx settings
wamae 0:f930f0440fd5 38 #define REG_LR_LNA 0x0C
wamae 0:f930f0440fd5 39 // LoRa registers
wamae 0:f930f0440fd5 40 #define REG_LR_FIFOADDRPTR 0x0D
wamae 0:f930f0440fd5 41 #define REG_LR_FIFOTXBASEADDR 0x0E
wamae 0:f930f0440fd5 42 #define REG_LR_FIFORXBASEADDR 0x0F
wamae 0:f930f0440fd5 43 #define REG_LR_FIFORXCURRENTADDR 0x10
wamae 0:f930f0440fd5 44 #define REG_LR_IRQFLAGSMASK 0x11
wamae 0:f930f0440fd5 45 #define REG_LR_IRQFLAGS 0x12
wamae 0:f930f0440fd5 46 #define REG_LR_RXNBBYTES 0x13
wamae 0:f930f0440fd5 47 #define REG_LR_RXHEADERCNTVALUEMSB 0x14
wamae 0:f930f0440fd5 48 #define REG_LR_RXHEADERCNTVALUELSB 0x15
wamae 0:f930f0440fd5 49 #define REG_LR_RXPACKETCNTVALUEMSB 0x16
wamae 0:f930f0440fd5 50 #define REG_LR_RXPACKETCNTVALUELSB 0x17
wamae 0:f930f0440fd5 51 #define REG_LR_MODEMSTAT 0x18
wamae 0:f930f0440fd5 52 #define REG_LR_PKTSNRVALUE 0x19
wamae 0:f930f0440fd5 53 #define REG_LR_PKTRSSIVALUE 0x1A
wamae 0:f930f0440fd5 54 #define REG_LR_RSSIVALUE 0x1B
wamae 0:f930f0440fd5 55 #define REG_LR_HOPCHANNEL 0x1C
wamae 0:f930f0440fd5 56 #define REG_LR_MODEMCONFIG1 0x1D
wamae 0:f930f0440fd5 57 #define REG_LR_MODEMCONFIG2 0x1E
wamae 0:f930f0440fd5 58 #define REG_LR_SYMBTIMEOUTLSB 0x1F
wamae 0:f930f0440fd5 59 #define REG_LR_PREAMBLEMSB 0x20
wamae 0:f930f0440fd5 60 #define REG_LR_PREAMBLELSB 0x21
wamae 0:f930f0440fd5 61 #define REG_LR_PAYLOADLENGTH 0x22
wamae 0:f930f0440fd5 62 #define REG_LR_PAYLOADMAXLENGTH 0x23
wamae 0:f930f0440fd5 63 #define REG_LR_HOPPERIOD 0x24
wamae 0:f930f0440fd5 64 #define REG_LR_FIFORXBYTEADDR 0x25
wamae 0:f930f0440fd5 65 #define REG_LR_FEIMSB 0x28
wamae 0:f930f0440fd5 66 #define REG_LR_FEIMID 0x29
wamae 0:f930f0440fd5 67 #define REG_LR_FEILSB 0x2A
wamae 0:f930f0440fd5 68 #define REG_LR_RSSIWIDEBAND 0x2C
wamae 0:f930f0440fd5 69 #define REG_LR_DETECTOPTIMIZE 0x31
wamae 0:f930f0440fd5 70 #define REG_LR_INVERTIQ 0x33
wamae 0:f930f0440fd5 71 #define REG_LR_DETECTIONTHRESHOLD 0x37
wamae 0:f930f0440fd5 72 #define REG_LR_SYNCWORD 0x39
wamae 0:f930f0440fd5 73 #define REG_LR_INVERTIQ2 0x3B
wamae 0:f930f0440fd5 74
wamae 0:f930f0440fd5 75 // end of documented register in datasheet
wamae 0:f930f0440fd5 76 // I/O settings
wamae 0:f930f0440fd5 77 #define REG_LR_DIOMAPPING1 0x40
wamae 0:f930f0440fd5 78 #define REG_LR_DIOMAPPING2 0x41
wamae 0:f930f0440fd5 79 // Version
wamae 0:f930f0440fd5 80 #define REG_LR_VERSION 0x42
wamae 0:f930f0440fd5 81 // Additional settings
wamae 0:f930f0440fd5 82 #define REG_LR_AGCREF 0x43
wamae 0:f930f0440fd5 83 #define REG_LR_AGCTHRESH1 0x44
wamae 0:f930f0440fd5 84 #define REG_LR_AGCTHRESH2 0x45
wamae 0:f930f0440fd5 85 #define REG_LR_AGCTHRESH3 0x46
wamae 0:f930f0440fd5 86 #define REG_LR_PLLHOP 0x4B
wamae 0:f930f0440fd5 87 #define REG_LR_TCXO 0x58
wamae 0:f930f0440fd5 88 #define REG_LR_PADAC 0x5A
wamae 0:f930f0440fd5 89 #define REG_LR_PLL 0x5C
wamae 0:f930f0440fd5 90 #define REG_LR_PLLLOWPN 0x5E
wamae 0:f930f0440fd5 91 #define REG_LR_FORMERTEMP 0x6C
wamae 0:f930f0440fd5 92
wamae 0:f930f0440fd5 93 /*!
wamae 0:f930f0440fd5 94 * ============================================================================
wamae 0:f930f0440fd5 95 * SX1272 LoRa bits control definition
wamae 0:f930f0440fd5 96 * ============================================================================
wamae 0:f930f0440fd5 97 */
wamae 0:f930f0440fd5 98
wamae 0:f930f0440fd5 99 /*!
wamae 0:f930f0440fd5 100 * RegFifo
wamae 0:f930f0440fd5 101 */
wamae 0:f930f0440fd5 102
wamae 0:f930f0440fd5 103 /*!
wamae 0:f930f0440fd5 104 * RegOpMode
wamae 0:f930f0440fd5 105 */
wamae 0:f930f0440fd5 106 #define RFLR_OPMODE_LONGRANGEMODE_MASK 0x7F
wamae 0:f930f0440fd5 107 #define RFLR_OPMODE_LONGRANGEMODE_OFF 0x00 // Default
wamae 0:f930f0440fd5 108 #define RFLR_OPMODE_LONGRANGEMODE_ON 0x80
wamae 0:f930f0440fd5 109
wamae 0:f930f0440fd5 110 #define RFLR_OPMODE_ACCESSSHAREDREG_MASK 0xBF
wamae 0:f930f0440fd5 111 #define RFLR_OPMODE_ACCESSSHAREDREG_ENABLE 0x40
wamae 0:f930f0440fd5 112 #define RFLR_OPMODE_ACCESSSHAREDREG_DISABLE 0x00 // Default
wamae 0:f930f0440fd5 113
wamae 0:f930f0440fd5 114 #define RFLR_OPMODE_MASK 0xF8
wamae 0:f930f0440fd5 115 #define RFLR_OPMODE_SLEEP 0x00
wamae 0:f930f0440fd5 116 #define RFLR_OPMODE_STANDBY 0x01 // Default
wamae 0:f930f0440fd5 117 #define RFLR_OPMODE_SYNTHESIZER_TX 0x02
wamae 0:f930f0440fd5 118 #define RFLR_OPMODE_TRANSMITTER 0x03
wamae 0:f930f0440fd5 119 #define RFLR_OPMODE_SYNTHESIZER_RX 0x04
wamae 0:f930f0440fd5 120 #define RFLR_OPMODE_RECEIVER 0x05
wamae 0:f930f0440fd5 121 // LoRa specific modes
wamae 0:f930f0440fd5 122 #define RFLR_OPMODE_RECEIVER_SINGLE 0x06
wamae 0:f930f0440fd5 123 #define RFLR_OPMODE_CAD 0x07
wamae 0:f930f0440fd5 124
wamae 0:f930f0440fd5 125 /*!
wamae 0:f930f0440fd5 126 * RegFrf (MHz)
wamae 0:f930f0440fd5 127 */
wamae 0:f930f0440fd5 128 #define RFLR_FRFMSB_915_MHZ 0xE4 // Default
wamae 0:f930f0440fd5 129 #define RFLR_FRFMID_915_MHZ 0xC0 // Default
wamae 0:f930f0440fd5 130 #define RFLR_FRFLSB_915_MHZ 0x00 // Default
wamae 0:f930f0440fd5 131
wamae 0:f930f0440fd5 132 /*!
wamae 0:f930f0440fd5 133 * RegPaConfig
wamae 0:f930f0440fd5 134 */
wamae 0:f930f0440fd5 135 #define RFLR_PACONFIG_PASELECT_MASK 0x7F
wamae 0:f930f0440fd5 136 #define RFLR_PACONFIG_PASELECT_PABOOST 0x80
wamae 0:f930f0440fd5 137 #define RFLR_PACONFIG_PASELECT_RFO 0x00 // Default
wamae 0:f930f0440fd5 138
wamae 0:f930f0440fd5 139 #define RFLR_PACONFIG_OUTPUTPOWER_MASK 0xF0
wamae 0:f930f0440fd5 140
wamae 0:f930f0440fd5 141 /*!
wamae 0:f930f0440fd5 142 * RegPaRamp
wamae 0:f930f0440fd5 143 */
wamae 0:f930f0440fd5 144 #define RFLR_PARAMP_LOWPNTXPLL_MASK 0xE0
wamae 0:f930f0440fd5 145 #define RFLR_PARAMP_LOWPNTXPLL_OFF 0x10 // Default
wamae 0:f930f0440fd5 146 #define RFLR_PARAMP_LOWPNTXPLL_ON 0x00
wamae 0:f930f0440fd5 147
wamae 0:f930f0440fd5 148 #define RFLR_PARAMP_MASK 0xF0
wamae 0:f930f0440fd5 149 #define RFLR_PARAMP_3400_US 0x00
wamae 0:f930f0440fd5 150 #define RFLR_PARAMP_2000_US 0x01
wamae 0:f930f0440fd5 151 #define RFLR_PARAMP_1000_US 0x02
wamae 0:f930f0440fd5 152 #define RFLR_PARAMP_0500_US 0x03
wamae 0:f930f0440fd5 153 #define RFLR_PARAMP_0250_US 0x04
wamae 0:f930f0440fd5 154 #define RFLR_PARAMP_0125_US 0x05
wamae 0:f930f0440fd5 155 #define RFLR_PARAMP_0100_US 0x06
wamae 0:f930f0440fd5 156 #define RFLR_PARAMP_0062_US 0x07
wamae 0:f930f0440fd5 157 #define RFLR_PARAMP_0050_US 0x08
wamae 0:f930f0440fd5 158 #define RFLR_PARAMP_0040_US 0x09 // Default
wamae 0:f930f0440fd5 159 #define RFLR_PARAMP_0031_US 0x0A
wamae 0:f930f0440fd5 160 #define RFLR_PARAMP_0025_US 0x0B
wamae 0:f930f0440fd5 161 #define RFLR_PARAMP_0020_US 0x0C
wamae 0:f930f0440fd5 162 #define RFLR_PARAMP_0015_US 0x0D
wamae 0:f930f0440fd5 163 #define RFLR_PARAMP_0012_US 0x0E
wamae 0:f930f0440fd5 164 #define RFLR_PARAMP_0010_US 0x0F
wamae 0:f930f0440fd5 165
wamae 0:f930f0440fd5 166 /*!
wamae 0:f930f0440fd5 167 * RegOcp
wamae 0:f930f0440fd5 168 */
wamae 0:f930f0440fd5 169 #define RFLR_OCP_MASK 0xDF
wamae 0:f930f0440fd5 170 #define RFLR_OCP_ON 0x20 // Default
wamae 0:f930f0440fd5 171 #define RFLR_OCP_OFF 0x00
wamae 0:f930f0440fd5 172
wamae 0:f930f0440fd5 173 #define RFLR_OCP_TRIM_MASK 0xE0
wamae 0:f930f0440fd5 174 #define RFLR_OCP_TRIM_045_MA 0x00
wamae 0:f930f0440fd5 175 #define RFLR_OCP_TRIM_050_MA 0x01
wamae 0:f930f0440fd5 176 #define RFLR_OCP_TRIM_055_MA 0x02
wamae 0:f930f0440fd5 177 #define RFLR_OCP_TRIM_060_MA 0x03
wamae 0:f930f0440fd5 178 #define RFLR_OCP_TRIM_065_MA 0x04
wamae 0:f930f0440fd5 179 #define RFLR_OCP_TRIM_070_MA 0x05
wamae 0:f930f0440fd5 180 #define RFLR_OCP_TRIM_075_MA 0x06
wamae 0:f930f0440fd5 181 #define RFLR_OCP_TRIM_080_MA 0x07
wamae 0:f930f0440fd5 182 #define RFLR_OCP_TRIM_085_MA 0x08
wamae 0:f930f0440fd5 183 #define RFLR_OCP_TRIM_090_MA 0x09
wamae 0:f930f0440fd5 184 #define RFLR_OCP_TRIM_095_MA 0x0A
wamae 0:f930f0440fd5 185 #define RFLR_OCP_TRIM_100_MA 0x0B // Default
wamae 0:f930f0440fd5 186 #define RFLR_OCP_TRIM_105_MA 0x0C
wamae 0:f930f0440fd5 187 #define RFLR_OCP_TRIM_110_MA 0x0D
wamae 0:f930f0440fd5 188 #define RFLR_OCP_TRIM_115_MA 0x0E
wamae 0:f930f0440fd5 189 #define RFLR_OCP_TRIM_120_MA 0x0F
wamae 0:f930f0440fd5 190 #define RFLR_OCP_TRIM_130_MA 0x10
wamae 0:f930f0440fd5 191 #define RFLR_OCP_TRIM_140_MA 0x11
wamae 0:f930f0440fd5 192 #define RFLR_OCP_TRIM_150_MA 0x12
wamae 0:f930f0440fd5 193 #define RFLR_OCP_TRIM_160_MA 0x13
wamae 0:f930f0440fd5 194 #define RFLR_OCP_TRIM_170_MA 0x14
wamae 0:f930f0440fd5 195 #define RFLR_OCP_TRIM_180_MA 0x15
wamae 0:f930f0440fd5 196 #define RFLR_OCP_TRIM_190_MA 0x16
wamae 0:f930f0440fd5 197 #define RFLR_OCP_TRIM_200_MA 0x17
wamae 0:f930f0440fd5 198 #define RFLR_OCP_TRIM_210_MA 0x18
wamae 0:f930f0440fd5 199 #define RFLR_OCP_TRIM_220_MA 0x19
wamae 0:f930f0440fd5 200 #define RFLR_OCP_TRIM_230_MA 0x1A
wamae 0:f930f0440fd5 201 #define RFLR_OCP_TRIM_240_MA 0x1B
wamae 0:f930f0440fd5 202
wamae 0:f930f0440fd5 203 /*!
wamae 0:f930f0440fd5 204 * RegLna
wamae 0:f930f0440fd5 205 */
wamae 0:f930f0440fd5 206 #define RFLR_LNA_GAIN_MASK 0x1F
wamae 0:f930f0440fd5 207 #define RFLR_LNA_GAIN_G1 0x20 // Default
wamae 0:f930f0440fd5 208 #define RFLR_LNA_GAIN_G2 0x40
wamae 0:f930f0440fd5 209 #define RFLR_LNA_GAIN_G3 0x60
wamae 0:f930f0440fd5 210 #define RFLR_LNA_GAIN_G4 0x80
wamae 0:f930f0440fd5 211 #define RFLR_LNA_GAIN_G5 0xA0
wamae 0:f930f0440fd5 212 #define RFLR_LNA_GAIN_G6 0xC0
wamae 0:f930f0440fd5 213
wamae 0:f930f0440fd5 214 #define RFLR_LNA_BOOST_MASK 0xFC
wamae 0:f930f0440fd5 215 #define RFLR_LNA_BOOST_OFF 0x00 // Default
wamae 0:f930f0440fd5 216 #define RFLR_LNA_BOOST_ON 0x03
wamae 0:f930f0440fd5 217
wamae 0:f930f0440fd5 218 /*!
wamae 0:f930f0440fd5 219 * RegFifoAddrPtr
wamae 0:f930f0440fd5 220 */
wamae 0:f930f0440fd5 221 #define RFLR_FIFOADDRPTR 0x00 // Default
wamae 0:f930f0440fd5 222
wamae 0:f930f0440fd5 223 /*!
wamae 0:f930f0440fd5 224 * RegFifoTxBaseAddr
wamae 0:f930f0440fd5 225 */
wamae 0:f930f0440fd5 226 #define RFLR_FIFOTXBASEADDR 0x80 // Default
wamae 0:f930f0440fd5 227
wamae 0:f930f0440fd5 228 /*!
wamae 0:f930f0440fd5 229 * RegFifoTxBaseAddr
wamae 0:f930f0440fd5 230 */
wamae 0:f930f0440fd5 231 #define RFLR_FIFORXBASEADDR 0x00 // Default
wamae 0:f930f0440fd5 232
wamae 0:f930f0440fd5 233 /*!
wamae 0:f930f0440fd5 234 * RegFifoRxCurrentAddr (Read Only)
wamae 0:f930f0440fd5 235 */
wamae 0:f930f0440fd5 236
wamae 0:f930f0440fd5 237 /*!
wamae 0:f930f0440fd5 238 * RegIrqFlagsMask
wamae 0:f930f0440fd5 239 */
wamae 0:f930f0440fd5 240 #define RFLR_IRQFLAGS_RXTIMEOUT_MASK 0x80
wamae 0:f930f0440fd5 241 #define RFLR_IRQFLAGS_RXDONE_MASK 0x40
wamae 0:f930f0440fd5 242 #define RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK 0x20
wamae 0:f930f0440fd5 243 #define RFLR_IRQFLAGS_VALIDHEADER_MASK 0x10
wamae 0:f930f0440fd5 244 #define RFLR_IRQFLAGS_TXDONE_MASK 0x08
wamae 0:f930f0440fd5 245 #define RFLR_IRQFLAGS_CADDONE_MASK 0x04
wamae 0:f930f0440fd5 246 #define RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL_MASK 0x02
wamae 0:f930f0440fd5 247 #define RFLR_IRQFLAGS_CADDETECTED_MASK 0x01
wamae 0:f930f0440fd5 248
wamae 0:f930f0440fd5 249 /*!
wamae 0:f930f0440fd5 250 * RegIrqFlags
wamae 0:f930f0440fd5 251 */
wamae 0:f930f0440fd5 252 #define RFLR_IRQFLAGS_RXTIMEOUT 0x80
wamae 0:f930f0440fd5 253 #define RFLR_IRQFLAGS_RXDONE 0x40
wamae 0:f930f0440fd5 254 #define RFLR_IRQFLAGS_PAYLOADCRCERROR 0x20
wamae 0:f930f0440fd5 255 #define RFLR_IRQFLAGS_VALIDHEADER 0x10
wamae 0:f930f0440fd5 256 #define RFLR_IRQFLAGS_TXDONE 0x08
wamae 0:f930f0440fd5 257 #define RFLR_IRQFLAGS_CADDONE 0x04
wamae 0:f930f0440fd5 258 #define RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL 0x02
wamae 0:f930f0440fd5 259 #define RFLR_IRQFLAGS_CADDETECTED 0x01
wamae 0:f930f0440fd5 260
wamae 0:f930f0440fd5 261 /*!
wamae 0:f930f0440fd5 262 * RegFifoRxNbBytes (Read Only)
wamae 0:f930f0440fd5 263 */
wamae 0:f930f0440fd5 264
wamae 0:f930f0440fd5 265 /*!
wamae 0:f930f0440fd5 266 * RegRxHeaderCntValueMsb (Read Only)
wamae 0:f930f0440fd5 267 */
wamae 0:f930f0440fd5 268
wamae 0:f930f0440fd5 269 /*!
wamae 0:f930f0440fd5 270 * RegRxHeaderCntValueLsb (Read Only)
wamae 0:f930f0440fd5 271 */
wamae 0:f930f0440fd5 272
wamae 0:f930f0440fd5 273 /*!
wamae 0:f930f0440fd5 274 * RegRxPacketCntValueMsb (Read Only)
wamae 0:f930f0440fd5 275 */
wamae 0:f930f0440fd5 276
wamae 0:f930f0440fd5 277 /*!
wamae 0:f930f0440fd5 278 * RegRxPacketCntValueLsb (Read Only)
wamae 0:f930f0440fd5 279 */
wamae 0:f930f0440fd5 280
wamae 0:f930f0440fd5 281 /*!
wamae 0:f930f0440fd5 282 * RegModemStat (Read Only)
wamae 0:f930f0440fd5 283 */
wamae 0:f930f0440fd5 284 #define RFLR_MODEMSTAT_RX_CR_MASK 0x1F
wamae 0:f930f0440fd5 285 #define RFLR_MODEMSTAT_MODEM_STATUS_MASK 0xE0
wamae 0:f930f0440fd5 286
wamae 0:f930f0440fd5 287 /*!
wamae 0:f930f0440fd5 288 * RegPktSnrValue (Read Only)
wamae 0:f930f0440fd5 289 */
wamae 0:f930f0440fd5 290
wamae 0:f930f0440fd5 291 /*!
wamae 0:f930f0440fd5 292 * RegPktRssiValue (Read Only)
wamae 0:f930f0440fd5 293 */
wamae 0:f930f0440fd5 294
wamae 0:f930f0440fd5 295 /*!
wamae 0:f930f0440fd5 296 * RegRssiValue (Read Only)
wamae 0:f930f0440fd5 297 */
wamae 0:f930f0440fd5 298
wamae 0:f930f0440fd5 299 /*!
wamae 0:f930f0440fd5 300 * RegHopChannel (Read Only)
wamae 0:f930f0440fd5 301 */
wamae 0:f930f0440fd5 302 #define RFLR_HOPCHANNEL_PLL_LOCK_TIMEOUT_MASK 0x7F
wamae 0:f930f0440fd5 303 #define RFLR_HOPCHANNEL_PLL_LOCK_FAIL 0x80
wamae 0:f930f0440fd5 304 #define RFLR_HOPCHANNEL_PLL_LOCK_SUCCEED 0x00 // Default
wamae 0:f930f0440fd5 305
wamae 0:f930f0440fd5 306 #define RFLR_HOPCHANNEL_CRCONPAYLOAD_MASK 0xBF
wamae 0:f930f0440fd5 307 #define RFLR_HOPCHANNEL_CRCONPAYLOAD_ON 0x40
wamae 0:f930f0440fd5 308 #define RFLR_HOPCHANNEL_CRCONPAYLOAD_OFF 0x00 // Default
wamae 0:f930f0440fd5 309
wamae 0:f930f0440fd5 310 #define RFLR_HOPCHANNEL_CHANNEL_MASK 0x3F
wamae 0:f930f0440fd5 311
wamae 0:f930f0440fd5 312 /*!
wamae 0:f930f0440fd5 313 * RegModemConfig1
wamae 0:f930f0440fd5 314 */
wamae 0:f930f0440fd5 315 #define RFLR_MODEMCONFIG1_BW_MASK 0x3F
wamae 0:f930f0440fd5 316 #define RFLR_MODEMCONFIG1_BW_125_KHZ 0x00 // Default
wamae 0:f930f0440fd5 317 #define RFLR_MODEMCONFIG1_BW_250_KHZ 0x40
wamae 0:f930f0440fd5 318 #define RFLR_MODEMCONFIG1_BW_500_KHZ 0x80
wamae 0:f930f0440fd5 319
wamae 0:f930f0440fd5 320 #define RFLR_MODEMCONFIG1_CODINGRATE_MASK 0xC7
wamae 0:f930f0440fd5 321 #define RFLR_MODEMCONFIG1_CODINGRATE_4_5 0x08
wamae 0:f930f0440fd5 322 #define RFLR_MODEMCONFIG1_CODINGRATE_4_6 0x10 // Default
wamae 0:f930f0440fd5 323 #define RFLR_MODEMCONFIG1_CODINGRATE_4_7 0x18
wamae 0:f930f0440fd5 324 #define RFLR_MODEMCONFIG1_CODINGRATE_4_8 0x20
wamae 0:f930f0440fd5 325
wamae 0:f930f0440fd5 326 #define RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK 0xFB
wamae 0:f930f0440fd5 327 #define RFLR_MODEMCONFIG1_IMPLICITHEADER_ON 0x04
wamae 0:f930f0440fd5 328 #define RFLR_MODEMCONFIG1_IMPLICITHEADER_OFF 0x00 // Default
wamae 0:f930f0440fd5 329
wamae 0:f930f0440fd5 330 #define RFLR_MODEMCONFIG1_RXPAYLOADCRC_MASK 0xFD
wamae 0:f930f0440fd5 331 #define RFLR_MODEMCONFIG1_RXPAYLOADCRC_ON 0x02
wamae 0:f930f0440fd5 332 #define RFLR_MODEMCONFIG1_RXPAYLOADCRC_OFF 0x00 // Default
wamae 0:f930f0440fd5 333
wamae 0:f930f0440fd5 334 #define RFLR_MODEMCONFIG1_LOWDATARATEOPTIMIZE_MASK 0xFE
wamae 0:f930f0440fd5 335 #define RFLR_MODEMCONFIG1_LOWDATARATEOPTIMIZE_ON 0x01
wamae 0:f930f0440fd5 336 #define RFLR_MODEMCONFIG1_LOWDATARATEOPTIMIZE_OFF 0x00 // Default
wamae 0:f930f0440fd5 337
wamae 0:f930f0440fd5 338 /*!
wamae 0:f930f0440fd5 339 * RegModemConfig2
wamae 0:f930f0440fd5 340 */
wamae 0:f930f0440fd5 341 #define RFLR_MODEMCONFIG2_SF_MASK 0x0F
wamae 0:f930f0440fd5 342 #define RFLR_MODEMCONFIG2_SF_6 0x60
wamae 0:f930f0440fd5 343 #define RFLR_MODEMCONFIG2_SF_7 0x70 // Default
wamae 0:f930f0440fd5 344 #define RFLR_MODEMCONFIG2_SF_8 0x80
wamae 0:f930f0440fd5 345 #define RFLR_MODEMCONFIG2_SF_9 0x90
wamae 0:f930f0440fd5 346 #define RFLR_MODEMCONFIG2_SF_10 0xA0
wamae 0:f930f0440fd5 347 #define RFLR_MODEMCONFIG2_SF_11 0xB0
wamae 0:f930f0440fd5 348 #define RFLR_MODEMCONFIG2_SF_12 0xC0
wamae 0:f930f0440fd5 349
wamae 0:f930f0440fd5 350 #define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_MASK 0xF7
wamae 0:f930f0440fd5 351 #define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_ON 0x08
wamae 0:f930f0440fd5 352 #define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_OFF 0x00
wamae 0:f930f0440fd5 353
wamae 0:f930f0440fd5 354 #define RFLR_MODEMCONFIG2_AGCAUTO_MASK 0xFB
wamae 0:f930f0440fd5 355 #define RFLR_MODEMCONFIG2_AGCAUTO_ON 0x04 // Default
wamae 0:f930f0440fd5 356 #define RFLR_MODEMCONFIG2_AGCAUTO_OFF 0x00
wamae 0:f930f0440fd5 357
wamae 0:f930f0440fd5 358 #define RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK 0xFC
wamae 0:f930f0440fd5 359 #define RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB 0x00 // Default
wamae 0:f930f0440fd5 360
wamae 0:f930f0440fd5 361 /*!
wamae 0:f930f0440fd5 362 * RegSymbTimeoutLsb
wamae 0:f930f0440fd5 363 */
wamae 0:f930f0440fd5 364 #define RFLR_SYMBTIMEOUTLSB_SYMBTIMEOUT 0x64 // Default
wamae 0:f930f0440fd5 365
wamae 0:f930f0440fd5 366 /*!
wamae 0:f930f0440fd5 367 * RegPreambleLengthMsb
wamae 0:f930f0440fd5 368 */
wamae 0:f930f0440fd5 369 #define RFLR_PREAMBLELENGTHMSB 0x00 // Default
wamae 0:f930f0440fd5 370
wamae 0:f930f0440fd5 371 /*!
wamae 0:f930f0440fd5 372 * RegPreambleLengthLsb
wamae 0:f930f0440fd5 373 */
wamae 0:f930f0440fd5 374 #define RFLR_PREAMBLELENGTHLSB 0x08 // Default
wamae 0:f930f0440fd5 375
wamae 0:f930f0440fd5 376 /*!
wamae 0:f930f0440fd5 377 * RegPayloadLength
wamae 0:f930f0440fd5 378 */
wamae 0:f930f0440fd5 379 #define RFLR_PAYLOADLENGTH 0x0E // Default
wamae 0:f930f0440fd5 380
wamae 0:f930f0440fd5 381 /*!
wamae 0:f930f0440fd5 382 * RegPayloadMaxLength
wamae 0:f930f0440fd5 383 */
wamae 0:f930f0440fd5 384 #define RFLR_PAYLOADMAXLENGTH 0xFF // Default
wamae 0:f930f0440fd5 385
wamae 0:f930f0440fd5 386 /*!
wamae 0:f930f0440fd5 387 * RegHopPeriod
wamae 0:f930f0440fd5 388 */
wamae 0:f930f0440fd5 389 #define RFLR_HOPPERIOD_FREQFOPPINGPERIOD 0x00 // Default
wamae 0:f930f0440fd5 390
wamae 0:f930f0440fd5 391 /*!
wamae 0:f930f0440fd5 392 * RegFifoRxByteAddr (Read Only)
wamae 0:f930f0440fd5 393 */
wamae 0:f930f0440fd5 394
wamae 0:f930f0440fd5 395 /*!
wamae 0:f930f0440fd5 396 * RegFeiMsb (Read Only)
wamae 0:f930f0440fd5 397 */
wamae 0:f930f0440fd5 398
wamae 0:f930f0440fd5 399 /*!
wamae 0:f930f0440fd5 400 * RegFeiMid (Read Only)
wamae 0:f930f0440fd5 401 */
wamae 0:f930f0440fd5 402
wamae 0:f930f0440fd5 403 /*!
wamae 0:f930f0440fd5 404 * RegFeiLsb (Read Only)
wamae 0:f930f0440fd5 405 */
wamae 0:f930f0440fd5 406
wamae 0:f930f0440fd5 407 /*!
wamae 0:f930f0440fd5 408 * RegRssiWideband (Read Only)
wamae 0:f930f0440fd5 409 */
wamae 0:f930f0440fd5 410
wamae 0:f930f0440fd5 411 /*!
wamae 0:f930f0440fd5 412 * RegDetectOptimize
wamae 0:f930f0440fd5 413 */
wamae 0:f930f0440fd5 414 #define RFLR_DETECTIONOPTIMIZE_MASK 0xF8
wamae 0:f930f0440fd5 415 #define RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 0x03 // Default
wamae 0:f930f0440fd5 416 #define RFLR_DETECTIONOPTIMIZE_SF6 0x05
wamae 0:f930f0440fd5 417
wamae 0:f930f0440fd5 418 /*!
wamae 0:f930f0440fd5 419 * RegInvertIQ
wamae 0:f930f0440fd5 420 */
wamae 0:f930f0440fd5 421 #define RFLR_INVERTIQ_RX_MASK 0xBF
wamae 0:f930f0440fd5 422 #define RFLR_INVERTIQ_RX_OFF 0x00
wamae 0:f930f0440fd5 423 #define RFLR_INVERTIQ_RX_ON 0x40
wamae 0:f930f0440fd5 424 #define RFLR_INVERTIQ_TX_MASK 0xFE
wamae 0:f930f0440fd5 425 #define RFLR_INVERTIQ_TX_OFF 0x01
wamae 0:f930f0440fd5 426 #define RFLR_INVERTIQ_TX_ON 0x00
wamae 0:f930f0440fd5 427
wamae 0:f930f0440fd5 428 /*!
wamae 0:f930f0440fd5 429 * RegDetectionThreshold
wamae 0:f930f0440fd5 430 */
wamae 0:f930f0440fd5 431 #define RFLR_DETECTIONTHRESH_SF7_TO_SF12 0x0A // Default
wamae 0:f930f0440fd5 432 #define RFLR_DETECTIONTHRESH_SF6 0x0C
wamae 0:f930f0440fd5 433
wamae 0:f930f0440fd5 434 /*!
wamae 0:f930f0440fd5 435 * RegInvertIQ2
wamae 0:f930f0440fd5 436 */
wamae 0:f930f0440fd5 437 #define RFLR_INVERTIQ2_ON 0x19
wamae 0:f930f0440fd5 438 #define RFLR_INVERTIQ2_OFF 0x1D
wamae 0:f930f0440fd5 439
wamae 0:f930f0440fd5 440 /*!
wamae 0:f930f0440fd5 441 * RegDioMapping1
wamae 0:f930f0440fd5 442 */
wamae 0:f930f0440fd5 443 #define RFLR_DIOMAPPING1_DIO0_MASK 0x3F
wamae 0:f930f0440fd5 444 #define RFLR_DIOMAPPING1_DIO0_00 0x00 // Default
wamae 0:f930f0440fd5 445 #define RFLR_DIOMAPPING1_DIO0_01 0x40
wamae 0:f930f0440fd5 446 #define RFLR_DIOMAPPING1_DIO0_10 0x80
wamae 0:f930f0440fd5 447 #define RFLR_DIOMAPPING1_DIO0_11 0xC0
wamae 0:f930f0440fd5 448
wamae 0:f930f0440fd5 449 #define RFLR_DIOMAPPING1_DIO1_MASK 0xCF
wamae 0:f930f0440fd5 450 #define RFLR_DIOMAPPING1_DIO1_00 0x00 // Default
wamae 0:f930f0440fd5 451 #define RFLR_DIOMAPPING1_DIO1_01 0x10
wamae 0:f930f0440fd5 452 #define RFLR_DIOMAPPING1_DIO1_10 0x20
wamae 0:f930f0440fd5 453 #define RFLR_DIOMAPPING1_DIO1_11 0x30
wamae 0:f930f0440fd5 454
wamae 0:f930f0440fd5 455 #define RFLR_DIOMAPPING1_DIO2_MASK 0xF3
wamae 0:f930f0440fd5 456 #define RFLR_DIOMAPPING1_DIO2_00 0x00 // Default
wamae 0:f930f0440fd5 457 #define RFLR_DIOMAPPING1_DIO2_01 0x04
wamae 0:f930f0440fd5 458 #define RFLR_DIOMAPPING1_DIO2_10 0x08
wamae 0:f930f0440fd5 459 #define RFLR_DIOMAPPING1_DIO2_11 0x0C
wamae 0:f930f0440fd5 460
wamae 0:f930f0440fd5 461 #define RFLR_DIOMAPPING1_DIO3_MASK 0xFC
wamae 0:f930f0440fd5 462 #define RFLR_DIOMAPPING1_DIO3_00 0x00 // Default
wamae 0:f930f0440fd5 463 #define RFLR_DIOMAPPING1_DIO3_01 0x01
wamae 0:f930f0440fd5 464 #define RFLR_DIOMAPPING1_DIO3_10 0x02
wamae 0:f930f0440fd5 465 #define RFLR_DIOMAPPING1_DIO3_11 0x03
wamae 0:f930f0440fd5 466
wamae 0:f930f0440fd5 467 /*!
wamae 0:f930f0440fd5 468 * RegDioMapping2
wamae 0:f930f0440fd5 469 */
wamae 0:f930f0440fd5 470 #define RFLR_DIOMAPPING2_DIO4_MASK 0x3F
wamae 0:f930f0440fd5 471 #define RFLR_DIOMAPPING2_DIO4_00 0x00 // Default
wamae 0:f930f0440fd5 472 #define RFLR_DIOMAPPING2_DIO4_01 0x40
wamae 0:f930f0440fd5 473 #define RFLR_DIOMAPPING2_DIO4_10 0x80
wamae 0:f930f0440fd5 474 #define RFLR_DIOMAPPING2_DIO4_11 0xC0
wamae 0:f930f0440fd5 475
wamae 0:f930f0440fd5 476 #define RFLR_DIOMAPPING2_DIO5_MASK 0xCF
wamae 0:f930f0440fd5 477 #define RFLR_DIOMAPPING2_DIO5_00 0x00 // Default
wamae 0:f930f0440fd5 478 #define RFLR_DIOMAPPING2_DIO5_01 0x10
wamae 0:f930f0440fd5 479 #define RFLR_DIOMAPPING2_DIO5_10 0x20
wamae 0:f930f0440fd5 480 #define RFLR_DIOMAPPING2_DIO5_11 0x30
wamae 0:f930f0440fd5 481
wamae 0:f930f0440fd5 482 #define RFLR_DIOMAPPING2_MAP_MASK 0xFE
wamae 0:f930f0440fd5 483 #define RFLR_DIOMAPPING2_MAP_PREAMBLEDETECT 0x01
wamae 0:f930f0440fd5 484 #define RFLR_DIOMAPPING2_MAP_RSSI 0x00 // Default
wamae 0:f930f0440fd5 485
wamae 0:f930f0440fd5 486 /*!
wamae 0:f930f0440fd5 487 * RegVersion (Read Only)
wamae 0:f930f0440fd5 488 */
wamae 0:f930f0440fd5 489
wamae 0:f930f0440fd5 490 /*!
wamae 0:f930f0440fd5 491 * RegAgcRef
wamae 0:f930f0440fd5 492 */
wamae 0:f930f0440fd5 493
wamae 0:f930f0440fd5 494 /*!
wamae 0:f930f0440fd5 495 * RegAgcThresh1
wamae 0:f930f0440fd5 496 */
wamae 0:f930f0440fd5 497
wamae 0:f930f0440fd5 498 /*!
wamae 0:f930f0440fd5 499 * RegAgcThresh2
wamae 0:f930f0440fd5 500 */
wamae 0:f930f0440fd5 501
wamae 0:f930f0440fd5 502 /*!
wamae 0:f930f0440fd5 503 * RegAgcThresh3
wamae 0:f930f0440fd5 504 */
wamae 0:f930f0440fd5 505
wamae 0:f930f0440fd5 506 /*!
wamae 0:f930f0440fd5 507 * RegPllHop
wamae 0:f930f0440fd5 508 */
wamae 0:f930f0440fd5 509 #define RFLR_PLLHOP_FASTHOP_MASK 0x7F
wamae 0:f930f0440fd5 510 #define RFLR_PLLHOP_FASTHOP_ON 0x80
wamae 0:f930f0440fd5 511 #define RFLR_PLLHOP_FASTHOP_OFF 0x00 // Default
wamae 0:f930f0440fd5 512
wamae 0:f930f0440fd5 513 /*!
wamae 0:f930f0440fd5 514 * RegTcxo
wamae 0:f930f0440fd5 515 */
wamae 0:f930f0440fd5 516 #define RFLR_TCXO_TCXOINPUT_MASK 0xEF
wamae 0:f930f0440fd5 517 #define RFLR_TCXO_TCXOINPUT_ON 0x10
wamae 0:f930f0440fd5 518 #define RFLR_TCXO_TCXOINPUT_OFF 0x00 // Default
wamae 0:f930f0440fd5 519
wamae 0:f930f0440fd5 520 /*!
wamae 0:f930f0440fd5 521 * RegPaDac
wamae 0:f930f0440fd5 522 */
wamae 0:f930f0440fd5 523 #define RFLR_PADAC_20DBM_MASK 0xF8
wamae 0:f930f0440fd5 524 #define RFLR_PADAC_20DBM_ON 0x07
wamae 0:f930f0440fd5 525 #define RFLR_PADAC_20DBM_OFF 0x04 // Default
wamae 0:f930f0440fd5 526
wamae 0:f930f0440fd5 527 /*!
wamae 0:f930f0440fd5 528 * RegPll
wamae 0:f930f0440fd5 529 */
wamae 0:f930f0440fd5 530 #define RFLR_PLL_BANDWIDTH_MASK 0x3F
wamae 0:f930f0440fd5 531 #define RFLR_PLL_BANDWIDTH_75 0x00
wamae 0:f930f0440fd5 532 #define RFLR_PLL_BANDWIDTH_150 0x40
wamae 0:f930f0440fd5 533 #define RFLR_PLL_BANDWIDTH_225 0x80
wamae 0:f930f0440fd5 534 #define RFLR_PLL_BANDWIDTH_300 0xC0 // Default
wamae 0:f930f0440fd5 535
wamae 0:f930f0440fd5 536 /*!
wamae 0:f930f0440fd5 537 * RegPllLowPn
wamae 0:f930f0440fd5 538 */
wamae 0:f930f0440fd5 539 #define RFLR_PLLLOWPN_BANDWIDTH_MASK 0x3F
wamae 0:f930f0440fd5 540 #define RFLR_PLLLOWPN_BANDWIDTH_75 0x00
wamae 0:f930f0440fd5 541 #define RFLR_PLLLOWPN_BANDWIDTH_150 0x40
wamae 0:f930f0440fd5 542 #define RFLR_PLLLOWPN_BANDWIDTH_225 0x80
wamae 0:f930f0440fd5 543 #define RFLR_PLLLOWPN_BANDWIDTH_300 0xC0 // Default
wamae 0:f930f0440fd5 544
wamae 0:f930f0440fd5 545 /*!
wamae 0:f930f0440fd5 546 * RegFormerTemp
wamae 0:f930f0440fd5 547 */
wamae 0:f930f0440fd5 548
wamae 0:f930f0440fd5 549 #endif // __SX1272_REGS_LORA_H__