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targets/hal/TARGET_NXP/TARGET_LPC11UXX/pinmap.c@35:db417d6d0a5c, 2013-10-16 (annotated)

Committer:
vsluiter
Date:
Wed Oct 16 07:57:27 2013 +0000
Revision:
35:db417d6d0a5c
Parent:
19:398f4c622e1b 
Changed startup_MKL25Z4.s

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 10:3bc89ef62ce7 1 /* mbed Microcontroller Library
emilmont 10:3bc89ef62ce7 2 * Copyright (c) 2006-2013 ARM Limited
emilmont 10:3bc89ef62ce7 3 *
emilmont 10:3bc89ef62ce7 4 * Licensed under the Apache License, Version 2.0 (the "License");
emilmont 10:3bc89ef62ce7 5 * you may not use this file except in compliance with the License.
emilmont 10:3bc89ef62ce7 6 * You may obtain a copy of the License at
emilmont 10:3bc89ef62ce7 7 *
emilmont 10:3bc89ef62ce7 8 * http://www.apache.org/licenses/LICENSE-2.0
emilmont 10:3bc89ef62ce7 9 *
emilmont 10:3bc89ef62ce7 10 * Unless required by applicable law or agreed to in writing, software
emilmont 10:3bc89ef62ce7 11 * distributed under the License is distributed on an "AS IS" BASIS,
emilmont 10:3bc89ef62ce7 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
emilmont 10:3bc89ef62ce7 13 * See the License for the specific language governing permissions and
emilmont 10:3bc89ef62ce7 14 * limitations under the License.
emilmont 10:3bc89ef62ce7 15 */
emilmont 10:3bc89ef62ce7 16 #include "pinmap.h"
emilmont 10:3bc89ef62ce7 17 #include "error.h"
emilmont 10:3bc89ef62ce7 18
emilmont 10:3bc89ef62ce7 19 #define LPC_IOCON0_BASE (LPC_IOCON_BASE)
emilmont 10:3bc89ef62ce7 20 #define LPC_IOCON1_BASE (LPC_IOCON_BASE + 0x60)
emilmont 10:3bc89ef62ce7 21
emilmont 10:3bc89ef62ce7 22 void pin_function(PinName pin, int function) {
bogdanm 19:398f4c622e1b 23 if (pin == (PinName)NC) return;
emilmont 10:3bc89ef62ce7 24
emilmont 10:3bc89ef62ce7 25 uint32_t pin_number = (uint32_t)pin;
emilmont 10:3bc89ef62ce7 26
emilmont 10:3bc89ef62ce7 27 __IO uint32_t *reg = (pin_number < 32) ?
emilmont 10:3bc89ef62ce7 28 (__IO uint32_t*)(LPC_IOCON0_BASE + 4 * pin_number) :
emilmont 10:3bc89ef62ce7 29 (__IO uint32_t*)(LPC_IOCON1_BASE + 4 * (pin_number - 32));
emilmont 10:3bc89ef62ce7 30
emilmont 10:3bc89ef62ce7 31 // pin function bits: [2:0] -> 111 = (0x7)
emilmont 10:3bc89ef62ce7 32 *reg = (*reg & ~0x7) | (function & 0x7);
emilmont 10:3bc89ef62ce7 33 }
emilmont 10:3bc89ef62ce7 34
emilmont 10:3bc89ef62ce7 35 void pin_mode(PinName pin, PinMode mode) {
bogdanm 19:398f4c622e1b 36 if (pin == (PinName)NC) { return; }
emilmont 10:3bc89ef62ce7 37
emilmont 10:3bc89ef62ce7 38 uint32_t pin_number = (uint32_t)pin;
emilmont 10:3bc89ef62ce7 39 uint32_t drain = ((uint32_t) mode & (uint32_t) OpenDrain) >> 2;
emilmont 10:3bc89ef62ce7 40
emilmont 10:3bc89ef62ce7 41 __IO uint32_t *reg = (pin_number < 32) ?
emilmont 10:3bc89ef62ce7 42 (__IO uint32_t*)(LPC_IOCON0_BASE + 4 * pin_number) :
emilmont 10:3bc89ef62ce7 43 (__IO uint32_t*)(LPC_IOCON1_BASE + 4 * (pin_number - 32));
emilmont 10:3bc89ef62ce7 44 uint32_t tmp = *reg;
emilmont 10:3bc89ef62ce7 45
emilmont 10:3bc89ef62ce7 46 // pin mode bits: [4:3] -> 11000 = (0x3 << 3)
emilmont 10:3bc89ef62ce7 47 tmp &= ~(0x3 << 3);
emilmont 10:3bc89ef62ce7 48 tmp |= (mode & 0x3) << 3;
emilmont 10:3bc89ef62ce7 49
emilmont 10:3bc89ef62ce7 50 // drain
emilmont 10:3bc89ef62ce7 51 tmp &= ~(0x1 << 10);
emilmont 10:3bc89ef62ce7 52 tmp |= drain << 10;
emilmont 10:3bc89ef62ce7 53
emilmont 10:3bc89ef62ce7 54 *reg = tmp;
emilmont 10:3bc89ef62ce7 55 }