Vergil Cola / Mbed OS MQTTGatewayK64

Fork of my MQTTGateway

Dependencies:   mbed-http

easy-connect/stm-spirit1-rf-driver/source/radio_spi.cpp@0:f1d3878b8dd9, 2017-04-08 (annotated)

Committer:
vpcola
Date:
Sat Apr 08 14:45:51 2017 +0000
Revision:
0:f1d3878b8dd9
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
vpcola 0:f1d3878b8dd9 1 /**
vpcola 0:f1d3878b8dd9 2 ******************************************************************************
vpcola 0:f1d3878b8dd9 3 * @file radio_spi.c
vpcola 0:f1d3878b8dd9 4 * @author System Lab - NOIDA
vpcola 0:f1d3878b8dd9 5 * @version V1.0.0
vpcola 0:f1d3878b8dd9 6 * @date 15-May-2014
vpcola 0:f1d3878b8dd9 7 * @brief This file provides code for the configuration of the SPI instances.
vpcola 0:f1d3878b8dd9 8 ******************************************************************************
vpcola 0:f1d3878b8dd9 9 * @attention
vpcola 0:f1d3878b8dd9 10 *
vpcola 0:f1d3878b8dd9 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
vpcola 0:f1d3878b8dd9 12 *
vpcola 0:f1d3878b8dd9 13 * Redistribution and use in source and binary forms, with or without modification,
vpcola 0:f1d3878b8dd9 14 * are permitted provided that the following conditions are met:
vpcola 0:f1d3878b8dd9 15 * 1. Redistributions of source code must retain the above copyright notice,
vpcola 0:f1d3878b8dd9 16 * this list of conditions and the following disclaimer.
vpcola 0:f1d3878b8dd9 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
vpcola 0:f1d3878b8dd9 18 * this list of conditions and the following disclaimer in the documentation
vpcola 0:f1d3878b8dd9 19 * and/or other materials provided with the distribution.
vpcola 0:f1d3878b8dd9 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
vpcola 0:f1d3878b8dd9 21 * may be used to endorse or promote products derived from this software
vpcola 0:f1d3878b8dd9 22 * without specific prior written permission.
vpcola 0:f1d3878b8dd9 23 *
vpcola 0:f1d3878b8dd9 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
vpcola 0:f1d3878b8dd9 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
vpcola 0:f1d3878b8dd9 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
vpcola 0:f1d3878b8dd9 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
vpcola 0:f1d3878b8dd9 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
vpcola 0:f1d3878b8dd9 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
vpcola 0:f1d3878b8dd9 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
vpcola 0:f1d3878b8dd9 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
vpcola 0:f1d3878b8dd9 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
vpcola 0:f1d3878b8dd9 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
vpcola 0:f1d3878b8dd9 34 *
vpcola 0:f1d3878b8dd9 35 ******************************************************************************
vpcola 0:f1d3878b8dd9 36 */
vpcola 0:f1d3878b8dd9 37
vpcola 0:f1d3878b8dd9 38
vpcola 0:f1d3878b8dd9 39 /* Includes ------------------------------------------------------------------*/
vpcola 0:f1d3878b8dd9 40 #include "radio_spi.h"
vpcola 0:f1d3878b8dd9 41
vpcola 0:f1d3878b8dd9 42 #include "SimpleSpirit1.h"
vpcola 0:f1d3878b8dd9 43
vpcola 0:f1d3878b8dd9 44
vpcola 0:f1d3878b8dd9 45 /**
vpcola 0:f1d3878b8dd9 46 * @addtogroup BSP
vpcola 0:f1d3878b8dd9 47 * @{
vpcola 0:f1d3878b8dd9 48 */
vpcola 0:f1d3878b8dd9 49
vpcola 0:f1d3878b8dd9 50
vpcola 0:f1d3878b8dd9 51 /**
vpcola 0:f1d3878b8dd9 52 * @addtogroup X-NUCLEO-IDS02Ax
vpcola 0:f1d3878b8dd9 53 * @{
vpcola 0:f1d3878b8dd9 54 */
vpcola 0:f1d3878b8dd9 55
vpcola 0:f1d3878b8dd9 56
vpcola 0:f1d3878b8dd9 57 /**
vpcola 0:f1d3878b8dd9 58 * @defgroup RADIO_SPI_Private_TypesDefinitions RADIO_SPI Private Types Definitions
vpcola 0:f1d3878b8dd9 59 * @{
vpcola 0:f1d3878b8dd9 60 */
vpcola 0:f1d3878b8dd9 61
vpcola 0:f1d3878b8dd9 62 /**
vpcola 0:f1d3878b8dd9 63 * @}
vpcola 0:f1d3878b8dd9 64 */
vpcola 0:f1d3878b8dd9 65
vpcola 0:f1d3878b8dd9 66
vpcola 0:f1d3878b8dd9 67 /**
vpcola 0:f1d3878b8dd9 68 * @defgroup RADIO_SPI_Private_Defines RADIO_SPI Private Defines
vpcola 0:f1d3878b8dd9 69 * @{
vpcola 0:f1d3878b8dd9 70 */
vpcola 0:f1d3878b8dd9 71
vpcola 0:f1d3878b8dd9 72 /**
vpcola 0:f1d3878b8dd9 73 * @}
vpcola 0:f1d3878b8dd9 74 */
vpcola 0:f1d3878b8dd9 75
vpcola 0:f1d3878b8dd9 76
vpcola 0:f1d3878b8dd9 77 /**
vpcola 0:f1d3878b8dd9 78 * @defgroup RADIO_SPI_Private_Macros RADIO_SPI Private Macros
vpcola 0:f1d3878b8dd9 79 * @{
vpcola 0:f1d3878b8dd9 80 */
vpcola 0:f1d3878b8dd9 81
vpcola 0:f1d3878b8dd9 82 /**
vpcola 0:f1d3878b8dd9 83 * @}
vpcola 0:f1d3878b8dd9 84 */
vpcola 0:f1d3878b8dd9 85
vpcola 0:f1d3878b8dd9 86
vpcola 0:f1d3878b8dd9 87 /**
vpcola 0:f1d3878b8dd9 88 * @defgroup RADIO_SPI_Private_Variables RADIO_SPI Private Variables
vpcola 0:f1d3878b8dd9 89 * @{
vpcola 0:f1d3878b8dd9 90 */
vpcola 0:f1d3878b8dd9 91
vpcola 0:f1d3878b8dd9 92 /**
vpcola 0:f1d3878b8dd9 93 * @}
vpcola 0:f1d3878b8dd9 94 */
vpcola 0:f1d3878b8dd9 95
vpcola 0:f1d3878b8dd9 96
vpcola 0:f1d3878b8dd9 97 /**
vpcola 0:f1d3878b8dd9 98 * @defgroup RADIO_SPI_Private_FunctionPrototypes RADIO_SPI Private Function Prototypes
vpcola 0:f1d3878b8dd9 99 * @{
vpcola 0:f1d3878b8dd9 100 */
vpcola 0:f1d3878b8dd9 101
vpcola 0:f1d3878b8dd9 102 /**
vpcola 0:f1d3878b8dd9 103 * @}
vpcola 0:f1d3878b8dd9 104 */
vpcola 0:f1d3878b8dd9 105
vpcola 0:f1d3878b8dd9 106 /**
vpcola 0:f1d3878b8dd9 107 * @defgroup RADIO_SPI_Private_Functions RADIO_SPI Private Functions
vpcola 0:f1d3878b8dd9 108 * @{
vpcola 0:f1d3878b8dd9 109 */
vpcola 0:f1d3878b8dd9 110
vpcola 0:f1d3878b8dd9 111 /**
vpcola 0:f1d3878b8dd9 112 * @}
vpcola 0:f1d3878b8dd9 113 */
vpcola 0:f1d3878b8dd9 114
vpcola 0:f1d3878b8dd9 115 /**
vpcola 0:f1d3878b8dd9 116 * @brief Write single or multiple RF Transceivers register
vpcola 0:f1d3878b8dd9 117 * @param cRegAddress: base register's address to be write
vpcola 0:f1d3878b8dd9 118 * @param cNbBytes: number of registers and bytes to be write
vpcola 0:f1d3878b8dd9 119 * @param pcBuffer: pointer to the buffer of values have to be written into registers
vpcola 0:f1d3878b8dd9 120 * @retval StatusBytes
vpcola 0:f1d3878b8dd9 121 */
vpcola 0:f1d3878b8dd9 122 StatusBytes SdkEvalSpiWriteRegisters(uint8_t cRegAddress, uint8_t cNbBytes, uint8_t* pcBuffer)
vpcola 0:f1d3878b8dd9 123 {
vpcola 0:f1d3878b8dd9 124 return SimpleSpirit1::Instance().SdkEvalSpiWriteRegisters(cRegAddress, cNbBytes, pcBuffer);
vpcola 0:f1d3878b8dd9 125 }
vpcola 0:f1d3878b8dd9 126
vpcola 0:f1d3878b8dd9 127 StatusBytes SimpleSpirit1::SdkEvalSpiWriteRegisters(uint8_t cRegAddress, uint8_t cNbBytes, uint8_t* pcBuffer)
vpcola 0:f1d3878b8dd9 128 {
vpcola 0:f1d3878b8dd9 129 uint8_t aHeader[2] = {0};
vpcola 0:f1d3878b8dd9 130 uint16_t tmpstatus = 0x0000;
vpcola 0:f1d3878b8dd9 131 StatusBytes *pStatus=(StatusBytes *)&tmpstatus;
vpcola 0:f1d3878b8dd9 132
vpcola 0:f1d3878b8dd9 133 /* Built the aHeader bytes */
vpcola 0:f1d3878b8dd9 134 aHeader[0] = WRITE_HEADER;
vpcola 0:f1d3878b8dd9 135 aHeader[1] = cRegAddress;
vpcola 0:f1d3878b8dd9 136
vpcola 0:f1d3878b8dd9 137 /* Puts the SPI chip select low to start the transaction */
vpcola 0:f1d3878b8dd9 138 chip_sync_select();
vpcola 0:f1d3878b8dd9 139
vpcola 0:f1d3878b8dd9 140 /* Write the aHeader bytes and read the SPIRIT1 status bytes */
vpcola 0:f1d3878b8dd9 141 tmpstatus = _spi.write(aHeader[0]);
vpcola 0:f1d3878b8dd9 142 tmpstatus = tmpstatus << 8;
vpcola 0:f1d3878b8dd9 143
vpcola 0:f1d3878b8dd9 144 /* Write the aHeader bytes and read the SPIRIT1 status bytes */
vpcola 0:f1d3878b8dd9 145 tmpstatus |= _spi.write(aHeader[1]);
vpcola 0:f1d3878b8dd9 146
vpcola 0:f1d3878b8dd9 147 /* Writes the registers according to the number of bytes */
vpcola 0:f1d3878b8dd9 148 for (int index = 0; index < cNbBytes; index++)
vpcola 0:f1d3878b8dd9 149 {
vpcola 0:f1d3878b8dd9 150 _spi.write(pcBuffer[index]);
vpcola 0:f1d3878b8dd9 151 }
vpcola 0:f1d3878b8dd9 152
vpcola 0:f1d3878b8dd9 153 /* Puts the SPI chip select high to end the transaction */
vpcola 0:f1d3878b8dd9 154 chip_sync_unselect();
vpcola 0:f1d3878b8dd9 155
vpcola 0:f1d3878b8dd9 156 return *pStatus;
vpcola 0:f1d3878b8dd9 157 }
vpcola 0:f1d3878b8dd9 158
vpcola 0:f1d3878b8dd9 159
vpcola 0:f1d3878b8dd9 160 /**
vpcola 0:f1d3878b8dd9 161 * @brief Read single or multiple SPIRIT1 register
vpcola 0:f1d3878b8dd9 162 * @param cRegAddress: base register's address to be read
vpcola 0:f1d3878b8dd9 163 * @param cNbBytes: number of registers and bytes to be read
vpcola 0:f1d3878b8dd9 164 * @param pcBuffer: pointer to the buffer of registers' values read
vpcola 0:f1d3878b8dd9 165 * @retval StatusBytes
vpcola 0:f1d3878b8dd9 166 */
vpcola 0:f1d3878b8dd9 167 StatusBytes SdkEvalSpiReadRegisters(uint8_t cRegAddress, uint8_t cNbBytes, uint8_t* pcBuffer)
vpcola 0:f1d3878b8dd9 168 {
vpcola 0:f1d3878b8dd9 169 return SimpleSpirit1::Instance().SdkEvalSpiReadRegisters(cRegAddress, cNbBytes, pcBuffer);
vpcola 0:f1d3878b8dd9 170 }
vpcola 0:f1d3878b8dd9 171
vpcola 0:f1d3878b8dd9 172 StatusBytes SimpleSpirit1::SdkEvalSpiReadRegisters(uint8_t cRegAddress, uint8_t cNbBytes, uint8_t* pcBuffer)
vpcola 0:f1d3878b8dd9 173 {
vpcola 0:f1d3878b8dd9 174 uint16_t tmpstatus = 0x00;
vpcola 0:f1d3878b8dd9 175 StatusBytes *pStatus = (StatusBytes *)&tmpstatus;
vpcola 0:f1d3878b8dd9 176
vpcola 0:f1d3878b8dd9 177 uint8_t aHeader[2] = {0};
vpcola 0:f1d3878b8dd9 178
vpcola 0:f1d3878b8dd9 179 /* Built the aHeader bytes */
vpcola 0:f1d3878b8dd9 180 aHeader[0] = READ_HEADER;
vpcola 0:f1d3878b8dd9 181 aHeader[1] = cRegAddress;
vpcola 0:f1d3878b8dd9 182
vpcola 0:f1d3878b8dd9 183 /* Put the SPI chip select low to start the transaction */
vpcola 0:f1d3878b8dd9 184 chip_sync_select();
vpcola 0:f1d3878b8dd9 185
vpcola 0:f1d3878b8dd9 186 /* Write the aHeader bytes and read the SPIRIT1 status bytes */
vpcola 0:f1d3878b8dd9 187 tmpstatus = _spi.write(aHeader[0]);
vpcola 0:f1d3878b8dd9 188 tmpstatus = tmpstatus << 8;
vpcola 0:f1d3878b8dd9 189
vpcola 0:f1d3878b8dd9 190 /* Write the aHeader bytes and read the SPIRIT1 status bytes */
vpcola 0:f1d3878b8dd9 191 tmpstatus |= _spi.write(aHeader[1]);
vpcola 0:f1d3878b8dd9 192
vpcola 0:f1d3878b8dd9 193 for (int index = 0; index < cNbBytes; index++)
vpcola 0:f1d3878b8dd9 194 {
vpcola 0:f1d3878b8dd9 195 pcBuffer[index] = _spi.write(0xFF);
vpcola 0:f1d3878b8dd9 196 }
vpcola 0:f1d3878b8dd9 197
vpcola 0:f1d3878b8dd9 198 /* Put the SPI chip select high to end the transaction */
vpcola 0:f1d3878b8dd9 199 chip_sync_unselect();
vpcola 0:f1d3878b8dd9 200
vpcola 0:f1d3878b8dd9 201 return *pStatus;
vpcola 0:f1d3878b8dd9 202 }
vpcola 0:f1d3878b8dd9 203
vpcola 0:f1d3878b8dd9 204
vpcola 0:f1d3878b8dd9 205 /**
vpcola 0:f1d3878b8dd9 206 * @brief Send a command
vpcola 0:f1d3878b8dd9 207 * @param cCommandCode: command code to be sent
vpcola 0:f1d3878b8dd9 208 * @retval StatusBytes
vpcola 0:f1d3878b8dd9 209 */
vpcola 0:f1d3878b8dd9 210 StatusBytes SdkEvalSpiCommandStrobes(uint8_t cCommandCode)
vpcola 0:f1d3878b8dd9 211 {
vpcola 0:f1d3878b8dd9 212 return SimpleSpirit1::Instance().SdkEvalSpiCommandStrobes(cCommandCode);
vpcola 0:f1d3878b8dd9 213 }
vpcola 0:f1d3878b8dd9 214
vpcola 0:f1d3878b8dd9 215 StatusBytes SimpleSpirit1::SdkEvalSpiCommandStrobes(uint8_t cCommandCode)
vpcola 0:f1d3878b8dd9 216 {
vpcola 0:f1d3878b8dd9 217 uint8_t aHeader[2] = {0};
vpcola 0:f1d3878b8dd9 218 uint16_t tmpstatus = 0x0000;
vpcola 0:f1d3878b8dd9 219
vpcola 0:f1d3878b8dd9 220 StatusBytes *pStatus = (StatusBytes *)&tmpstatus;
vpcola 0:f1d3878b8dd9 221
vpcola 0:f1d3878b8dd9 222 /* Built the aHeader bytes */
vpcola 0:f1d3878b8dd9 223 aHeader[0] = COMMAND_HEADER;
vpcola 0:f1d3878b8dd9 224 aHeader[1] = cCommandCode;
vpcola 0:f1d3878b8dd9 225
vpcola 0:f1d3878b8dd9 226 /* Puts the SPI chip select low to start the transaction */
vpcola 0:f1d3878b8dd9 227 chip_sync_select();
vpcola 0:f1d3878b8dd9 228
vpcola 0:f1d3878b8dd9 229 /* Write the aHeader bytes and read the SPIRIT1 status bytes */
vpcola 0:f1d3878b8dd9 230 tmpstatus = _spi.write(aHeader[0]);
vpcola 0:f1d3878b8dd9 231 tmpstatus = tmpstatus<<8;
vpcola 0:f1d3878b8dd9 232
vpcola 0:f1d3878b8dd9 233 /* Write the aHeader bytes and read the SPIRIT1 status bytes */
vpcola 0:f1d3878b8dd9 234 tmpstatus |= _spi.write(aHeader[1]);
vpcola 0:f1d3878b8dd9 235
vpcola 0:f1d3878b8dd9 236 /* Puts the SPI chip select high to end the transaction */
vpcola 0:f1d3878b8dd9 237 chip_sync_unselect();
vpcola 0:f1d3878b8dd9 238
vpcola 0:f1d3878b8dd9 239 return *pStatus;
vpcola 0:f1d3878b8dd9 240 }
vpcola 0:f1d3878b8dd9 241
vpcola 0:f1d3878b8dd9 242
vpcola 0:f1d3878b8dd9 243 /**
vpcola 0:f1d3878b8dd9 244 * @brief Write data into TX FIFO
vpcola 0:f1d3878b8dd9 245 * @param cNbBytes: number of bytes to be written into TX FIFO
vpcola 0:f1d3878b8dd9 246 * @param pcBuffer: pointer to data to write
vpcola 0:f1d3878b8dd9 247 * @retval StatusBytes
vpcola 0:f1d3878b8dd9 248 */
vpcola 0:f1d3878b8dd9 249 StatusBytes SdkEvalSpiWriteFifo(uint8_t cNbBytes, uint8_t* pcBuffer)
vpcola 0:f1d3878b8dd9 250 {
vpcola 0:f1d3878b8dd9 251 return SimpleSpirit1::Instance().SdkEvalSpiWriteFifo(cNbBytes, pcBuffer);
vpcola 0:f1d3878b8dd9 252 }
vpcola 0:f1d3878b8dd9 253
vpcola 0:f1d3878b8dd9 254 StatusBytes SimpleSpirit1::SdkEvalSpiWriteFifo(uint8_t cNbBytes, uint8_t* pcBuffer)
vpcola 0:f1d3878b8dd9 255 {
vpcola 0:f1d3878b8dd9 256 uint16_t tmpstatus = 0x0000;
vpcola 0:f1d3878b8dd9 257 StatusBytes *pStatus = (StatusBytes *)&tmpstatus;
vpcola 0:f1d3878b8dd9 258
vpcola 0:f1d3878b8dd9 259 uint8_t aHeader[2] = {0};
vpcola 0:f1d3878b8dd9 260
vpcola 0:f1d3878b8dd9 261 /* Built the aHeader bytes */
vpcola 0:f1d3878b8dd9 262 aHeader[0] = WRITE_HEADER;
vpcola 0:f1d3878b8dd9 263 aHeader[1] = LINEAR_FIFO_ADDRESS;
vpcola 0:f1d3878b8dd9 264
vpcola 0:f1d3878b8dd9 265 /* Put the SPI chip select low to start the transaction */
vpcola 0:f1d3878b8dd9 266 chip_sync_select();
vpcola 0:f1d3878b8dd9 267
vpcola 0:f1d3878b8dd9 268 /* Write the aHeader bytes and read the SPIRIT1 status bytes */
vpcola 0:f1d3878b8dd9 269 tmpstatus = _spi.write(aHeader[0]);
vpcola 0:f1d3878b8dd9 270 tmpstatus = tmpstatus<<8;
vpcola 0:f1d3878b8dd9 271
vpcola 0:f1d3878b8dd9 272 /* Write the aHeader bytes and read the SPIRIT1 status bytes */
vpcola 0:f1d3878b8dd9 273 tmpstatus |= _spi.write(aHeader[1]);
vpcola 0:f1d3878b8dd9 274
vpcola 0:f1d3878b8dd9 275 /* Writes the registers according to the number of bytes */
vpcola 0:f1d3878b8dd9 276 for (int index = 0; index < cNbBytes; index++)
vpcola 0:f1d3878b8dd9 277 {
vpcola 0:f1d3878b8dd9 278 _spi.write(pcBuffer[index]);
vpcola 0:f1d3878b8dd9 279 }
vpcola 0:f1d3878b8dd9 280
vpcola 0:f1d3878b8dd9 281 /* Put the SPI chip select high to end the transaction */
vpcola 0:f1d3878b8dd9 282 chip_sync_unselect();
vpcola 0:f1d3878b8dd9 283
vpcola 0:f1d3878b8dd9 284 return *pStatus;
vpcola 0:f1d3878b8dd9 285 }
vpcola 0:f1d3878b8dd9 286
vpcola 0:f1d3878b8dd9 287 /**
vpcola 0:f1d3878b8dd9 288 * @brief Read data from RX FIFO
vpcola 0:f1d3878b8dd9 289 * @param cNbBytes: number of bytes to read from RX FIFO
vpcola 0:f1d3878b8dd9 290 * @param pcBuffer: pointer to data read from RX FIFO
vpcola 0:f1d3878b8dd9 291 * @retval StatusBytes
vpcola 0:f1d3878b8dd9 292 */
vpcola 0:f1d3878b8dd9 293 StatusBytes SdkEvalSpiReadFifo(uint8_t cNbBytes, uint8_t* pcBuffer)
vpcola 0:f1d3878b8dd9 294 {
vpcola 0:f1d3878b8dd9 295 return SimpleSpirit1::Instance().SdkEvalSpiReadFifo(cNbBytes, pcBuffer);
vpcola 0:f1d3878b8dd9 296 }
vpcola 0:f1d3878b8dd9 297
vpcola 0:f1d3878b8dd9 298 StatusBytes SimpleSpirit1::SdkEvalSpiReadFifo(uint8_t cNbBytes, uint8_t* pcBuffer)
vpcola 0:f1d3878b8dd9 299 {
vpcola 0:f1d3878b8dd9 300 uint16_t tmpstatus = 0x0000;
vpcola 0:f1d3878b8dd9 301 StatusBytes *pStatus = (StatusBytes *)&tmpstatus;
vpcola 0:f1d3878b8dd9 302
vpcola 0:f1d3878b8dd9 303 uint8_t aHeader[2];
vpcola 0:f1d3878b8dd9 304
vpcola 0:f1d3878b8dd9 305 /* Built the aHeader bytes */
vpcola 0:f1d3878b8dd9 306 aHeader[0]=READ_HEADER;
vpcola 0:f1d3878b8dd9 307 aHeader[1]=LINEAR_FIFO_ADDRESS;
vpcola 0:f1d3878b8dd9 308
vpcola 0:f1d3878b8dd9 309 /* Put the SPI chip select low to start the transaction */
vpcola 0:f1d3878b8dd9 310 chip_sync_select();
vpcola 0:f1d3878b8dd9 311
vpcola 0:f1d3878b8dd9 312 /* Write the aHeader bytes and read the SPIRIT1 status bytes */
vpcola 0:f1d3878b8dd9 313 tmpstatus = _spi.write(aHeader[0]);
vpcola 0:f1d3878b8dd9 314 tmpstatus = tmpstatus<<8;
vpcola 0:f1d3878b8dd9 315
vpcola 0:f1d3878b8dd9 316 /* Write the aHeader bytes and read the SPIRIT1 status bytes */
vpcola 0:f1d3878b8dd9 317 tmpstatus |= _spi.write(aHeader[1]);
vpcola 0:f1d3878b8dd9 318
vpcola 0:f1d3878b8dd9 319 for (int index = 0; index < cNbBytes; index++)
vpcola 0:f1d3878b8dd9 320 {
vpcola 0:f1d3878b8dd9 321 pcBuffer[index] = _spi.write(0xFF);
vpcola 0:f1d3878b8dd9 322 }
vpcola 0:f1d3878b8dd9 323
vpcola 0:f1d3878b8dd9 324 /* Put the SPI chip select high to end the transaction */
vpcola 0:f1d3878b8dd9 325 chip_sync_unselect();
vpcola 0:f1d3878b8dd9 326
vpcola 0:f1d3878b8dd9 327 return *pStatus;
vpcola 0:f1d3878b8dd9 328 }
vpcola 0:f1d3878b8dd9 329
vpcola 0:f1d3878b8dd9 330
vpcola 0:f1d3878b8dd9 331 /**
vpcola 0:f1d3878b8dd9 332 * @}
vpcola 0:f1d3878b8dd9 333 */
vpcola 0:f1d3878b8dd9 334
vpcola 0:f1d3878b8dd9 335 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/