Vergil Cola / Mbed OS MQTTGatewayK64

Fork of my MQTTGateway

Dependencies:   mbed-http

easy-connect/mcr20a-rf-driver/source/MCR20Reg.h@0:f1d3878b8dd9, 2017-04-08 (annotated)

Committer:
vpcola
Date:
Sat Apr 08 14:45:51 2017 +0000
Revision:
0:f1d3878b8dd9
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
vpcola 0:f1d3878b8dd9 1 /*!
vpcola 0:f1d3878b8dd9 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
vpcola 0:f1d3878b8dd9 3 * All rights reserved.
vpcola 0:f1d3878b8dd9 4 *
vpcola 0:f1d3878b8dd9 5 * \file MCR20reg.h
vpcola 0:f1d3878b8dd9 6 * MCR20 Registers
vpcola 0:f1d3878b8dd9 7 *
vpcola 0:f1d3878b8dd9 8 * Redistribution and use in source and binary forms, with or without modification,
vpcola 0:f1d3878b8dd9 9 * are permitted provided that the following conditions are met:
vpcola 0:f1d3878b8dd9 10 *
vpcola 0:f1d3878b8dd9 11 * o Redistributions of source code must retain the above copyright notice, this list
vpcola 0:f1d3878b8dd9 12 * of conditions and the following disclaimer.
vpcola 0:f1d3878b8dd9 13 *
vpcola 0:f1d3878b8dd9 14 * o Redistributions in binary form must reproduce the above copyright notice, this
vpcola 0:f1d3878b8dd9 15 * list of conditions and the following disclaimer in the documentation and/or
vpcola 0:f1d3878b8dd9 16 * other materials provided with the distribution.
vpcola 0:f1d3878b8dd9 17 *
vpcola 0:f1d3878b8dd9 18 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
vpcola 0:f1d3878b8dd9 19 * contributors may be used to endorse or promote products derived from this
vpcola 0:f1d3878b8dd9 20 * software without specific prior written permission.
vpcola 0:f1d3878b8dd9 21 *
vpcola 0:f1d3878b8dd9 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
vpcola 0:f1d3878b8dd9 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
vpcola 0:f1d3878b8dd9 24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
vpcola 0:f1d3878b8dd9 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
vpcola 0:f1d3878b8dd9 26 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
vpcola 0:f1d3878b8dd9 27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
vpcola 0:f1d3878b8dd9 28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
vpcola 0:f1d3878b8dd9 29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
vpcola 0:f1d3878b8dd9 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
vpcola 0:f1d3878b8dd9 31 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
vpcola 0:f1d3878b8dd9 32 */
vpcola 0:f1d3878b8dd9 33
vpcola 0:f1d3878b8dd9 34 #ifndef __MCR20_REG_H__
vpcola 0:f1d3878b8dd9 35 #define __MCR20_REG_H__
vpcola 0:f1d3878b8dd9 36 /*****************************************************************************
vpcola 0:f1d3878b8dd9 37 * INCLUDED HEADERS *
vpcola 0:f1d3878b8dd9 38 *---------------------------------------------------------------------------*
vpcola 0:f1d3878b8dd9 39 * Add to this section all the headers that this module needs to include. *
vpcola 0:f1d3878b8dd9 40 * Note that it is not a good practice to include header files into header *
vpcola 0:f1d3878b8dd9 41 * files, so use this section only if there is no other better solution. *
vpcola 0:f1d3878b8dd9 42 *---------------------------------------------------------------------------*
vpcola 0:f1d3878b8dd9 43 *****************************************************************************/
vpcola 0:f1d3878b8dd9 44
vpcola 0:f1d3878b8dd9 45 /****************************************************************************/
vpcola 0:f1d3878b8dd9 46 /* Transceiver SPI Registers */
vpcola 0:f1d3878b8dd9 47 /****************************************************************************/
vpcola 0:f1d3878b8dd9 48
vpcola 0:f1d3878b8dd9 49 #define TransceiverSPI_IARIndexReg (0x3E)
vpcola 0:f1d3878b8dd9 50
vpcola 0:f1d3878b8dd9 51 #define TransceiverSPI_ReadSelect (1<<7)
vpcola 0:f1d3878b8dd9 52 #define TransceiverSPI_WriteSelect (0<<7)
vpcola 0:f1d3878b8dd9 53 #define TransceiverSPI_RegisterAccessSelect (0<<6)
vpcola 0:f1d3878b8dd9 54 #define TransceiverSPI_PacketBuffAccessSelect (1<<6)
vpcola 0:f1d3878b8dd9 55 #define TransceiverSPI_PacketBuffBurstModeSelect (0<<5)
vpcola 0:f1d3878b8dd9 56 #define TransceiverSPI_PacketBuffByteModeSelect (1<<5)
vpcola 0:f1d3878b8dd9 57
vpcola 0:f1d3878b8dd9 58 #define TransceiverSPI_DirectRegisterAddressMask (0x3F)
vpcola 0:f1d3878b8dd9 59
vpcola 0:f1d3878b8dd9 60 #define IRQSTS1 0x00
vpcola 0:f1d3878b8dd9 61 #define IRQSTS2 0x01
vpcola 0:f1d3878b8dd9 62 #define IRQSTS3 0x02
vpcola 0:f1d3878b8dd9 63 #define PHY_CTRL1 0x03
vpcola 0:f1d3878b8dd9 64 #define PHY_CTRL2 0x04
vpcola 0:f1d3878b8dd9 65 #define PHY_CTRL3 0x05
vpcola 0:f1d3878b8dd9 66 #define RX_FRM_LEN 0x06
vpcola 0:f1d3878b8dd9 67 #define PHY_CTRL4 0x07
vpcola 0:f1d3878b8dd9 68 #define SRC_CTRL 0x08
vpcola 0:f1d3878b8dd9 69 #define SRC_ADDRS_SUM_LSB 0x09
vpcola 0:f1d3878b8dd9 70 #define SRC_ADDRS_SUM_MSB 0x0A
vpcola 0:f1d3878b8dd9 71 #define CCA1_ED_FNL 0x0B
vpcola 0:f1d3878b8dd9 72 #define EVENT_TMR_LSB 0x0C
vpcola 0:f1d3878b8dd9 73 #define EVENT_TMR_MSB 0x0D
vpcola 0:f1d3878b8dd9 74 #define EVENT_TMR_USB 0x0E
vpcola 0:f1d3878b8dd9 75 #define TIMESTAMP_LSB 0x0F
vpcola 0:f1d3878b8dd9 76 #define TIMESTAMP_MSB 0x10
vpcola 0:f1d3878b8dd9 77 #define TIMESTAMP_USB 0x11
vpcola 0:f1d3878b8dd9 78 #define T3CMP_LSB 0x12
vpcola 0:f1d3878b8dd9 79 #define T3CMP_MSB 0x13
vpcola 0:f1d3878b8dd9 80 #define T3CMP_USB 0x14
vpcola 0:f1d3878b8dd9 81 #define T2PRIMECMP_LSB 0x15
vpcola 0:f1d3878b8dd9 82 #define T2PRIMECMP_MSB 0x16
vpcola 0:f1d3878b8dd9 83 #define T1CMP_LSB 0x17
vpcola 0:f1d3878b8dd9 84 #define T1CMP_MSB 0x18
vpcola 0:f1d3878b8dd9 85 #define T1CMP_USB 0x19
vpcola 0:f1d3878b8dd9 86 #define T2CMP_LSB 0x1A
vpcola 0:f1d3878b8dd9 87 #define T2CMP_MSB 0x1B
vpcola 0:f1d3878b8dd9 88 #define T2CMP_USB 0x1C
vpcola 0:f1d3878b8dd9 89 #define T4CMP_LSB 0x1D
vpcola 0:f1d3878b8dd9 90 #define T4CMP_MSB 0x1E
vpcola 0:f1d3878b8dd9 91 #define T4CMP_USB 0x1F
vpcola 0:f1d3878b8dd9 92 #define PLL_INT0 0x20
vpcola 0:f1d3878b8dd9 93 #define PLL_FRAC0_LSB 0x21
vpcola 0:f1d3878b8dd9 94 #define PLL_FRAC0_MSB 0x22
vpcola 0:f1d3878b8dd9 95 #define PA_PWR 0x23
vpcola 0:f1d3878b8dd9 96 #define SEQ_STATE 0x24
vpcola 0:f1d3878b8dd9 97 #define LQI_VALUE 0x25
vpcola 0:f1d3878b8dd9 98 #define RSSI_CCA_CONT 0x26
vpcola 0:f1d3878b8dd9 99 //-------------- 0x27
vpcola 0:f1d3878b8dd9 100 #define ASM_CTRL1 0x28
vpcola 0:f1d3878b8dd9 101 #define ASM_CTRL2 0x29
vpcola 0:f1d3878b8dd9 102 #define ASM_DATA_0 0x2A
vpcola 0:f1d3878b8dd9 103 #define ASM_DATA_1 0x2B
vpcola 0:f1d3878b8dd9 104 #define ASM_DATA_2 0x2C
vpcola 0:f1d3878b8dd9 105 #define ASM_DATA_3 0x2D
vpcola 0:f1d3878b8dd9 106 #define ASM_DATA_4 0x2E
vpcola 0:f1d3878b8dd9 107 #define ASM_DATA_5 0x2F
vpcola 0:f1d3878b8dd9 108 #define ASM_DATA_6 0x30
vpcola 0:f1d3878b8dd9 109 #define ASM_DATA_7 0x31
vpcola 0:f1d3878b8dd9 110 #define ASM_DATA_8 0x32
vpcola 0:f1d3878b8dd9 111 #define ASM_DATA_9 0x33
vpcola 0:f1d3878b8dd9 112 #define ASM_DATA_A 0x34
vpcola 0:f1d3878b8dd9 113 #define ASM_DATA_B 0x35
vpcola 0:f1d3878b8dd9 114 #define ASM_DATA_C 0x36
vpcola 0:f1d3878b8dd9 115 #define ASM_DATA_D 0x37
vpcola 0:f1d3878b8dd9 116 #define ASM_DATA_E 0x38
vpcola 0:f1d3878b8dd9 117 #define ASM_DATA_F 0x39
vpcola 0:f1d3878b8dd9 118 //------------------- 0x3A
vpcola 0:f1d3878b8dd9 119 #define OVERWRITE_VER 0x3B
vpcola 0:f1d3878b8dd9 120 #define CLK_OUT_CTRL 0x3C
vpcola 0:f1d3878b8dd9 121 #define PWR_MODES 0x3D
vpcola 0:f1d3878b8dd9 122 #define IAR_INDEX 0x3E
vpcola 0:f1d3878b8dd9 123 #define IAR_DATA 0x3F
vpcola 0:f1d3878b8dd9 124
vpcola 0:f1d3878b8dd9 125
vpcola 0:f1d3878b8dd9 126 #define PART_ID 0x00
vpcola 0:f1d3878b8dd9 127 #define XTAL_TRIM 0x01
vpcola 0:f1d3878b8dd9 128 #define PMC_LP_TRIM 0x02
vpcola 0:f1d3878b8dd9 129 #define MACPANID0_LSB 0x03
vpcola 0:f1d3878b8dd9 130 #define MACPANID0_MSB 0x04
vpcola 0:f1d3878b8dd9 131 #define MACSHORTADDRS0_LSB 0x05
vpcola 0:f1d3878b8dd9 132 #define MACSHORTADDRS0_MSB 0x06
vpcola 0:f1d3878b8dd9 133 #define MACLONGADDRS0_0 0x07
vpcola 0:f1d3878b8dd9 134 #define MACLONGADDRS0_8 0x08
vpcola 0:f1d3878b8dd9 135 #define MACLONGADDRS0_16 0x09
vpcola 0:f1d3878b8dd9 136 #define MACLONGADDRS0_24 0x0A
vpcola 0:f1d3878b8dd9 137 #define MACLONGADDRS0_32 0x0B
vpcola 0:f1d3878b8dd9 138 #define MACLONGADDRS0_40 0x0C
vpcola 0:f1d3878b8dd9 139 #define MACLONGADDRS0_48 0x0D
vpcola 0:f1d3878b8dd9 140 #define MACLONGADDRS0_56 0x0E
vpcola 0:f1d3878b8dd9 141 #define RX_FRAME_FILTER 0x0F
vpcola 0:f1d3878b8dd9 142 #define PLL_INT1 0x10
vpcola 0:f1d3878b8dd9 143 #define PLL_FRAC1_LSB 0x11
vpcola 0:f1d3878b8dd9 144 #define PLL_FRAC1_MSB 0x12
vpcola 0:f1d3878b8dd9 145 #define MACPANID1_LSB 0x13
vpcola 0:f1d3878b8dd9 146 #define MACPANID1_MSB 0x14
vpcola 0:f1d3878b8dd9 147 #define MACSHORTADDRS1_LSB 0x15
vpcola 0:f1d3878b8dd9 148 #define MACSHORTADDRS1_MSB 0x16
vpcola 0:f1d3878b8dd9 149 #define MACLONGADDRS1_0 0x17
vpcola 0:f1d3878b8dd9 150 #define MACLONGADDRS1_8 0x18
vpcola 0:f1d3878b8dd9 151 #define MACLONGADDRS1_16 0x19
vpcola 0:f1d3878b8dd9 152 #define MACLONGADDRS1_24 0x1A
vpcola 0:f1d3878b8dd9 153 #define MACLONGADDRS1_32 0x1B
vpcola 0:f1d3878b8dd9 154 #define MACLONGADDRS1_40 0x1C
vpcola 0:f1d3878b8dd9 155 #define MACLONGADDRS1_48 0x1D
vpcola 0:f1d3878b8dd9 156 #define MACLONGADDRS1_56 0x1E
vpcola 0:f1d3878b8dd9 157 #define DUAL_PAN_CTRL 0x1F
vpcola 0:f1d3878b8dd9 158 #define DUAL_PAN_DWELL 0x20
vpcola 0:f1d3878b8dd9 159 #define DUAL_PAN_STS 0x21
vpcola 0:f1d3878b8dd9 160 #define CCA1_THRESH 0x22
vpcola 0:f1d3878b8dd9 161 #define CCA1_ED_OFFSET_COMP 0x23
vpcola 0:f1d3878b8dd9 162 #define LQI_OFFSET_COMP 0x24
vpcola 0:f1d3878b8dd9 163 #define CCA_CTRL 0x25
vpcola 0:f1d3878b8dd9 164 #define CCA2_CORR_PEAKS 0x26
vpcola 0:f1d3878b8dd9 165 #define CCA2_CORR_THRESH 0x27
vpcola 0:f1d3878b8dd9 166 #define TMR_PRESCALE 0x28
vpcola 0:f1d3878b8dd9 167 //---------------- 0x29
vpcola 0:f1d3878b8dd9 168 #define GPIO_DATA 0x2A
vpcola 0:f1d3878b8dd9 169 #define GPIO_DIR 0x2B
vpcola 0:f1d3878b8dd9 170 #define GPIO_PUL_EN 0x2C
vpcola 0:f1d3878b8dd9 171 #define GPIO_PUL_SEL 0x2D
vpcola 0:f1d3878b8dd9 172 #define GPIO_DS 0x2E
vpcola 0:f1d3878b8dd9 173 //-------------- 0x2F
vpcola 0:f1d3878b8dd9 174 #define ANT_PAD_CTRL 0x30
vpcola 0:f1d3878b8dd9 175 #define MISC_PAD_CTRL 0x31
vpcola 0:f1d3878b8dd9 176 #define BSM_CTRL 0x32
vpcola 0:f1d3878b8dd9 177 //--------------- 0x33
vpcola 0:f1d3878b8dd9 178 #define _RNG 0x34
vpcola 0:f1d3878b8dd9 179 #define RX_BYTE_COUNT 0x35
vpcola 0:f1d3878b8dd9 180 #define RX_WTR_MARK 0x36
vpcola 0:f1d3878b8dd9 181 #define SOFT_RESET 0x37
vpcola 0:f1d3878b8dd9 182 #define TXDELAY 0x38
vpcola 0:f1d3878b8dd9 183 #define ACKDELAY 0x39
vpcola 0:f1d3878b8dd9 184 #define SEQ_MGR_CTRL 0x3A
vpcola 0:f1d3878b8dd9 185 #define SEQ_MGR_STS 0x3B
vpcola 0:f1d3878b8dd9 186 #define SEQ_T_STS 0x3C
vpcola 0:f1d3878b8dd9 187 #define ABORT_STS 0x3D
vpcola 0:f1d3878b8dd9 188 #define CCCA_BUSY_CNT 0x3E
vpcola 0:f1d3878b8dd9 189 #define SRC_ADDR_CHECKSUM1 0x3F
vpcola 0:f1d3878b8dd9 190 #define SRC_ADDR_CHECKSUM2 0x40
vpcola 0:f1d3878b8dd9 191 #define SRC_TBL_VALID1 0x41
vpcola 0:f1d3878b8dd9 192 #define SRC_TBL_VALID2 0x42
vpcola 0:f1d3878b8dd9 193 #define FILTERFAIL_CODE1 0x43
vpcola 0:f1d3878b8dd9 194 #define FILTERFAIL_CODE2 0x44
vpcola 0:f1d3878b8dd9 195 #define SLOT_PRELOAD 0x45
vpcola 0:f1d3878b8dd9 196 //---------------- 0x46
vpcola 0:f1d3878b8dd9 197 #define CORR_VT 0x47
vpcola 0:f1d3878b8dd9 198 #define SYNC_CTRL 0x48
vpcola 0:f1d3878b8dd9 199 #define PN_LSB_0 0x49
vpcola 0:f1d3878b8dd9 200 #define PN_LSB_1 0x4A
vpcola 0:f1d3878b8dd9 201 #define PN_MSB_0 0x4B
vpcola 0:f1d3878b8dd9 202 #define PN_MSB_1 0x4C
vpcola 0:f1d3878b8dd9 203 #define CORR_NVAL 0x4D
vpcola 0:f1d3878b8dd9 204 #define TX_MODE_CTRL 0x4E
vpcola 0:f1d3878b8dd9 205 #define SNF_THR 0x4F
vpcola 0:f1d3878b8dd9 206 #define FAD_THR 0x50
vpcola 0:f1d3878b8dd9 207 #define ANT_AGC_CTRL 0x51
vpcola 0:f1d3878b8dd9 208 #define AGC_THR1 0x52
vpcola 0:f1d3878b8dd9 209 #define AGC_THR2 0x53
vpcola 0:f1d3878b8dd9 210 #define AGC_HYS 0x54
vpcola 0:f1d3878b8dd9 211 #define AFC 0x55
vpcola 0:f1d3878b8dd9 212 //--------------- 0x56
vpcola 0:f1d3878b8dd9 213 //--------------- 0x57
vpcola 0:f1d3878b8dd9 214 #define PHY_STS 0x58
vpcola 0:f1d3878b8dd9 215 #define RX_MAX_CORR 0x59
vpcola 0:f1d3878b8dd9 216 #define RX_MAX_PREAMBLE 0x5A
vpcola 0:f1d3878b8dd9 217 #define RSSI 0x5B
vpcola 0:f1d3878b8dd9 218 //--------------- 0x5C
vpcola 0:f1d3878b8dd9 219 //--------------- 0x5D
vpcola 0:f1d3878b8dd9 220 #define PLL_DIG_CTRL 0x5E
vpcola 0:f1d3878b8dd9 221 #define VCO_CAL 0x5F
vpcola 0:f1d3878b8dd9 222 #define VCO_BEST_DIFF 0x60
vpcola 0:f1d3878b8dd9 223 #define VCO_BIAS 0x61
vpcola 0:f1d3878b8dd9 224 #define KMOD_CTRL 0x62
vpcola 0:f1d3878b8dd9 225 #define KMOD_CAL 0x63
vpcola 0:f1d3878b8dd9 226 #define PA_CAL 0x64
vpcola 0:f1d3878b8dd9 227 #define PA_PWRCAL 0x65
vpcola 0:f1d3878b8dd9 228 #define ATT_RSSI1 0x66
vpcola 0:f1d3878b8dd9 229 #define ATT_RSSI2 0x67
vpcola 0:f1d3878b8dd9 230 #define RSSI_OFFSET 0x68
vpcola 0:f1d3878b8dd9 231 #define RSSI_SLOPE 0x69
vpcola 0:f1d3878b8dd9 232 #define RSSI_CAL1 0x6A
vpcola 0:f1d3878b8dd9 233 #define RSSI_CAL2 0x6B
vpcola 0:f1d3878b8dd9 234 //--------------- 0x6C
vpcola 0:f1d3878b8dd9 235 //--------------- 0x6D
vpcola 0:f1d3878b8dd9 236 #define XTAL_CTRL 0x6E
vpcola 0:f1d3878b8dd9 237 #define XTAL_COMP_MIN 0x6F
vpcola 0:f1d3878b8dd9 238 #define XTAL_COMP_MAX 0x70
vpcola 0:f1d3878b8dd9 239 #define XTAL_GM 0x71
vpcola 0:f1d3878b8dd9 240 //--------------- 0x72
vpcola 0:f1d3878b8dd9 241 //--------------- 0x73
vpcola 0:f1d3878b8dd9 242 #define LNA_TUNE 0x74
vpcola 0:f1d3878b8dd9 243 #define LNA_AGCGAIN 0x75
vpcola 0:f1d3878b8dd9 244 //--------------- 0x76
vpcola 0:f1d3878b8dd9 245 //--------------- 0x77
vpcola 0:f1d3878b8dd9 246 #define CHF_PMA_GAIN 0x78
vpcola 0:f1d3878b8dd9 247 #define CHF_IBUF 0x79
vpcola 0:f1d3878b8dd9 248 #define CHF_QBUF 0x7A
vpcola 0:f1d3878b8dd9 249 #define CHF_IRIN 0x7B
vpcola 0:f1d3878b8dd9 250 #define CHF_QRIN 0x7C
vpcola 0:f1d3878b8dd9 251 #define CHF_IL 0x7D
vpcola 0:f1d3878b8dd9 252 #define CHF_QL 0x7E
vpcola 0:f1d3878b8dd9 253 #define CHF_CC1 0x7F
vpcola 0:f1d3878b8dd9 254 #define CHF_CCL 0x80
vpcola 0:f1d3878b8dd9 255 #define CHF_CC2 0x81
vpcola 0:f1d3878b8dd9 256 #define CHF_IROUT 0x82
vpcola 0:f1d3878b8dd9 257 #define CHF_QROUT 0x83
vpcola 0:f1d3878b8dd9 258 //--------------- 0x84
vpcola 0:f1d3878b8dd9 259 //--------------- 0x85
vpcola 0:f1d3878b8dd9 260 #define RSSI_CTRL 0x86
vpcola 0:f1d3878b8dd9 261 //--------------- 0x87
vpcola 0:f1d3878b8dd9 262 //--------------- 0x88
vpcola 0:f1d3878b8dd9 263 #define PA_BIAS 0x89
vpcola 0:f1d3878b8dd9 264 #define PA_TUNING 0x8A
vpcola 0:f1d3878b8dd9 265 //--------------- 0x8B
vpcola 0:f1d3878b8dd9 266 //--------------- 0x8C
vpcola 0:f1d3878b8dd9 267 #define PMC_HP_TRIM 0x8D
vpcola 0:f1d3878b8dd9 268 #define VREGA_TRIM 0x8E
vpcola 0:f1d3878b8dd9 269 //--------------- 0x8F
vpcola 0:f1d3878b8dd9 270 //--------------- 0x90
vpcola 0:f1d3878b8dd9 271 #define VCO_CTRL1 0x91
vpcola 0:f1d3878b8dd9 272 #define VCO_CTRL2 0x92
vpcola 0:f1d3878b8dd9 273 //--------------- 0x93
vpcola 0:f1d3878b8dd9 274 //--------------- 0x94
vpcola 0:f1d3878b8dd9 275 #define ANA_SPARE_OUT1 0x95
vpcola 0:f1d3878b8dd9 276 #define ANA_SPARE_OUT2 0x96
vpcola 0:f1d3878b8dd9 277 #define ANA_SPARE_IN 0x97
vpcola 0:f1d3878b8dd9 278 #define MISCELLANEOUS 0x98
vpcola 0:f1d3878b8dd9 279 //--------------- 0x99
vpcola 0:f1d3878b8dd9 280 #define SEQ_MGR_OVRD0 0x9A
vpcola 0:f1d3878b8dd9 281 #define SEQ_MGR_OVRD1 0x9B
vpcola 0:f1d3878b8dd9 282 #define SEQ_MGR_OVRD2 0x9C
vpcola 0:f1d3878b8dd9 283 #define SEQ_MGR_OVRD3 0x9D
vpcola 0:f1d3878b8dd9 284 #define SEQ_MGR_OVRD4 0x9E
vpcola 0:f1d3878b8dd9 285 #define SEQ_MGR_OVRD5 0x9F
vpcola 0:f1d3878b8dd9 286 #define SEQ_MGR_OVRD6 0xA0
vpcola 0:f1d3878b8dd9 287 #define SEQ_MGR_OVRD7 0xA1
vpcola 0:f1d3878b8dd9 288 //--------------- 0xA2
vpcola 0:f1d3878b8dd9 289 #define TESTMODE_CTRL 0xA3
vpcola 0:f1d3878b8dd9 290 #define DTM_CTRL1 0xA4
vpcola 0:f1d3878b8dd9 291 #define DTM_CTRL2 0xA5
vpcola 0:f1d3878b8dd9 292 #define ATM_CTRL1 0xA6
vpcola 0:f1d3878b8dd9 293 #define ATM_CTRL2 0xA7
vpcola 0:f1d3878b8dd9 294 #define ATM_CTRL3 0xA8
vpcola 0:f1d3878b8dd9 295 //--------------- 0xA9
vpcola 0:f1d3878b8dd9 296 #define LIM_FE_TEST_CTRL 0xAA
vpcola 0:f1d3878b8dd9 297 #define CHF_TEST_CTRL 0xAB
vpcola 0:f1d3878b8dd9 298 #define VCO_TEST_CTRL 0xAC
vpcola 0:f1d3878b8dd9 299 #define PLL_TEST_CTRL 0xAD
vpcola 0:f1d3878b8dd9 300 #define PA_TEST_CTRL 0xAE
vpcola 0:f1d3878b8dd9 301 #define PMC_TEST_CTRL 0xAF
vpcola 0:f1d3878b8dd9 302 #define SCAN_DTM_PROTECT_1 0xFE
vpcola 0:f1d3878b8dd9 303 #define SCAN_DTM_PROTECT_0 0xFF
vpcola 0:f1d3878b8dd9 304
vpcola 0:f1d3878b8dd9 305 // IRQSTS1 bits
vpcola 0:f1d3878b8dd9 306 #define cIRQSTS1_RX_FRM_PEND (1<<7)
vpcola 0:f1d3878b8dd9 307 #define cIRQSTS1_PLL_UNLOCK_IRQ (1<<6)
vpcola 0:f1d3878b8dd9 308 #define cIRQSTS1_FILTERFAIL_IRQ (1<<5)
vpcola 0:f1d3878b8dd9 309 #define cIRQSTS1_RXWTRMRKIRQ (1<<4)
vpcola 0:f1d3878b8dd9 310 #define cIRQSTS1_CCAIRQ (1<<3)
vpcola 0:f1d3878b8dd9 311 #define cIRQSTS1_RXIRQ (1<<2)
vpcola 0:f1d3878b8dd9 312 #define cIRQSTS1_TXIRQ (1<<1)
vpcola 0:f1d3878b8dd9 313 #define cIRQSTS1_SEQIRQ (1<<0)
vpcola 0:f1d3878b8dd9 314
vpcola 0:f1d3878b8dd9 315 typedef union regIRQSTS1_tag{
vpcola 0:f1d3878b8dd9 316 uint8_t byte;
vpcola 0:f1d3878b8dd9 317 struct{
vpcola 0:f1d3878b8dd9 318 uint8_t SEQIRQ:1;
vpcola 0:f1d3878b8dd9 319 uint8_t TXIRQ:1;
vpcola 0:f1d3878b8dd9 320 uint8_t RXIRQ:1;
vpcola 0:f1d3878b8dd9 321 uint8_t CCAIRQ:1;
vpcola 0:f1d3878b8dd9 322 uint8_t RXWTRMRKIRQ:1;
vpcola 0:f1d3878b8dd9 323 uint8_t FILTERFAIL_IRQ:1;
vpcola 0:f1d3878b8dd9 324 uint8_t PLL_UNLOCK_IRQ:1;
vpcola 0:f1d3878b8dd9 325 uint8_t RX_FRM_PEND:1;
vpcola 0:f1d3878b8dd9 326 }bit;
vpcola 0:f1d3878b8dd9 327 } regIRQSTS1_t;
vpcola 0:f1d3878b8dd9 328
vpcola 0:f1d3878b8dd9 329 // IRQSTS2 bits
vpcola 0:f1d3878b8dd9 330 #define cIRQSTS2_CRCVALID (1<<7)
vpcola 0:f1d3878b8dd9 331 #define cIRQSTS2_CCA (1<<6)
vpcola 0:f1d3878b8dd9 332 #define cIRQSTS2_SRCADDR (1<<5)
vpcola 0:f1d3878b8dd9 333 #define cIRQSTS2_PI (1<<4)
vpcola 0:f1d3878b8dd9 334 #define cIRQSTS2_TMRSTATUS (1<<3)
vpcola 0:f1d3878b8dd9 335 #define cIRQSTS2_ASM_IRQ (1<<2)
vpcola 0:f1d3878b8dd9 336 #define cIRQSTS2_PB_ERR_IRQ (1<<1)
vpcola 0:f1d3878b8dd9 337 #define cIRQSTS2_WAKE_IRQ (1<<0)
vpcola 0:f1d3878b8dd9 338
vpcola 0:f1d3878b8dd9 339 typedef union regIRQSTS2_tag{
vpcola 0:f1d3878b8dd9 340 uint8_t byte;
vpcola 0:f1d3878b8dd9 341 struct{
vpcola 0:f1d3878b8dd9 342 uint8_t WAKE_IRQ:1;
vpcola 0:f1d3878b8dd9 343 uint8_t PB_ERR_IRQ:1;
vpcola 0:f1d3878b8dd9 344 uint8_t ASM_IRQ:1;
vpcola 0:f1d3878b8dd9 345 uint8_t TMRSTATUS:1;
vpcola 0:f1d3878b8dd9 346 uint8_t PI:1;
vpcola 0:f1d3878b8dd9 347 uint8_t SRCADDR:1;
vpcola 0:f1d3878b8dd9 348 uint8_t CCA:1;
vpcola 0:f1d3878b8dd9 349 uint8_t CRCVALID:1;
vpcola 0:f1d3878b8dd9 350 }bit;
vpcola 0:f1d3878b8dd9 351 } regIRQSTS2_t;
vpcola 0:f1d3878b8dd9 352
vpcola 0:f1d3878b8dd9 353 // IRQSTS3 bits
vpcola 0:f1d3878b8dd9 354 #define cIRQSTS3_TMR4MSK (1<<7)
vpcola 0:f1d3878b8dd9 355 #define cIRQSTS3_TMR3MSK (1<<6)
vpcola 0:f1d3878b8dd9 356 #define cIRQSTS3_TMR2MSK (1<<5)
vpcola 0:f1d3878b8dd9 357 #define cIRQSTS3_TMR1MSK (1<<4)
vpcola 0:f1d3878b8dd9 358 #define cIRQSTS3_TMR4IRQ (1<<3)
vpcola 0:f1d3878b8dd9 359 #define cIRQSTS3_TMR3IRQ (1<<2)
vpcola 0:f1d3878b8dd9 360 #define cIRQSTS3_TMR2IRQ (1<<1)
vpcola 0:f1d3878b8dd9 361 #define cIRQSTS3_TMR1IRQ (1<<0)
vpcola 0:f1d3878b8dd9 362
vpcola 0:f1d3878b8dd9 363 typedef union regIRQSTS3_tag{
vpcola 0:f1d3878b8dd9 364 uint8_t byte;
vpcola 0:f1d3878b8dd9 365 struct{
vpcola 0:f1d3878b8dd9 366 uint8_t TMR1IRQ:1;
vpcola 0:f1d3878b8dd9 367 uint8_t TMR2IRQ:1;
vpcola 0:f1d3878b8dd9 368 uint8_t TMR3IRQ:1;
vpcola 0:f1d3878b8dd9 369 uint8_t TMR4IRQ:1;
vpcola 0:f1d3878b8dd9 370 uint8_t TMR1MSK:1;
vpcola 0:f1d3878b8dd9 371 uint8_t TMR2MSK:1;
vpcola 0:f1d3878b8dd9 372 uint8_t TMR3MSK:1;
vpcola 0:f1d3878b8dd9 373 uint8_t TMR4MSK:1;
vpcola 0:f1d3878b8dd9 374 }bit;
vpcola 0:f1d3878b8dd9 375 } regIRQSTS3_t;
vpcola 0:f1d3878b8dd9 376
vpcola 0:f1d3878b8dd9 377 // PHY_CTRL1 bits
vpcola 0:f1d3878b8dd9 378 #define cPHY_CTRL1_TMRTRIGEN (1<<7)
vpcola 0:f1d3878b8dd9 379 #define cPHY_CTRL1_SLOTTED (1<<6)
vpcola 0:f1d3878b8dd9 380 #define cPHY_CTRL1_CCABFRTX (1<<5)
vpcola 0:f1d3878b8dd9 381 #define cPHY_CTRL1_RXACKRQD (1<<4)
vpcola 0:f1d3878b8dd9 382 #define cPHY_CTRL1_AUTOACK (1<<3)
vpcola 0:f1d3878b8dd9 383 #define cPHY_CTRL1_XCVSEQ (7<<0)
vpcola 0:f1d3878b8dd9 384
vpcola 0:f1d3878b8dd9 385 typedef union regPHY_CTRL1_tag{
vpcola 0:f1d3878b8dd9 386 uint8_t byte;
vpcola 0:f1d3878b8dd9 387 struct{
vpcola 0:f1d3878b8dd9 388 uint8_t XCVSEQ:3;
vpcola 0:f1d3878b8dd9 389 uint8_t AUTOACK:1;
vpcola 0:f1d3878b8dd9 390 uint8_t RXACKRQD:1;
vpcola 0:f1d3878b8dd9 391 uint8_t CCABFRTX:1;
vpcola 0:f1d3878b8dd9 392 uint8_t SLOTTED:1;
vpcola 0:f1d3878b8dd9 393 uint8_t TMRTRIGEN:1;
vpcola 0:f1d3878b8dd9 394 }bit;
vpcola 0:f1d3878b8dd9 395 } regPHY_CTRL1_t;
vpcola 0:f1d3878b8dd9 396
vpcola 0:f1d3878b8dd9 397 // PHY_CTRL2 bits
vpcola 0:f1d3878b8dd9 398 #define cPHY_CTRL2_CRC_MSK (1<<7)
vpcola 0:f1d3878b8dd9 399 #define cPHY_CTRL2_PLL_UNLOCK_MSK (1<<6)
vpcola 0:f1d3878b8dd9 400 #define cPHY_CTRL2_FILTERFAIL_MSK (1<<5)
vpcola 0:f1d3878b8dd9 401 #define cPHY_CTRL2_RX_WMRK_MSK (1<<4)
vpcola 0:f1d3878b8dd9 402 #define cPHY_CTRL2_CCAMSK (1<<3)
vpcola 0:f1d3878b8dd9 403 #define cPHY_CTRL2_RXMSK (1<<2)
vpcola 0:f1d3878b8dd9 404 #define cPHY_CTRL2_TXMSK (1<<1)
vpcola 0:f1d3878b8dd9 405 #define cPHY_CTRL2_SEQMSK (1<<0)
vpcola 0:f1d3878b8dd9 406
vpcola 0:f1d3878b8dd9 407 typedef union regPHY_CTRL2_tag{
vpcola 0:f1d3878b8dd9 408 uint8_t byte;
vpcola 0:f1d3878b8dd9 409 struct{
vpcola 0:f1d3878b8dd9 410 uint8_t SEQMSK:1;
vpcola 0:f1d3878b8dd9 411 uint8_t TXMSK:1;
vpcola 0:f1d3878b8dd9 412 uint8_t RXMSK:1;
vpcola 0:f1d3878b8dd9 413 uint8_t CCAMSK:1;
vpcola 0:f1d3878b8dd9 414 uint8_t RX_WMRK_MSK:1;
vpcola 0:f1d3878b8dd9 415 uint8_t FILTERFAIL_MSK:1;
vpcola 0:f1d3878b8dd9 416 uint8_t PLL_UNLOCK_MSK:1;
vpcola 0:f1d3878b8dd9 417 uint8_t CRC_MSK:1;
vpcola 0:f1d3878b8dd9 418 }bit;
vpcola 0:f1d3878b8dd9 419 } regPHY_CTRL2_t;
vpcola 0:f1d3878b8dd9 420
vpcola 0:f1d3878b8dd9 421 // PHY_CTRL3 bits
vpcola 0:f1d3878b8dd9 422 #define cPHY_CTRL3_TMR4CMP_EN (1<<7)
vpcola 0:f1d3878b8dd9 423 #define cPHY_CTRL3_TMR3CMP_EN (1<<6)
vpcola 0:f1d3878b8dd9 424 #define cPHY_CTRL3_TMR2CMP_EN (1<<5)
vpcola 0:f1d3878b8dd9 425 #define cPHY_CTRL3_TMR1CMP_EN (1<<4)
vpcola 0:f1d3878b8dd9 426 #define cPHY_CTRL3_ASM_MSK (1<<2)
vpcola 0:f1d3878b8dd9 427 #define cPHY_CTRL3_PB_ERR_MSK (1<<1)
vpcola 0:f1d3878b8dd9 428 #define cPHY_CTRL3_WAKE_MSK (1<<0)
vpcola 0:f1d3878b8dd9 429
vpcola 0:f1d3878b8dd9 430 typedef union regPHY_CTRL3_tag{
vpcola 0:f1d3878b8dd9 431 uint8_t byte;
vpcola 0:f1d3878b8dd9 432 struct{
vpcola 0:f1d3878b8dd9 433 uint8_t WAKE_MSK:1;
vpcola 0:f1d3878b8dd9 434 uint8_t PB_ERR_MSK:1;
vpcola 0:f1d3878b8dd9 435 uint8_t ASM_MSK:1;
vpcola 0:f1d3878b8dd9 436 uint8_t RESERVED:1;
vpcola 0:f1d3878b8dd9 437 uint8_t TMR1CMP_EN:1;
vpcola 0:f1d3878b8dd9 438 uint8_t TMR2CMP_EN:1;
vpcola 0:f1d3878b8dd9 439 uint8_t TMR3CMP_EN:1;
vpcola 0:f1d3878b8dd9 440 uint8_t TMR4CMP_EN:1;
vpcola 0:f1d3878b8dd9 441 }bit;
vpcola 0:f1d3878b8dd9 442 } regPHY_CTRL3_t;
vpcola 0:f1d3878b8dd9 443
vpcola 0:f1d3878b8dd9 444 // RX_FRM_LEN bits
vpcola 0:f1d3878b8dd9 445 #define cRX_FRAME_LENGTH (0x7F)
vpcola 0:f1d3878b8dd9 446
vpcola 0:f1d3878b8dd9 447 // PHY_CTRL4 bits
vpcola 0:f1d3878b8dd9 448 #define cPHY_CTRL4_TRCV_MSK (1<<7)
vpcola 0:f1d3878b8dd9 449 #define cPHY_CTRL4_TC3TMOUT (1<<6)
vpcola 0:f1d3878b8dd9 450 #define cPHY_CTRL4_PANCORDNTR0 (1<<5)
vpcola 0:f1d3878b8dd9 451 #define cPHY_CTRL4_CCATYPE (3<<0)
vpcola 0:f1d3878b8dd9 452 #define cPHY_CTRL4_CCATYPE_Shift_c (3)
vpcola 0:f1d3878b8dd9 453 #define cPHY_CTRL4_TMRLOAD (1<<2)
vpcola 0:f1d3878b8dd9 454 #define cPHY_CTRL4_PROMISCUOUS (1<<1)
vpcola 0:f1d3878b8dd9 455 #define cPHY_CTRL4_TC2PRIME_EN (1<<0)
vpcola 0:f1d3878b8dd9 456
vpcola 0:f1d3878b8dd9 457 typedef union regPHY_CTRL4_tag{
vpcola 0:f1d3878b8dd9 458 uint8_t byte;
vpcola 0:f1d3878b8dd9 459 struct{
vpcola 0:f1d3878b8dd9 460 uint8_t TC2PRIME_EN:1;
vpcola 0:f1d3878b8dd9 461 uint8_t PROMISCUOUS:1;
vpcola 0:f1d3878b8dd9 462 uint8_t TMRLOAD:1;
vpcola 0:f1d3878b8dd9 463 uint8_t CCATYPE:2;
vpcola 0:f1d3878b8dd9 464 uint8_t PANCORDNTR0:1;
vpcola 0:f1d3878b8dd9 465 uint8_t TC3TMOUT:1;
vpcola 0:f1d3878b8dd9 466 uint8_t TRCV_MSK:1;
vpcola 0:f1d3878b8dd9 467 }bit;
vpcola 0:f1d3878b8dd9 468 } regPHY_CTRL4_t;
vpcola 0:f1d3878b8dd9 469
vpcola 0:f1d3878b8dd9 470 // SRC_CTRL bits
vpcola 0:f1d3878b8dd9 471 #define cSRC_CTRL_INDEX (0x0F)
vpcola 0:f1d3878b8dd9 472 #define cSRC_CTRL_INDEX_Shift_c (4)
vpcola 0:f1d3878b8dd9 473 #define cSRC_CTRL_ACK_FRM_PND (1<<3)
vpcola 0:f1d3878b8dd9 474 #define cSRC_CTRL_SRCADDR_EN (1<<2)
vpcola 0:f1d3878b8dd9 475 #define cSRC_CTRL_INDEX_EN (1<<1)
vpcola 0:f1d3878b8dd9 476 #define cSRC_CTRL_INDEX_DISABLE (1<<0)
vpcola 0:f1d3878b8dd9 477
vpcola 0:f1d3878b8dd9 478 typedef union regSRC_CTRL_tag{
vpcola 0:f1d3878b8dd9 479 uint8_t byte;
vpcola 0:f1d3878b8dd9 480 struct{
vpcola 0:f1d3878b8dd9 481 uint8_t INDEX_DISABLE:1;
vpcola 0:f1d3878b8dd9 482 uint8_t INDEX_EN:1;
vpcola 0:f1d3878b8dd9 483 uint8_t SRCADDR_EN:1;
vpcola 0:f1d3878b8dd9 484 uint8_t ACK_FRM_PND:1;
vpcola 0:f1d3878b8dd9 485 uint8_t INDEX:4;
vpcola 0:f1d3878b8dd9 486 }bit;
vpcola 0:f1d3878b8dd9 487 } regSRC_CTRL_t;
vpcola 0:f1d3878b8dd9 488
vpcola 0:f1d3878b8dd9 489 // ASM_CTRL1 bits
vpcola 0:f1d3878b8dd9 490 #define cASM_CTRL1_CLEAR (1<<7)
vpcola 0:f1d3878b8dd9 491 #define cASM_CTRL1_START (1<<6)
vpcola 0:f1d3878b8dd9 492 #define cASM_CTRL1_SELFTST (1<<5)
vpcola 0:f1d3878b8dd9 493 #define cASM_CTRL1_CTR (1<<4)
vpcola 0:f1d3878b8dd9 494 #define cASM_CTRL1_CBC (1<<3)
vpcola 0:f1d3878b8dd9 495 #define cASM_CTRL1_AES (1<<2)
vpcola 0:f1d3878b8dd9 496 #define cASM_CTRL1_LOAD_MAC (1<<1)
vpcola 0:f1d3878b8dd9 497
vpcola 0:f1d3878b8dd9 498 // ASM_CTRL2 bits
vpcola 0:f1d3878b8dd9 499 #define cASM_CTRL2_DATA_REG_TYPE_SEL (7)
vpcola 0:f1d3878b8dd9 500 #define cASM_CTRL2_DATA_REG_TYPE_SEL_Shift_c (5)
vpcola 0:f1d3878b8dd9 501 #define cASM_CTRL2_TSTPAS (1<<1)
vpcola 0:f1d3878b8dd9 502
vpcola 0:f1d3878b8dd9 503 // CLK_OUT_CTRL bits
vpcola 0:f1d3878b8dd9 504 #define cCLK_OUT_CTRL_EXTEND (1<<7)
vpcola 0:f1d3878b8dd9 505 #define cCLK_OUT_CTRL_HIZ (1<<6)
vpcola 0:f1d3878b8dd9 506 #define cCLK_OUT_CTRL_SR (1<<5)
vpcola 0:f1d3878b8dd9 507 #define cCLK_OUT_CTRL_DS (1<<4)
vpcola 0:f1d3878b8dd9 508 #define cCLK_OUT_CTRL_EN (1<<3)
vpcola 0:f1d3878b8dd9 509 #define cCLK_OUT_CTRL_DIV (7)
vpcola 0:f1d3878b8dd9 510
vpcola 0:f1d3878b8dd9 511 // PWR_MODES bits
vpcola 0:f1d3878b8dd9 512 #define cPWR_MODES_XTAL_READY (1<<5)
vpcola 0:f1d3878b8dd9 513 #define cPWR_MODES_XTALEN (1<<4)
vpcola 0:f1d3878b8dd9 514 #define cPWR_MODES_ASM_CLK_EN (1<<3)
vpcola 0:f1d3878b8dd9 515 #define cPWR_MODES_AUTODOZE (1<<1)
vpcola 0:f1d3878b8dd9 516 #define cPWR_MODES_PMC_MODE (1<<0)
vpcola 0:f1d3878b8dd9 517
vpcola 0:f1d3878b8dd9 518 // RX_FRAME_FILTER bits
vpcola 0:f1d3878b8dd9 519 #define cRX_FRAME_FLT_FRM_VER (0xC0)
vpcola 0:f1d3878b8dd9 520 #define cRX_FRAME_FLT_FRM_VER_Shift_c (6)
vpcola 0:f1d3878b8dd9 521 #define cRX_FRAME_FLT_ACTIVE_PROMISCUOUS (1<<5)
vpcola 0:f1d3878b8dd9 522 #define cRX_FRAME_FLT_NS_FT (1<<4)
vpcola 0:f1d3878b8dd9 523 #define cRX_FRAME_FLT_CMD_FT (1<<3)
vpcola 0:f1d3878b8dd9 524 #define cRX_FRAME_FLT_ACK_FT (1<<2)
vpcola 0:f1d3878b8dd9 525 #define cRX_FRAME_FLT_DATA_FT (1<<1)
vpcola 0:f1d3878b8dd9 526 #define cRX_FRAME_FLT_BEACON_FT (1<<0)
vpcola 0:f1d3878b8dd9 527
vpcola 0:f1d3878b8dd9 528 typedef union regRX_FRAME_FILTER_tag{
vpcola 0:f1d3878b8dd9 529 uint8_t byte;
vpcola 0:f1d3878b8dd9 530 struct{
vpcola 0:f1d3878b8dd9 531 uint8_t FRAME_FLT_BEACON_FT:1;
vpcola 0:f1d3878b8dd9 532 uint8_t FRAME_FLT_DATA_FT:1;
vpcola 0:f1d3878b8dd9 533 uint8_t FRAME_FLT_ACK_FT:1;
vpcola 0:f1d3878b8dd9 534 uint8_t FRAME_FLT_CMD_FT:1;
vpcola 0:f1d3878b8dd9 535 uint8_t FRAME_FLT_NS_FT:1;
vpcola 0:f1d3878b8dd9 536 uint8_t FRAME_FLT_ACTIVE_PROMISCUOUS:1;
vpcola 0:f1d3878b8dd9 537 uint8_t FRAME_FLT_FRM_VER:2;
vpcola 0:f1d3878b8dd9 538 }bit;
vpcola 0:f1d3878b8dd9 539 } regRX_FRAME_FILTER_t;
vpcola 0:f1d3878b8dd9 540
vpcola 0:f1d3878b8dd9 541 // DUAL_PAN_CTRL bits
vpcola 0:f1d3878b8dd9 542 #define cDUAL_PAN_CTRL_DUAL_PAN_SAM_LVL_MSK (0xF0)
vpcola 0:f1d3878b8dd9 543 #define cDUAL_PAN_CTRL_DUAL_PAN_SAM_LVL_Shift_c (4)
vpcola 0:f1d3878b8dd9 544 #define cDUAL_PAN_CTRL_CURRENT_NETWORK (1<<3)
vpcola 0:f1d3878b8dd9 545 #define cDUAL_PAN_CTRL_PANCORDNTR1 (1<<2)
vpcola 0:f1d3878b8dd9 546 #define cDUAL_PAN_CTRL_DUAL_PAN_AUTO (1<<1)
vpcola 0:f1d3878b8dd9 547 #define cDUAL_PAN_CTRL_ACTIVE_NETWORK (1<<0)
vpcola 0:f1d3878b8dd9 548
vpcola 0:f1d3878b8dd9 549 // DUAL_PAN_STS bits
vpcola 0:f1d3878b8dd9 550 #define cDUAL_PAN_STS_RECD_ON_PAN1 (1<<7)
vpcola 0:f1d3878b8dd9 551 #define cDUAL_PAN_STS_RECD_ON_PAN0 (1<<6)
vpcola 0:f1d3878b8dd9 552 #define cDUAL_PAN_STS_DUAL_PAN_REMAIN (0x3F)
vpcola 0:f1d3878b8dd9 553
vpcola 0:f1d3878b8dd9 554 // CCA_CTRL bits
vpcola 0:f1d3878b8dd9 555 #define cCCA_CTRL_AGC_FRZ_EN (1<<6)
vpcola 0:f1d3878b8dd9 556 #define cCCA_CTRL_CONT_RSSI_EN (1<<5)
vpcola 0:f1d3878b8dd9 557 #define cCCA_CTRL_LQI_RSSI_NOT_CORR (1<<4)
vpcola 0:f1d3878b8dd9 558 #define cCCA_CTRL_CCA3_AND_NOT_OR (1<<3)
vpcola 0:f1d3878b8dd9 559 #define cCCA_CTRL_POWER_COMP_EN_LQI (1<<2)
vpcola 0:f1d3878b8dd9 560 #define cCCA_CTRL_POWER_COMP_EN_ED (1<<1)
vpcola 0:f1d3878b8dd9 561 #define cCCA_CTRL_POWER_COMP_EN_CCA1 (1<<0)
vpcola 0:f1d3878b8dd9 562
vpcola 0:f1d3878b8dd9 563 // GPIO_DATA bits
vpcola 0:f1d3878b8dd9 564 #define cGPIO_DATA_7 (1<<7)
vpcola 0:f1d3878b8dd9 565 #define cGPIO_DATA_6 (1<<6)
vpcola 0:f1d3878b8dd9 566 #define cGPIO_DATA_5 (1<<5)
vpcola 0:f1d3878b8dd9 567 #define cGPIO_DATA_4 (1<<4)
vpcola 0:f1d3878b8dd9 568 #define cGPIO_DATA_3 (1<<3)
vpcola 0:f1d3878b8dd9 569 #define cGPIO_DATA_2 (1<<2)
vpcola 0:f1d3878b8dd9 570 #define cGPIO_DATA_1 (1<<1)
vpcola 0:f1d3878b8dd9 571 #define cGPIO_DATA_0 (1<<0)
vpcola 0:f1d3878b8dd9 572
vpcola 0:f1d3878b8dd9 573 // GPIO_DIR bits
vpcola 0:f1d3878b8dd9 574 #define cGPIO_DIR_7 (1<<7)
vpcola 0:f1d3878b8dd9 575 #define cGPIO_DIR_6 (1<<6)
vpcola 0:f1d3878b8dd9 576 #define cGPIO_DIR_5 (1<<5)
vpcola 0:f1d3878b8dd9 577 #define cGPIO_DIR_4 (1<<4)
vpcola 0:f1d3878b8dd9 578 #define cGPIO_DIR_3 (1<<3)
vpcola 0:f1d3878b8dd9 579 #define cGPIO_DIR_2 (1<<2)
vpcola 0:f1d3878b8dd9 580 #define cGPIO_DIR_1 (1<<1)
vpcola 0:f1d3878b8dd9 581 #define cGPIO_DIR_0 (1<<0)
vpcola 0:f1d3878b8dd9 582
vpcola 0:f1d3878b8dd9 583 // GPIO_PUL_EN bits
vpcola 0:f1d3878b8dd9 584 #define cGPIO_PUL_EN_7 (1<<7)
vpcola 0:f1d3878b8dd9 585 #define cGPIO_PUL_EN_6 (1<<6)
vpcola 0:f1d3878b8dd9 586 #define cGPIO_PUL_EN_5 (1<<5)
vpcola 0:f1d3878b8dd9 587 #define cGPIO_PUL_EN_4 (1<<4)
vpcola 0:f1d3878b8dd9 588 #define cGPIO_PUL_EN_3 (1<<3)
vpcola 0:f1d3878b8dd9 589 #define cGPIO_PUL_EN_2 (1<<2)
vpcola 0:f1d3878b8dd9 590 #define cGPIO_PUL_EN_1 (1<<1)
vpcola 0:f1d3878b8dd9 591 #define cGPIO_PUL_EN_0 (1<<0)
vpcola 0:f1d3878b8dd9 592
vpcola 0:f1d3878b8dd9 593 // GPIO_PUL_SEL bits
vpcola 0:f1d3878b8dd9 594 #define cGPIO_PUL_SEL_7 (1<<7)
vpcola 0:f1d3878b8dd9 595 #define cGPIO_PUL_SEL_6 (1<<6)
vpcola 0:f1d3878b8dd9 596 #define cGPIO_PUL_SEL_5 (1<<5)
vpcola 0:f1d3878b8dd9 597 #define cGPIO_PUL_SEL_4 (1<<4)
vpcola 0:f1d3878b8dd9 598 #define cGPIO_PUL_SEL_3 (1<<3)
vpcola 0:f1d3878b8dd9 599 #define cGPIO_PUL_SEL_2 (1<<2)
vpcola 0:f1d3878b8dd9 600 #define cGPIO_PUL_SEL_1 (1<<1)
vpcola 0:f1d3878b8dd9 601 #define cGPIO_PUL_SEL_0 (1<<0)
vpcola 0:f1d3878b8dd9 602
vpcola 0:f1d3878b8dd9 603 // GPIO_DS bits
vpcola 0:f1d3878b8dd9 604 #define cGPIO_DS_7 (1<<7)
vpcola 0:f1d3878b8dd9 605 #define cGPIO_DS_6 (1<<6)
vpcola 0:f1d3878b8dd9 606 #define cGPIO_DS_5 (1<<5)
vpcola 0:f1d3878b8dd9 607 #define cGPIO_DS_4 (1<<4)
vpcola 0:f1d3878b8dd9 608 #define cGPIO_DS_3 (1<<3)
vpcola 0:f1d3878b8dd9 609 #define cGPIO_DS_2 (1<<2)
vpcola 0:f1d3878b8dd9 610 #define cGPIO_DS_1 (1<<1)
vpcola 0:f1d3878b8dd9 611 #define cGPIO_DS_0 (1<<0)
vpcola 0:f1d3878b8dd9 612
vpcola 0:f1d3878b8dd9 613 // SPI_CTRL bits
vpcola 0:f1d3878b8dd9 614 //#define cSPI_CTRL_MISO_HIZ_EN (1<<1)
vpcola 0:f1d3878b8dd9 615 //#define cSPI_CTRL_PB_PROTECT (1<<0)
vpcola 0:f1d3878b8dd9 616
vpcola 0:f1d3878b8dd9 617 // ANT_PAD_CTRL bits
vpcola 0:f1d3878b8dd9 618 #define cANT_PAD_CTRL_ANTX_POL (0x0F)
vpcola 0:f1d3878b8dd9 619 #define cANT_PAD_CTRL_ANTX_POL_Shift_c (4)
vpcola 0:f1d3878b8dd9 620 #define cANT_PAD_CTRL_ANTX_CTRLMODE (1<<3)
vpcola 0:f1d3878b8dd9 621 #define cANT_PAD_CTRL_ANTX_HZ (1<<2)
vpcola 0:f1d3878b8dd9 622 #define cANT_PAD_CTRL_ANTX_EN (3)
vpcola 0:f1d3878b8dd9 623
vpcola 0:f1d3878b8dd9 624 // MISC_PAD_CTRL bits
vpcola 0:f1d3878b8dd9 625 #define cMISC_PAD_CTRL_MISO_HIZ_EN (1<<3)
vpcola 0:f1d3878b8dd9 626 #define cMISC_PAD_CTRL_IRQ_B_OD (1<<2)
vpcola 0:f1d3878b8dd9 627 #define cMISC_PAD_CTRL_NON_GPIO_DS (1<<1)
vpcola 0:f1d3878b8dd9 628 #define cMISC_PAD_CTRL_ANTX_CURR (1<<0)
vpcola 0:f1d3878b8dd9 629
vpcola 0:f1d3878b8dd9 630 // ANT_AGC_CTRL bits
vpcola 0:f1d3878b8dd9 631 #define cANT_AGC_CTRL_FAD_EN_Shift_c (0)
vpcola 0:f1d3878b8dd9 632 #define cANT_AGC_CTRL_FAD_EN_Mask_c (1<<cANT_AGC_CTRL_FAD_EN_Shift_c)
vpcola 0:f1d3878b8dd9 633 #define cANT_AGC_CTRL_ANTX_Shift_c (1)
vpcola 0:f1d3878b8dd9 634 #define cANT_AGC_CTRL_ANTX_Mask_c (1<<cANT_AGC_CTRL_ANTX_Shift_c)
vpcola 0:f1d3878b8dd9 635
vpcola 0:f1d3878b8dd9 636 // BSM_CTRL bits
vpcola 0:f1d3878b8dd9 637 #define cBSM_CTRL_BSM_EN (1<<0)
vpcola 0:f1d3878b8dd9 638
vpcola 0:f1d3878b8dd9 639 // SOFT_RESET bits
vpcola 0:f1d3878b8dd9 640 #define cSOFT_RESET_SOG_RST (1<<7)
vpcola 0:f1d3878b8dd9 641 #define cSOFT_RESET_REGS_RST (1<<4)
vpcola 0:f1d3878b8dd9 642 #define cSOFT_RESET_PLL_RST (1<<3)
vpcola 0:f1d3878b8dd9 643 #define cSOFT_RESET_TX_RST (1<<2)
vpcola 0:f1d3878b8dd9 644 #define cSOFT_RESET_RX_RST (1<<1)
vpcola 0:f1d3878b8dd9 645 #define cSOFT_RESET_SEQ_MGR_RST (1<<0)
vpcola 0:f1d3878b8dd9 646
vpcola 0:f1d3878b8dd9 647 // SEQ_MGR_CTRL bits
vpcola 0:f1d3878b8dd9 648 #define cSEQ_MGR_CTRL_SEQ_STATE_CTRL (3)
vpcola 0:f1d3878b8dd9 649 #define cSEQ_MGR_CTRL_SEQ_STATE_CTRL_Shift_c (6)
vpcola 0:f1d3878b8dd9 650 #define cSEQ_MGR_CTRL_NO_RX_RECYCLE (1<<5)
vpcola 0:f1d3878b8dd9 651 #define cSEQ_MGR_CTRL_LATCH_PREAMBLE (1<<4)
vpcola 0:f1d3878b8dd9 652 #define cSEQ_MGR_CTRL_EVENT_TMR_DO_NOT_LATCH (1<<3)
vpcola 0:f1d3878b8dd9 653 #define cSEQ_MGR_CTRL_CLR_NEW_SEQ_INHIBIT (1<<2)
vpcola 0:f1d3878b8dd9 654 #define cSEQ_MGR_CTRL_PSM_LOCK_DIS (1<<1)
vpcola 0:f1d3878b8dd9 655 #define cSEQ_MGR_CTRL_PLL_ABORT_OVRD (1<<0)
vpcola 0:f1d3878b8dd9 656
vpcola 0:f1d3878b8dd9 657 // SEQ_MGR_STS bits
vpcola 0:f1d3878b8dd9 658 #define cSEQ_MGR_STS_TMR2_SEQ_TRIG_ARMED (1<<7)
vpcola 0:f1d3878b8dd9 659 #define cSEQ_MGR_STS_RX_MODE (1<<6)
vpcola 0:f1d3878b8dd9 660 #define cSEQ_MGR_STS_RX_TIMEOUT_PENDING (1<<5)
vpcola 0:f1d3878b8dd9 661 #define cSEQ_MGR_STS_NEW_SEQ_INHIBIT (1<<4)
vpcola 0:f1d3878b8dd9 662 #define cSEQ_MGR_STS_SEQ_IDLE (1<<3)
vpcola 0:f1d3878b8dd9 663 #define cSEQ_MGR_STS_XCVSEQ_ACTUAL (7)
vpcola 0:f1d3878b8dd9 664
vpcola 0:f1d3878b8dd9 665 // ABORT_STS bits
vpcola 0:f1d3878b8dd9 666 #define cABORT_STS_PLL_ABORTED (1<<2)
vpcola 0:f1d3878b8dd9 667 #define cABORT_STS_TC3_ABORTED (1<<1)
vpcola 0:f1d3878b8dd9 668 #define cABORT_STS_SW_ABORTED (1<<0)
vpcola 0:f1d3878b8dd9 669
vpcola 0:f1d3878b8dd9 670 // FILTERFAIL_CODE2 bits
vpcola 0:f1d3878b8dd9 671 #define cFILTERFAIL_CODE2_PAN_SEL (1<<7)
vpcola 0:f1d3878b8dd9 672 #define cFILTERFAIL_CODE2_9_8 (3)
vpcola 0:f1d3878b8dd9 673
vpcola 0:f1d3878b8dd9 674 // PHY_STS bits
vpcola 0:f1d3878b8dd9 675 #define cPHY_STS_PLL_UNLOCK (1<<7)
vpcola 0:f1d3878b8dd9 676 #define cPHY_STS_PLL_LOCK_ERR (1<<6)
vpcola 0:f1d3878b8dd9 677 #define cPHY_STS_PLL_LOCK (1<<5)
vpcola 0:f1d3878b8dd9 678 #define cPHY_STS_CRCVALID (1<<3)
vpcola 0:f1d3878b8dd9 679 #define cPHY_STS_FILTERFAIL_FLAG_SEL (1<<2)
vpcola 0:f1d3878b8dd9 680 #define cPHY_STS_SFD_DET (1<<1)
vpcola 0:f1d3878b8dd9 681 #define cPHY_STS_PREAMBLE_DET (1<<0)
vpcola 0:f1d3878b8dd9 682
vpcola 0:f1d3878b8dd9 683 // TESTMODE_CTRL bits
vpcola 0:f1d3878b8dd9 684 #define cTEST_MODE_CTRL_HOT_ANT (1<<4)
vpcola 0:f1d3878b8dd9 685 #define cTEST_MODE_CTRL_IDEAL_RSSI_EN (1<<3)
vpcola 0:f1d3878b8dd9 686 #define cTEST_MODE_CTRL_IDEAL_PFC_EN (1<<2)
vpcola 0:f1d3878b8dd9 687 #define cTEST_MODE_CTRL_CONTINUOUS_EN (1<<1)
vpcola 0:f1d3878b8dd9 688 #define cTEST_MODE_CTRL_FPGA_EN (1<<0)
vpcola 0:f1d3878b8dd9 689
vpcola 0:f1d3878b8dd9 690 // DTM_CTRL1 bits
vpcola 0:f1d3878b8dd9 691 #define cDTM_CTRL1_ATM_LOCKED (1<<7)
vpcola 0:f1d3878b8dd9 692 #define cDTM_CTRL1_DTM_EN (1<<6)
vpcola 0:f1d3878b8dd9 693 #define cDTM_CTRL1_PAGE5 (1<<5)
vpcola 0:f1d3878b8dd9 694 #define cDTM_CTRL1_PAGE4 (1<<4)
vpcola 0:f1d3878b8dd9 695 #define cDTM_CTRL1_PAGE3 (1<<3)
vpcola 0:f1d3878b8dd9 696 #define cDTM_CTRL1_PAGE2 (1<<2)
vpcola 0:f1d3878b8dd9 697 #define cDTM_CTRL1_PAGE1 (1<<1)
vpcola 0:f1d3878b8dd9 698 #define cDTM_CTRL1_PAGE0 (1<<0)
vpcola 0:f1d3878b8dd9 699
vpcola 0:f1d3878b8dd9 700 // TX_MODE_CTRL
vpcola 0:f1d3878b8dd9 701 #define cTX_MODE_CTRL_TX_INV (1<<4)
vpcola 0:f1d3878b8dd9 702 #define cTX_MODE_CTRL_BT_EN (1<<3)
vpcola 0:f1d3878b8dd9 703 #define cTX_MODE_CTRL_DTS2 (1<<2)
vpcola 0:f1d3878b8dd9 704 #define cTX_MODE_CTRL_DTS1 (1<<1)
vpcola 0:f1d3878b8dd9 705 #define cTX_MODE_CTRL_DTS0 (1<<0)
vpcola 0:f1d3878b8dd9 706
vpcola 0:f1d3878b8dd9 707 #define cTX_MODE_CTRL_DTS_MASK (7)
vpcola 0:f1d3878b8dd9 708
vpcola 0:f1d3878b8dd9 709 // CLK_OUT_CTRL bits
vpcola 0:f1d3878b8dd9 710 #define cCLK_OUT_EXTEND (1<<7)
vpcola 0:f1d3878b8dd9 711 #define cCLK_OUT_HIZ (1<<6)
vpcola 0:f1d3878b8dd9 712 #define cCLK_OUT_SR (1<<5)
vpcola 0:f1d3878b8dd9 713 #define cCLK_OUT_DS (1<<4)
vpcola 0:f1d3878b8dd9 714 #define cCLK_OUT_EN (1<<3)
vpcola 0:f1d3878b8dd9 715 #define cCLK_OUT_DIV_Mask (7<<0)
vpcola 0:f1d3878b8dd9 716
vpcola 0:f1d3878b8dd9 717 #define gCLK_OUT_FREQ_32_MHz (0)
vpcola 0:f1d3878b8dd9 718 #define gCLK_OUT_FREQ_16_MHz (1)
vpcola 0:f1d3878b8dd9 719 #define gCLK_OUT_FREQ_8_MHz (2)
vpcola 0:f1d3878b8dd9 720 #define gCLK_OUT_FREQ_4_MHz (3)
vpcola 0:f1d3878b8dd9 721 #define gCLK_OUT_FREQ_1_MHz (4)
vpcola 0:f1d3878b8dd9 722 #define gCLK_OUT_FREQ_250_KHz (5)
vpcola 0:f1d3878b8dd9 723 #define gCLK_OUT_FREQ_62_5_KHz (6)
vpcola 0:f1d3878b8dd9 724 #define gCLK_OUT_FREQ_32_78_KHz (7)
vpcola 0:f1d3878b8dd9 725 #define gCLK_OUT_FREQ_DISABLE (8)
vpcola 0:f1d3878b8dd9 726
vpcola 0:f1d3878b8dd9 727
vpcola 0:f1d3878b8dd9 728
vpcola 0:f1d3878b8dd9 729
vpcola 0:f1d3878b8dd9 730 #endif /* __MCR20_REG_H__ */