Vergil Cola / Mbed OS MQTTGatewayK64

Fork of my MQTTGateway

Dependencies:   mbed-http

easy-connect/mcr20a-rf-driver/source/MCR20Overwrites.h@0:f1d3878b8dd9, 2017-04-08 (annotated)

Committer:
vpcola
Date:
Sat Apr 08 14:45:51 2017 +0000
Revision:
0:f1d3878b8dd9
Initial commit

Who changed what in which revision?

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vpcola 0:f1d3878b8dd9 1 /*!
vpcola 0:f1d3878b8dd9 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
vpcola 0:f1d3878b8dd9 3 * All rights reserved.
vpcola 0:f1d3878b8dd9 4 *
vpcola 0:f1d3878b8dd9 5 * \file MCR20Overwrites.h
vpcola 0:f1d3878b8dd9 6 * Description: Overwrites header file for MCR20 Register values
vpcola 0:f1d3878b8dd9 7 *
vpcola 0:f1d3878b8dd9 8 * Redistribution and use in source and binary forms, with or without modification,
vpcola 0:f1d3878b8dd9 9 * are permitted provided that the following conditions are met:
vpcola 0:f1d3878b8dd9 10 *
vpcola 0:f1d3878b8dd9 11 * o Redistributions of source code must retain the above copyright notice, this list
vpcola 0:f1d3878b8dd9 12 * of conditions and the following disclaimer.
vpcola 0:f1d3878b8dd9 13 *
vpcola 0:f1d3878b8dd9 14 * o Redistributions in binary form must reproduce the above copyright notice, this
vpcola 0:f1d3878b8dd9 15 * list of conditions and the following disclaimer in the documentation and/or
vpcola 0:f1d3878b8dd9 16 * other materials provided with the distribution.
vpcola 0:f1d3878b8dd9 17 *
vpcola 0:f1d3878b8dd9 18 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
vpcola 0:f1d3878b8dd9 19 * contributors may be used to endorse or promote products derived from this
vpcola 0:f1d3878b8dd9 20 * software without specific prior written permission.
vpcola 0:f1d3878b8dd9 21 *
vpcola 0:f1d3878b8dd9 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
vpcola 0:f1d3878b8dd9 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
vpcola 0:f1d3878b8dd9 24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
vpcola 0:f1d3878b8dd9 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
vpcola 0:f1d3878b8dd9 26 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
vpcola 0:f1d3878b8dd9 27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
vpcola 0:f1d3878b8dd9 28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
vpcola 0:f1d3878b8dd9 29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
vpcola 0:f1d3878b8dd9 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
vpcola 0:f1d3878b8dd9 31 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
vpcola 0:f1d3878b8dd9 32 */
vpcola 0:f1d3878b8dd9 33
vpcola 0:f1d3878b8dd9 34 #ifndef OVERWRITES_H_
vpcola 0:f1d3878b8dd9 35 #define OVERWRITES_H_
vpcola 0:f1d3878b8dd9 36
vpcola 0:f1d3878b8dd9 37 typedef struct overwrites_tag {
vpcola 0:f1d3878b8dd9 38 char address;
vpcola 0:f1d3878b8dd9 39 char data;
vpcola 0:f1d3878b8dd9 40 }overwrites_t;
vpcola 0:f1d3878b8dd9 41
vpcola 0:f1d3878b8dd9 42
vpcola 0:f1d3878b8dd9 43 /*****************************************************************************************************************/
vpcola 0:f1d3878b8dd9 44 // This file is created exclusively for use with the transceiver 2.0 silicon
vpcola 0:f1d3878b8dd9 45 // and is provided for the world to use. It contains a list of all
vpcola 0:f1d3878b8dd9 46 // known overwrite values. Overwrite values are non-default register
vpcola 0:f1d3878b8dd9 47 // values that configure the transceiver device to a more optimally performing
vpcola 0:f1d3878b8dd9 48 // posture. It is expected that low level software (i.e. PHY) will
vpcola 0:f1d3878b8dd9 49 // consume this file as a #include, and transfer the contents to the
vpcola 0:f1d3878b8dd9 50 // the indicated addresses in the transceiver's memory space. This file has
vpcola 0:f1d3878b8dd9 51 // at least one required entry, that being its own version current version
vpcola 0:f1d3878b8dd9 52 // number, to be stored at transceiver's location 0x3B the
vpcola 0:f1d3878b8dd9 53 // OVERWRITES_VERSION_NUMBER register. The RAM register is provided in
vpcola 0:f1d3878b8dd9 54 // the transceiver address space to assist in future debug efforts. The
vpcola 0:f1d3878b8dd9 55 // analyst may read this location (once device has been booted with
vpcola 0:f1d3878b8dd9 56 // mysterious software) and have a good indication of what register
vpcola 0:f1d3878b8dd9 57 // overwrites were performed (with all versions of the overwrites.h file
vpcola 0:f1d3878b8dd9 58 // being archived forever at the Compass location shown above.
vpcola 0:f1d3878b8dd9 59 //
vpcola 0:f1d3878b8dd9 60 // The transceiver has an indirect register (IAR) space. Write access to this space
vpcola 0:f1d3878b8dd9 61 // requires 3 or more writes:
vpcola 0:f1d3878b8dd9 62 // 1st) the first write is an index value to the indirect (write Bit7=0, register access Bit 6=0) + 0x3E
vpcola 0:f1d3878b8dd9 63 // 2nd) IAR Register #0x00 - 0xFF.
vpcola 0:f1d3878b8dd9 64 // 3rd) The data to write
vpcola 0:f1d3878b8dd9 65 // nth) Burst mode additional data if required.
vpcola 0:f1d3878b8dd9 66 //
vpcola 0:f1d3878b8dd9 67 // Write access to direct space requires only a single address, data pair.
vpcola 0:f1d3878b8dd9 68
vpcola 0:f1d3878b8dd9 69 overwrites_t const overwrites_direct[] ={
vpcola 0:f1d3878b8dd9 70 {0x3B, 0x0C}, //version 0C: new value for ACKDELAY targeting 198us (23 May, 2013, Larry Roshak)
vpcola 0:f1d3878b8dd9 71 {0x23, 0x17} //PA_PWR new default Power Step is "23"
vpcola 0:f1d3878b8dd9 72 };
vpcola 0:f1d3878b8dd9 73
vpcola 0:f1d3878b8dd9 74 overwrites_t const overwrites_indirect[] ={
vpcola 0:f1d3878b8dd9 75 {0x31, 0x02}, //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents)
vpcola 0:f1d3878b8dd9 76 {0x91, 0xB3}, //VCO_CTRL1 override VCOALC_REF_TX to 3
vpcola 0:f1d3878b8dd9 77 {0x92, 0x07}, //VCO_CTRL2 override VCOALC_REF_RX to 3, keep VCO_BUF_BOOST = 1
vpcola 0:f1d3878b8dd9 78 {0x8A, 0x71}, //PA_TUNING override PA_COILTUNING to 001 (27 Nov 2012, D. Brown, on behalf of S. Eid)
vpcola 0:f1d3878b8dd9 79 {0x79, 0x2F}, //CHF_IBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:f1d3878b8dd9 80 {0x7A, 0x2F}, //CHF_QBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:f1d3878b8dd9 81 {0x7B, 0x24}, //CHF_IRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:f1d3878b8dd9 82 {0x7C, 0x24}, //CHF_QRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:f1d3878b8dd9 83 {0x7D, 0x24}, //CHF_IL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:f1d3878b8dd9 84 {0x7E, 0x24}, //CHF_QL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:f1d3878b8dd9 85 {0x7F, 0x32}, //CHF_CC1 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:f1d3878b8dd9 86 {0x80, 0x1D}, //CHF_CCL Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:f1d3878b8dd9 87 {0x81, 0x2D}, //CHF_CC2 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:f1d3878b8dd9 88 {0x82, 0x24}, //CHF_IROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:f1d3878b8dd9 89 {0x83, 0x24}, //CHF_QROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:f1d3878b8dd9 90 {0x64, 0x28}, //PA_CAL_DIS=1 Disabled PA calibration
vpcola 0:f1d3878b8dd9 91 {0x52, 0x55}, //AGC_THR1 RSSI tune up
vpcola 0:f1d3878b8dd9 92 {0x53, 0x2D}, //AGC_THR2 RSSI tune up
vpcola 0:f1d3878b8dd9 93 {0x66, 0x5F}, //ATT_RSSI1 tune up
vpcola 0:f1d3878b8dd9 94 {0x67, 0x8F}, //ATT_RSSI2 tune up
vpcola 0:f1d3878b8dd9 95 {0x68, 0x61}, //RSSI_OFFSET
vpcola 0:f1d3878b8dd9 96 {0x78, 0x03}, //CHF_PMAGAIN
vpcola 0:f1d3878b8dd9 97 {0x22, 0x50}, //CCA1_THRESH
vpcola 0:f1d3878b8dd9 98 {0x4D, 0x13}, //CORR_NVAL moved from 0x14 to 0x13 for 0.5 dB improved Rx Sensitivity
vpcola 0:f1d3878b8dd9 99 {0x39, 0x3D} //ACKDELAY new value targeting a delay of 198us (23 May, 2013, Larry Roshak)
vpcola 0:f1d3878b8dd9 100 };
vpcola 0:f1d3878b8dd9 101
vpcola 0:f1d3878b8dd9 102
vpcola 0:f1d3878b8dd9 103 /* begin of deprecated versions
vpcola 0:f1d3878b8dd9 104
vpcola 0:f1d3878b8dd9 105 ==VERSION 1==
vpcola 0:f1d3878b8dd9 106 (version 1 is empty)
vpcola 0:f1d3878b8dd9 107
vpcola 0:f1d3878b8dd9 108 ==VERSION 2==
vpcola 0:f1d3878b8dd9 109 overwrites_t const overwrites_indirect[] ={
vpcola 0:f1d3878b8dd9 110 {0x31, 0x02} //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents)
vpcola 0:f1d3878b8dd9 111 };
vpcola 0:f1d3878b8dd9 112
vpcola 0:f1d3878b8dd9 113 ==VERSION 3==
vpcola 0:f1d3878b8dd9 114 overwrites_t const overwrites_indirect[] ={
vpcola 0:f1d3878b8dd9 115 {0x31, 0x02}, //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents)
vpcola 0:f1d3878b8dd9 116 {0x91, 0xB3}, //VCO_CTRL1: override VCOALC_REF_TX to 3
vpcola 0:f1d3878b8dd9 117 {0x92, 0x07} //VCO_CTRL2: override VCOALC_REF_RX to 3, keep VCO_BUF_BOOST = 1
vpcola 0:f1d3878b8dd9 118 };
vpcola 0:f1d3878b8dd9 119
vpcola 0:f1d3878b8dd9 120 ==VERSION 4==
vpcola 0:f1d3878b8dd9 121 overwrites_t const overwrites_direct[] ={
vpcola 0:f1d3878b8dd9 122 {0x3B, 0x04} //version 04 is the current version: update PA_COILTUNING default
vpcola 0:f1d3878b8dd9 123 };
vpcola 0:f1d3878b8dd9 124
vpcola 0:f1d3878b8dd9 125 overwrites_t const overwrites_indirect[] ={
vpcola 0:f1d3878b8dd9 126 {0x31, 0x02}, //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents)
vpcola 0:f1d3878b8dd9 127 {0x91, 0xB3}, //VCO_CTRL1: override VCOALC_REF_TX to 3
vpcola 0:f1d3878b8dd9 128 {0x92, 0x07} //VCO_CTRL2: override VCOALC_REF_RX to 3, keep VCO_BUF_BOOST = 1
vpcola 0:f1d3878b8dd9 129 {0x8A, 0x71} //PA_TUNING: override PA_COILTUNING to 001 (27 Nov 2012, D. Brown, on behalf of S. Eid)
vpcola 0:f1d3878b8dd9 130 };
vpcola 0:f1d3878b8dd9 131
vpcola 0:f1d3878b8dd9 132 ==VERSION 5==
vpcola 0:f1d3878b8dd9 133 overwrites_t const overwrites_direct[] ={
vpcola 0:f1d3878b8dd9 134 {0x3B, 0x05} //version 05: updates Channel Filter Register set (21 Dec 2012, on behalf of S. Soca)
vpcola 0:f1d3878b8dd9 135 };
vpcola 0:f1d3878b8dd9 136
vpcola 0:f1d3878b8dd9 137 overwrites_t const overwrites_indirect[] ={
vpcola 0:f1d3878b8dd9 138 {0x31, 0x02}, //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents)
vpcola 0:f1d3878b8dd9 139 {0x91, 0xB3}, //VCO_CTRL1 override VCOALC_REF_TX to 3
vpcola 0:f1d3878b8dd9 140 {0x92, 0x07} //VCO_CTRL2 override VCOALC_REF_RX to 3, keep VCO_BUF_BOOST = 1
vpcola 0:f1d3878b8dd9 141 {0x8A, 0x71} //PA_TUNING override PA_COILTUNING to 001 (27 Nov 2012, D. Brown, on behalf of S. Eid)
vpcola 0:f1d3878b8dd9 142 {0x79, 0x2F} //CHF_IBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:f1d3878b8dd9 143 {0x7A, 0x2F} //CHF_QBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:f1d3878b8dd9 144 {0x7B, 0x24} //CHF_IRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:f1d3878b8dd9 145 {0x7C, 0x24} //CHF_QRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:f1d3878b8dd9 146 {0x7D, 0x24} //CHF_IL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:f1d3878b8dd9 147 {0x7E, 0x24} //CHF_QL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:f1d3878b8dd9 148 {0x82, 0x24} //CHF_IROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:f1d3878b8dd9 149 {0x83, 0x24} //CHF_QROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:f1d3878b8dd9 150 {0x7F, 0x32} //CHF_CC1 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:f1d3878b8dd9 151 {0x80, 0x1D} //CHF_CCL Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:f1d3878b8dd9 152 {0x81, 0x2D} //CHF_CC2 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:f1d3878b8dd9 153 };
vpcola 0:f1d3878b8dd9 154
vpcola 0:f1d3878b8dd9 155 ==VERSION 6==
vpcola 0:f1d3878b8dd9 156 overwrites_t const overwrites_direct[] ={
vpcola 0:f1d3878b8dd9 157 {0x3B, 0x06} //version 06: disable PA calibration
vpcola 0:f1d3878b8dd9 158 };
vpcola 0:f1d3878b8dd9 159
vpcola 0:f1d3878b8dd9 160 overwrites_t const overwrites_indirect[] ={
vpcola 0:f1d3878b8dd9 161 {0x31, 0x02}, //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents)
vpcola 0:f1d3878b8dd9 162 {0x91, 0xB3}, //VCO_CTRL1 override VCOALC_REF_TX to 3
vpcola 0:f1d3878b8dd9 163 {0x92, 0x07} //VCO_CTRL2 override VCOALC_REF_RX to 3, keep VCO_BUF_BOOST = 1
vpcola 0:f1d3878b8dd9 164 {0x8A, 0x71} //PA_TUNING override PA_COILTUNING to 001 (27 Nov 2012, D. Brown, on behalf of S. Eid)
vpcola 0:f1d3878b8dd9 165 {0x79, 0x2F} //CHF_IBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:f1d3878b8dd9 166 {0x7A, 0x2F} //CHF_QBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:f1d3878b8dd9 167 {0x7B, 0x24} //CHF_IRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:f1d3878b8dd9 168 {0x7C, 0x24} //CHF_QRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:f1d3878b8dd9 169 {0x7D, 0x24} //CHF_IL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:f1d3878b8dd9 170 {0x7E, 0x24} //CHF_QL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:f1d3878b8dd9 171 {0x82, 0x24} //CHF_IROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:f1d3878b8dd9 172 {0x83, 0x24} //CHF_QROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:f1d3878b8dd9 173 {0x7F, 0x32} //CHF_CC1 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:f1d3878b8dd9 174 {0x80, 0x1D} //CHF_CCL Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:f1d3878b8dd9 175 {0x81, 0x2D} //CHF_CC2 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:f1d3878b8dd9 176 {0x64, 0x28} //PA_CAL_DIS=1 Disabled PA calibration
vpcola 0:f1d3878b8dd9 177 };
vpcola 0:f1d3878b8dd9 178
vpcola 0:f1d3878b8dd9 179 ==VERSION 7==
vpcola 0:f1d3878b8dd9 180 overwrites_t const overwrites_direct[] ={
vpcola 0:f1d3878b8dd9 181 {0x3B, 0x07} //version 07: updated registers for ED/RSSI
vpcola 0:f1d3878b8dd9 182 };
vpcola 0:f1d3878b8dd9 183
vpcola 0:f1d3878b8dd9 184 overwrites_t const overwrites_indirect[] ={
vpcola 0:f1d3878b8dd9 185 {0x31, 0x02}, //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents)
vpcola 0:f1d3878b8dd9 186 {0x91, 0xB3}, //VCO_CTRL1 override VCOALC_REF_TX to 3
vpcola 0:f1d3878b8dd9 187 {0x92, 0x07}, //VCO_CTRL2 override VCOALC_REF_RX to 3, keep VCO_BUF_BOOST = 1
vpcola 0:f1d3878b8dd9 188 {0x8A, 0x71}, //PA_TUNING override PA_COILTUNING to 001 (27 Nov 2012, D. Brown, on behalf of S. Eid)
vpcola 0:f1d3878b8dd9 189 {0x79, 0x2F}, //CHF_IBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:f1d3878b8dd9 190 {0x7A, 0x2F}, //CHF_QBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:f1d3878b8dd9 191 {0x7B, 0x24}, //CHF_IRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:f1d3878b8dd9 192 {0x7C, 0x24}, //CHF_QRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:f1d3878b8dd9 193 {0x7D, 0x24}, //CHF_IL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:f1d3878b8dd9 194 {0x7E, 0x24}, //CHF_QL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:f1d3878b8dd9 195 {0x82, 0x24}, //CHF_IROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:f1d3878b8dd9 196 {0x83, 0x24}, //CHF_QROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:f1d3878b8dd9 197 {0x7F, 0x32}, //CHF_CC1 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:f1d3878b8dd9 198 {0x80, 0x1D}, //CHF_CCL Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:f1d3878b8dd9 199 {0x81, 0x2D}, //CHF_CC2 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:f1d3878b8dd9 200 {0x64, 0x28}, //PA_CAL_DIS=1 Disabled PA calibration
vpcola 0:f1d3878b8dd9 201 {0x52, 0x73}, //AGC_THR1 RSSI tune up
vpcola 0:f1d3878b8dd9 202 {0x53, 0x2D}, //AGC_THR2 RSSI tune up
vpcola 0:f1d3878b8dd9 203 {0x66, 0x5F}, //ATT_RSSI1 tune up
vpcola 0:f1d3878b8dd9 204 {0x67, 0x8F}, //ATT_RSSI2 tune up
vpcola 0:f1d3878b8dd9 205 {0x68, 0x60}, //RSSI_OFFSET
vpcola 0:f1d3878b8dd9 206 {0x69, 0x65} //RSSI_SLOPE
vpcola 0:f1d3878b8dd9 207 };
vpcola 0:f1d3878b8dd9 208
vpcola 0:f1d3878b8dd9 209
vpcola 0:f1d3878b8dd9 210 ==VERSION 8==
vpcola 0:f1d3878b8dd9 211 overwrites_t const overwrites_direct[] ={
vpcola 0:f1d3878b8dd9 212 {0x3B, 0x08} //version 08: updated registers for ED/RSSI
vpcola 0:f1d3878b8dd9 213 };
vpcola 0:f1d3878b8dd9 214
vpcola 0:f1d3878b8dd9 215 overwrites_t const overwrites_indirect[] ={
vpcola 0:f1d3878b8dd9 216 {0x31, 0x02}, //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents)
vpcola 0:f1d3878b8dd9 217 {0x91, 0xB3}, //VCO_CTRL1 override VCOALC_REF_TX to 3
vpcola 0:f1d3878b8dd9 218 {0x92, 0x07}, //VCO_CTRL2 override VCOALC_REF_RX to 3, keep VCO_BUF_BOOST = 1
vpcola 0:f1d3878b8dd9 219 {0x8A, 0x71}, //PA_TUNING override PA_COILTUNING to 001 (27 Nov 2012, D. Brown, on behalf of S. Eid)
vpcola 0:f1d3878b8dd9 220 {0x79, 0x2F}, //CHF_IBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:f1d3878b8dd9 221 {0x7A, 0x2F}, //CHF_QBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:f1d3878b8dd9 222 {0x7B, 0x24}, //CHF_IRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:f1d3878b8dd9 223 {0x7C, 0x24}, //CHF_QRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:f1d3878b8dd9 224 {0x7D, 0x24}, //CHF_IL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:f1d3878b8dd9 225 {0x7E, 0x24}, //CHF_QL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:f1d3878b8dd9 226 {0x82, 0x24}, //CHF_IROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:f1d3878b8dd9 227 {0x83, 0x24}, //CHF_QROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:f1d3878b8dd9 228 {0x7F, 0x32}, //CHF_CC1 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:f1d3878b8dd9 229 {0x80, 0x1D}, //CHF_CCL Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:f1d3878b8dd9 230 {0x81, 0x2D}, //CHF_CC2 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:f1d3878b8dd9 231 {0x64, 0x28}, //PA_CAL_DIS=1 Disabled PA calibration
vpcola 0:f1d3878b8dd9 232 {0x52, 0x73}, //AGC_THR1 RSSI tune up
vpcola 0:f1d3878b8dd9 233 {0x53, 0x2D}, //AGC_THR2 RSSI tune up
vpcola 0:f1d3878b8dd9 234 {0x66, 0x5F}, //ATT_RSSI1 tune up
vpcola 0:f1d3878b8dd9 235 {0x67, 0x8F}, //ATT_RSSI2 tune up
vpcola 0:f1d3878b8dd9 236 {0x69, 0x65} //RSSI_SLOPE
vpcola 0:f1d3878b8dd9 237 {0x68, 0x61}, //RSSI_OFFSET
vpcola 0:f1d3878b8dd9 238 {0x78, 0x03} //CHF_PMAGAIN
vpcola 0:f1d3878b8dd9 239 };
vpcola 0:f1d3878b8dd9 240
vpcola 0:f1d3878b8dd9 241
vpcola 0:f1d3878b8dd9 242 ==VERSION 9==
vpcola 0:f1d3878b8dd9 243 overwrites_t const overwrites_direct[] ={
vpcola 0:f1d3878b8dd9 244 {0x3B, 0x09} //version 09: updated registers for ED/RSSI and PowerStep
vpcola 0:f1d3878b8dd9 245 {0x23, 0x17} //PA_PWR new default value
vpcola 0:f1d3878b8dd9 246 };
vpcola 0:f1d3878b8dd9 247
vpcola 0:f1d3878b8dd9 248 overwrites_t const overwrites_indirect[] ={
vpcola 0:f1d3878b8dd9 249 {0x31, 0x02}, //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents)
vpcola 0:f1d3878b8dd9 250 {0x91, 0xB3}, //VCO_CTRL1 override VCOALC_REF_TX to 3
vpcola 0:f1d3878b8dd9 251 {0x92, 0x07}, //VCO_CTRL2 override VCOALC_REF_RX to 3, keep VCO_BUF_BOOST = 1
vpcola 0:f1d3878b8dd9 252 {0x8A, 0x71}, //PA_TUNING override PA_COILTUNING to 001 (27 Nov 2012, D. Brown, on behalf of S. Eid)
vpcola 0:f1d3878b8dd9 253 {0x79, 0x2F}, //CHF_IBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:f1d3878b8dd9 254 {0x7A, 0x2F}, //CHF_QBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:f1d3878b8dd9 255 {0x7B, 0x24}, //CHF_IRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:f1d3878b8dd9 256 {0x7C, 0x24}, //CHF_QRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:f1d3878b8dd9 257 {0x7D, 0x24}, //CHF_IL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:f1d3878b8dd9 258 {0x7E, 0x24}, //CHF_QL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:f1d3878b8dd9 259 {0x7F, 0x32}, //CHF_CC1 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:f1d3878b8dd9 260 {0x80, 0x1D}, //CHF_CCL Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:f1d3878b8dd9 261 {0x81, 0x2D}, //CHF_CC2 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:f1d3878b8dd9 262 {0x82, 0x24}, //CHF_IROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:f1d3878b8dd9 263 {0x83, 0x24}, //CHF_QROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:f1d3878b8dd9 264 {0x64, 0x28}, //PA_CAL_DIS=1 Disabled PA calibration
vpcola 0:f1d3878b8dd9 265 {0x52, 0x55}, //AGC_THR1 RSSI tune up
vpcola 0:f1d3878b8dd9 266 {0x53, 0x2D}, //AGC_THR2 RSSI tune up
vpcola 0:f1d3878b8dd9 267 {0x66, 0x5F}, //ATT_RSSI1 tune up
vpcola 0:f1d3878b8dd9 268 {0x67, 0x8F}, //ATT_RSSI2 tune up
vpcola 0:f1d3878b8dd9 269 {0x68, 0x61}, //RSSI_OFFSET
vpcola 0:f1d3878b8dd9 270 {0x78, 0x03} //CHF_PMAGAIN
vpcola 0:f1d3878b8dd9 271 };
vpcola 0:f1d3878b8dd9 272
vpcola 0:f1d3878b8dd9 273 ==VERSION A==
vpcola 0:f1d3878b8dd9 274 overwrites_t const overwrites_direct[] ={
vpcola 0:f1d3878b8dd9 275 {0x3B, 0x0A} //version 0A: updated registers for CCA
vpcola 0:f1d3878b8dd9 276 {0x23, 0x17} //PA_PWR new default Power Step is "23"
vpcola 0:f1d3878b8dd9 277 };
vpcola 0:f1d3878b8dd9 278
vpcola 0:f1d3878b8dd9 279 overwrites_t const overwrites_indirect[] ={
vpcola 0:f1d3878b8dd9 280 {0x31, 0x02}, //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents)
vpcola 0:f1d3878b8dd9 281 {0x91, 0xB3}, //VCO_CTRL1 override VCOALC_REF_TX to 3
vpcola 0:f1d3878b8dd9 282 {0x92, 0x07}, //VCO_CTRL2 override VCOALC_REF_RX to 3, keep VCO_BUF_BOOST = 1
vpcola 0:f1d3878b8dd9 283 {0x8A, 0x71}, //PA_TUNING override PA_COILTUNING to 001 (27 Nov 2012, D. Brown, on behalf of S. Eid)
vpcola 0:f1d3878b8dd9 284 {0x79, 0x2F}, //CHF_IBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:f1d3878b8dd9 285 {0x7A, 0x2F}, //CHF_QBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:f1d3878b8dd9 286 {0x7B, 0x24}, //CHF_IRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:f1d3878b8dd9 287 {0x7C, 0x24}, //CHF_QRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:f1d3878b8dd9 288 {0x7D, 0x24}, //CHF_IL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:f1d3878b8dd9 289 {0x7E, 0x24}, //CHF_QL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:f1d3878b8dd9 290 {0x7F, 0x32}, //CHF_CC1 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:f1d3878b8dd9 291 {0x80, 0x1D}, //CHF_CCL Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:f1d3878b8dd9 292 {0x81, 0x2D}, //CHF_CC2 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:f1d3878b8dd9 293 {0x82, 0x24}, //CHF_IROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:f1d3878b8dd9 294 {0x83, 0x24}, //CHF_QROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:f1d3878b8dd9 295 {0x64, 0x28}, //PA_CAL_DIS=1 Disabled PA calibration
vpcola 0:f1d3878b8dd9 296 {0x52, 0x55}, //AGC_THR1 RSSI tune up
vpcola 0:f1d3878b8dd9 297 {0x53, 0x2D}, //AGC_THR2 RSSI tune up
vpcola 0:f1d3878b8dd9 298 {0x66, 0x5F}, //ATT_RSSI1 tune up
vpcola 0:f1d3878b8dd9 299 {0x67, 0x8F}, //ATT_RSSI2 tune up
vpcola 0:f1d3878b8dd9 300 {0x68, 0x61}, //RSSI_OFFSET
vpcola 0:f1d3878b8dd9 301 {0x78, 0x03} //CHF_PMAGAIN
vpcola 0:f1d3878b8dd9 302 {0x22, 0x50} //CCA1_THRESH
vpcola 0:f1d3878b8dd9 303 };
vpcola 0:f1d3878b8dd9 304
vpcola 0:f1d3878b8dd9 305 end of deprecated versions */
vpcola 0:f1d3878b8dd9 306
vpcola 0:f1d3878b8dd9 307
vpcola 0:f1d3878b8dd9 308 #endif //OVERWRITES_H_
vpcola 0:f1d3878b8dd9 309