Vergil Cola / Mbed OS MQTTGatewayK64

Fork of my MQTTGateway

Dependencies:   mbed-http

easy-connect/mcr20a-rf-driver/source/MCR20Drv.c@0:f1d3878b8dd9, 2017-04-08 (annotated)

Committer:
vpcola
Date:
Sat Apr 08 14:45:51 2017 +0000
Revision:
0:f1d3878b8dd9
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
vpcola 0:f1d3878b8dd9 1 /*!
vpcola 0:f1d3878b8dd9 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
vpcola 0:f1d3878b8dd9 3 * All rights reserved.
vpcola 0:f1d3878b8dd9 4 *
vpcola 0:f1d3878b8dd9 5 * \file MCR20Drv.c
vpcola 0:f1d3878b8dd9 6 *
vpcola 0:f1d3878b8dd9 7 * Redistribution and use in source and binary forms, with or without modification,
vpcola 0:f1d3878b8dd9 8 * are permitted provided that the following conditions are met:
vpcola 0:f1d3878b8dd9 9 *
vpcola 0:f1d3878b8dd9 10 * o Redistributions of source code must retain the above copyright notice, this list
vpcola 0:f1d3878b8dd9 11 * of conditions and the following disclaimer.
vpcola 0:f1d3878b8dd9 12 *
vpcola 0:f1d3878b8dd9 13 * o Redistributions in binary form must reproduce the above copyright notice, this
vpcola 0:f1d3878b8dd9 14 * list of conditions and the following disclaimer in the documentation and/or
vpcola 0:f1d3878b8dd9 15 * other materials provided with the distribution.
vpcola 0:f1d3878b8dd9 16 *
vpcola 0:f1d3878b8dd9 17 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
vpcola 0:f1d3878b8dd9 18 * contributors may be used to endorse or promote products derived from this
vpcola 0:f1d3878b8dd9 19 * software without specific prior written permission.
vpcola 0:f1d3878b8dd9 20 *
vpcola 0:f1d3878b8dd9 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
vpcola 0:f1d3878b8dd9 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
vpcola 0:f1d3878b8dd9 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
vpcola 0:f1d3878b8dd9 24 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
vpcola 0:f1d3878b8dd9 25 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
vpcola 0:f1d3878b8dd9 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
vpcola 0:f1d3878b8dd9 27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
vpcola 0:f1d3878b8dd9 28 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
vpcola 0:f1d3878b8dd9 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
vpcola 0:f1d3878b8dd9 30 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
vpcola 0:f1d3878b8dd9 31 */
vpcola 0:f1d3878b8dd9 32
vpcola 0:f1d3878b8dd9 33
vpcola 0:f1d3878b8dd9 34 /*****************************************************************************
vpcola 0:f1d3878b8dd9 35 * INCLUDED HEADERS *
vpcola 0:f1d3878b8dd9 36 *---------------------------------------------------------------------------*
vpcola 0:f1d3878b8dd9 37 * Add to this section all the headers that this module needs to include. *
vpcola 0:f1d3878b8dd9 38 *---------------------------------------------------------------------------*
vpcola 0:f1d3878b8dd9 39 *****************************************************************************/
vpcola 0:f1d3878b8dd9 40
vpcola 0:f1d3878b8dd9 41 #include "platform/arm_hal_interrupt.h"
vpcola 0:f1d3878b8dd9 42 #include "MCR20Drv.h"
vpcola 0:f1d3878b8dd9 43 #include "MCR20Reg.h"
vpcola 0:f1d3878b8dd9 44 #include "XcvrSpi.h"
vpcola 0:f1d3878b8dd9 45
vpcola 0:f1d3878b8dd9 46
vpcola 0:f1d3878b8dd9 47 /*****************************************************************************
vpcola 0:f1d3878b8dd9 48 * PRIVATE VARIABLES *
vpcola 0:f1d3878b8dd9 49 *---------------------------------------------------------------------------*
vpcola 0:f1d3878b8dd9 50 * Add to this section all the variables and constants that have local *
vpcola 0:f1d3878b8dd9 51 * (file) scope. *
vpcola 0:f1d3878b8dd9 52 * Each of this declarations shall be preceded by the 'static' keyword. *
vpcola 0:f1d3878b8dd9 53 * These variables / constants cannot be accessed outside this module. *
vpcola 0:f1d3878b8dd9 54 *---------------------------------------------------------------------------*
vpcola 0:f1d3878b8dd9 55 *****************************************************************************/
vpcola 0:f1d3878b8dd9 56 uint32_t mPhyIrqDisableCnt = 1;
vpcola 0:f1d3878b8dd9 57
vpcola 0:f1d3878b8dd9 58 /*****************************************************************************
vpcola 0:f1d3878b8dd9 59 * PUBLIC VARIABLES *
vpcola 0:f1d3878b8dd9 60 *---------------------------------------------------------------------------*
vpcola 0:f1d3878b8dd9 61 * Add to this section all the variables and constants that have global *
vpcola 0:f1d3878b8dd9 62 * (project) scope. *
vpcola 0:f1d3878b8dd9 63 * These variables / constants can be accessed outside this module. *
vpcola 0:f1d3878b8dd9 64 * These variables / constants shall be preceded by the 'extern' keyword in *
vpcola 0:f1d3878b8dd9 65 * the interface header. *
vpcola 0:f1d3878b8dd9 66 *---------------------------------------------------------------------------*
vpcola 0:f1d3878b8dd9 67 *****************************************************************************/
vpcola 0:f1d3878b8dd9 68
vpcola 0:f1d3878b8dd9 69 /*****************************************************************************
vpcola 0:f1d3878b8dd9 70 * PRIVATE FUNCTIONS PROTOTYPES *
vpcola 0:f1d3878b8dd9 71 *---------------------------------------------------------------------------*
vpcola 0:f1d3878b8dd9 72 * Add to this section all the functions prototypes that have local (file) *
vpcola 0:f1d3878b8dd9 73 * scope. *
vpcola 0:f1d3878b8dd9 74 * These functions cannot be accessed outside this module. *
vpcola 0:f1d3878b8dd9 75 * These declarations shall be preceded by the 'static' keyword. *
vpcola 0:f1d3878b8dd9 76 *---------------------------------------------------------------------------*
vpcola 0:f1d3878b8dd9 77 *****************************************************************************/
vpcola 0:f1d3878b8dd9 78
vpcola 0:f1d3878b8dd9 79 /*****************************************************************************
vpcola 0:f1d3878b8dd9 80 * PRIVATE FUNCTIONS *
vpcola 0:f1d3878b8dd9 81 *---------------------------------------------------------------------------*
vpcola 0:f1d3878b8dd9 82 * Add to this section all the functions that have local (file) scope. *
vpcola 0:f1d3878b8dd9 83 * These functions cannot be accessed outside this module. *
vpcola 0:f1d3878b8dd9 84 * These definitions shall be preceded by the 'static' keyword. *
vpcola 0:f1d3878b8dd9 85 *---------------------------------------------------------------------------*
vpcola 0:f1d3878b8dd9 86 *****************************************************************************/
vpcola 0:f1d3878b8dd9 87
vpcola 0:f1d3878b8dd9 88
vpcola 0:f1d3878b8dd9 89 /*****************************************************************************
vpcola 0:f1d3878b8dd9 90 * PUBLIC FUNCTIONS *
vpcola 0:f1d3878b8dd9 91 *---------------------------------------------------------------------------*
vpcola 0:f1d3878b8dd9 92 * Add to this section all the functions that have global (project) scope. *
vpcola 0:f1d3878b8dd9 93 * These functions can be accessed outside this module. *
vpcola 0:f1d3878b8dd9 94 * These functions shall have their declarations (prototypes) within the *
vpcola 0:f1d3878b8dd9 95 * interface header file and shall be preceded by the 'extern' keyword. *
vpcola 0:f1d3878b8dd9 96 *---------------------------------------------------------------------------*
vpcola 0:f1d3878b8dd9 97 *****************************************************************************/
vpcola 0:f1d3878b8dd9 98
vpcola 0:f1d3878b8dd9 99 /*---------------------------------------------------------------------------
vpcola 0:f1d3878b8dd9 100 * Name: MCR20Drv_Init
vpcola 0:f1d3878b8dd9 101 * Description: -
vpcola 0:f1d3878b8dd9 102 * Parameters: -
vpcola 0:f1d3878b8dd9 103 * Return: -
vpcola 0:f1d3878b8dd9 104 *---------------------------------------------------------------------------*/
vpcola 0:f1d3878b8dd9 105 void MCR20Drv_Init
vpcola 0:f1d3878b8dd9 106 (
vpcola 0:f1d3878b8dd9 107 void
vpcola 0:f1d3878b8dd9 108 )
vpcola 0:f1d3878b8dd9 109 {
vpcola 0:f1d3878b8dd9 110 xcvr_spi_init(gXcvrSpiInstance_c);
vpcola 0:f1d3878b8dd9 111 xcvr_spi_configure_speed(gXcvrSpiInstance_c, 8000000);
vpcola 0:f1d3878b8dd9 112
vpcola 0:f1d3878b8dd9 113 gXcvrDeassertCS_d();
vpcola 0:f1d3878b8dd9 114 MCR20Drv_RST_B_Deassert();
vpcola 0:f1d3878b8dd9 115 RF_IRQ_Init();
vpcola 0:f1d3878b8dd9 116 RF_IRQ_Disable();
vpcola 0:f1d3878b8dd9 117 mPhyIrqDisableCnt = 1;
vpcola 0:f1d3878b8dd9 118 }
vpcola 0:f1d3878b8dd9 119
vpcola 0:f1d3878b8dd9 120 /*---------------------------------------------------------------------------
vpcola 0:f1d3878b8dd9 121 * Name: MCR20Drv_DirectAccessSPIWrite
vpcola 0:f1d3878b8dd9 122 * Description: -
vpcola 0:f1d3878b8dd9 123 * Parameters: -
vpcola 0:f1d3878b8dd9 124 * Return: -
vpcola 0:f1d3878b8dd9 125 *---------------------------------------------------------------------------*/
vpcola 0:f1d3878b8dd9 126 void MCR20Drv_DirectAccessSPIWrite
vpcola 0:f1d3878b8dd9 127 (
vpcola 0:f1d3878b8dd9 128 uint8_t address,
vpcola 0:f1d3878b8dd9 129 uint8_t value
vpcola 0:f1d3878b8dd9 130 )
vpcola 0:f1d3878b8dd9 131 {
vpcola 0:f1d3878b8dd9 132 uint16_t txData;
vpcola 0:f1d3878b8dd9 133
vpcola 0:f1d3878b8dd9 134 ProtectFromMCR20Interrupt();
vpcola 0:f1d3878b8dd9 135
vpcola 0:f1d3878b8dd9 136 xcvr_spi_configure_speed(gXcvrSpiInstance_c, 16000000);
vpcola 0:f1d3878b8dd9 137
vpcola 0:f1d3878b8dd9 138 gXcvrAssertCS_d();
vpcola 0:f1d3878b8dd9 139
vpcola 0:f1d3878b8dd9 140 txData = (address & TransceiverSPI_DirectRegisterAddressMask);
vpcola 0:f1d3878b8dd9 141 txData |= value << 8;
vpcola 0:f1d3878b8dd9 142
vpcola 0:f1d3878b8dd9 143 xcvr_spi_transfer(gXcvrSpiInstance_c, (uint8_t *)&txData, 0, sizeof(txData));
vpcola 0:f1d3878b8dd9 144
vpcola 0:f1d3878b8dd9 145 gXcvrDeassertCS_d();
vpcola 0:f1d3878b8dd9 146 UnprotectFromMCR20Interrupt();
vpcola 0:f1d3878b8dd9 147 }
vpcola 0:f1d3878b8dd9 148
vpcola 0:f1d3878b8dd9 149 /*---------------------------------------------------------------------------
vpcola 0:f1d3878b8dd9 150 * Name: MCR20Drv_DirectAccessSPIMultiByteWrite
vpcola 0:f1d3878b8dd9 151 * Description: -
vpcola 0:f1d3878b8dd9 152 * Parameters: -
vpcola 0:f1d3878b8dd9 153 * Return: -
vpcola 0:f1d3878b8dd9 154 *---------------------------------------------------------------------------*/
vpcola 0:f1d3878b8dd9 155 void MCR20Drv_DirectAccessSPIMultiByteWrite
vpcola 0:f1d3878b8dd9 156 (
vpcola 0:f1d3878b8dd9 157 uint8_t startAddress,
vpcola 0:f1d3878b8dd9 158 uint8_t * byteArray,
vpcola 0:f1d3878b8dd9 159 uint8_t numOfBytes
vpcola 0:f1d3878b8dd9 160 )
vpcola 0:f1d3878b8dd9 161 {
vpcola 0:f1d3878b8dd9 162 uint8_t txData;
vpcola 0:f1d3878b8dd9 163
vpcola 0:f1d3878b8dd9 164 if( (numOfBytes == 0) || (byteArray == 0) )
vpcola 0:f1d3878b8dd9 165 {
vpcola 0:f1d3878b8dd9 166 return;
vpcola 0:f1d3878b8dd9 167 }
vpcola 0:f1d3878b8dd9 168
vpcola 0:f1d3878b8dd9 169 ProtectFromMCR20Interrupt();
vpcola 0:f1d3878b8dd9 170
vpcola 0:f1d3878b8dd9 171 xcvr_spi_configure_speed(gXcvrSpiInstance_c, 16000000);
vpcola 0:f1d3878b8dd9 172
vpcola 0:f1d3878b8dd9 173 gXcvrAssertCS_d();
vpcola 0:f1d3878b8dd9 174
vpcola 0:f1d3878b8dd9 175 txData = (startAddress & TransceiverSPI_DirectRegisterAddressMask);
vpcola 0:f1d3878b8dd9 176
vpcola 0:f1d3878b8dd9 177 xcvr_spi_transfer(gXcvrSpiInstance_c, &txData, 0, sizeof(txData));
vpcola 0:f1d3878b8dd9 178 xcvr_spi_transfer(gXcvrSpiInstance_c, byteArray, 0, numOfBytes);
vpcola 0:f1d3878b8dd9 179
vpcola 0:f1d3878b8dd9 180 gXcvrDeassertCS_d();
vpcola 0:f1d3878b8dd9 181 UnprotectFromMCR20Interrupt();
vpcola 0:f1d3878b8dd9 182 }
vpcola 0:f1d3878b8dd9 183
vpcola 0:f1d3878b8dd9 184 /*---------------------------------------------------------------------------
vpcola 0:f1d3878b8dd9 185 * Name: MCR20Drv_PB_SPIByteWrite
vpcola 0:f1d3878b8dd9 186 * Description: -
vpcola 0:f1d3878b8dd9 187 * Parameters: -
vpcola 0:f1d3878b8dd9 188 * Return: -
vpcola 0:f1d3878b8dd9 189 *---------------------------------------------------------------------------*/
vpcola 0:f1d3878b8dd9 190 void MCR20Drv_PB_SPIByteWrite
vpcola 0:f1d3878b8dd9 191 (
vpcola 0:f1d3878b8dd9 192 uint8_t address,
vpcola 0:f1d3878b8dd9 193 uint8_t value
vpcola 0:f1d3878b8dd9 194 )
vpcola 0:f1d3878b8dd9 195 {
vpcola 0:f1d3878b8dd9 196 uint32_t txData;
vpcola 0:f1d3878b8dd9 197
vpcola 0:f1d3878b8dd9 198 ProtectFromMCR20Interrupt();
vpcola 0:f1d3878b8dd9 199
vpcola 0:f1d3878b8dd9 200 xcvr_spi_configure_speed(gXcvrSpiInstance_c, 16000000);
vpcola 0:f1d3878b8dd9 201
vpcola 0:f1d3878b8dd9 202 gXcvrAssertCS_d();
vpcola 0:f1d3878b8dd9 203
vpcola 0:f1d3878b8dd9 204 txData = TransceiverSPI_WriteSelect |
vpcola 0:f1d3878b8dd9 205 TransceiverSPI_PacketBuffAccessSelect |
vpcola 0:f1d3878b8dd9 206 TransceiverSPI_PacketBuffByteModeSelect;
vpcola 0:f1d3878b8dd9 207 txData |= (address) << 8;
vpcola 0:f1d3878b8dd9 208 txData |= (value) << 16;
vpcola 0:f1d3878b8dd9 209
vpcola 0:f1d3878b8dd9 210 xcvr_spi_transfer(gXcvrSpiInstance_c, (uint8_t*)&txData, 0, 3);
vpcola 0:f1d3878b8dd9 211
vpcola 0:f1d3878b8dd9 212 gXcvrDeassertCS_d();
vpcola 0:f1d3878b8dd9 213 UnprotectFromMCR20Interrupt();
vpcola 0:f1d3878b8dd9 214 }
vpcola 0:f1d3878b8dd9 215
vpcola 0:f1d3878b8dd9 216 /*---------------------------------------------------------------------------
vpcola 0:f1d3878b8dd9 217 * Name: MCR20Drv_PB_SPIBurstWrite
vpcola 0:f1d3878b8dd9 218 * Description: -
vpcola 0:f1d3878b8dd9 219 * Parameters: -
vpcola 0:f1d3878b8dd9 220 * Return: -
vpcola 0:f1d3878b8dd9 221 *---------------------------------------------------------------------------*/
vpcola 0:f1d3878b8dd9 222 void MCR20Drv_PB_SPIBurstWrite
vpcola 0:f1d3878b8dd9 223 (
vpcola 0:f1d3878b8dd9 224 uint8_t * byteArray,
vpcola 0:f1d3878b8dd9 225 uint8_t numOfBytes
vpcola 0:f1d3878b8dd9 226 )
vpcola 0:f1d3878b8dd9 227 {
vpcola 0:f1d3878b8dd9 228 uint8_t txData;
vpcola 0:f1d3878b8dd9 229
vpcola 0:f1d3878b8dd9 230 if( (numOfBytes == 0) || (byteArray == 0) )
vpcola 0:f1d3878b8dd9 231 {
vpcola 0:f1d3878b8dd9 232 return;
vpcola 0:f1d3878b8dd9 233 }
vpcola 0:f1d3878b8dd9 234
vpcola 0:f1d3878b8dd9 235 ProtectFromMCR20Interrupt();
vpcola 0:f1d3878b8dd9 236
vpcola 0:f1d3878b8dd9 237 xcvr_spi_configure_speed(gXcvrSpiInstance_c, 16000000);
vpcola 0:f1d3878b8dd9 238
vpcola 0:f1d3878b8dd9 239 gXcvrAssertCS_d();
vpcola 0:f1d3878b8dd9 240
vpcola 0:f1d3878b8dd9 241 txData = TransceiverSPI_WriteSelect |
vpcola 0:f1d3878b8dd9 242 TransceiverSPI_PacketBuffAccessSelect |
vpcola 0:f1d3878b8dd9 243 TransceiverSPI_PacketBuffBurstModeSelect;
vpcola 0:f1d3878b8dd9 244
vpcola 0:f1d3878b8dd9 245 xcvr_spi_transfer(gXcvrSpiInstance_c, &txData, 0, 1);
vpcola 0:f1d3878b8dd9 246 xcvr_spi_transfer(gXcvrSpiInstance_c, byteArray, 0, numOfBytes);
vpcola 0:f1d3878b8dd9 247
vpcola 0:f1d3878b8dd9 248 gXcvrDeassertCS_d();
vpcola 0:f1d3878b8dd9 249 UnprotectFromMCR20Interrupt();
vpcola 0:f1d3878b8dd9 250 }
vpcola 0:f1d3878b8dd9 251
vpcola 0:f1d3878b8dd9 252 /*---------------------------------------------------------------------------
vpcola 0:f1d3878b8dd9 253 * Name: MCR20Drv_DirectAccessSPIRead
vpcola 0:f1d3878b8dd9 254 * Description: -
vpcola 0:f1d3878b8dd9 255 * Parameters: -
vpcola 0:f1d3878b8dd9 256 * Return: -
vpcola 0:f1d3878b8dd9 257 *---------------------------------------------------------------------------*/
vpcola 0:f1d3878b8dd9 258
vpcola 0:f1d3878b8dd9 259 uint8_t MCR20Drv_DirectAccessSPIRead
vpcola 0:f1d3878b8dd9 260 (
vpcola 0:f1d3878b8dd9 261 uint8_t address
vpcola 0:f1d3878b8dd9 262 )
vpcola 0:f1d3878b8dd9 263 {
vpcola 0:f1d3878b8dd9 264 uint8_t txData;
vpcola 0:f1d3878b8dd9 265 uint8_t rxData;
vpcola 0:f1d3878b8dd9 266
vpcola 0:f1d3878b8dd9 267 ProtectFromMCR20Interrupt();
vpcola 0:f1d3878b8dd9 268
vpcola 0:f1d3878b8dd9 269 xcvr_spi_configure_speed(gXcvrSpiInstance_c, 8000000);
vpcola 0:f1d3878b8dd9 270
vpcola 0:f1d3878b8dd9 271 gXcvrAssertCS_d();
vpcola 0:f1d3878b8dd9 272
vpcola 0:f1d3878b8dd9 273 txData = (address & TransceiverSPI_DirectRegisterAddressMask) |
vpcola 0:f1d3878b8dd9 274 TransceiverSPI_ReadSelect;
vpcola 0:f1d3878b8dd9 275
vpcola 0:f1d3878b8dd9 276 xcvr_spi_transfer(gXcvrSpiInstance_c, &txData, 0, sizeof(txData));
vpcola 0:f1d3878b8dd9 277 xcvr_spi_transfer(gXcvrSpiInstance_c, 0, &rxData, sizeof(rxData));
vpcola 0:f1d3878b8dd9 278
vpcola 0:f1d3878b8dd9 279 gXcvrDeassertCS_d();
vpcola 0:f1d3878b8dd9 280 UnprotectFromMCR20Interrupt();
vpcola 0:f1d3878b8dd9 281
vpcola 0:f1d3878b8dd9 282 return rxData;
vpcola 0:f1d3878b8dd9 283
vpcola 0:f1d3878b8dd9 284 }
vpcola 0:f1d3878b8dd9 285
vpcola 0:f1d3878b8dd9 286 /*---------------------------------------------------------------------------
vpcola 0:f1d3878b8dd9 287 * Name: MCR20Drv_DirectAccessSPIMultyByteRead
vpcola 0:f1d3878b8dd9 288 * Description: -
vpcola 0:f1d3878b8dd9 289 * Parameters: -
vpcola 0:f1d3878b8dd9 290 * Return: -
vpcola 0:f1d3878b8dd9 291 *---------------------------------------------------------------------------*/
vpcola 0:f1d3878b8dd9 292 uint8_t MCR20Drv_DirectAccessSPIMultiByteRead
vpcola 0:f1d3878b8dd9 293 (
vpcola 0:f1d3878b8dd9 294 uint8_t startAddress,
vpcola 0:f1d3878b8dd9 295 uint8_t * byteArray,
vpcola 0:f1d3878b8dd9 296 uint8_t numOfBytes
vpcola 0:f1d3878b8dd9 297 )
vpcola 0:f1d3878b8dd9 298 {
vpcola 0:f1d3878b8dd9 299 uint8_t txData;
vpcola 0:f1d3878b8dd9 300 uint8_t phyIRQSTS1;
vpcola 0:f1d3878b8dd9 301
vpcola 0:f1d3878b8dd9 302 if( (numOfBytes == 0) || (byteArray == 0) )
vpcola 0:f1d3878b8dd9 303 {
vpcola 0:f1d3878b8dd9 304 return 0;
vpcola 0:f1d3878b8dd9 305 }
vpcola 0:f1d3878b8dd9 306
vpcola 0:f1d3878b8dd9 307 ProtectFromMCR20Interrupt();
vpcola 0:f1d3878b8dd9 308
vpcola 0:f1d3878b8dd9 309 xcvr_spi_configure_speed(gXcvrSpiInstance_c, 8000000);
vpcola 0:f1d3878b8dd9 310
vpcola 0:f1d3878b8dd9 311 gXcvrAssertCS_d();
vpcola 0:f1d3878b8dd9 312
vpcola 0:f1d3878b8dd9 313 txData = (startAddress & TransceiverSPI_DirectRegisterAddressMask) |
vpcola 0:f1d3878b8dd9 314 TransceiverSPI_ReadSelect;
vpcola 0:f1d3878b8dd9 315
vpcola 0:f1d3878b8dd9 316 xcvr_spi_transfer(gXcvrSpiInstance_c, &txData, &phyIRQSTS1, sizeof(txData));
vpcola 0:f1d3878b8dd9 317 xcvr_spi_transfer(gXcvrSpiInstance_c, 0, byteArray, numOfBytes);
vpcola 0:f1d3878b8dd9 318
vpcola 0:f1d3878b8dd9 319 gXcvrDeassertCS_d();
vpcola 0:f1d3878b8dd9 320 UnprotectFromMCR20Interrupt();
vpcola 0:f1d3878b8dd9 321
vpcola 0:f1d3878b8dd9 322 return phyIRQSTS1;
vpcola 0:f1d3878b8dd9 323 }
vpcola 0:f1d3878b8dd9 324
vpcola 0:f1d3878b8dd9 325 /*---------------------------------------------------------------------------
vpcola 0:f1d3878b8dd9 326 * Name: MCR20Drv_PB_SPIBurstRead
vpcola 0:f1d3878b8dd9 327 * Description: -
vpcola 0:f1d3878b8dd9 328 * Parameters: -
vpcola 0:f1d3878b8dd9 329 * Return: -
vpcola 0:f1d3878b8dd9 330 *---------------------------------------------------------------------------*/
vpcola 0:f1d3878b8dd9 331 uint8_t MCR20Drv_PB_SPIBurstRead
vpcola 0:f1d3878b8dd9 332 (
vpcola 0:f1d3878b8dd9 333 uint8_t * byteArray,
vpcola 0:f1d3878b8dd9 334 uint8_t numOfBytes
vpcola 0:f1d3878b8dd9 335 )
vpcola 0:f1d3878b8dd9 336 {
vpcola 0:f1d3878b8dd9 337 uint8_t txData;
vpcola 0:f1d3878b8dd9 338 uint8_t phyIRQSTS1;
vpcola 0:f1d3878b8dd9 339
vpcola 0:f1d3878b8dd9 340 if( (numOfBytes == 0) || (byteArray == 0) )
vpcola 0:f1d3878b8dd9 341 {
vpcola 0:f1d3878b8dd9 342 return 0;
vpcola 0:f1d3878b8dd9 343 }
vpcola 0:f1d3878b8dd9 344
vpcola 0:f1d3878b8dd9 345 ProtectFromMCR20Interrupt();
vpcola 0:f1d3878b8dd9 346
vpcola 0:f1d3878b8dd9 347 xcvr_spi_configure_speed(gXcvrSpiInstance_c, 8000000);
vpcola 0:f1d3878b8dd9 348
vpcola 0:f1d3878b8dd9 349 gXcvrAssertCS_d();
vpcola 0:f1d3878b8dd9 350
vpcola 0:f1d3878b8dd9 351 txData = TransceiverSPI_ReadSelect |
vpcola 0:f1d3878b8dd9 352 TransceiverSPI_PacketBuffAccessSelect |
vpcola 0:f1d3878b8dd9 353 TransceiverSPI_PacketBuffBurstModeSelect;
vpcola 0:f1d3878b8dd9 354
vpcola 0:f1d3878b8dd9 355 xcvr_spi_transfer(gXcvrSpiInstance_c, &txData, &phyIRQSTS1, sizeof(txData));
vpcola 0:f1d3878b8dd9 356 xcvr_spi_transfer(gXcvrSpiInstance_c, 0, byteArray, numOfBytes);
vpcola 0:f1d3878b8dd9 357
vpcola 0:f1d3878b8dd9 358 gXcvrDeassertCS_d();
vpcola 0:f1d3878b8dd9 359 UnprotectFromMCR20Interrupt();
vpcola 0:f1d3878b8dd9 360
vpcola 0:f1d3878b8dd9 361 return phyIRQSTS1;
vpcola 0:f1d3878b8dd9 362 }
vpcola 0:f1d3878b8dd9 363
vpcola 0:f1d3878b8dd9 364 /*---------------------------------------------------------------------------
vpcola 0:f1d3878b8dd9 365 * Name: MCR20Drv_IndirectAccessSPIWrite
vpcola 0:f1d3878b8dd9 366 * Description: -
vpcola 0:f1d3878b8dd9 367 * Parameters: -
vpcola 0:f1d3878b8dd9 368 * Return: -
vpcola 0:f1d3878b8dd9 369 *---------------------------------------------------------------------------*/
vpcola 0:f1d3878b8dd9 370 void MCR20Drv_IndirectAccessSPIWrite
vpcola 0:f1d3878b8dd9 371 (
vpcola 0:f1d3878b8dd9 372 uint8_t address,
vpcola 0:f1d3878b8dd9 373 uint8_t value
vpcola 0:f1d3878b8dd9 374 )
vpcola 0:f1d3878b8dd9 375 {
vpcola 0:f1d3878b8dd9 376 uint32_t txData;
vpcola 0:f1d3878b8dd9 377
vpcola 0:f1d3878b8dd9 378 ProtectFromMCR20Interrupt();
vpcola 0:f1d3878b8dd9 379
vpcola 0:f1d3878b8dd9 380 xcvr_spi_configure_speed(gXcvrSpiInstance_c, 16000000);
vpcola 0:f1d3878b8dd9 381
vpcola 0:f1d3878b8dd9 382 gXcvrAssertCS_d();
vpcola 0:f1d3878b8dd9 383
vpcola 0:f1d3878b8dd9 384 txData = TransceiverSPI_IARIndexReg;
vpcola 0:f1d3878b8dd9 385 txData |= (address) << 8;
vpcola 0:f1d3878b8dd9 386 txData |= (value) << 16;
vpcola 0:f1d3878b8dd9 387
vpcola 0:f1d3878b8dd9 388 xcvr_spi_transfer(gXcvrSpiInstance_c, (uint8_t*)&txData, 0, 3);
vpcola 0:f1d3878b8dd9 389
vpcola 0:f1d3878b8dd9 390 gXcvrDeassertCS_d();
vpcola 0:f1d3878b8dd9 391 UnprotectFromMCR20Interrupt();
vpcola 0:f1d3878b8dd9 392 }
vpcola 0:f1d3878b8dd9 393
vpcola 0:f1d3878b8dd9 394 /*---------------------------------------------------------------------------
vpcola 0:f1d3878b8dd9 395 * Name: MCR20Drv_IndirectAccessSPIMultiByteWrite
vpcola 0:f1d3878b8dd9 396 * Description: -
vpcola 0:f1d3878b8dd9 397 * Parameters: -
vpcola 0:f1d3878b8dd9 398 * Return: -
vpcola 0:f1d3878b8dd9 399 *---------------------------------------------------------------------------*/
vpcola 0:f1d3878b8dd9 400 void MCR20Drv_IndirectAccessSPIMultiByteWrite
vpcola 0:f1d3878b8dd9 401 (
vpcola 0:f1d3878b8dd9 402 uint8_t startAddress,
vpcola 0:f1d3878b8dd9 403 uint8_t * byteArray,
vpcola 0:f1d3878b8dd9 404 uint8_t numOfBytes
vpcola 0:f1d3878b8dd9 405 )
vpcola 0:f1d3878b8dd9 406 {
vpcola 0:f1d3878b8dd9 407 uint16_t txData;
vpcola 0:f1d3878b8dd9 408
vpcola 0:f1d3878b8dd9 409 if( (numOfBytes == 0) || (byteArray == 0) )
vpcola 0:f1d3878b8dd9 410 {
vpcola 0:f1d3878b8dd9 411 return;
vpcola 0:f1d3878b8dd9 412 }
vpcola 0:f1d3878b8dd9 413
vpcola 0:f1d3878b8dd9 414 ProtectFromMCR20Interrupt();
vpcola 0:f1d3878b8dd9 415
vpcola 0:f1d3878b8dd9 416 xcvr_spi_configure_speed(gXcvrSpiInstance_c, 16000000);
vpcola 0:f1d3878b8dd9 417
vpcola 0:f1d3878b8dd9 418 gXcvrAssertCS_d();
vpcola 0:f1d3878b8dd9 419
vpcola 0:f1d3878b8dd9 420 txData = TransceiverSPI_IARIndexReg;
vpcola 0:f1d3878b8dd9 421 txData |= (startAddress) << 8;
vpcola 0:f1d3878b8dd9 422
vpcola 0:f1d3878b8dd9 423 xcvr_spi_transfer(gXcvrSpiInstance_c, (uint8_t*)&txData, 0, sizeof(txData));
vpcola 0:f1d3878b8dd9 424 xcvr_spi_transfer(gXcvrSpiInstance_c, (uint8_t*)byteArray, 0, numOfBytes);
vpcola 0:f1d3878b8dd9 425
vpcola 0:f1d3878b8dd9 426 gXcvrDeassertCS_d();
vpcola 0:f1d3878b8dd9 427 UnprotectFromMCR20Interrupt();
vpcola 0:f1d3878b8dd9 428 }
vpcola 0:f1d3878b8dd9 429
vpcola 0:f1d3878b8dd9 430 /*---------------------------------------------------------------------------
vpcola 0:f1d3878b8dd9 431 * Name: MCR20Drv_IndirectAccessSPIRead
vpcola 0:f1d3878b8dd9 432 * Description: -
vpcola 0:f1d3878b8dd9 433 * Parameters: -
vpcola 0:f1d3878b8dd9 434 * Return: -
vpcola 0:f1d3878b8dd9 435 *---------------------------------------------------------------------------*/
vpcola 0:f1d3878b8dd9 436 uint8_t MCR20Drv_IndirectAccessSPIRead
vpcola 0:f1d3878b8dd9 437 (
vpcola 0:f1d3878b8dd9 438 uint8_t address
vpcola 0:f1d3878b8dd9 439 )
vpcola 0:f1d3878b8dd9 440 {
vpcola 0:f1d3878b8dd9 441 uint16_t txData;
vpcola 0:f1d3878b8dd9 442 uint8_t rxData;
vpcola 0:f1d3878b8dd9 443
vpcola 0:f1d3878b8dd9 444 ProtectFromMCR20Interrupt();
vpcola 0:f1d3878b8dd9 445
vpcola 0:f1d3878b8dd9 446 xcvr_spi_configure_speed(gXcvrSpiInstance_c, 8000000);
vpcola 0:f1d3878b8dd9 447
vpcola 0:f1d3878b8dd9 448 gXcvrAssertCS_d();
vpcola 0:f1d3878b8dd9 449
vpcola 0:f1d3878b8dd9 450 txData = TransceiverSPI_IARIndexReg | TransceiverSPI_ReadSelect;
vpcola 0:f1d3878b8dd9 451 txData |= (address) << 8;
vpcola 0:f1d3878b8dd9 452
vpcola 0:f1d3878b8dd9 453 xcvr_spi_transfer(gXcvrSpiInstance_c, (uint8_t*)&txData, 0, sizeof(txData));
vpcola 0:f1d3878b8dd9 454 xcvr_spi_transfer(gXcvrSpiInstance_c, 0, &rxData, sizeof(rxData));
vpcola 0:f1d3878b8dd9 455
vpcola 0:f1d3878b8dd9 456 gXcvrDeassertCS_d();
vpcola 0:f1d3878b8dd9 457 UnprotectFromMCR20Interrupt();
vpcola 0:f1d3878b8dd9 458
vpcola 0:f1d3878b8dd9 459 return rxData;
vpcola 0:f1d3878b8dd9 460 }
vpcola 0:f1d3878b8dd9 461
vpcola 0:f1d3878b8dd9 462 /*---------------------------------------------------------------------------
vpcola 0:f1d3878b8dd9 463 * Name: MCR20Drv_IndirectAccessSPIMultiByteRead
vpcola 0:f1d3878b8dd9 464 * Description: -
vpcola 0:f1d3878b8dd9 465 * Parameters: -
vpcola 0:f1d3878b8dd9 466 * Return: -
vpcola 0:f1d3878b8dd9 467 *---------------------------------------------------------------------------*/
vpcola 0:f1d3878b8dd9 468 void MCR20Drv_IndirectAccessSPIMultiByteRead
vpcola 0:f1d3878b8dd9 469 (
vpcola 0:f1d3878b8dd9 470 uint8_t startAddress,
vpcola 0:f1d3878b8dd9 471 uint8_t * byteArray,
vpcola 0:f1d3878b8dd9 472 uint8_t numOfBytes
vpcola 0:f1d3878b8dd9 473 )
vpcola 0:f1d3878b8dd9 474 {
vpcola 0:f1d3878b8dd9 475 uint16_t txData;
vpcola 0:f1d3878b8dd9 476
vpcola 0:f1d3878b8dd9 477 if( (numOfBytes == 0) || (byteArray == 0) )
vpcola 0:f1d3878b8dd9 478 {
vpcola 0:f1d3878b8dd9 479 return;
vpcola 0:f1d3878b8dd9 480 }
vpcola 0:f1d3878b8dd9 481
vpcola 0:f1d3878b8dd9 482 ProtectFromMCR20Interrupt();
vpcola 0:f1d3878b8dd9 483
vpcola 0:f1d3878b8dd9 484 xcvr_spi_configure_speed(gXcvrSpiInstance_c, 8000000);
vpcola 0:f1d3878b8dd9 485
vpcola 0:f1d3878b8dd9 486 gXcvrAssertCS_d();
vpcola 0:f1d3878b8dd9 487
vpcola 0:f1d3878b8dd9 488 txData = (TransceiverSPI_IARIndexReg | TransceiverSPI_ReadSelect);
vpcola 0:f1d3878b8dd9 489 txData |= (startAddress) << 8;
vpcola 0:f1d3878b8dd9 490
vpcola 0:f1d3878b8dd9 491 xcvr_spi_transfer(gXcvrSpiInstance_c, (uint8_t*)&txData, 0, sizeof(txData));
vpcola 0:f1d3878b8dd9 492 xcvr_spi_transfer(gXcvrSpiInstance_c, 0, byteArray, numOfBytes);
vpcola 0:f1d3878b8dd9 493
vpcola 0:f1d3878b8dd9 494 gXcvrDeassertCS_d();
vpcola 0:f1d3878b8dd9 495 UnprotectFromMCR20Interrupt();
vpcola 0:f1d3878b8dd9 496 }
vpcola 0:f1d3878b8dd9 497
vpcola 0:f1d3878b8dd9 498 /*---------------------------------------------------------------------------
vpcola 0:f1d3878b8dd9 499 * Name: MCR20Drv_IsIrqPending
vpcola 0:f1d3878b8dd9 500 * Description: -
vpcola 0:f1d3878b8dd9 501 * Parameters: -
vpcola 0:f1d3878b8dd9 502 * Return: -
vpcola 0:f1d3878b8dd9 503 *---------------------------------------------------------------------------*/
vpcola 0:f1d3878b8dd9 504 uint32_t MCR20Drv_IsIrqPending
vpcola 0:f1d3878b8dd9 505 (
vpcola 0:f1d3878b8dd9 506 void
vpcola 0:f1d3878b8dd9 507 )
vpcola 0:f1d3878b8dd9 508 {
vpcola 0:f1d3878b8dd9 509 return RF_isIRQ_Pending();
vpcola 0:f1d3878b8dd9 510 }
vpcola 0:f1d3878b8dd9 511
vpcola 0:f1d3878b8dd9 512 /*---------------------------------------------------------------------------
vpcola 0:f1d3878b8dd9 513 * Name: MCR20Drv_IRQ_Disable
vpcola 0:f1d3878b8dd9 514 * Description: -
vpcola 0:f1d3878b8dd9 515 * Parameters: -
vpcola 0:f1d3878b8dd9 516 * Return: -
vpcola 0:f1d3878b8dd9 517 *---------------------------------------------------------------------------*/
vpcola 0:f1d3878b8dd9 518 void MCR20Drv_IRQ_Disable
vpcola 0:f1d3878b8dd9 519 (
vpcola 0:f1d3878b8dd9 520 void
vpcola 0:f1d3878b8dd9 521 )
vpcola 0:f1d3878b8dd9 522 {
vpcola 0:f1d3878b8dd9 523 platform_enter_critical();
vpcola 0:f1d3878b8dd9 524
vpcola 0:f1d3878b8dd9 525 if( mPhyIrqDisableCnt == 0 )
vpcola 0:f1d3878b8dd9 526 {
vpcola 0:f1d3878b8dd9 527 RF_IRQ_Disable();
vpcola 0:f1d3878b8dd9 528 }
vpcola 0:f1d3878b8dd9 529
vpcola 0:f1d3878b8dd9 530 mPhyIrqDisableCnt++;
vpcola 0:f1d3878b8dd9 531
vpcola 0:f1d3878b8dd9 532 platform_exit_critical();
vpcola 0:f1d3878b8dd9 533 }
vpcola 0:f1d3878b8dd9 534
vpcola 0:f1d3878b8dd9 535 /*---------------------------------------------------------------------------
vpcola 0:f1d3878b8dd9 536 * Name: MCR20Drv_IRQ_Enable
vpcola 0:f1d3878b8dd9 537 * Description: -
vpcola 0:f1d3878b8dd9 538 * Parameters: -
vpcola 0:f1d3878b8dd9 539 * Return: -
vpcola 0:f1d3878b8dd9 540 *---------------------------------------------------------------------------*/
vpcola 0:f1d3878b8dd9 541 void MCR20Drv_IRQ_Enable
vpcola 0:f1d3878b8dd9 542 (
vpcola 0:f1d3878b8dd9 543 void
vpcola 0:f1d3878b8dd9 544 )
vpcola 0:f1d3878b8dd9 545 {
vpcola 0:f1d3878b8dd9 546 platform_enter_critical();
vpcola 0:f1d3878b8dd9 547
vpcola 0:f1d3878b8dd9 548 if( mPhyIrqDisableCnt )
vpcola 0:f1d3878b8dd9 549 {
vpcola 0:f1d3878b8dd9 550 mPhyIrqDisableCnt--;
vpcola 0:f1d3878b8dd9 551
vpcola 0:f1d3878b8dd9 552 if( mPhyIrqDisableCnt == 0 )
vpcola 0:f1d3878b8dd9 553 {
vpcola 0:f1d3878b8dd9 554 RF_IRQ_Enable();
vpcola 0:f1d3878b8dd9 555 }
vpcola 0:f1d3878b8dd9 556 }
vpcola 0:f1d3878b8dd9 557
vpcola 0:f1d3878b8dd9 558 platform_exit_critical();
vpcola 0:f1d3878b8dd9 559 }
vpcola 0:f1d3878b8dd9 560
vpcola 0:f1d3878b8dd9 561 /*---------------------------------------------------------------------------
vpcola 0:f1d3878b8dd9 562 * Name: MCR20Drv_RST_Assert
vpcola 0:f1d3878b8dd9 563 * Description: -
vpcola 0:f1d3878b8dd9 564 * Parameters: -
vpcola 0:f1d3878b8dd9 565 * Return: -
vpcola 0:f1d3878b8dd9 566 *---------------------------------------------------------------------------*/
vpcola 0:f1d3878b8dd9 567 void MCR20Drv_RST_B_Assert
vpcola 0:f1d3878b8dd9 568 (
vpcola 0:f1d3878b8dd9 569 void
vpcola 0:f1d3878b8dd9 570 )
vpcola 0:f1d3878b8dd9 571 {
vpcola 0:f1d3878b8dd9 572 RF_RST_Set(0);
vpcola 0:f1d3878b8dd9 573 }
vpcola 0:f1d3878b8dd9 574
vpcola 0:f1d3878b8dd9 575 /*---------------------------------------------------------------------------
vpcola 0:f1d3878b8dd9 576 * Name: MCR20Drv_RST_Deassert
vpcola 0:f1d3878b8dd9 577 * Description: -
vpcola 0:f1d3878b8dd9 578 * Parameters: -
vpcola 0:f1d3878b8dd9 579 * Return: -
vpcola 0:f1d3878b8dd9 580 *---------------------------------------------------------------------------*/
vpcola 0:f1d3878b8dd9 581 void MCR20Drv_RST_B_Deassert
vpcola 0:f1d3878b8dd9 582 (
vpcola 0:f1d3878b8dd9 583 void
vpcola 0:f1d3878b8dd9 584 )
vpcola 0:f1d3878b8dd9 585 {
vpcola 0:f1d3878b8dd9 586 RF_RST_Set(1);
vpcola 0:f1d3878b8dd9 587 }
vpcola 0:f1d3878b8dd9 588
vpcola 0:f1d3878b8dd9 589 /*---------------------------------------------------------------------------
vpcola 0:f1d3878b8dd9 590 * Name: MCR20Drv_SoftRST_Assert
vpcola 0:f1d3878b8dd9 591 * Description: -
vpcola 0:f1d3878b8dd9 592 * Parameters: -
vpcola 0:f1d3878b8dd9 593 * Return: -
vpcola 0:f1d3878b8dd9 594 *---------------------------------------------------------------------------*/
vpcola 0:f1d3878b8dd9 595 void MCR20Drv_SoftRST_Assert
vpcola 0:f1d3878b8dd9 596 (
vpcola 0:f1d3878b8dd9 597 void
vpcola 0:f1d3878b8dd9 598 )
vpcola 0:f1d3878b8dd9 599 {
vpcola 0:f1d3878b8dd9 600 MCR20Drv_IndirectAccessSPIWrite(SOFT_RESET, (0x80));
vpcola 0:f1d3878b8dd9 601 }
vpcola 0:f1d3878b8dd9 602
vpcola 0:f1d3878b8dd9 603 /*---------------------------------------------------------------------------
vpcola 0:f1d3878b8dd9 604 * Name: MCR20Drv_SoftRST_Deassert
vpcola 0:f1d3878b8dd9 605 * Description: -
vpcola 0:f1d3878b8dd9 606 * Parameters: -
vpcola 0:f1d3878b8dd9 607 * Return: -
vpcola 0:f1d3878b8dd9 608 *---------------------------------------------------------------------------*/
vpcola 0:f1d3878b8dd9 609 void MCR20Drv_SoftRST_Deassert
vpcola 0:f1d3878b8dd9 610 (
vpcola 0:f1d3878b8dd9 611 void
vpcola 0:f1d3878b8dd9 612 )
vpcola 0:f1d3878b8dd9 613 {
vpcola 0:f1d3878b8dd9 614 MCR20Drv_IndirectAccessSPIWrite(SOFT_RESET, (0x00));
vpcola 0:f1d3878b8dd9 615 }
vpcola 0:f1d3878b8dd9 616
vpcola 0:f1d3878b8dd9 617 /*---------------------------------------------------------------------------
vpcola 0:f1d3878b8dd9 618 * Name: MCR20Drv_Soft_RESET
vpcola 0:f1d3878b8dd9 619 * Description: -
vpcola 0:f1d3878b8dd9 620 * Parameters: -
vpcola 0:f1d3878b8dd9 621 * Return: -
vpcola 0:f1d3878b8dd9 622 *---------------------------------------------------------------------------*/
vpcola 0:f1d3878b8dd9 623 void MCR20Drv_Soft_RESET
vpcola 0:f1d3878b8dd9 624 (
vpcola 0:f1d3878b8dd9 625 void
vpcola 0:f1d3878b8dd9 626 )
vpcola 0:f1d3878b8dd9 627 {
vpcola 0:f1d3878b8dd9 628 //assert SOG_RST
vpcola 0:f1d3878b8dd9 629 MCR20Drv_IndirectAccessSPIWrite(SOFT_RESET, (0x80));
vpcola 0:f1d3878b8dd9 630
vpcola 0:f1d3878b8dd9 631 //deassert SOG_RST
vpcola 0:f1d3878b8dd9 632 MCR20Drv_IndirectAccessSPIWrite(SOFT_RESET, (0x00));
vpcola 0:f1d3878b8dd9 633 }
vpcola 0:f1d3878b8dd9 634
vpcola 0:f1d3878b8dd9 635 /*---------------------------------------------------------------------------
vpcola 0:f1d3878b8dd9 636 * Name: MCR20Drv_RESET
vpcola 0:f1d3878b8dd9 637 * Description: -
vpcola 0:f1d3878b8dd9 638 * Parameters: -
vpcola 0:f1d3878b8dd9 639 * Return: -
vpcola 0:f1d3878b8dd9 640 *---------------------------------------------------------------------------*/
vpcola 0:f1d3878b8dd9 641 void MCR20Drv_RESET
vpcola 0:f1d3878b8dd9 642 (
vpcola 0:f1d3878b8dd9 643 void
vpcola 0:f1d3878b8dd9 644 )
vpcola 0:f1d3878b8dd9 645 {
vpcola 0:f1d3878b8dd9 646 volatile uint32_t delay = 1000;
vpcola 0:f1d3878b8dd9 647 //assert RST_B
vpcola 0:f1d3878b8dd9 648 MCR20Drv_RST_B_Assert();
vpcola 0:f1d3878b8dd9 649
vpcola 0:f1d3878b8dd9 650 while(delay--);
vpcola 0:f1d3878b8dd9 651
vpcola 0:f1d3878b8dd9 652 //deassert RST_B
vpcola 0:f1d3878b8dd9 653 MCR20Drv_RST_B_Deassert();
vpcola 0:f1d3878b8dd9 654 }
vpcola 0:f1d3878b8dd9 655
vpcola 0:f1d3878b8dd9 656 /*---------------------------------------------------------------------------
vpcola 0:f1d3878b8dd9 657 * Name: MCR20Drv_Set_CLK_OUT_Freq
vpcola 0:f1d3878b8dd9 658 * Description: -
vpcola 0:f1d3878b8dd9 659 * Parameters: -
vpcola 0:f1d3878b8dd9 660 * Return: -
vpcola 0:f1d3878b8dd9 661 *---------------------------------------------------------------------------*/
vpcola 0:f1d3878b8dd9 662 void MCR20Drv_Set_CLK_OUT_Freq
vpcola 0:f1d3878b8dd9 663 (
vpcola 0:f1d3878b8dd9 664 uint8_t freqDiv
vpcola 0:f1d3878b8dd9 665 )
vpcola 0:f1d3878b8dd9 666 {
vpcola 0:f1d3878b8dd9 667 uint8_t clkOutCtrlReg = (freqDiv & cCLK_OUT_DIV_Mask) | cCLK_OUT_EN | cCLK_OUT_EXTEND;
vpcola 0:f1d3878b8dd9 668
vpcola 0:f1d3878b8dd9 669 if(freqDiv == gCLK_OUT_FREQ_DISABLE)
vpcola 0:f1d3878b8dd9 670 {
vpcola 0:f1d3878b8dd9 671 clkOutCtrlReg = (cCLK_OUT_EXTEND | gCLK_OUT_FREQ_4_MHz); //reset value with clock out disabled
vpcola 0:f1d3878b8dd9 672 }
vpcola 0:f1d3878b8dd9 673
vpcola 0:f1d3878b8dd9 674 MCR20Drv_DirectAccessSPIWrite((uint8_t) CLK_OUT_CTRL, clkOutCtrlReg);
vpcola 0:f1d3878b8dd9 675 }