Vergil Cola / Mbed OS MQTTGatewayK64

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easy-connect/atmel-rf-driver/source/AT86RFReg.h@0:f1d3878b8dd9, 2017-04-08 (annotated)

Committer:
vpcola
Date:
Sat Apr 08 14:45:51 2017 +0000
Revision:
0:f1d3878b8dd9
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
vpcola 0:f1d3878b8dd9 1 /*
vpcola 0:f1d3878b8dd9 2 * Copyright (c) 2014-2015 ARM Limited. All rights reserved.
vpcola 0:f1d3878b8dd9 3 * SPDX-License-Identifier: Apache-2.0
vpcola 0:f1d3878b8dd9 4 * Licensed under the Apache License, Version 2.0 (the License); you may
vpcola 0:f1d3878b8dd9 5 * not use this file except in compliance with the License.
vpcola 0:f1d3878b8dd9 6 * You may obtain a copy of the License at
vpcola 0:f1d3878b8dd9 7 *
vpcola 0:f1d3878b8dd9 8 * http://www.apache.org/licenses/LICENSE-2.0
vpcola 0:f1d3878b8dd9 9 *
vpcola 0:f1d3878b8dd9 10 * Unless required by applicable law or agreed to in writing, software
vpcola 0:f1d3878b8dd9 11 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
vpcola 0:f1d3878b8dd9 12 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
vpcola 0:f1d3878b8dd9 13 * See the License for the specific language governing permissions and
vpcola 0:f1d3878b8dd9 14 * limitations under the License.
vpcola 0:f1d3878b8dd9 15 */
vpcola 0:f1d3878b8dd9 16
vpcola 0:f1d3878b8dd9 17 #ifndef AT86RFREG_H_
vpcola 0:f1d3878b8dd9 18 #define AT86RFREG_H_
vpcola 0:f1d3878b8dd9 19 #ifdef __cplusplus
vpcola 0:f1d3878b8dd9 20 extern "C" {
vpcola 0:f1d3878b8dd9 21 #endif
vpcola 0:f1d3878b8dd9 22
vpcola 0:f1d3878b8dd9 23 /*AT86RF212 PHY Modes*/
vpcola 0:f1d3878b8dd9 24 #define BPSK_20 0x00
vpcola 0:f1d3878b8dd9 25 #define BPSK_40 0x04
vpcola 0:f1d3878b8dd9 26 #define BPSK_40_ALT 0x14
vpcola 0:f1d3878b8dd9 27 #define OQPSK_SIN_RC_100 0x08
vpcola 0:f1d3878b8dd9 28 #define OQPSK_SIN_RC_200 0x09
vpcola 0:f1d3878b8dd9 29 #define OQPSK_RC_100 0x18
vpcola 0:f1d3878b8dd9 30 #define OQPSK_RC_200 0x19
vpcola 0:f1d3878b8dd9 31 #define OQPSK_SIN_250 0x0c
vpcola 0:f1d3878b8dd9 32 #define OQPSK_SIN_500 0x0d
vpcola 0:f1d3878b8dd9 33 #define OQPSK_SIN_500_ALT 0x0f
vpcola 0:f1d3878b8dd9 34 #define OQPSK_RC_250 0x1c
vpcola 0:f1d3878b8dd9 35 #define OQPSK_RC_500 0x1d
vpcola 0:f1d3878b8dd9 36 #define OQPSK_RC_500_ALT 0x1f
vpcola 0:f1d3878b8dd9 37 #define OQPSK_SIN_RC_400_SCR_ON 0x2A
vpcola 0:f1d3878b8dd9 38 #define OQPSK_SIN_RC_400_SCR_OFF 0x0A
vpcola 0:f1d3878b8dd9 39 #define OQPSK_RC_400_SCR_ON 0x3A
vpcola 0:f1d3878b8dd9 40 #define OQPSK_RC_400_SCR_OFF 0x1A
vpcola 0:f1d3878b8dd9 41 #define OQPSK_SIN_1000_SCR_ON 0x2E
vpcola 0:f1d3878b8dd9 42 #define OQPSK_SIN_1000_SCR_OFF 0x0E
vpcola 0:f1d3878b8dd9 43 #define OQPSK_RC_1000_SCR_ON 0x3E
vpcola 0:f1d3878b8dd9 44 #define OQPSK_RC_1000_SCR_OFF 0x1E
vpcola 0:f1d3878b8dd9 45
vpcola 0:f1d3878b8dd9 46 /*Supported transceivers*/
vpcola 0:f1d3878b8dd9 47 #define PART_AT86RF231 0x03
vpcola 0:f1d3878b8dd9 48 #define PART_AT86RF212 0x07
vpcola 0:f1d3878b8dd9 49 #define PART_AT86RF233 0x0B
vpcola 0:f1d3878b8dd9 50 #define VERSION_AT86RF212 0x01
vpcola 0:f1d3878b8dd9 51 #define VERSION_AT86RF212B 0x03
vpcola 0:f1d3878b8dd9 52
vpcola 0:f1d3878b8dd9 53 /*RF Configuration Registers*/
vpcola 0:f1d3878b8dd9 54 #define TRX_STATUS 0x01
vpcola 0:f1d3878b8dd9 55 #define TRX_STATE 0x02
vpcola 0:f1d3878b8dd9 56 #define TRX_CTRL_0 0x03
vpcola 0:f1d3878b8dd9 57 #define TRX_CTRL_1 0x04
vpcola 0:f1d3878b8dd9 58 #define PHY_TX_PWR 0x05
vpcola 0:f1d3878b8dd9 59 #define PHY_RSSI 0x06
vpcola 0:f1d3878b8dd9 60 #define PHY_ED_LEVEL 0x07
vpcola 0:f1d3878b8dd9 61 #define PHY_CC_CCA 0x08
vpcola 0:f1d3878b8dd9 62 #define RX_CTRL 0x0A
vpcola 0:f1d3878b8dd9 63 #define SFD_VALUE 0x0B
vpcola 0:f1d3878b8dd9 64 #define TRX_CTRL_2 0x0C
vpcola 0:f1d3878b8dd9 65 #define ANT_DIV 0x0D
vpcola 0:f1d3878b8dd9 66 #define IRQ_MASK 0x0E
vpcola 0:f1d3878b8dd9 67 #define IRQ_STATUS 0x0F
vpcola 0:f1d3878b8dd9 68 #define VREG_CTRL 0x10
vpcola 0:f1d3878b8dd9 69 #define BATMON 0x11
vpcola 0:f1d3878b8dd9 70 #define XOSC_CTRL 0x12
vpcola 0:f1d3878b8dd9 71 #define CC_CTRL_0 0x13
vpcola 0:f1d3878b8dd9 72 #define CC_CTRL_1 0x14
vpcola 0:f1d3878b8dd9 73 #define RX_SYN 0x15
vpcola 0:f1d3878b8dd9 74 #define TRX_RPC 0x16
vpcola 0:f1d3878b8dd9 75 #define RF_CTRL_0 0x16
vpcola 0:f1d3878b8dd9 76 #define XAH_CTRL_1 0x17
vpcola 0:f1d3878b8dd9 77 #define FTN_CTRL 0x18
vpcola 0:f1d3878b8dd9 78 #define PLL_CF 0x1A
vpcola 0:f1d3878b8dd9 79 #define PLL_DCU 0x1B
vpcola 0:f1d3878b8dd9 80 #define PART_NUM 0x1C
vpcola 0:f1d3878b8dd9 81 #define VERSION_NUM 0x1D
vpcola 0:f1d3878b8dd9 82 #define MAN_ID_0 0x1E
vpcola 0:f1d3878b8dd9 83 #define MAN_ID_1 0x1F
vpcola 0:f1d3878b8dd9 84 #define SHORT_ADDR_0 0x20
vpcola 0:f1d3878b8dd9 85 #define SHORT_ADDR_1 0x21
vpcola 0:f1d3878b8dd9 86 #define PAN_ID_0 0x22
vpcola 0:f1d3878b8dd9 87 #define PAN_ID_1 0x23
vpcola 0:f1d3878b8dd9 88 #define IEEE_ADDR_0 0x24
vpcola 0:f1d3878b8dd9 89 #define IEEE_ADDR_1 0x25
vpcola 0:f1d3878b8dd9 90 #define IEEE_ADDR_2 0x26
vpcola 0:f1d3878b8dd9 91 #define IEEE_ADDR_3 0x27
vpcola 0:f1d3878b8dd9 92 #define IEEE_ADDR_4 0x28
vpcola 0:f1d3878b8dd9 93 #define IEEE_ADDR_5 0x29
vpcola 0:f1d3878b8dd9 94 #define IEEE_ADDR_6 0x2A
vpcola 0:f1d3878b8dd9 95 #define IEEE_ADDR_7 0x2B
vpcola 0:f1d3878b8dd9 96 #define XAH_CTRL_0 0x2C
vpcola 0:f1d3878b8dd9 97 #define CSMA_SEED_0 0x2D
vpcola 0:f1d3878b8dd9 98 #define CSMA_SEED_1 0x2E
vpcola 0:f1d3878b8dd9 99 #define CSMA_BE 0x2F
vpcola 0:f1d3878b8dd9 100
vpcola 0:f1d3878b8dd9 101 /* CSMA_SEED_1*/
vpcola 0:f1d3878b8dd9 102 #define AACK_FVN_MODE1 7
vpcola 0:f1d3878b8dd9 103 #define AACK_FVN_MODE0 6
vpcola 0:f1d3878b8dd9 104 #define AACK_SET_PD 5
vpcola 0:f1d3878b8dd9 105 #define AACK_DIS_ACK 4
vpcola 0:f1d3878b8dd9 106 #define AACK_I_AM_COORD 3
vpcola 0:f1d3878b8dd9 107 #define CSMA_SEED_12 2
vpcola 0:f1d3878b8dd9 108 #define CSMA_SEED_11 1
vpcola 0:f1d3878b8dd9 109 #define CSMA_SEED_10 0
vpcola 0:f1d3878b8dd9 110
vpcola 0:f1d3878b8dd9 111 /*TRX_STATUS bits*/
vpcola 0:f1d3878b8dd9 112 #define CCA_STATUS 0x40
vpcola 0:f1d3878b8dd9 113 #define CCA_DONE 0x80
vpcola 0:f1d3878b8dd9 114
vpcola 0:f1d3878b8dd9 115 /*PHY_CC_CCA bits*/
vpcola 0:f1d3878b8dd9 116 #define CCA_REQUEST 0x80
vpcola 0:f1d3878b8dd9 117 #define CCA_MODE_1 0x20
vpcola 0:f1d3878b8dd9 118 #define CCA_MODE_3 0x60
vpcola 0:f1d3878b8dd9 119
vpcola 0:f1d3878b8dd9 120 /*IRQ_MASK bits*/
vpcola 0:f1d3878b8dd9 121 #define RX_START 0x04
vpcola 0:f1d3878b8dd9 122 #define TRX_END 0x08
vpcola 0:f1d3878b8dd9 123 #define CCA_ED_DONE 0x10
vpcola 0:f1d3878b8dd9 124 #define AMI 0x20
vpcola 0:f1d3878b8dd9 125 #define TRX_UR 0x40
vpcola 0:f1d3878b8dd9 126
vpcola 0:f1d3878b8dd9 127 /*ANT_DIV bits*/
vpcola 0:f1d3878b8dd9 128 #define ANT_DIV_EN 0x08
vpcola 0:f1d3878b8dd9 129 #define ANT_EXT_SW_EN 0x04
vpcola 0:f1d3878b8dd9 130 #define ANT_CTRL_DEFAULT 0x03
vpcola 0:f1d3878b8dd9 131
vpcola 0:f1d3878b8dd9 132 /*TRX_CTRL_1 bits*/
vpcola 0:f1d3878b8dd9 133 #define PA_EXT_EN 0x80
vpcola 0:f1d3878b8dd9 134
vpcola 0:f1d3878b8dd9 135 /*FTN_CTRL bits*/
vpcola 0:f1d3878b8dd9 136 #define FTN_START 0x80
vpcola 0:f1d3878b8dd9 137
vpcola 0:f1d3878b8dd9 138 /*PHY_RSSI bits*/
vpcola 0:f1d3878b8dd9 139 #define CRC_VALID 0x80
vpcola 0:f1d3878b8dd9 140
vpcola 0:f1d3878b8dd9 141 /*RX_SYN bits*/
vpcola 0:f1d3878b8dd9 142 #define RX_PDT_DIS 0x80
vpcola 0:f1d3878b8dd9 143
vpcola 0:f1d3878b8dd9 144 /*TRX_RPC bits */
vpcola 0:f1d3878b8dd9 145 #define RX_RPC_CTRL 0xC0
vpcola 0:f1d3878b8dd9 146 #define RX_RPC_EN 0x20
vpcola 0:f1d3878b8dd9 147 #define PDT_RPC_EN 0x10
vpcola 0:f1d3878b8dd9 148 #define PLL_RPC_EN 0x08
vpcola 0:f1d3878b8dd9 149 #define XAH_TX_RPC_EN 0x04
vpcola 0:f1d3878b8dd9 150 #define IPAN_RPC_EN 0x02
vpcola 0:f1d3878b8dd9 151 #define TRX_RPC_RSVD_1 0x01
vpcola 0:f1d3878b8dd9 152
vpcola 0:f1d3878b8dd9 153 /*XAH_CTRL_1 bits*/
vpcola 0:f1d3878b8dd9 154 #define AACK_PROM_MODE 0x02
vpcola 0:f1d3878b8dd9 155
vpcola 0:f1d3878b8dd9 156
vpcola 0:f1d3878b8dd9 157 #ifdef __cplusplus
vpcola 0:f1d3878b8dd9 158 }
vpcola 0:f1d3878b8dd9 159 #endif
vpcola 0:f1d3878b8dd9 160
vpcola 0:f1d3878b8dd9 161 #endif /* AT86RFREG_H_ */