Vergil Cola
/
MQTTGateway2
Fork of my original MQTTGateway
easy-connect/stm-spirit1-rf-driver/source/libs/spirit1/SPIRIT1_Library/Inc/SPIRIT_Irq.h@0:a1734fe1ec4b, 2017-04-08 (annotated)
- Committer:
- vpcola
- Date:
- Sat Apr 08 14:43:14 2017 +0000
- Revision:
- 0:a1734fe1ec4b
Initial commit
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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vpcola | 0:a1734fe1ec4b | 1 | /** |
vpcola | 0:a1734fe1ec4b | 2 | ****************************************************************************** |
vpcola | 0:a1734fe1ec4b | 3 | * @file SPIRIT_Irq.h |
vpcola | 0:a1734fe1ec4b | 4 | * @author VMA division - AMS |
vpcola | 0:a1734fe1ec4b | 5 | * @version 3.2.2 |
vpcola | 0:a1734fe1ec4b | 6 | * @date 08-July-2015 |
vpcola | 0:a1734fe1ec4b | 7 | * @brief Configuration and management of SPIRIT IRQs. |
vpcola | 0:a1734fe1ec4b | 8 | * |
vpcola | 0:a1734fe1ec4b | 9 | * @details |
vpcola | 0:a1734fe1ec4b | 10 | * |
vpcola | 0:a1734fe1ec4b | 11 | * On the Spirit side specific IRQs can be enabled by setting a specific bitmask. |
vpcola | 0:a1734fe1ec4b | 12 | * The Spirit libraries allow the user to do this in two different ways: |
vpcola | 0:a1734fe1ec4b | 13 | * <ul> |
vpcola | 0:a1734fe1ec4b | 14 | * |
vpcola | 0:a1734fe1ec4b | 15 | * <li>The first enables the IRQs one by one, i.e. using an SPI transaction for each |
vpcola | 0:a1734fe1ec4b | 16 | * IRQ to enable. |
vpcola | 0:a1734fe1ec4b | 17 | * |
vpcola | 0:a1734fe1ec4b | 18 | * <b>Example:</b> |
vpcola | 0:a1734fe1ec4b | 19 | * @code |
vpcola | 0:a1734fe1ec4b | 20 | * |
vpcola | 0:a1734fe1ec4b | 21 | * SpiritIrqDeInit(NULL); // this call is used to reset the IRQ mask registers |
vpcola | 0:a1734fe1ec4b | 22 | * SpiritIrq(RX_DATA_READY , S_ENABLE); |
vpcola | 0:a1734fe1ec4b | 23 | * SpiritIrq(VALID_SYNC , S_ENABLE); |
vpcola | 0:a1734fe1ec4b | 24 | * SpiritIrq(RX_TIMEOUT , S_ENABLE); |
vpcola | 0:a1734fe1ec4b | 25 | * |
vpcola | 0:a1734fe1ec4b | 26 | * @endcode |
vpcola | 0:a1734fe1ec4b | 27 | * |
vpcola | 0:a1734fe1ec4b | 28 | * </li> |
vpcola | 0:a1734fe1ec4b | 29 | * |
vpcola | 0:a1734fe1ec4b | 30 | * <li>The second strategy is to set the IRQ bitfields structure. So, during the initialization the user |
vpcola | 0:a1734fe1ec4b | 31 | * has to fill the @ref SpiritIrqs structure setting to one the single field related to the IRQ he |
vpcola | 0:a1734fe1ec4b | 32 | * wants to enable, and to zero the single field related to all the IRQs he wants to disable. |
vpcola | 0:a1734fe1ec4b | 33 | * |
vpcola | 0:a1734fe1ec4b | 34 | * <b>Example:</b> |
vpcola | 0:a1734fe1ec4b | 35 | * @code |
vpcola | 0:a1734fe1ec4b | 36 | * |
vpcola | 0:a1734fe1ec4b | 37 | * SpiritIrqs irqMask; |
vpcola | 0:a1734fe1ec4b | 38 | * |
vpcola | 0:a1734fe1ec4b | 39 | * ... |
vpcola | 0:a1734fe1ec4b | 40 | * |
vpcola | 0:a1734fe1ec4b | 41 | * SpiritIrqDeInit(&irqMask); // this call is used to reset the IRQ mask registers |
vpcola | 0:a1734fe1ec4b | 42 | * // and to set to 0x00000000 the irq mask in order to disable |
vpcola | 0:a1734fe1ec4b | 43 | * // all IRQs (disabled by default on startup) |
vpcola | 0:a1734fe1ec4b | 44 | * irqMask.IRQ_RX_DATA_READY = 1; |
vpcola | 0:a1734fe1ec4b | 45 | * irqMask.IRQ_VALID_SYNC = 1; |
vpcola | 0:a1734fe1ec4b | 46 | * irqMask.IRQ_RX_TIMEOUT = 1; |
vpcola | 0:a1734fe1ec4b | 47 | * |
vpcola | 0:a1734fe1ec4b | 48 | * ... |
vpcola | 0:a1734fe1ec4b | 49 | * @endcode |
vpcola | 0:a1734fe1ec4b | 50 | * </li> |
vpcola | 0:a1734fe1ec4b | 51 | * </ul> |
vpcola | 0:a1734fe1ec4b | 52 | * |
vpcola | 0:a1734fe1ec4b | 53 | * The most applications will require a Spirit IRQ notification on an microcontroller EXTI line. |
vpcola | 0:a1734fe1ec4b | 54 | * Then, the user can check which IRQ has been raised using two different ways. |
vpcola | 0:a1734fe1ec4b | 55 | * |
vpcola | 0:a1734fe1ec4b | 56 | * On the ISR of the EXTI line phisically linked to the Spirit pin configured for IRQ: |
vpcola | 0:a1734fe1ec4b | 57 | * |
vpcola | 0:a1734fe1ec4b | 58 | * <ul> |
vpcola | 0:a1734fe1ec4b | 59 | * <li> Check <b>only one</b> Spirit IRQ (because the Spirit IRQ status register automatically blanks itself |
vpcola | 0:a1734fe1ec4b | 60 | * after an SPI reading) into the ISR. |
vpcola | 0:a1734fe1ec4b | 61 | * |
vpcola | 0:a1734fe1ec4b | 62 | * <b>Example:</b> |
vpcola | 0:a1734fe1ec4b | 63 | * @code |
vpcola | 0:a1734fe1ec4b | 64 | * |
vpcola | 0:a1734fe1ec4b | 65 | * if(SpiritIrqCheckFlag(RX_DATA_READY)) |
vpcola | 0:a1734fe1ec4b | 66 | * { |
vpcola | 0:a1734fe1ec4b | 67 | * // do something... |
vpcola | 0:a1734fe1ec4b | 68 | * } |
vpcola | 0:a1734fe1ec4b | 69 | * |
vpcola | 0:a1734fe1ec4b | 70 | * @endcode |
vpcola | 0:a1734fe1ec4b | 71 | * </li> |
vpcola | 0:a1734fe1ec4b | 72 | * |
vpcola | 0:a1734fe1ec4b | 73 | * <li> Check more than one Spirit IRQ status by storing the entire IRQ status registers into a bitfields <i>@ref SpiritIrqs</i> structure |
vpcola | 0:a1734fe1ec4b | 74 | * and then check the interested bits. |
vpcola | 0:a1734fe1ec4b | 75 | * |
vpcola | 0:a1734fe1ec4b | 76 | * <b>Example:</b> |
vpcola | 0:a1734fe1ec4b | 77 | * @code |
vpcola | 0:a1734fe1ec4b | 78 | * |
vpcola | 0:a1734fe1ec4b | 79 | * SpiritIrqGetStatus(&irqStatus); |
vpcola | 0:a1734fe1ec4b | 80 | * |
vpcola | 0:a1734fe1ec4b | 81 | * if(irqStatus.IRQ_RX_DATA_READY) |
vpcola | 0:a1734fe1ec4b | 82 | * { |
vpcola | 0:a1734fe1ec4b | 83 | * // do something... |
vpcola | 0:a1734fe1ec4b | 84 | * } |
vpcola | 0:a1734fe1ec4b | 85 | * if(irqStatus.IRQ_VALID_SYNC) |
vpcola | 0:a1734fe1ec4b | 86 | * { |
vpcola | 0:a1734fe1ec4b | 87 | * // do something... |
vpcola | 0:a1734fe1ec4b | 88 | * } |
vpcola | 0:a1734fe1ec4b | 89 | * if(irqStatus.RX_TIMEOUT) |
vpcola | 0:a1734fe1ec4b | 90 | * { |
vpcola | 0:a1734fe1ec4b | 91 | * // do something... |
vpcola | 0:a1734fe1ec4b | 92 | * } |
vpcola | 0:a1734fe1ec4b | 93 | * |
vpcola | 0:a1734fe1ec4b | 94 | * @endcode |
vpcola | 0:a1734fe1ec4b | 95 | * </li> |
vpcola | 0:a1734fe1ec4b | 96 | * </ul> |
vpcola | 0:a1734fe1ec4b | 97 | * |
vpcola | 0:a1734fe1ec4b | 98 | |
vpcola | 0:a1734fe1ec4b | 99 | * @attention |
vpcola | 0:a1734fe1ec4b | 100 | * |
vpcola | 0:a1734fe1ec4b | 101 | * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> |
vpcola | 0:a1734fe1ec4b | 102 | * |
vpcola | 0:a1734fe1ec4b | 103 | * Redistribution and use in source and binary forms, with or without modification, |
vpcola | 0:a1734fe1ec4b | 104 | * are permitted provided that the following conditions are met: |
vpcola | 0:a1734fe1ec4b | 105 | * 1. Redistributions of source code must retain the above copyright notice, |
vpcola | 0:a1734fe1ec4b | 106 | * this list of conditions and the following disclaimer. |
vpcola | 0:a1734fe1ec4b | 107 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
vpcola | 0:a1734fe1ec4b | 108 | * this list of conditions and the following disclaimer in the documentation |
vpcola | 0:a1734fe1ec4b | 109 | * and/or other materials provided with the distribution. |
vpcola | 0:a1734fe1ec4b | 110 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
vpcola | 0:a1734fe1ec4b | 111 | * may be used to endorse or promote products derived from this software |
vpcola | 0:a1734fe1ec4b | 112 | * without specific prior written permission. |
vpcola | 0:a1734fe1ec4b | 113 | * |
vpcola | 0:a1734fe1ec4b | 114 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
vpcola | 0:a1734fe1ec4b | 115 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
vpcola | 0:a1734fe1ec4b | 116 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
vpcola | 0:a1734fe1ec4b | 117 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
vpcola | 0:a1734fe1ec4b | 118 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
vpcola | 0:a1734fe1ec4b | 119 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
vpcola | 0:a1734fe1ec4b | 120 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
vpcola | 0:a1734fe1ec4b | 121 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
vpcola | 0:a1734fe1ec4b | 122 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
vpcola | 0:a1734fe1ec4b | 123 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
vpcola | 0:a1734fe1ec4b | 124 | * |
vpcola | 0:a1734fe1ec4b | 125 | ****************************************************************************** |
vpcola | 0:a1734fe1ec4b | 126 | */ |
vpcola | 0:a1734fe1ec4b | 127 | |
vpcola | 0:a1734fe1ec4b | 128 | /* Define to prevent recursive inclusion -------------------------------------*/ |
vpcola | 0:a1734fe1ec4b | 129 | #ifndef __SPIRIT1_IRQ_H |
vpcola | 0:a1734fe1ec4b | 130 | #define __SPIRIT1_IRQ_H |
vpcola | 0:a1734fe1ec4b | 131 | |
vpcola | 0:a1734fe1ec4b | 132 | |
vpcola | 0:a1734fe1ec4b | 133 | /* Includes ------------------------------------------------------------------*/ |
vpcola | 0:a1734fe1ec4b | 134 | |
vpcola | 0:a1734fe1ec4b | 135 | #include "SPIRIT_Regs.h" |
vpcola | 0:a1734fe1ec4b | 136 | #include "SPIRIT_Types.h" |
vpcola | 0:a1734fe1ec4b | 137 | |
vpcola | 0:a1734fe1ec4b | 138 | |
vpcola | 0:a1734fe1ec4b | 139 | #ifdef __cplusplus |
vpcola | 0:a1734fe1ec4b | 140 | extern "C" { |
vpcola | 0:a1734fe1ec4b | 141 | #endif |
vpcola | 0:a1734fe1ec4b | 142 | |
vpcola | 0:a1734fe1ec4b | 143 | |
vpcola | 0:a1734fe1ec4b | 144 | /** |
vpcola | 0:a1734fe1ec4b | 145 | * @addtogroup SPIRIT_Libraries |
vpcola | 0:a1734fe1ec4b | 146 | * @{ |
vpcola | 0:a1734fe1ec4b | 147 | */ |
vpcola | 0:a1734fe1ec4b | 148 | |
vpcola | 0:a1734fe1ec4b | 149 | |
vpcola | 0:a1734fe1ec4b | 150 | /** |
vpcola | 0:a1734fe1ec4b | 151 | * @defgroup SPIRIT_Irq IRQ |
vpcola | 0:a1734fe1ec4b | 152 | * @brief Configuration and management of SPIRIT IRQs. |
vpcola | 0:a1734fe1ec4b | 153 | * @details See the file <i>@ref SPIRIT_Irq.h</i> for more details. |
vpcola | 0:a1734fe1ec4b | 154 | * @{ |
vpcola | 0:a1734fe1ec4b | 155 | */ |
vpcola | 0:a1734fe1ec4b | 156 | |
vpcola | 0:a1734fe1ec4b | 157 | /** |
vpcola | 0:a1734fe1ec4b | 158 | * @defgroup Irq_Exported_Types IRQ Exported Types |
vpcola | 0:a1734fe1ec4b | 159 | * @{ |
vpcola | 0:a1734fe1ec4b | 160 | */ |
vpcola | 0:a1734fe1ec4b | 161 | |
vpcola | 0:a1734fe1ec4b | 162 | |
vpcola | 0:a1734fe1ec4b | 163 | /** |
vpcola | 0:a1734fe1ec4b | 164 | * @brief IRQ bitfield structure for SPIRIT. This structure is used to read or write the single IRQ bit. |
vpcola | 0:a1734fe1ec4b | 165 | * During the initialization the user has to fill this structure setting to one the single field related |
vpcola | 0:a1734fe1ec4b | 166 | * to the IRQ he wants to enable, and to zero the single field related to all the IRQs he wants to disable. |
vpcola | 0:a1734fe1ec4b | 167 | * The same structure can be used to retrieve all the IRQ events from the IRQ registers IRQ_STATUS[3:0], |
vpcola | 0:a1734fe1ec4b | 168 | * and read if one or more specific IRQ raised. |
vpcola | 0:a1734fe1ec4b | 169 | * @note The fields order in the structure depends on used endianness (little or big |
vpcola | 0:a1734fe1ec4b | 170 | * endian). The actual definition is valid ONLY for LITTLE ENDIAN mode. Be sure to |
vpcola | 0:a1734fe1ec4b | 171 | * change opportunely the fields order when use a different endianness. |
vpcola | 0:a1734fe1ec4b | 172 | */ |
vpcola | 0:a1734fe1ec4b | 173 | typedef struct |
vpcola | 0:a1734fe1ec4b | 174 | { |
vpcola | 0:a1734fe1ec4b | 175 | SpiritFlagStatus IRQ_SYNTH_LOCK_TIMEOUT:1; /*!< IRQ: only for debug; LOCK state timeout */ |
vpcola | 0:a1734fe1ec4b | 176 | SpiritFlagStatus IRQ_SYNTH_LOCK_STARTUP:1; /*!< IRQ: only for debug; see CALIBR_START_COUNTER */ |
vpcola | 0:a1734fe1ec4b | 177 | SpiritFlagStatus IRQ_SYNTH_CAL_TIMEOUT:1; /*!< IRQ: only for debug; SYNTH calibration timeout */ |
vpcola | 0:a1734fe1ec4b | 178 | SpiritFlagStatus IRQ_TX_START_TIME:1; /*!< IRQ: only for debug; TX circuitry startup time; see TX_START_COUNTER */ |
vpcola | 0:a1734fe1ec4b | 179 | SpiritFlagStatus IRQ_RX_START_TIME:1; /*!< IRQ: only for debug; RX circuitry startup time; see TX_START_COUNTER */ |
vpcola | 0:a1734fe1ec4b | 180 | SpiritFlagStatus IRQ_RX_TIMEOUT:1; /*!< IRQ: RX operation timeout */ |
vpcola | 0:a1734fe1ec4b | 181 | SpiritFlagStatus IRQ_AES_END:1; /*!< IRQ: AES End of operation */ |
vpcola | 0:a1734fe1ec4b | 182 | SpiritFlagStatus reserved:1; /*!< Reserved bit */ |
vpcola | 0:a1734fe1ec4b | 183 | |
vpcola | 0:a1734fe1ec4b | 184 | SpiritFlagStatus IRQ_READY:1; /*!< IRQ: READY state */ |
vpcola | 0:a1734fe1ec4b | 185 | SpiritFlagStatus IRQ_STANDBY_DELAYED:1; /*!< IRQ: STANDBY state after MCU_CK_CONF_CLOCK_TAIL_X clock cycles */ |
vpcola | 0:a1734fe1ec4b | 186 | SpiritFlagStatus IRQ_LOW_BATT_LVL:1; /*!< IRQ: Battery level below threshold*/ |
vpcola | 0:a1734fe1ec4b | 187 | SpiritFlagStatus IRQ_POR:1; /*!< IRQ: Power On Reset */ |
vpcola | 0:a1734fe1ec4b | 188 | SpiritFlagStatus IRQ_BOR:1; /*!< IRQ: Brown out event (both accurate and inaccurate)*/ |
vpcola | 0:a1734fe1ec4b | 189 | SpiritFlagStatus IRQ_LOCK:1; /*!< IRQ: LOCK state */ |
vpcola | 0:a1734fe1ec4b | 190 | SpiritFlagStatus IRQ_PM_COUNT_EXPIRED:1; /*!< IRQ: only for debug; Power Management startup timer expiration (see reg PM_START_COUNTER, 0xB5) */ |
vpcola | 0:a1734fe1ec4b | 191 | SpiritFlagStatus IRQ_XO_COUNT_EXPIRED:1; /*!< IRQ: only for debug; Crystal oscillator settling time counter expired */ |
vpcola | 0:a1734fe1ec4b | 192 | |
vpcola | 0:a1734fe1ec4b | 193 | SpiritFlagStatus IRQ_TX_FIFO_ALMOST_EMPTY:1; /*!< IRQ: TX FIFO almost empty */ |
vpcola | 0:a1734fe1ec4b | 194 | SpiritFlagStatus IRQ_RX_FIFO_ALMOST_FULL:1; /*!< IRQ: RX FIFO almost full */ |
vpcola | 0:a1734fe1ec4b | 195 | SpiritFlagStatus IRQ_RX_FIFO_ALMOST_EMPTY:1; /*!< IRQ: RX FIFO almost empty */ |
vpcola | 0:a1734fe1ec4b | 196 | SpiritFlagStatus IRQ_MAX_BO_CCA_REACH:1; /*!< IRQ: Max number of back-off during CCA */ |
vpcola | 0:a1734fe1ec4b | 197 | SpiritFlagStatus IRQ_VALID_PREAMBLE:1; /*!< IRQ: Valid preamble detected */ |
vpcola | 0:a1734fe1ec4b | 198 | SpiritFlagStatus IRQ_VALID_SYNC:1; /*!< IRQ: Sync word detected */ |
vpcola | 0:a1734fe1ec4b | 199 | SpiritFlagStatus IRQ_RSSI_ABOVE_TH:1; /*!< IRQ: RSSI above threshold */ |
vpcola | 0:a1734fe1ec4b | 200 | SpiritFlagStatus IRQ_WKUP_TOUT_LDC:1; /*!< IRQ: Wake-up timeout in LDC mode */ |
vpcola | 0:a1734fe1ec4b | 201 | |
vpcola | 0:a1734fe1ec4b | 202 | SpiritFlagStatus IRQ_RX_DATA_READY:1; /*!< IRQ: RX data ready */ |
vpcola | 0:a1734fe1ec4b | 203 | SpiritFlagStatus IRQ_RX_DATA_DISC:1; /*!< IRQ: RX data discarded (upon filtering) */ |
vpcola | 0:a1734fe1ec4b | 204 | SpiritFlagStatus IRQ_TX_DATA_SENT:1; /*!< IRQ: TX data sent */ |
vpcola | 0:a1734fe1ec4b | 205 | SpiritFlagStatus IRQ_MAX_RE_TX_REACH:1; /*!< IRQ: Max re-TX reached */ |
vpcola | 0:a1734fe1ec4b | 206 | SpiritFlagStatus IRQ_CRC_ERROR:1; /*!< IRQ: CRC error */ |
vpcola | 0:a1734fe1ec4b | 207 | SpiritFlagStatus IRQ_TX_FIFO_ERROR:1; /*!< IRQ: TX FIFO underflow/overflow error */ |
vpcola | 0:a1734fe1ec4b | 208 | SpiritFlagStatus IRQ_RX_FIFO_ERROR:1; /*!< IRQ: RX FIFO underflow/overflow error */ |
vpcola | 0:a1734fe1ec4b | 209 | SpiritFlagStatus IRQ_TX_FIFO_ALMOST_FULL:1; /*!< IRQ: TX FIFO almost full */ |
vpcola | 0:a1734fe1ec4b | 210 | } SpiritIrqs; |
vpcola | 0:a1734fe1ec4b | 211 | |
vpcola | 0:a1734fe1ec4b | 212 | // betzw: uint32_t masks |
vpcola | 0:a1734fe1ec4b | 213 | #define IRQ_TX_FIFO_ALMOST_EMPTY_MASK (0x00010000) /* (1<<16) */ |
vpcola | 0:a1734fe1ec4b | 214 | #define IRQ_RX_FIFO_ALMOST_FULL_MASK (0x00020000) /* (1<<17) */ |
vpcola | 0:a1734fe1ec4b | 215 | #define IRQ_VALID_SYNC_MASK (0x00200000) /* (1<<21) */ |
vpcola | 0:a1734fe1ec4b | 216 | #define IRQ_RX_DATA_READY_MASK (0x01000000) /* (1<<24) */ |
vpcola | 0:a1734fe1ec4b | 217 | #define IRQ_RX_DATA_DISC_MASK (0x02000000) /* (1<<25) */ |
vpcola | 0:a1734fe1ec4b | 218 | #define IRQ_TX_DATA_SENT_MASK (0x04000000) /* (1<<26) */ |
vpcola | 0:a1734fe1ec4b | 219 | #define IRQ_TX_FIFO_ERROR_MASK (0x20000000) /* (1<<29) */ |
vpcola | 0:a1734fe1ec4b | 220 | #define IRQ_RX_FIFO_ERROR_MASK (0x40000000) /* (1<<30) */ |
vpcola | 0:a1734fe1ec4b | 221 | |
vpcola | 0:a1734fe1ec4b | 222 | /** |
vpcola | 0:a1734fe1ec4b | 223 | * @brief IRQ list enumeration for SPIRIT. This enumeration type can be used to address a |
vpcola | 0:a1734fe1ec4b | 224 | * specific IRQ. |
vpcola | 0:a1734fe1ec4b | 225 | */ |
vpcola | 0:a1734fe1ec4b | 226 | typedef enum |
vpcola | 0:a1734fe1ec4b | 227 | { |
vpcola | 0:a1734fe1ec4b | 228 | RX_DATA_READY = 0x00000001, /*!< IRQ: RX data ready */ |
vpcola | 0:a1734fe1ec4b | 229 | RX_DATA_DISC = 0x00000002, /*!< IRQ: RX data discarded (upon filtering) */ |
vpcola | 0:a1734fe1ec4b | 230 | TX_DATA_SENT = 0x00000004, /*!< IRQ: TX data sent */ |
vpcola | 0:a1734fe1ec4b | 231 | MAX_RE_TX_REACH = 0x00000008, /*!< IRQ: Max re-TX reached */ |
vpcola | 0:a1734fe1ec4b | 232 | CRC_ERROR = 0x00000010, /*!< IRQ: CRC error */ |
vpcola | 0:a1734fe1ec4b | 233 | TX_FIFO_ERROR = 0x00000020, /*!< IRQ: TX FIFO underflow/overflow error */ |
vpcola | 0:a1734fe1ec4b | 234 | RX_FIFO_ERROR = 0x00000040, /*!< IRQ: RX FIFO underflow/overflow error */ |
vpcola | 0:a1734fe1ec4b | 235 | TX_FIFO_ALMOST_FULL = 0x00000080, /*!< IRQ: TX FIFO almost full */ |
vpcola | 0:a1734fe1ec4b | 236 | TX_FIFO_ALMOST_EMPTY = 0x00000100, /*!< IRQ: TX FIFO almost empty */ |
vpcola | 0:a1734fe1ec4b | 237 | RX_FIFO_ALMOST_FULL = 0x00000200, /*!< IRQ: RX FIFO almost full */ |
vpcola | 0:a1734fe1ec4b | 238 | RX_FIFO_ALMOST_EMPTY = 0x00000400, /*!< IRQ: RX FIFO almost empty */ |
vpcola | 0:a1734fe1ec4b | 239 | MAX_BO_CCA_REACH = 0x00000800, /*!< IRQ: Max number of back-off during CCA */ |
vpcola | 0:a1734fe1ec4b | 240 | VALID_PREAMBLE = 0x00001000, /*!< IRQ: Valid preamble detected */ |
vpcola | 0:a1734fe1ec4b | 241 | VALID_SYNC = 0x00002000, /*!< IRQ: Sync word detected */ |
vpcola | 0:a1734fe1ec4b | 242 | RSSI_ABOVE_TH = 0x00004000, /*!< IRQ: RSSI above threshold */ |
vpcola | 0:a1734fe1ec4b | 243 | WKUP_TOUT_LDC = 0x00008000, /*!< IRQ: Wake-up timeout in LDC mode */ |
vpcola | 0:a1734fe1ec4b | 244 | READY = 0x00010000, /*!< IRQ: READY state */ |
vpcola | 0:a1734fe1ec4b | 245 | STANDBY_DELAYED = 0x00020000, /*!< IRQ: STANDBY state after MCU_CK_CONF_CLOCK_TAIL_X clock cycles */ |
vpcola | 0:a1734fe1ec4b | 246 | LOW_BATT_LVL = 0x00040000, /*!< IRQ: Battery level below threshold*/ |
vpcola | 0:a1734fe1ec4b | 247 | POR = 0x00080000, /*!< IRQ: Power On Reset */ |
vpcola | 0:a1734fe1ec4b | 248 | BOR = 0x00100000, /*!< IRQ: Brown out event (both accurate and inaccurate)*/ |
vpcola | 0:a1734fe1ec4b | 249 | LOCK = 0x00200000, /*!< IRQ: LOCK state */ |
vpcola | 0:a1734fe1ec4b | 250 | PM_COUNT_EXPIRED = 0x00400000, /*!< IRQ: only for debug; Power Management startup timer expiration (see reg PM_START_COUNTER, 0xB5) */ |
vpcola | 0:a1734fe1ec4b | 251 | XO_COUNT_EXPIRED = 0x00800000, /*!< IRQ: only for debug; Crystal oscillator settling time counter expired */ |
vpcola | 0:a1734fe1ec4b | 252 | SYNTH_LOCK_TIMEOUT = 0x01000000, /*!< IRQ: only for debug; LOCK state timeout */ |
vpcola | 0:a1734fe1ec4b | 253 | SYNTH_LOCK_STARTUP = 0x02000000, /*!< IRQ: only for debug; see CALIBR_START_COUNTER */ |
vpcola | 0:a1734fe1ec4b | 254 | SYNTH_CAL_TIMEOUT = 0x04000000, /*!< IRQ: only for debug; SYNTH calibration timeout */ |
vpcola | 0:a1734fe1ec4b | 255 | TX_START_TIME = 0x08000000, /*!< IRQ: only for debug; TX circuitry startup time; see TX_START_COUNTER */ |
vpcola | 0:a1734fe1ec4b | 256 | RX_START_TIME = 0x10000000, /*!< IRQ: only for debug; RX circuitry startup time; see TX_START_COUNTER */ |
vpcola | 0:a1734fe1ec4b | 257 | RX_TIMEOUT = 0x20000000, /*!< IRQ: RX operation timeout */ |
vpcola | 0:a1734fe1ec4b | 258 | AES_END = 0x40000000, /*!< IRQ: AES End of operation */ |
vpcola | 0:a1734fe1ec4b | 259 | ALL_IRQ = 0x7FFFFFFF /*!< All the above mentioned IRQs */ |
vpcola | 0:a1734fe1ec4b | 260 | |
vpcola | 0:a1734fe1ec4b | 261 | } IrqList; |
vpcola | 0:a1734fe1ec4b | 262 | |
vpcola | 0:a1734fe1ec4b | 263 | #define IS_SPIRIT_IRQ_LIST(VALUE) ((VALUE == RX_DATA_READY) || \ |
vpcola | 0:a1734fe1ec4b | 264 | (VALUE == RX_DATA_DISC) || \ |
vpcola | 0:a1734fe1ec4b | 265 | (VALUE == TX_DATA_SENT) || \ |
vpcola | 0:a1734fe1ec4b | 266 | (VALUE == MAX_RE_TX_REACH) || \ |
vpcola | 0:a1734fe1ec4b | 267 | (VALUE == CRC_ERROR) || \ |
vpcola | 0:a1734fe1ec4b | 268 | (VALUE == TX_FIFO_ERROR) || \ |
vpcola | 0:a1734fe1ec4b | 269 | (VALUE == RX_FIFO_ERROR) || \ |
vpcola | 0:a1734fe1ec4b | 270 | (VALUE == TX_FIFO_ALMOST_FULL) || \ |
vpcola | 0:a1734fe1ec4b | 271 | (VALUE == TX_FIFO_ALMOST_EMPTY) || \ |
vpcola | 0:a1734fe1ec4b | 272 | (VALUE == RX_FIFO_ALMOST_FULL) || \ |
vpcola | 0:a1734fe1ec4b | 273 | (VALUE == RX_FIFO_ALMOST_EMPTY) || \ |
vpcola | 0:a1734fe1ec4b | 274 | (VALUE == MAX_BO_CCA_REACH) || \ |
vpcola | 0:a1734fe1ec4b | 275 | (VALUE == VALID_PREAMBLE) || \ |
vpcola | 0:a1734fe1ec4b | 276 | (VALUE == VALID_SYNC) || \ |
vpcola | 0:a1734fe1ec4b | 277 | (VALUE == RSSI_ABOVE_TH) || \ |
vpcola | 0:a1734fe1ec4b | 278 | (VALUE == WKUP_TOUT_LDC) || \ |
vpcola | 0:a1734fe1ec4b | 279 | (VALUE == READY) || \ |
vpcola | 0:a1734fe1ec4b | 280 | (VALUE == STANDBY_DELAYED) || \ |
vpcola | 0:a1734fe1ec4b | 281 | (VALUE == LOW_BATT_LVL) || \ |
vpcola | 0:a1734fe1ec4b | 282 | (VALUE == POR) || \ |
vpcola | 0:a1734fe1ec4b | 283 | (VALUE == BOR) || \ |
vpcola | 0:a1734fe1ec4b | 284 | (VALUE == LOCK) || \ |
vpcola | 0:a1734fe1ec4b | 285 | (VALUE == PM_COUNT_EXPIRED) || \ |
vpcola | 0:a1734fe1ec4b | 286 | (VALUE == XO_COUNT_EXPIRED) || \ |
vpcola | 0:a1734fe1ec4b | 287 | (VALUE == SYNTH_LOCK_TIMEOUT) || \ |
vpcola | 0:a1734fe1ec4b | 288 | (VALUE == SYNTH_LOCK_STARTUP) || \ |
vpcola | 0:a1734fe1ec4b | 289 | (VALUE == SYNTH_CAL_TIMEOUT) || \ |
vpcola | 0:a1734fe1ec4b | 290 | (VALUE == TX_START_TIME) || \ |
vpcola | 0:a1734fe1ec4b | 291 | (VALUE == RX_START_TIME) || \ |
vpcola | 0:a1734fe1ec4b | 292 | (VALUE == RX_TIMEOUT) || \ |
vpcola | 0:a1734fe1ec4b | 293 | (VALUE == AES_END) || \ |
vpcola | 0:a1734fe1ec4b | 294 | (VALUE == ALL_IRQ )) |
vpcola | 0:a1734fe1ec4b | 295 | |
vpcola | 0:a1734fe1ec4b | 296 | |
vpcola | 0:a1734fe1ec4b | 297 | /** |
vpcola | 0:a1734fe1ec4b | 298 | * @} |
vpcola | 0:a1734fe1ec4b | 299 | */ |
vpcola | 0:a1734fe1ec4b | 300 | |
vpcola | 0:a1734fe1ec4b | 301 | |
vpcola | 0:a1734fe1ec4b | 302 | /** |
vpcola | 0:a1734fe1ec4b | 303 | * @defgroup Irq_Exported_Constants IRQ Exported Constants |
vpcola | 0:a1734fe1ec4b | 304 | * @{ |
vpcola | 0:a1734fe1ec4b | 305 | */ |
vpcola | 0:a1734fe1ec4b | 306 | |
vpcola | 0:a1734fe1ec4b | 307 | |
vpcola | 0:a1734fe1ec4b | 308 | /** |
vpcola | 0:a1734fe1ec4b | 309 | * @} |
vpcola | 0:a1734fe1ec4b | 310 | */ |
vpcola | 0:a1734fe1ec4b | 311 | |
vpcola | 0:a1734fe1ec4b | 312 | |
vpcola | 0:a1734fe1ec4b | 313 | /** |
vpcola | 0:a1734fe1ec4b | 314 | * @defgroup Irq_Exported_Macros IRQ Exported Macros |
vpcola | 0:a1734fe1ec4b | 315 | * @{ |
vpcola | 0:a1734fe1ec4b | 316 | */ |
vpcola | 0:a1734fe1ec4b | 317 | |
vpcola | 0:a1734fe1ec4b | 318 | |
vpcola | 0:a1734fe1ec4b | 319 | /** |
vpcola | 0:a1734fe1ec4b | 320 | * @} |
vpcola | 0:a1734fe1ec4b | 321 | */ |
vpcola | 0:a1734fe1ec4b | 322 | |
vpcola | 0:a1734fe1ec4b | 323 | |
vpcola | 0:a1734fe1ec4b | 324 | /** |
vpcola | 0:a1734fe1ec4b | 325 | * @defgroup Irq_Exported_Functions IRQ Exported Functions |
vpcola | 0:a1734fe1ec4b | 326 | * @{ |
vpcola | 0:a1734fe1ec4b | 327 | */ |
vpcola | 0:a1734fe1ec4b | 328 | |
vpcola | 0:a1734fe1ec4b | 329 | void SpiritIrqDeInit(SpiritIrqs* pxIrqInit); |
vpcola | 0:a1734fe1ec4b | 330 | void SpiritIrqInit(SpiritIrqs* pxIrqInit); |
vpcola | 0:a1734fe1ec4b | 331 | void SpiritIrq(IrqList xIrq, SpiritFunctionalState xNewState); |
vpcola | 0:a1734fe1ec4b | 332 | void SpiritIrqGetMask(SpiritIrqs* pxIrqMask); |
vpcola | 0:a1734fe1ec4b | 333 | void SpiritIrqGetStatus(SpiritIrqs* pxIrqStatus); |
vpcola | 0:a1734fe1ec4b | 334 | void SpiritIrqClearStatus(void); |
vpcola | 0:a1734fe1ec4b | 335 | SpiritBool SpiritIrqCheckFlag(IrqList xFlag); |
vpcola | 0:a1734fe1ec4b | 336 | |
vpcola | 0:a1734fe1ec4b | 337 | /** |
vpcola | 0:a1734fe1ec4b | 338 | * @} |
vpcola | 0:a1734fe1ec4b | 339 | */ |
vpcola | 0:a1734fe1ec4b | 340 | |
vpcola | 0:a1734fe1ec4b | 341 | /** |
vpcola | 0:a1734fe1ec4b | 342 | * @} |
vpcola | 0:a1734fe1ec4b | 343 | */ |
vpcola | 0:a1734fe1ec4b | 344 | |
vpcola | 0:a1734fe1ec4b | 345 | |
vpcola | 0:a1734fe1ec4b | 346 | /** |
vpcola | 0:a1734fe1ec4b | 347 | * @} |
vpcola | 0:a1734fe1ec4b | 348 | */ |
vpcola | 0:a1734fe1ec4b | 349 | |
vpcola | 0:a1734fe1ec4b | 350 | |
vpcola | 0:a1734fe1ec4b | 351 | #ifdef __cplusplus |
vpcola | 0:a1734fe1ec4b | 352 | } |
vpcola | 0:a1734fe1ec4b | 353 | #endif |
vpcola | 0:a1734fe1ec4b | 354 | |
vpcola | 0:a1734fe1ec4b | 355 | #endif |
vpcola | 0:a1734fe1ec4b | 356 | |
vpcola | 0:a1734fe1ec4b | 357 | /******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/ |