V M / Mbed 2 deprecated NRF24L01_receiver

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Dependencies:   mbed nRF24L01P

mbed-rtos/rtx/rt_HAL_CM.h@0:fdfe93cb9255, 2013-05-27 (annotated)

Committer:
vmihalcut
Date:
Mon May 27 06:06:31 2013 +0000
Revision:
0:fdfe93cb9255
NRF24L01 receiver

Who changed what in which revision?

UserRevisionLine numberNew contents of line
vmihalcut 0:fdfe93cb9255 1 /*----------------------------------------------------------------------------
vmihalcut 0:fdfe93cb9255 2 * RL-ARM - RTX
vmihalcut 0:fdfe93cb9255 3 *----------------------------------------------------------------------------
vmihalcut 0:fdfe93cb9255 4 * Name: RT_HAL_CM.H
vmihalcut 0:fdfe93cb9255 5 * Purpose: Hardware Abstraction Layer for Cortex-M definitions
vmihalcut 0:fdfe93cb9255 6 * Rev.: V4.60
vmihalcut 0:fdfe93cb9255 7 *----------------------------------------------------------------------------
vmihalcut 0:fdfe93cb9255 8 *
vmihalcut 0:fdfe93cb9255 9 * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH
vmihalcut 0:fdfe93cb9255 10 * All rights reserved.
vmihalcut 0:fdfe93cb9255 11 * Redistribution and use in source and binary forms, with or without
vmihalcut 0:fdfe93cb9255 12 * modification, are permitted provided that the following conditions are met:
vmihalcut 0:fdfe93cb9255 13 * - Redistributions of source code must retain the above copyright
vmihalcut 0:fdfe93cb9255 14 * notice, this list of conditions and the following disclaimer.
vmihalcut 0:fdfe93cb9255 15 * - Redistributions in binary form must reproduce the above copyright
vmihalcut 0:fdfe93cb9255 16 * notice, this list of conditions and the following disclaimer in the
vmihalcut 0:fdfe93cb9255 17 * documentation and/or other materials provided with the distribution.
vmihalcut 0:fdfe93cb9255 18 * - Neither the name of ARM nor the names of its contributors may be used
vmihalcut 0:fdfe93cb9255 19 * to endorse or promote products derived from this software without
vmihalcut 0:fdfe93cb9255 20 * specific prior written permission.
vmihalcut 0:fdfe93cb9255 21 *
vmihalcut 0:fdfe93cb9255 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
vmihalcut 0:fdfe93cb9255 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
vmihalcut 0:fdfe93cb9255 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
vmihalcut 0:fdfe93cb9255 25 * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
vmihalcut 0:fdfe93cb9255 26 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
vmihalcut 0:fdfe93cb9255 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
vmihalcut 0:fdfe93cb9255 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
vmihalcut 0:fdfe93cb9255 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
vmihalcut 0:fdfe93cb9255 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
vmihalcut 0:fdfe93cb9255 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
vmihalcut 0:fdfe93cb9255 32 * POSSIBILITY OF SUCH DAMAGE.
vmihalcut 0:fdfe93cb9255 33 *---------------------------------------------------------------------------*/
vmihalcut 0:fdfe93cb9255 34
vmihalcut 0:fdfe93cb9255 35 /* Definitions */
vmihalcut 0:fdfe93cb9255 36 #define INITIAL_xPSR 0x01000000
vmihalcut 0:fdfe93cb9255 37 #define DEMCR_TRCENA 0x01000000
vmihalcut 0:fdfe93cb9255 38 #define ITM_ITMENA 0x00000001
vmihalcut 0:fdfe93cb9255 39 #define MAGIC_WORD 0xE25A2EA5
vmihalcut 0:fdfe93cb9255 40
vmihalcut 0:fdfe93cb9255 41 #if defined (__CC_ARM) /* ARM Compiler */
vmihalcut 0:fdfe93cb9255 42
vmihalcut 0:fdfe93cb9255 43 #if ((__TARGET_ARCH_7_M || __TARGET_ARCH_7E_M) && !NO_EXCLUSIVE_ACCESS)
vmihalcut 0:fdfe93cb9255 44 #define __USE_EXCLUSIVE_ACCESS
vmihalcut 0:fdfe93cb9255 45 #else
vmihalcut 0:fdfe93cb9255 46 #undef __USE_EXCLUSIVE_ACCESS
vmihalcut 0:fdfe93cb9255 47 #endif
vmihalcut 0:fdfe93cb9255 48
vmihalcut 0:fdfe93cb9255 49 #elif defined (__GNUC__) /* GNU Compiler */
vmihalcut 0:fdfe93cb9255 50
vmihalcut 0:fdfe93cb9255 51 #undef __USE_EXCLUSIVE_ACCESS
vmihalcut 0:fdfe93cb9255 52
vmihalcut 0:fdfe93cb9255 53 #if defined (__CORTEX_M0) || defined (__CORTEX_M0PLUS)
vmihalcut 0:fdfe93cb9255 54 #define __TARGET_ARCH_6S_M 1
vmihalcut 0:fdfe93cb9255 55 #else
vmihalcut 0:fdfe93cb9255 56 #define __TARGET_ARCH_6S_M 0
vmihalcut 0:fdfe93cb9255 57 #endif
vmihalcut 0:fdfe93cb9255 58
vmihalcut 0:fdfe93cb9255 59 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
vmihalcut 0:fdfe93cb9255 60 #define __TARGET_FPU_VFP 1
vmihalcut 0:fdfe93cb9255 61 #else
vmihalcut 0:fdfe93cb9255 62 #define __TARGET_FPU_VFP 0
vmihalcut 0:fdfe93cb9255 63 #endif
vmihalcut 0:fdfe93cb9255 64
vmihalcut 0:fdfe93cb9255 65 #define __inline inline
vmihalcut 0:fdfe93cb9255 66 #define __weak __attribute__((weak))
vmihalcut 0:fdfe93cb9255 67
vmihalcut 0:fdfe93cb9255 68 #ifndef __CMSIS_GENERIC
vmihalcut 0:fdfe93cb9255 69
vmihalcut 0:fdfe93cb9255 70 __attribute__((always_inline)) static inline void __enable_irq(void)
vmihalcut 0:fdfe93cb9255 71 {
vmihalcut 0:fdfe93cb9255 72 __asm volatile ("cpsie i");
vmihalcut 0:fdfe93cb9255 73 }
vmihalcut 0:fdfe93cb9255 74
vmihalcut 0:fdfe93cb9255 75 __attribute__((always_inline)) static inline U32 __disable_irq(void)
vmihalcut 0:fdfe93cb9255 76 {
vmihalcut 0:fdfe93cb9255 77 U32 result;
vmihalcut 0:fdfe93cb9255 78
vmihalcut 0:fdfe93cb9255 79 __asm volatile ("mrs %0, primask" : "=r" (result));
vmihalcut 0:fdfe93cb9255 80 __asm volatile ("cpsid i");
vmihalcut 0:fdfe93cb9255 81 return(result & 1);
vmihalcut 0:fdfe93cb9255 82 }
vmihalcut 0:fdfe93cb9255 83
vmihalcut 0:fdfe93cb9255 84 #endif
vmihalcut 0:fdfe93cb9255 85
vmihalcut 0:fdfe93cb9255 86 __attribute__(( always_inline)) static inline U8 __clz(U32 value)
vmihalcut 0:fdfe93cb9255 87 {
vmihalcut 0:fdfe93cb9255 88 U8 result;
vmihalcut 0:fdfe93cb9255 89
vmihalcut 0:fdfe93cb9255 90 __asm volatile ("clz %0, %1" : "=r" (result) : "r" (value));
vmihalcut 0:fdfe93cb9255 91 return(result);
vmihalcut 0:fdfe93cb9255 92 }
vmihalcut 0:fdfe93cb9255 93
vmihalcut 0:fdfe93cb9255 94 #elif defined (__ICCARM__) /* IAR Compiler */
vmihalcut 0:fdfe93cb9255 95
vmihalcut 0:fdfe93cb9255 96 #undef __USE_EXCLUSIVE_ACCESS
vmihalcut 0:fdfe93cb9255 97
vmihalcut 0:fdfe93cb9255 98 #if (__CORE__ == __ARM6M__)
vmihalcut 0:fdfe93cb9255 99 #define __TARGET_ARCH_6S_M 1
vmihalcut 0:fdfe93cb9255 100 #else
vmihalcut 0:fdfe93cb9255 101 #define __TARGET_ARCH_6S_M 0
vmihalcut 0:fdfe93cb9255 102 #endif
vmihalcut 0:fdfe93cb9255 103
vmihalcut 0:fdfe93cb9255 104 #if defined __ARMVFP__
vmihalcut 0:fdfe93cb9255 105 #define __TARGET_FPU_VFP 1
vmihalcut 0:fdfe93cb9255 106 #else
vmihalcut 0:fdfe93cb9255 107 #define __TARGET_FPU_VFP 0
vmihalcut 0:fdfe93cb9255 108 #endif
vmihalcut 0:fdfe93cb9255 109
vmihalcut 0:fdfe93cb9255 110 #define __inline inline
vmihalcut 0:fdfe93cb9255 111
vmihalcut 0:fdfe93cb9255 112 #ifndef __CMSIS_GENERIC
vmihalcut 0:fdfe93cb9255 113
vmihalcut 0:fdfe93cb9255 114 static inline void __enable_irq(void)
vmihalcut 0:fdfe93cb9255 115 {
vmihalcut 0:fdfe93cb9255 116 __asm volatile ("cpsie i");
vmihalcut 0:fdfe93cb9255 117 }
vmihalcut 0:fdfe93cb9255 118
vmihalcut 0:fdfe93cb9255 119 static inline U32 __disable_irq(void)
vmihalcut 0:fdfe93cb9255 120 {
vmihalcut 0:fdfe93cb9255 121 U32 result;
vmihalcut 0:fdfe93cb9255 122
vmihalcut 0:fdfe93cb9255 123 __asm volatile ("mrs %0, primask" : "=r" (result));
vmihalcut 0:fdfe93cb9255 124 __asm volatile ("cpsid i");
vmihalcut 0:fdfe93cb9255 125 return(result & 1);
vmihalcut 0:fdfe93cb9255 126 }
vmihalcut 0:fdfe93cb9255 127
vmihalcut 0:fdfe93cb9255 128 #endif
vmihalcut 0:fdfe93cb9255 129
vmihalcut 0:fdfe93cb9255 130 static inline U8 __clz(U32 value)
vmihalcut 0:fdfe93cb9255 131 {
vmihalcut 0:fdfe93cb9255 132 U8 result;
vmihalcut 0:fdfe93cb9255 133
vmihalcut 0:fdfe93cb9255 134 __asm volatile ("clz %0, %1" : "=r" (result) : "r" (value));
vmihalcut 0:fdfe93cb9255 135 return(result);
vmihalcut 0:fdfe93cb9255 136 }
vmihalcut 0:fdfe93cb9255 137
vmihalcut 0:fdfe93cb9255 138 #endif
vmihalcut 0:fdfe93cb9255 139
vmihalcut 0:fdfe93cb9255 140 /* NVIC registers */
vmihalcut 0:fdfe93cb9255 141 #define NVIC_ST_CTRL (*((volatile U32 *)0xE000E010))
vmihalcut 0:fdfe93cb9255 142 #define NVIC_ST_RELOAD (*((volatile U32 *)0xE000E014))
vmihalcut 0:fdfe93cb9255 143 #define NVIC_ST_CURRENT (*((volatile U32 *)0xE000E018))
vmihalcut 0:fdfe93cb9255 144 #define NVIC_ISER ((volatile U32 *)0xE000E100)
vmihalcut 0:fdfe93cb9255 145 #define NVIC_ICER ((volatile U32 *)0xE000E180)
vmihalcut 0:fdfe93cb9255 146 #if (__TARGET_ARCH_6S_M)
vmihalcut 0:fdfe93cb9255 147 #define NVIC_IP ((volatile U32 *)0xE000E400)
vmihalcut 0:fdfe93cb9255 148 #else
vmihalcut 0:fdfe93cb9255 149 #define NVIC_IP ((volatile U8 *)0xE000E400)
vmihalcut 0:fdfe93cb9255 150 #endif
vmihalcut 0:fdfe93cb9255 151 #define NVIC_INT_CTRL (*((volatile U32 *)0xE000ED04))
vmihalcut 0:fdfe93cb9255 152 #define NVIC_AIR_CTRL (*((volatile U32 *)0xE000ED0C))
vmihalcut 0:fdfe93cb9255 153 #define NVIC_SYS_PRI2 (*((volatile U32 *)0xE000ED1C))
vmihalcut 0:fdfe93cb9255 154 #define NVIC_SYS_PRI3 (*((volatile U32 *)0xE000ED20))
vmihalcut 0:fdfe93cb9255 155
vmihalcut 0:fdfe93cb9255 156 #define OS_PEND_IRQ() NVIC_INT_CTRL = (1<<28)
vmihalcut 0:fdfe93cb9255 157 #define OS_PENDING ((NVIC_INT_CTRL >> 26) & (1<<2 | 1))
vmihalcut 0:fdfe93cb9255 158 #define OS_UNPEND(fl) NVIC_INT_CTRL = (*fl = OS_PENDING) << 25
vmihalcut 0:fdfe93cb9255 159 #define OS_PEND(fl,p) NVIC_INT_CTRL = (fl | p<<2) << 26
vmihalcut 0:fdfe93cb9255 160 #define OS_LOCK() NVIC_ST_CTRL = 0x0005
vmihalcut 0:fdfe93cb9255 161 #define OS_UNLOCK() NVIC_ST_CTRL = 0x0007
vmihalcut 0:fdfe93cb9255 162
vmihalcut 0:fdfe93cb9255 163 #define OS_X_PENDING ((NVIC_INT_CTRL >> 28) & 1)
vmihalcut 0:fdfe93cb9255 164 #define OS_X_UNPEND(fl) NVIC_INT_CTRL = (*fl = OS_X_PENDING) << 27
vmihalcut 0:fdfe93cb9255 165 #define OS_X_PEND(fl,p) NVIC_INT_CTRL = (fl | p) << 28
vmihalcut 0:fdfe93cb9255 166 #if (__TARGET_ARCH_6S_M)
vmihalcut 0:fdfe93cb9255 167 #define OS_X_INIT(n) NVIC_IP[n>>2] |= 0xFF << (8*(n & 0x03)); \
vmihalcut 0:fdfe93cb9255 168 NVIC_ISER[n>>5] = 1 << (n & 0x1F)
vmihalcut 0:fdfe93cb9255 169 #else
vmihalcut 0:fdfe93cb9255 170 #define OS_X_INIT(n) NVIC_IP[n] = 0xFF; \
vmihalcut 0:fdfe93cb9255 171 NVIC_ISER[n>>5] = 1 << (n & 0x1F)
vmihalcut 0:fdfe93cb9255 172 #endif
vmihalcut 0:fdfe93cb9255 173 #define OS_X_LOCK(n) NVIC_ICER[n>>5] = 1 << (n & 0x1F)
vmihalcut 0:fdfe93cb9255 174 #define OS_X_UNLOCK(n) NVIC_ISER[n>>5] = 1 << (n & 0x1F)
vmihalcut 0:fdfe93cb9255 175
vmihalcut 0:fdfe93cb9255 176 /* Core Debug registers */
vmihalcut 0:fdfe93cb9255 177 #define DEMCR (*((volatile U32 *)0xE000EDFC))
vmihalcut 0:fdfe93cb9255 178
vmihalcut 0:fdfe93cb9255 179 /* ITM registers */
vmihalcut 0:fdfe93cb9255 180 #define ITM_CONTROL (*((volatile U32 *)0xE0000E80))
vmihalcut 0:fdfe93cb9255 181 #define ITM_ENABLE (*((volatile U32 *)0xE0000E00))
vmihalcut 0:fdfe93cb9255 182 #define ITM_PORT30_U32 (*((volatile U32 *)0xE0000078))
vmihalcut 0:fdfe93cb9255 183 #define ITM_PORT31_U32 (*((volatile U32 *)0xE000007C))
vmihalcut 0:fdfe93cb9255 184 #define ITM_PORT31_U16 (*((volatile U16 *)0xE000007C))
vmihalcut 0:fdfe93cb9255 185 #define ITM_PORT31_U8 (*((volatile U8 *)0xE000007C))
vmihalcut 0:fdfe93cb9255 186
vmihalcut 0:fdfe93cb9255 187 /* Variables */
vmihalcut 0:fdfe93cb9255 188 extern BIT dbg_msg;
vmihalcut 0:fdfe93cb9255 189
vmihalcut 0:fdfe93cb9255 190 /* Functions */
vmihalcut 0:fdfe93cb9255 191 #ifdef __USE_EXCLUSIVE_ACCESS
vmihalcut 0:fdfe93cb9255 192 #define rt_inc(p) while(__strex((__ldrex(p)+1),p))
vmihalcut 0:fdfe93cb9255 193 #define rt_dec(p) while(__strex((__ldrex(p)-1),p))
vmihalcut 0:fdfe93cb9255 194 #else
vmihalcut 0:fdfe93cb9255 195 #define rt_inc(p) __disable_irq();(*p)++;__enable_irq();
vmihalcut 0:fdfe93cb9255 196 #define rt_dec(p) __disable_irq();(*p)--;__enable_irq();
vmihalcut 0:fdfe93cb9255 197 #endif
vmihalcut 0:fdfe93cb9255 198
vmihalcut 0:fdfe93cb9255 199 __inline static U32 rt_inc_qi (U32 size, U8 *count, U8 *first) {
vmihalcut 0:fdfe93cb9255 200 U32 cnt,c2;
vmihalcut 0:fdfe93cb9255 201 #ifdef __USE_EXCLUSIVE_ACCESS
vmihalcut 0:fdfe93cb9255 202 do {
vmihalcut 0:fdfe93cb9255 203 if ((cnt = __ldrex(count)) == size) {
vmihalcut 0:fdfe93cb9255 204 __clrex();
vmihalcut 0:fdfe93cb9255 205 return (cnt); }
vmihalcut 0:fdfe93cb9255 206 } while (__strex(cnt+1, count));
vmihalcut 0:fdfe93cb9255 207 do {
vmihalcut 0:fdfe93cb9255 208 c2 = (cnt = __ldrex(first)) + 1;
vmihalcut 0:fdfe93cb9255 209 if (c2 == size) c2 = 0;
vmihalcut 0:fdfe93cb9255 210 } while (__strex(c2, first));
vmihalcut 0:fdfe93cb9255 211 #else
vmihalcut 0:fdfe93cb9255 212 __disable_irq();
vmihalcut 0:fdfe93cb9255 213 if ((cnt = *count) < size) {
vmihalcut 0:fdfe93cb9255 214 *count = cnt+1;
vmihalcut 0:fdfe93cb9255 215 c2 = (cnt = *first) + 1;
vmihalcut 0:fdfe93cb9255 216 if (c2 == size) c2 = 0;
vmihalcut 0:fdfe93cb9255 217 *first = c2;
vmihalcut 0:fdfe93cb9255 218 }
vmihalcut 0:fdfe93cb9255 219 __enable_irq ();
vmihalcut 0:fdfe93cb9255 220 #endif
vmihalcut 0:fdfe93cb9255 221 return (cnt);
vmihalcut 0:fdfe93cb9255 222 }
vmihalcut 0:fdfe93cb9255 223
vmihalcut 0:fdfe93cb9255 224 __inline static void rt_systick_init (void) {
vmihalcut 0:fdfe93cb9255 225 NVIC_ST_RELOAD = os_trv;
vmihalcut 0:fdfe93cb9255 226 NVIC_ST_CURRENT = 0;
vmihalcut 0:fdfe93cb9255 227 NVIC_ST_CTRL = 0x0007;
vmihalcut 0:fdfe93cb9255 228 NVIC_SYS_PRI3 |= 0xFF000000;
vmihalcut 0:fdfe93cb9255 229 }
vmihalcut 0:fdfe93cb9255 230
vmihalcut 0:fdfe93cb9255 231 __inline static void rt_svc_init (void) {
vmihalcut 0:fdfe93cb9255 232 #if !(__TARGET_ARCH_6S_M)
vmihalcut 0:fdfe93cb9255 233 int sh,prigroup;
vmihalcut 0:fdfe93cb9255 234 #endif
vmihalcut 0:fdfe93cb9255 235 NVIC_SYS_PRI3 |= 0x00FF0000;
vmihalcut 0:fdfe93cb9255 236 #if (__TARGET_ARCH_6S_M)
vmihalcut 0:fdfe93cb9255 237 NVIC_SYS_PRI2 |= (NVIC_SYS_PRI3<<(8+1)) & 0xFC000000;
vmihalcut 0:fdfe93cb9255 238 #else
vmihalcut 0:fdfe93cb9255 239 sh = 8 - __clz (~((NVIC_SYS_PRI3 << 8) & 0xFF000000));
vmihalcut 0:fdfe93cb9255 240 prigroup = ((NVIC_AIR_CTRL >> 8) & 0x07);
vmihalcut 0:fdfe93cb9255 241 if (prigroup >= sh) {
vmihalcut 0:fdfe93cb9255 242 sh = prigroup + 1;
vmihalcut 0:fdfe93cb9255 243 }
vmihalcut 0:fdfe93cb9255 244 NVIC_SYS_PRI2 = ((0xFEFFFFFF << sh) & 0xFF000000) | (NVIC_SYS_PRI2 & 0x00FFFFFF);
vmihalcut 0:fdfe93cb9255 245 #endif
vmihalcut 0:fdfe93cb9255 246 }
vmihalcut 0:fdfe93cb9255 247
vmihalcut 0:fdfe93cb9255 248 extern void rt_set_PSP (U32 stack);
vmihalcut 0:fdfe93cb9255 249 extern U32 rt_get_PSP (void);
vmihalcut 0:fdfe93cb9255 250 extern void os_set_env (void);
vmihalcut 0:fdfe93cb9255 251 extern void *_alloc_box (void *box_mem);
vmihalcut 0:fdfe93cb9255 252 extern int _free_box (void *box_mem, void *box);
vmihalcut 0:fdfe93cb9255 253
vmihalcut 0:fdfe93cb9255 254 extern void rt_init_stack (P_TCB p_TCB, FUNCP task_body);
vmihalcut 0:fdfe93cb9255 255 extern void rt_ret_val (P_TCB p_TCB, U32 v0);
vmihalcut 0:fdfe93cb9255 256 extern void rt_ret_val2 (P_TCB p_TCB, U32 v0, U32 v1);
vmihalcut 0:fdfe93cb9255 257
vmihalcut 0:fdfe93cb9255 258 extern void dbg_init (void);
vmihalcut 0:fdfe93cb9255 259 extern void dbg_task_notify (P_TCB p_tcb, BOOL create);
vmihalcut 0:fdfe93cb9255 260 extern void dbg_task_switch (U32 task_id);
vmihalcut 0:fdfe93cb9255 261
vmihalcut 0:fdfe93cb9255 262 #ifdef DBG_MSG
vmihalcut 0:fdfe93cb9255 263 #define DBG_INIT() dbg_init()
vmihalcut 0:fdfe93cb9255 264 #define DBG_TASK_NOTIFY(p_tcb,create) if (dbg_msg) dbg_task_notify(p_tcb,create)
vmihalcut 0:fdfe93cb9255 265 #define DBG_TASK_SWITCH(task_id) if (dbg_msg && (os_tsk.new_tsk != os_tsk.run)) \
vmihalcut 0:fdfe93cb9255 266 dbg_task_switch(task_id)
vmihalcut 0:fdfe93cb9255 267 #else
vmihalcut 0:fdfe93cb9255 268 #define DBG_INIT()
vmihalcut 0:fdfe93cb9255 269 #define DBG_TASK_NOTIFY(p_tcb,create)
vmihalcut 0:fdfe93cb9255 270 #define DBG_TASK_SWITCH(task_id)
vmihalcut 0:fdfe93cb9255 271 #endif
vmihalcut 0:fdfe93cb9255 272
vmihalcut 0:fdfe93cb9255 273 /*----------------------------------------------------------------------------
vmihalcut 0:fdfe93cb9255 274 * end of file
vmihalcut 0:fdfe93cb9255 275 *---------------------------------------------------------------------------*/
vmihalcut 0:fdfe93cb9255 276