Vladimir Vana / mbed

pro vyuku PSS v Jecne

TARGET_NUCLEO_F103RB/stm32f1xx_hal_iwdg.h@0:23d1f73bf130, 2017-09-24 (annotated)

Committer:
vladvana
Date:
Sun Sep 24 12:31:52 2017 +0000
Revision:
0:23d1f73bf130
podklady pro cviceni z PSS

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vladvana 0:23d1f73bf130 1 /**
vladvana 0:23d1f73bf130 2 ******************************************************************************
vladvana 0:23d1f73bf130 3 * @file stm32f1xx_hal_iwdg.h
vladvana 0:23d1f73bf130 4 * @author MCD Application Team
vladvana 0:23d1f73bf130 5 * @version V1.0.0
vladvana 0:23d1f73bf130 6 * @date 15-December-2014
vladvana 0:23d1f73bf130 7 * @brief Header file of IWDG HAL module.
vladvana 0:23d1f73bf130 8 ******************************************************************************
vladvana 0:23d1f73bf130 9 * @attention
vladvana 0:23d1f73bf130 10 *
vladvana 0:23d1f73bf130 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
vladvana 0:23d1f73bf130 12 *
vladvana 0:23d1f73bf130 13 * Redistribution and use in source and binary forms, with or without modification,
vladvana 0:23d1f73bf130 14 * are permitted provided that the following conditions are met:
vladvana 0:23d1f73bf130 15 * 1. Redistributions of source code must retain the above copyright notice,
vladvana 0:23d1f73bf130 16 * this list of conditions and the following disclaimer.
vladvana 0:23d1f73bf130 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
vladvana 0:23d1f73bf130 18 * this list of conditions and the following disclaimer in the documentation
vladvana 0:23d1f73bf130 19 * and/or other materials provided with the distribution.
vladvana 0:23d1f73bf130 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
vladvana 0:23d1f73bf130 21 * may be used to endorse or promote products derived from this software
vladvana 0:23d1f73bf130 22 * without specific prior written permission.
vladvana 0:23d1f73bf130 23 *
vladvana 0:23d1f73bf130 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
vladvana 0:23d1f73bf130 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
vladvana 0:23d1f73bf130 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
vladvana 0:23d1f73bf130 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
vladvana 0:23d1f73bf130 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
vladvana 0:23d1f73bf130 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
vladvana 0:23d1f73bf130 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
vladvana 0:23d1f73bf130 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
vladvana 0:23d1f73bf130 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
vladvana 0:23d1f73bf130 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
vladvana 0:23d1f73bf130 34 *
vladvana 0:23d1f73bf130 35 ******************************************************************************
vladvana 0:23d1f73bf130 36 */
vladvana 0:23d1f73bf130 37
vladvana 0:23d1f73bf130 38 /* Define to prevent recursive inclusion -------------------------------------*/
vladvana 0:23d1f73bf130 39 #ifndef __STM32F1xx_HAL_IWDG_H
vladvana 0:23d1f73bf130 40 #define __STM32F1xx_HAL_IWDG_H
vladvana 0:23d1f73bf130 41
vladvana 0:23d1f73bf130 42 #ifdef __cplusplus
vladvana 0:23d1f73bf130 43 extern "C" {
vladvana 0:23d1f73bf130 44 #endif
vladvana 0:23d1f73bf130 45
vladvana 0:23d1f73bf130 46 /* Includes ------------------------------------------------------------------*/
vladvana 0:23d1f73bf130 47 #include "stm32f1xx_hal_def.h"
vladvana 0:23d1f73bf130 48
vladvana 0:23d1f73bf130 49 /** @addtogroup STM32F1xx_HAL_Driver
vladvana 0:23d1f73bf130 50 * @{
vladvana 0:23d1f73bf130 51 */
vladvana 0:23d1f73bf130 52
vladvana 0:23d1f73bf130 53 /** @addtogroup IWDG
vladvana 0:23d1f73bf130 54 * @{
vladvana 0:23d1f73bf130 55 */
vladvana 0:23d1f73bf130 56
vladvana 0:23d1f73bf130 57 /* Exported types ------------------------------------------------------------*/
vladvana 0:23d1f73bf130 58
vladvana 0:23d1f73bf130 59 /** @defgroup IWDG_Exported_Types IWDG Exported Types
vladvana 0:23d1f73bf130 60 * @{
vladvana 0:23d1f73bf130 61 */
vladvana 0:23d1f73bf130 62
vladvana 0:23d1f73bf130 63 /**
vladvana 0:23d1f73bf130 64 * @brief IWDG HAL State Structure definition
vladvana 0:23d1f73bf130 65 */
vladvana 0:23d1f73bf130 66 typedef enum
vladvana 0:23d1f73bf130 67 {
vladvana 0:23d1f73bf130 68 HAL_IWDG_STATE_RESET = 0x00, /*!< IWDG not yet initialized or disabled */
vladvana 0:23d1f73bf130 69 HAL_IWDG_STATE_READY = 0x01, /*!< IWDG initialized and ready for use */
vladvana 0:23d1f73bf130 70 HAL_IWDG_STATE_BUSY = 0x02, /*!< IWDG internal process is ongoing */
vladvana 0:23d1f73bf130 71 HAL_IWDG_STATE_TIMEOUT = 0x03, /*!< IWDG timeout state */
vladvana 0:23d1f73bf130 72 HAL_IWDG_STATE_ERROR = 0x04 /*!< IWDG error state */
vladvana 0:23d1f73bf130 73
vladvana 0:23d1f73bf130 74 }HAL_IWDG_StateTypeDef;
vladvana 0:23d1f73bf130 75
vladvana 0:23d1f73bf130 76 /**
vladvana 0:23d1f73bf130 77 * @brief IWDG Init structure definition
vladvana 0:23d1f73bf130 78 */
vladvana 0:23d1f73bf130 79 typedef struct
vladvana 0:23d1f73bf130 80 {
vladvana 0:23d1f73bf130 81 uint32_t Prescaler; /*!< Select the prescaler of the IWDG.
vladvana 0:23d1f73bf130 82 This parameter can be a value of @ref IWDG_Prescaler */
vladvana 0:23d1f73bf130 83
vladvana 0:23d1f73bf130 84 uint32_t Reload; /*!< Specifies the IWDG down-counter reload value.
vladvana 0:23d1f73bf130 85 This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
vladvana 0:23d1f73bf130 86
vladvana 0:23d1f73bf130 87 }IWDG_InitTypeDef;
vladvana 0:23d1f73bf130 88
vladvana 0:23d1f73bf130 89 /**
vladvana 0:23d1f73bf130 90 * @brief IWDG Handle Structure definition
vladvana 0:23d1f73bf130 91 */
vladvana 0:23d1f73bf130 92 typedef struct
vladvana 0:23d1f73bf130 93 {
vladvana 0:23d1f73bf130 94 IWDG_TypeDef *Instance; /*!< Register base address */
vladvana 0:23d1f73bf130 95
vladvana 0:23d1f73bf130 96 IWDG_InitTypeDef Init; /*!< IWDG required parameters */
vladvana 0:23d1f73bf130 97
vladvana 0:23d1f73bf130 98 HAL_LockTypeDef Lock; /*!< IWDG Locking object */
vladvana 0:23d1f73bf130 99
vladvana 0:23d1f73bf130 100 __IO HAL_IWDG_StateTypeDef State; /*!< IWDG communication state */
vladvana 0:23d1f73bf130 101
vladvana 0:23d1f73bf130 102 }IWDG_HandleTypeDef;
vladvana 0:23d1f73bf130 103
vladvana 0:23d1f73bf130 104 /**
vladvana 0:23d1f73bf130 105 * @}
vladvana 0:23d1f73bf130 106 */
vladvana 0:23d1f73bf130 107
vladvana 0:23d1f73bf130 108 /* Exported constants --------------------------------------------------------*/
vladvana 0:23d1f73bf130 109
vladvana 0:23d1f73bf130 110 /** @defgroup IWDG_Exported_Constants IWDG Exported Constants
vladvana 0:23d1f73bf130 111 * @{
vladvana 0:23d1f73bf130 112 */
vladvana 0:23d1f73bf130 113
vladvana 0:23d1f73bf130 114 /** @defgroup IWDG_Registers_BitMask IWDG Registers BitMask
vladvana 0:23d1f73bf130 115 * @brief IWDG registers bit mask
vladvana 0:23d1f73bf130 116 * @{
vladvana 0:23d1f73bf130 117 */
vladvana 0:23d1f73bf130 118 /* --- KR Register ---*/
vladvana 0:23d1f73bf130 119 /* KR register bit mask */
vladvana 0:23d1f73bf130 120 #define IWDG_KEY_RELOAD ((uint32_t)0xAAAA) /*!< IWDG Reload Counter Enable */
vladvana 0:23d1f73bf130 121 #define IWDG_KEY_ENABLE ((uint32_t)0xCCCC) /*!< IWDG Peripheral Enable */
vladvana 0:23d1f73bf130 122 #define IWDG_KEY_WRITE_ACCESS_ENABLE ((uint32_t)0x5555) /*!< IWDG KR Write Access Enable */
vladvana 0:23d1f73bf130 123 #define IWDG_KEY_WRITE_ACCESS_DISABLE ((uint32_t)0x0000) /*!< IWDG KR Write Access Disable */
vladvana 0:23d1f73bf130 124
vladvana 0:23d1f73bf130 125 /**
vladvana 0:23d1f73bf130 126 * @}
vladvana 0:23d1f73bf130 127 */
vladvana 0:23d1f73bf130 128
vladvana 0:23d1f73bf130 129 /** @defgroup IWDG_Flag_definition IWDG Flag definition
vladvana 0:23d1f73bf130 130 * @{
vladvana 0:23d1f73bf130 131 */
vladvana 0:23d1f73bf130 132 #define IWDG_FLAG_PVU ((uint32_t)IWDG_SR_PVU) /*!< Watchdog counter prescaler value update Flag */
vladvana 0:23d1f73bf130 133 #define IWDG_FLAG_RVU ((uint32_t)IWDG_SR_RVU) /*!< Watchdog counter reload value update Flag */
vladvana 0:23d1f73bf130 134
vladvana 0:23d1f73bf130 135 /**
vladvana 0:23d1f73bf130 136 * @}
vladvana 0:23d1f73bf130 137 */
vladvana 0:23d1f73bf130 138
vladvana 0:23d1f73bf130 139 /** @defgroup IWDG_Prescaler IWDG Prescaler
vladvana 0:23d1f73bf130 140 * @{
vladvana 0:23d1f73bf130 141 */
vladvana 0:23d1f73bf130 142 #define IWDG_PRESCALER_4 ((uint8_t)0x00) /*!< IWDG prescaler set to 4 */
vladvana 0:23d1f73bf130 143 #define IWDG_PRESCALER_8 ((uint8_t)(IWDG_PR_PR_0)) /*!< IWDG prescaler set to 8 */
vladvana 0:23d1f73bf130 144 #define IWDG_PRESCALER_16 ((uint8_t)(IWDG_PR_PR_1)) /*!< IWDG prescaler set to 16 */
vladvana 0:23d1f73bf130 145 #define IWDG_PRESCALER_32 ((uint8_t)(IWDG_PR_PR_1 | IWDG_PR_PR_0)) /*!< IWDG prescaler set to 32 */
vladvana 0:23d1f73bf130 146 #define IWDG_PRESCALER_64 ((uint8_t)(IWDG_PR_PR_2)) /*!< IWDG prescaler set to 64 */
vladvana 0:23d1f73bf130 147 #define IWDG_PRESCALER_128 ((uint8_t)(IWDG_PR_PR_2 | IWDG_PR_PR_0)) /*!< IWDG prescaler set to 128 */
vladvana 0:23d1f73bf130 148 #define IWDG_PRESCALER_256 ((uint8_t)(IWDG_PR_PR_2 | IWDG_PR_PR_1)) /*!< IWDG prescaler set to 256 */
vladvana 0:23d1f73bf130 149
vladvana 0:23d1f73bf130 150 /**
vladvana 0:23d1f73bf130 151 * @}
vladvana 0:23d1f73bf130 152 */
vladvana 0:23d1f73bf130 153
vladvana 0:23d1f73bf130 154
vladvana 0:23d1f73bf130 155 /**
vladvana 0:23d1f73bf130 156 * @}
vladvana 0:23d1f73bf130 157 */
vladvana 0:23d1f73bf130 158
vladvana 0:23d1f73bf130 159 /* Exported macros -----------------------------------------------------------*/
vladvana 0:23d1f73bf130 160
vladvana 0:23d1f73bf130 161 /** @defgroup IWDG_Exported_Macros IWDG Exported Macros
vladvana 0:23d1f73bf130 162 * @{
vladvana 0:23d1f73bf130 163 */
vladvana 0:23d1f73bf130 164
vladvana 0:23d1f73bf130 165 /** @brief Reset IWDG handle state
vladvana 0:23d1f73bf130 166 * @param __HANDLE__: IWDG handle.
vladvana 0:23d1f73bf130 167 * @retval None
vladvana 0:23d1f73bf130 168 */
vladvana 0:23d1f73bf130 169 #define __HAL_IWDG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_IWDG_STATE_RESET)
vladvana 0:23d1f73bf130 170
vladvana 0:23d1f73bf130 171 /**
vladvana 0:23d1f73bf130 172 * @brief Enables the IWDG peripheral.
vladvana 0:23d1f73bf130 173 * @param __HANDLE__: IWDG handle
vladvana 0:23d1f73bf130 174 * @retval None
vladvana 0:23d1f73bf130 175 */
vladvana 0:23d1f73bf130 176 #define __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)
vladvana 0:23d1f73bf130 177
vladvana 0:23d1f73bf130 178 /**
vladvana 0:23d1f73bf130 179 * @brief Reloads IWDG counter with value defined in the reload register
vladvana 0:23d1f73bf130 180 * (write access to IWDG_PR and IWDG_RLR registers disabled).
vladvana 0:23d1f73bf130 181 * @param __HANDLE__: IWDG handle
vladvana 0:23d1f73bf130 182 * @retval None
vladvana 0:23d1f73bf130 183 */
vladvana 0:23d1f73bf130 184 #define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)
vladvana 0:23d1f73bf130 185
vladvana 0:23d1f73bf130 186
vladvana 0:23d1f73bf130 187
vladvana 0:23d1f73bf130 188 /**
vladvana 0:23d1f73bf130 189 * @brief Gets the selected IWDG's flag status.
vladvana 0:23d1f73bf130 190 * @param __HANDLE__: IWDG handle
vladvana 0:23d1f73bf130 191 * @param __FLAG__: specifies the flag to check.
vladvana 0:23d1f73bf130 192 * This parameter can be one of the following values:
vladvana 0:23d1f73bf130 193 * @arg IWDG_FLAG_PVU: Watchdog counter reload value update flag
vladvana 0:23d1f73bf130 194 * @arg IWDG_FLAG_RVU: Watchdog counter prescaler value flag
vladvana 0:23d1f73bf130 195 * @retval The new state of __FLAG__ (TRUE or FALSE).
vladvana 0:23d1f73bf130 196 */
vladvana 0:23d1f73bf130 197 #define __HAL_IWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
vladvana 0:23d1f73bf130 198
vladvana 0:23d1f73bf130 199 /**
vladvana 0:23d1f73bf130 200 * @}
vladvana 0:23d1f73bf130 201 */
vladvana 0:23d1f73bf130 202
vladvana 0:23d1f73bf130 203 /* Private macro -------------------------------------------------------------*/
vladvana 0:23d1f73bf130 204
vladvana 0:23d1f73bf130 205 /** @defgroup IWDG_Private_Macros IWDG Private Macros
vladvana 0:23d1f73bf130 206 * @{
vladvana 0:23d1f73bf130 207 */
vladvana 0:23d1f73bf130 208
vladvana 0:23d1f73bf130 209
vladvana 0:23d1f73bf130 210 /**
vladvana 0:23d1f73bf130 211 * @brief Enables write access to IWDG_PR and IWDG_RLR registers.
vladvana 0:23d1f73bf130 212 * @param __HANDLE__: IWDG handle
vladvana 0:23d1f73bf130 213 * @retval None
vladvana 0:23d1f73bf130 214 */
vladvana 0:23d1f73bf130 215 #define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)
vladvana 0:23d1f73bf130 216
vladvana 0:23d1f73bf130 217 /**
vladvana 0:23d1f73bf130 218 * @brief Disables write access to IWDG_PR and IWDG_RLR registers.
vladvana 0:23d1f73bf130 219 * @param __HANDLE__: IWDG handle
vladvana 0:23d1f73bf130 220 * @retval None
vladvana 0:23d1f73bf130 221 */
vladvana 0:23d1f73bf130 222 #define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)
vladvana 0:23d1f73bf130 223
vladvana 0:23d1f73bf130 224
vladvana 0:23d1f73bf130 225 #define IS_IWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == IWDG_PRESCALER_4) || \
vladvana 0:23d1f73bf130 226 ((__PRESCALER__) == IWDG_PRESCALER_8) || \
vladvana 0:23d1f73bf130 227 ((__PRESCALER__) == IWDG_PRESCALER_16) || \
vladvana 0:23d1f73bf130 228 ((__PRESCALER__) == IWDG_PRESCALER_32) || \
vladvana 0:23d1f73bf130 229 ((__PRESCALER__) == IWDG_PRESCALER_64) || \
vladvana 0:23d1f73bf130 230 ((__PRESCALER__) == IWDG_PRESCALER_128)|| \
vladvana 0:23d1f73bf130 231 ((__PRESCALER__) == IWDG_PRESCALER_256))
vladvana 0:23d1f73bf130 232
vladvana 0:23d1f73bf130 233
vladvana 0:23d1f73bf130 234 #define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= 0xFFF)
vladvana 0:23d1f73bf130 235
vladvana 0:23d1f73bf130 236
vladvana 0:23d1f73bf130 237 /**
vladvana 0:23d1f73bf130 238 * @}
vladvana 0:23d1f73bf130 239 */
vladvana 0:23d1f73bf130 240
vladvana 0:23d1f73bf130 241
vladvana 0:23d1f73bf130 242
vladvana 0:23d1f73bf130 243 /* Exported functions --------------------------------------------------------*/
vladvana 0:23d1f73bf130 244
vladvana 0:23d1f73bf130 245 /** @addtogroup IWDG_Exported_Functions
vladvana 0:23d1f73bf130 246 * @{
vladvana 0:23d1f73bf130 247 */
vladvana 0:23d1f73bf130 248
vladvana 0:23d1f73bf130 249 /** @addtogroup IWDG_Exported_Functions_Group1
vladvana 0:23d1f73bf130 250 * @{
vladvana 0:23d1f73bf130 251 */
vladvana 0:23d1f73bf130 252 /* Initialization/de-initialization functions ********************************/
vladvana 0:23d1f73bf130 253 HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
vladvana 0:23d1f73bf130 254 void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg);
vladvana 0:23d1f73bf130 255
vladvana 0:23d1f73bf130 256 /**
vladvana 0:23d1f73bf130 257 * @}
vladvana 0:23d1f73bf130 258 */
vladvana 0:23d1f73bf130 259
vladvana 0:23d1f73bf130 260 /** @addtogroup IWDG_Exported_Functions_Group2
vladvana 0:23d1f73bf130 261 * @{
vladvana 0:23d1f73bf130 262 */
vladvana 0:23d1f73bf130 263 /* I/O operation functions ****************************************************/
vladvana 0:23d1f73bf130 264 HAL_StatusTypeDef HAL_IWDG_Start(IWDG_HandleTypeDef *hiwdg);
vladvana 0:23d1f73bf130 265 HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
vladvana 0:23d1f73bf130 266
vladvana 0:23d1f73bf130 267 /**
vladvana 0:23d1f73bf130 268 * @}
vladvana 0:23d1f73bf130 269 */
vladvana 0:23d1f73bf130 270
vladvana 0:23d1f73bf130 271 /** @addtogroup IWDG_Exported_Functions_Group3
vladvana 0:23d1f73bf130 272 * @{
vladvana 0:23d1f73bf130 273 */
vladvana 0:23d1f73bf130 274 /* Peripheral State functions ************************************************/
vladvana 0:23d1f73bf130 275 HAL_IWDG_StateTypeDef HAL_IWDG_GetState(IWDG_HandleTypeDef *hiwdg);
vladvana 0:23d1f73bf130 276
vladvana 0:23d1f73bf130 277 /**
vladvana 0:23d1f73bf130 278 * @}
vladvana 0:23d1f73bf130 279 */
vladvana 0:23d1f73bf130 280
vladvana 0:23d1f73bf130 281 /**
vladvana 0:23d1f73bf130 282 * @}
vladvana 0:23d1f73bf130 283 */
vladvana 0:23d1f73bf130 284
vladvana 0:23d1f73bf130 285 /**
vladvana 0:23d1f73bf130 286 * @}
vladvana 0:23d1f73bf130 287 */
vladvana 0:23d1f73bf130 288
vladvana 0:23d1f73bf130 289 /**
vladvana 0:23d1f73bf130 290 * @}
vladvana 0:23d1f73bf130 291 */
vladvana 0:23d1f73bf130 292
vladvana 0:23d1f73bf130 293 #ifdef __cplusplus
vladvana 0:23d1f73bf130 294 }
vladvana 0:23d1f73bf130 295 #endif
vladvana 0:23d1f73bf130 296
vladvana 0:23d1f73bf130 297 #endif /* __STM32F1xx_HAL_IWDG_H */
vladvana 0:23d1f73bf130 298
vladvana 0:23d1f73bf130 299 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/