Vladimir Vana
pro vyuku PSS v Jecne
TARGET_NUCLEO_F103RB/stm32f1xx_hal_gpio_ex.h@0:23d1f73bf130, 2017-09-24 (annotated)
- Committer:
- vladvana
- Date:
- Sun Sep 24 12:31:52 2017 +0000
- Revision:
- 0:23d1f73bf130
podklady pro cviceni z PSS
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| vladvana | 0:23d1f73bf130 | 1 | /** |
| vladvana | 0:23d1f73bf130 | 2 | ****************************************************************************** |
| vladvana | 0:23d1f73bf130 | 3 | * @file stm32f1xx_hal_gpio_ex.h |
| vladvana | 0:23d1f73bf130 | 4 | * @author MCD Application Team |
| vladvana | 0:23d1f73bf130 | 5 | * @version V1.0.0 |
| vladvana | 0:23d1f73bf130 | 6 | * @date 15-December-2014 |
| vladvana | 0:23d1f73bf130 | 7 | * @brief Header file of GPIO HAL Extension module. |
| vladvana | 0:23d1f73bf130 | 8 | ****************************************************************************** |
| vladvana | 0:23d1f73bf130 | 9 | * @attention |
| vladvana | 0:23d1f73bf130 | 10 | * |
| vladvana | 0:23d1f73bf130 | 11 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
| vladvana | 0:23d1f73bf130 | 12 | * |
| vladvana | 0:23d1f73bf130 | 13 | * Redistribution and use in source and binary forms, with or without modification, |
| vladvana | 0:23d1f73bf130 | 14 | * are permitted provided that the following conditions are met: |
| vladvana | 0:23d1f73bf130 | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
| vladvana | 0:23d1f73bf130 | 16 | * this list of conditions and the following disclaimer. |
| vladvana | 0:23d1f73bf130 | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| vladvana | 0:23d1f73bf130 | 18 | * this list of conditions and the following disclaimer in the documentation |
| vladvana | 0:23d1f73bf130 | 19 | * and/or other materials provided with the distribution. |
| vladvana | 0:23d1f73bf130 | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| vladvana | 0:23d1f73bf130 | 21 | * may be used to endorse or promote products derived from this software |
| vladvana | 0:23d1f73bf130 | 22 | * without specific prior written permission. |
| vladvana | 0:23d1f73bf130 | 23 | * |
| vladvana | 0:23d1f73bf130 | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| vladvana | 0:23d1f73bf130 | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| vladvana | 0:23d1f73bf130 | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| vladvana | 0:23d1f73bf130 | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| vladvana | 0:23d1f73bf130 | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| vladvana | 0:23d1f73bf130 | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| vladvana | 0:23d1f73bf130 | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| vladvana | 0:23d1f73bf130 | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| vladvana | 0:23d1f73bf130 | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| vladvana | 0:23d1f73bf130 | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| vladvana | 0:23d1f73bf130 | 34 | * |
| vladvana | 0:23d1f73bf130 | 35 | ****************************************************************************** |
| vladvana | 0:23d1f73bf130 | 36 | */ |
| vladvana | 0:23d1f73bf130 | 37 | |
| vladvana | 0:23d1f73bf130 | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| vladvana | 0:23d1f73bf130 | 39 | #ifndef __STM32F1xx_HAL_GPIO_EX_H |
| vladvana | 0:23d1f73bf130 | 40 | #define __STM32F1xx_HAL_GPIO_EX_H |
| vladvana | 0:23d1f73bf130 | 41 | |
| vladvana | 0:23d1f73bf130 | 42 | #ifdef __cplusplus |
| vladvana | 0:23d1f73bf130 | 43 | extern "C" { |
| vladvana | 0:23d1f73bf130 | 44 | #endif |
| vladvana | 0:23d1f73bf130 | 45 | |
| vladvana | 0:23d1f73bf130 | 46 | /* Includes ------------------------------------------------------------------*/ |
| vladvana | 0:23d1f73bf130 | 47 | #include "stm32f1xx_hal_def.h" |
| vladvana | 0:23d1f73bf130 | 48 | |
| vladvana | 0:23d1f73bf130 | 49 | /** @addtogroup STM32F1xx_HAL_Driver |
| vladvana | 0:23d1f73bf130 | 50 | * @{ |
| vladvana | 0:23d1f73bf130 | 51 | */ |
| vladvana | 0:23d1f73bf130 | 52 | |
| vladvana | 0:23d1f73bf130 | 53 | /** @defgroup GPIOEx GPIOEx |
| vladvana | 0:23d1f73bf130 | 54 | * @{ |
| vladvana | 0:23d1f73bf130 | 55 | */ |
| vladvana | 0:23d1f73bf130 | 56 | |
| vladvana | 0:23d1f73bf130 | 57 | /* Exported types ------------------------------------------------------------*/ |
| vladvana | 0:23d1f73bf130 | 58 | |
| vladvana | 0:23d1f73bf130 | 59 | /* Exported constants --------------------------------------------------------*/ |
| vladvana | 0:23d1f73bf130 | 60 | |
| vladvana | 0:23d1f73bf130 | 61 | /** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants |
| vladvana | 0:23d1f73bf130 | 62 | * @{ |
| vladvana | 0:23d1f73bf130 | 63 | */ |
| vladvana | 0:23d1f73bf130 | 64 | |
| vladvana | 0:23d1f73bf130 | 65 | /** @defgroup GPIOEx_EVENTOUT EVENTOUT Cortex Configuration |
| vladvana | 0:23d1f73bf130 | 66 | * @brief This section propose definition to use the Cortex EVENTOUT signal. |
| vladvana | 0:23d1f73bf130 | 67 | * @{ |
| vladvana | 0:23d1f73bf130 | 68 | */ |
| vladvana | 0:23d1f73bf130 | 69 | |
| vladvana | 0:23d1f73bf130 | 70 | /** @defgroup GPIOEx_EVENTOUT_PIN EVENTOUT Pin |
| vladvana | 0:23d1f73bf130 | 71 | * @{ |
| vladvana | 0:23d1f73bf130 | 72 | */ |
| vladvana | 0:23d1f73bf130 | 73 | |
| vladvana | 0:23d1f73bf130 | 74 | #define AFIO_EVENTOUT_PIN_0 AFIO_EVCR_PIN_PX0 /*!< EVENTOUT on pin 0 */ |
| vladvana | 0:23d1f73bf130 | 75 | #define AFIO_EVENTOUT_PIN_1 AFIO_EVCR_PIN_PX1 /*!< EVENTOUT on pin 1 */ |
| vladvana | 0:23d1f73bf130 | 76 | #define AFIO_EVENTOUT_PIN_2 AFIO_EVCR_PIN_PX2 /*!< EVENTOUT on pin 2 */ |
| vladvana | 0:23d1f73bf130 | 77 | #define AFIO_EVENTOUT_PIN_3 AFIO_EVCR_PIN_PX3 /*!< EVENTOUT on pin 3 */ |
| vladvana | 0:23d1f73bf130 | 78 | #define AFIO_EVENTOUT_PIN_4 AFIO_EVCR_PIN_PX4 /*!< EVENTOUT on pin 4 */ |
| vladvana | 0:23d1f73bf130 | 79 | #define AFIO_EVENTOUT_PIN_5 AFIO_EVCR_PIN_PX5 /*!< EVENTOUT on pin 5 */ |
| vladvana | 0:23d1f73bf130 | 80 | #define AFIO_EVENTOUT_PIN_6 AFIO_EVCR_PIN_PX6 /*!< EVENTOUT on pin 6 */ |
| vladvana | 0:23d1f73bf130 | 81 | #define AFIO_EVENTOUT_PIN_7 AFIO_EVCR_PIN_PX7 /*!< EVENTOUT on pin 7 */ |
| vladvana | 0:23d1f73bf130 | 82 | #define AFIO_EVENTOUT_PIN_8 AFIO_EVCR_PIN_PX8 /*!< EVENTOUT on pin 8 */ |
| vladvana | 0:23d1f73bf130 | 83 | #define AFIO_EVENTOUT_PIN_9 AFIO_EVCR_PIN_PX9 /*!< EVENTOUT on pin 9 */ |
| vladvana | 0:23d1f73bf130 | 84 | #define AFIO_EVENTOUT_PIN_10 AFIO_EVCR_PIN_PX10 /*!< EVENTOUT on pin 10 */ |
| vladvana | 0:23d1f73bf130 | 85 | #define AFIO_EVENTOUT_PIN_11 AFIO_EVCR_PIN_PX11 /*!< EVENTOUT on pin 11 */ |
| vladvana | 0:23d1f73bf130 | 86 | #define AFIO_EVENTOUT_PIN_12 AFIO_EVCR_PIN_PX12 /*!< EVENTOUT on pin 12 */ |
| vladvana | 0:23d1f73bf130 | 87 | #define AFIO_EVENTOUT_PIN_13 AFIO_EVCR_PIN_PX13 /*!< EVENTOUT on pin 13 */ |
| vladvana | 0:23d1f73bf130 | 88 | #define AFIO_EVENTOUT_PIN_14 AFIO_EVCR_PIN_PX14 /*!< EVENTOUT on pin 14 */ |
| vladvana | 0:23d1f73bf130 | 89 | #define AFIO_EVENTOUT_PIN_15 AFIO_EVCR_PIN_PX15 /*!< EVENTOUT on pin 15 */ |
| vladvana | 0:23d1f73bf130 | 90 | |
| vladvana | 0:23d1f73bf130 | 91 | #define IS_AFIO_EVENTOUT_PIN(__PIN__) (((__PIN__) == AFIO_EVENTOUT_PIN_0) || \ |
| vladvana | 0:23d1f73bf130 | 92 | ((__PIN__) == AFIO_EVENTOUT_PIN_1) || \ |
| vladvana | 0:23d1f73bf130 | 93 | ((__PIN__) == AFIO_EVENTOUT_PIN_2) || \ |
| vladvana | 0:23d1f73bf130 | 94 | ((__PIN__) == AFIO_EVENTOUT_PIN_3) || \ |
| vladvana | 0:23d1f73bf130 | 95 | ((__PIN__) == AFIO_EVENTOUT_PIN_4) || \ |
| vladvana | 0:23d1f73bf130 | 96 | ((__PIN__) == AFIO_EVENTOUT_PIN_5) || \ |
| vladvana | 0:23d1f73bf130 | 97 | ((__PIN__) == AFIO_EVENTOUT_PIN_6) || \ |
| vladvana | 0:23d1f73bf130 | 98 | ((__PIN__) == AFIO_EVENTOUT_PIN_7) || \ |
| vladvana | 0:23d1f73bf130 | 99 | ((__PIN__) == AFIO_EVENTOUT_PIN_8) || \ |
| vladvana | 0:23d1f73bf130 | 100 | ((__PIN__) == AFIO_EVENTOUT_PIN_9) || \ |
| vladvana | 0:23d1f73bf130 | 101 | ((__PIN__) == AFIO_EVENTOUT_PIN_10) || \ |
| vladvana | 0:23d1f73bf130 | 102 | ((__PIN__) == AFIO_EVENTOUT_PIN_11) || \ |
| vladvana | 0:23d1f73bf130 | 103 | ((__PIN__) == AFIO_EVENTOUT_PIN_12) || \ |
| vladvana | 0:23d1f73bf130 | 104 | ((__PIN__) == AFIO_EVENTOUT_PIN_13) || \ |
| vladvana | 0:23d1f73bf130 | 105 | ((__PIN__) == AFIO_EVENTOUT_PIN_14) || \ |
| vladvana | 0:23d1f73bf130 | 106 | ((__PIN__) == AFIO_EVENTOUT_PIN_15)) |
| vladvana | 0:23d1f73bf130 | 107 | /** |
| vladvana | 0:23d1f73bf130 | 108 | * @} |
| vladvana | 0:23d1f73bf130 | 109 | */ |
| vladvana | 0:23d1f73bf130 | 110 | |
| vladvana | 0:23d1f73bf130 | 111 | /** @defgroup GPIOEx_EVENTOUT_PORT EVENTOUT Port |
| vladvana | 0:23d1f73bf130 | 112 | * @{ |
| vladvana | 0:23d1f73bf130 | 113 | */ |
| vladvana | 0:23d1f73bf130 | 114 | |
| vladvana | 0:23d1f73bf130 | 115 | #define AFIO_EVENTOUT_PORT_A AFIO_EVCR_PORT_PA /*!< EVENTOUT on port A */ |
| vladvana | 0:23d1f73bf130 | 116 | #define AFIO_EVENTOUT_PORT_B AFIO_EVCR_PORT_PB /*!< EVENTOUT on port B */ |
| vladvana | 0:23d1f73bf130 | 117 | #define AFIO_EVENTOUT_PORT_C AFIO_EVCR_PORT_PC /*!< EVENTOUT on port C */ |
| vladvana | 0:23d1f73bf130 | 118 | #define AFIO_EVENTOUT_PORT_D AFIO_EVCR_PORT_PD /*!< EVENTOUT on port D */ |
| vladvana | 0:23d1f73bf130 | 119 | #define AFIO_EVENTOUT_PORT_E AFIO_EVCR_PORT_PE /*!< EVENTOUT on port E */ |
| vladvana | 0:23d1f73bf130 | 120 | |
| vladvana | 0:23d1f73bf130 | 121 | #define IS_AFIO_EVENTOUT_PORT(__PORT__) (((__PORT__) == AFIO_EVENTOUT_PORT_A) || \ |
| vladvana | 0:23d1f73bf130 | 122 | ((__PORT__) == AFIO_EVENTOUT_PORT_B) || \ |
| vladvana | 0:23d1f73bf130 | 123 | ((__PORT__) == AFIO_EVENTOUT_PORT_C) || \ |
| vladvana | 0:23d1f73bf130 | 124 | ((__PORT__) == AFIO_EVENTOUT_PORT_D) || \ |
| vladvana | 0:23d1f73bf130 | 125 | ((__PORT__) == AFIO_EVENTOUT_PORT_E)) |
| vladvana | 0:23d1f73bf130 | 126 | /** |
| vladvana | 0:23d1f73bf130 | 127 | * @} |
| vladvana | 0:23d1f73bf130 | 128 | */ |
| vladvana | 0:23d1f73bf130 | 129 | |
| vladvana | 0:23d1f73bf130 | 130 | /** |
| vladvana | 0:23d1f73bf130 | 131 | * @} |
| vladvana | 0:23d1f73bf130 | 132 | */ |
| vladvana | 0:23d1f73bf130 | 133 | |
| vladvana | 0:23d1f73bf130 | 134 | /** @defgroup GPIOEx_AFIO_AF_REMAPPING Alternate Function Remapping |
| vladvana | 0:23d1f73bf130 | 135 | * @brief This section propose definition to remap the alternate function to some other port/pins. |
| vladvana | 0:23d1f73bf130 | 136 | * @{ |
| vladvana | 0:23d1f73bf130 | 137 | */ |
| vladvana | 0:23d1f73bf130 | 138 | |
| vladvana | 0:23d1f73bf130 | 139 | /** |
| vladvana | 0:23d1f73bf130 | 140 | * @brief Enable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI. |
| vladvana | 0:23d1f73bf130 | 141 | * @note ENABLE: Remap (NSS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5) |
| vladvana | 0:23d1f73bf130 | 142 | * @retval None |
| vladvana | 0:23d1f73bf130 | 143 | */ |
| vladvana | 0:23d1f73bf130 | 144 | #define __HAL_AFIO_REMAP_SPI1_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_SPI1_REMAP) |
| vladvana | 0:23d1f73bf130 | 145 | |
| vladvana | 0:23d1f73bf130 | 146 | /** |
| vladvana | 0:23d1f73bf130 | 147 | * @brief Disable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI. |
| vladvana | 0:23d1f73bf130 | 148 | * @note DISABLE: No remap (NSS/PA4, SCK/PA5, MISO/PA6, MOSI/PA7) |
| vladvana | 0:23d1f73bf130 | 149 | * @retval None |
| vladvana | 0:23d1f73bf130 | 150 | */ |
| vladvana | 0:23d1f73bf130 | 151 | #define __HAL_AFIO_REMAP_SPI1_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_SPI1_REMAP) |
| vladvana | 0:23d1f73bf130 | 152 | |
| vladvana | 0:23d1f73bf130 | 153 | /** |
| vladvana | 0:23d1f73bf130 | 154 | * @brief Enable the remapping of I2C1 alternate function SCL and SDA. |
| vladvana | 0:23d1f73bf130 | 155 | * @note ENABLE: Remap (SCL/PB8, SDA/PB9) |
| vladvana | 0:23d1f73bf130 | 156 | * @retval None |
| vladvana | 0:23d1f73bf130 | 157 | */ |
| vladvana | 0:23d1f73bf130 | 158 | #define __HAL_AFIO_REMAP_I2C1_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_I2C1_REMAP) |
| vladvana | 0:23d1f73bf130 | 159 | |
| vladvana | 0:23d1f73bf130 | 160 | /** |
| vladvana | 0:23d1f73bf130 | 161 | * @brief Disable the remapping of I2C1 alternate function SCL and SDA. |
| vladvana | 0:23d1f73bf130 | 162 | * @note DISABLE: No remap (SCL/PB6, SDA/PB7) |
| vladvana | 0:23d1f73bf130 | 163 | * @retval None |
| vladvana | 0:23d1f73bf130 | 164 | */ |
| vladvana | 0:23d1f73bf130 | 165 | #define __HAL_AFIO_REMAP_I2C1_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_I2C1_REMAP) |
| vladvana | 0:23d1f73bf130 | 166 | |
| vladvana | 0:23d1f73bf130 | 167 | /** |
| vladvana | 0:23d1f73bf130 | 168 | * @brief Enable the remapping of USART1 alternate function TX and RX. |
| vladvana | 0:23d1f73bf130 | 169 | * @note ENABLE: Remap (TX/PB6, RX/PB7) |
| vladvana | 0:23d1f73bf130 | 170 | * @retval None |
| vladvana | 0:23d1f73bf130 | 171 | */ |
| vladvana | 0:23d1f73bf130 | 172 | #define __HAL_AFIO_REMAP_USART1_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_USART1_REMAP) |
| vladvana | 0:23d1f73bf130 | 173 | |
| vladvana | 0:23d1f73bf130 | 174 | /** |
| vladvana | 0:23d1f73bf130 | 175 | * @brief Disable the remapping of USART1 alternate function TX and RX. |
| vladvana | 0:23d1f73bf130 | 176 | * @note DISABLE: No remap (TX/PA9, RX/PA10) |
| vladvana | 0:23d1f73bf130 | 177 | * @retval None |
| vladvana | 0:23d1f73bf130 | 178 | */ |
| vladvana | 0:23d1f73bf130 | 179 | #define __HAL_AFIO_REMAP_USART1_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART1_REMAP) |
| vladvana | 0:23d1f73bf130 | 180 | |
| vladvana | 0:23d1f73bf130 | 181 | /** |
| vladvana | 0:23d1f73bf130 | 182 | * @brief Enable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX. |
| vladvana | 0:23d1f73bf130 | 183 | * @note ENABLE: Remap (CTS/PD3, RTS/PD4, TX/PD5, RX/PD6, CK/PD7) |
| vladvana | 0:23d1f73bf130 | 184 | * @retval None |
| vladvana | 0:23d1f73bf130 | 185 | */ |
| vladvana | 0:23d1f73bf130 | 186 | #define __HAL_AFIO_REMAP_USART2_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_USART2_REMAP) |
| vladvana | 0:23d1f73bf130 | 187 | |
| vladvana | 0:23d1f73bf130 | 188 | /** |
| vladvana | 0:23d1f73bf130 | 189 | * @brief Disable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX. |
| vladvana | 0:23d1f73bf130 | 190 | * @note DISABLE: No remap (CTS/PA0, RTS/PA1, TX/PA2, RX/PA3, CK/PA4) |
| vladvana | 0:23d1f73bf130 | 191 | * @retval None |
| vladvana | 0:23d1f73bf130 | 192 | */ |
| vladvana | 0:23d1f73bf130 | 193 | #define __HAL_AFIO_REMAP_USART2_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART2_REMAP) |
| vladvana | 0:23d1f73bf130 | 194 | |
| vladvana | 0:23d1f73bf130 | 195 | /** |
| vladvana | 0:23d1f73bf130 | 196 | * @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX. |
| vladvana | 0:23d1f73bf130 | 197 | * @note ENABLE: Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) |
| vladvana | 0:23d1f73bf130 | 198 | * @retval None |
| vladvana | 0:23d1f73bf130 | 199 | */ |
| vladvana | 0:23d1f73bf130 | 200 | #define __HAL_AFIO_REMAP_USART3_ENABLE() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_USART3_REMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP) |
| vladvana | 0:23d1f73bf130 | 201 | |
| vladvana | 0:23d1f73bf130 | 202 | /** |
| vladvana | 0:23d1f73bf130 | 203 | * @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX. |
| vladvana | 0:23d1f73bf130 | 204 | * @note PARTIAL: Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) |
| vladvana | 0:23d1f73bf130 | 205 | * @retval None |
| vladvana | 0:23d1f73bf130 | 206 | */ |
| vladvana | 0:23d1f73bf130 | 207 | #define __HAL_AFIO_REMAP_USART3_PARTIAL() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_USART3_REMAP, AFIO_MAPR_USART3_REMAP_PARTIALREMAP) |
| vladvana | 0:23d1f73bf130 | 208 | |
| vladvana | 0:23d1f73bf130 | 209 | /** |
| vladvana | 0:23d1f73bf130 | 210 | * @brief Disable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX. |
| vladvana | 0:23d1f73bf130 | 211 | * @note DISABLE: No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) |
| vladvana | 0:23d1f73bf130 | 212 | * @retval None |
| vladvana | 0:23d1f73bf130 | 213 | */ |
| vladvana | 0:23d1f73bf130 | 214 | #define __HAL_AFIO_REMAP_USART3_DISABLE() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_USART3_REMAP, AFIO_MAPR_USART3_REMAP_NOREMAP) |
| vladvana | 0:23d1f73bf130 | 215 | |
| vladvana | 0:23d1f73bf130 | 216 | /** |
| vladvana | 0:23d1f73bf130 | 217 | * @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN) |
| vladvana | 0:23d1f73bf130 | 218 | * @note ENABLE: Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) |
| vladvana | 0:23d1f73bf130 | 219 | * @retval None |
| vladvana | 0:23d1f73bf130 | 220 | */ |
| vladvana | 0:23d1f73bf130 | 221 | #define __HAL_AFIO_REMAP_TIM1_ENABLE() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP) |
| vladvana | 0:23d1f73bf130 | 222 | |
| vladvana | 0:23d1f73bf130 | 223 | /** |
| vladvana | 0:23d1f73bf130 | 224 | * @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN) |
| vladvana | 0:23d1f73bf130 | 225 | * @note PARTIAL: Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) |
| vladvana | 0:23d1f73bf130 | 226 | * @retval None |
| vladvana | 0:23d1f73bf130 | 227 | */ |
| vladvana | 0:23d1f73bf130 | 228 | #define __HAL_AFIO_REMAP_TIM1_PARTIAL() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP, AFIO_MAPR_TIM1_REMAP_PARTIALREMAP) |
| vladvana | 0:23d1f73bf130 | 229 | |
| vladvana | 0:23d1f73bf130 | 230 | /** |
| vladvana | 0:23d1f73bf130 | 231 | * @brief Disable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN) |
| vladvana | 0:23d1f73bf130 | 232 | * @note DISABLE: No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) |
| vladvana | 0:23d1f73bf130 | 233 | * @retval None |
| vladvana | 0:23d1f73bf130 | 234 | */ |
| vladvana | 0:23d1f73bf130 | 235 | #define __HAL_AFIO_REMAP_TIM1_DISABLE() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP, AFIO_MAPR_TIM1_REMAP_NOREMAP) |
| vladvana | 0:23d1f73bf130 | 236 | |
| vladvana | 0:23d1f73bf130 | 237 | /** |
| vladvana | 0:23d1f73bf130 | 238 | * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR) |
| vladvana | 0:23d1f73bf130 | 239 | * @note ENABLE: Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) |
| vladvana | 0:23d1f73bf130 | 240 | * @retval None |
| vladvana | 0:23d1f73bf130 | 241 | */ |
| vladvana | 0:23d1f73bf130 | 242 | #define __HAL_AFIO_REMAP_TIM2_ENABLE() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP, AFIO_MAPR_TIM2_REMAP_FULLREMAP) |
| vladvana | 0:23d1f73bf130 | 243 | |
| vladvana | 0:23d1f73bf130 | 244 | /** |
| vladvana | 0:23d1f73bf130 | 245 | * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR) |
| vladvana | 0:23d1f73bf130 | 246 | * @note PARTIAL_2: Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) |
| vladvana | 0:23d1f73bf130 | 247 | * @retval None |
| vladvana | 0:23d1f73bf130 | 248 | */ |
| vladvana | 0:23d1f73bf130 | 249 | #define __HAL_AFIO_REMAP_TIM2_PARTIAL_2() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP, AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2) |
| vladvana | 0:23d1f73bf130 | 250 | |
| vladvana | 0:23d1f73bf130 | 251 | /** |
| vladvana | 0:23d1f73bf130 | 252 | * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR) |
| vladvana | 0:23d1f73bf130 | 253 | * @note PARTIAL_1: Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) |
| vladvana | 0:23d1f73bf130 | 254 | * @retval None |
| vladvana | 0:23d1f73bf130 | 255 | */ |
| vladvana | 0:23d1f73bf130 | 256 | #define __HAL_AFIO_REMAP_TIM2_PARTIAL_1() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP, AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1) |
| vladvana | 0:23d1f73bf130 | 257 | |
| vladvana | 0:23d1f73bf130 | 258 | /** |
| vladvana | 0:23d1f73bf130 | 259 | * @brief Disable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR) |
| vladvana | 0:23d1f73bf130 | 260 | * @note DISABLE: No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) |
| vladvana | 0:23d1f73bf130 | 261 | * @retval None |
| vladvana | 0:23d1f73bf130 | 262 | */ |
| vladvana | 0:23d1f73bf130 | 263 | #define __HAL_AFIO_REMAP_TIM2_DISABLE() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP, AFIO_MAPR_TIM2_REMAP_NOREMAP) |
| vladvana | 0:23d1f73bf130 | 264 | |
| vladvana | 0:23d1f73bf130 | 265 | /** |
| vladvana | 0:23d1f73bf130 | 266 | * @brief Enable the remapping of TIM3 alternate function channels 1 to 4 |
| vladvana | 0:23d1f73bf130 | 267 | * @note ENABLE: Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) |
| vladvana | 0:23d1f73bf130 | 268 | * @note TIM3_ETR on PE0 is not re-mapped. |
| vladvana | 0:23d1f73bf130 | 269 | * @retval None |
| vladvana | 0:23d1f73bf130 | 270 | */ |
| vladvana | 0:23d1f73bf130 | 271 | #define __HAL_AFIO_REMAP_TIM3_ENABLE() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP, AFIO_MAPR_TIM3_REMAP_FULLREMAP) |
| vladvana | 0:23d1f73bf130 | 272 | |
| vladvana | 0:23d1f73bf130 | 273 | /** |
| vladvana | 0:23d1f73bf130 | 274 | * @brief Enable the remapping of TIM3 alternate function channels 1 to 4 |
| vladvana | 0:23d1f73bf130 | 275 | * @note PARTIAL: Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) |
| vladvana | 0:23d1f73bf130 | 276 | * @note TIM3_ETR on PE0 is not re-mapped. |
| vladvana | 0:23d1f73bf130 | 277 | * @retval None |
| vladvana | 0:23d1f73bf130 | 278 | */ |
| vladvana | 0:23d1f73bf130 | 279 | #define __HAL_AFIO_REMAP_TIM3_PARTIAL() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP, AFIO_MAPR_TIM3_REMAP_PARTIALREMAP) |
| vladvana | 0:23d1f73bf130 | 280 | |
| vladvana | 0:23d1f73bf130 | 281 | /** |
| vladvana | 0:23d1f73bf130 | 282 | * @brief Disable the remapping of TIM3 alternate function channels 1 to 4 |
| vladvana | 0:23d1f73bf130 | 283 | * @note DISABLE: No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) |
| vladvana | 0:23d1f73bf130 | 284 | * @note TIM3_ETR on PE0 is not re-mapped. |
| vladvana | 0:23d1f73bf130 | 285 | * @retval None |
| vladvana | 0:23d1f73bf130 | 286 | */ |
| vladvana | 0:23d1f73bf130 | 287 | #define __HAL_AFIO_REMAP_TIM3_DISABLE() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP, AFIO_MAPR_TIM3_REMAP_NOREMAP) |
| vladvana | 0:23d1f73bf130 | 288 | |
| vladvana | 0:23d1f73bf130 | 289 | /** |
| vladvana | 0:23d1f73bf130 | 290 | * @brief Enable the remapping of TIM4 alternate function channels 1 to 4. |
| vladvana | 0:23d1f73bf130 | 291 | * @note ENABLE: Full remap (TIM4_CH1/PD12, TIM4_CH2/PD13, TIM4_CH3/PD14, TIM4_CH4/PD15) |
| vladvana | 0:23d1f73bf130 | 292 | * @note TIM4_ETR on PE0 is not re-mapped. |
| vladvana | 0:23d1f73bf130 | 293 | * @retval None |
| vladvana | 0:23d1f73bf130 | 294 | */ |
| vladvana | 0:23d1f73bf130 | 295 | #define __HAL_AFIO_REMAP_TIM4_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM4_REMAP) |
| vladvana | 0:23d1f73bf130 | 296 | |
| vladvana | 0:23d1f73bf130 | 297 | /** |
| vladvana | 0:23d1f73bf130 | 298 | * @brief Disable the remapping of TIM4 alternate function channels 1 to 4. |
| vladvana | 0:23d1f73bf130 | 299 | * @note DISABLE: No remap (TIM4_CH1/PB6, TIM4_CH2/PB7, TIM4_CH3/PB8, TIM4_CH4/PB9) |
| vladvana | 0:23d1f73bf130 | 300 | * @note TIM4_ETR on PE0 is not re-mapped. |
| vladvana | 0:23d1f73bf130 | 301 | * @retval None |
| vladvana | 0:23d1f73bf130 | 302 | */ |
| vladvana | 0:23d1f73bf130 | 303 | #define __HAL_AFIO_REMAP_TIM4_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM4_REMAP) |
| vladvana | 0:23d1f73bf130 | 304 | |
| vladvana | 0:23d1f73bf130 | 305 | #if defined(AFIO_MAPR_CAN_REMAP_REMAP1) |
| vladvana | 0:23d1f73bf130 | 306 | |
| vladvana | 0:23d1f73bf130 | 307 | /** |
| vladvana | 0:23d1f73bf130 | 308 | * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface. |
| vladvana | 0:23d1f73bf130 | 309 | * @note CASE 1: CAN_RX mapped to PA11, CAN_TX mapped to PA12 |
| vladvana | 0:23d1f73bf130 | 310 | * @retval None |
| vladvana | 0:23d1f73bf130 | 311 | */ |
| vladvana | 0:23d1f73bf130 | 312 | #define __HAL_AFIO_REMAP_CAN1_1() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_CAN_REMAP, AFIO_MAPR_CAN_REMAP_REMAP1) |
| vladvana | 0:23d1f73bf130 | 313 | |
| vladvana | 0:23d1f73bf130 | 314 | /** |
| vladvana | 0:23d1f73bf130 | 315 | * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface. |
| vladvana | 0:23d1f73bf130 | 316 | * @note CASE 2: CAN_RX mapped to PB8, CAN_TX mapped to PB9 (not available on 36-pin package) |
| vladvana | 0:23d1f73bf130 | 317 | * @retval None |
| vladvana | 0:23d1f73bf130 | 318 | */ |
| vladvana | 0:23d1f73bf130 | 319 | #define __HAL_AFIO_REMAP_CAN1_2() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_CAN_REMAP, AFIO_MAPR_CAN_REMAP_REMAP2) |
| vladvana | 0:23d1f73bf130 | 320 | |
| vladvana | 0:23d1f73bf130 | 321 | /** |
| vladvana | 0:23d1f73bf130 | 322 | * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface. |
| vladvana | 0:23d1f73bf130 | 323 | * @note CASE 3: CAN_RX mapped to PD0, CAN_TX mapped to PD1 |
| vladvana | 0:23d1f73bf130 | 324 | * @retval None |
| vladvana | 0:23d1f73bf130 | 325 | */ |
| vladvana | 0:23d1f73bf130 | 326 | #define __HAL_AFIO_REMAP_CAN1_3() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_CAN_REMAP, AFIO_MAPR_CAN_REMAP_REMAP3) |
| vladvana | 0:23d1f73bf130 | 327 | #endif |
| vladvana | 0:23d1f73bf130 | 328 | |
| vladvana | 0:23d1f73bf130 | 329 | /** |
| vladvana | 0:23d1f73bf130 | 330 | * @brief Enable the remapping of PD0 and PD1. When the HSE oscillator is not used |
| vladvana | 0:23d1f73bf130 | 331 | * (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and |
| vladvana | 0:23d1f73bf130 | 332 | * OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available |
| vladvana | 0:23d1f73bf130 | 333 | * on 100-pin and 144-pin packages, no need for remapping). |
| vladvana | 0:23d1f73bf130 | 334 | * @note ENABLE: PD0 remapped on OSC_IN, PD1 remapped on OSC_OUT. |
| vladvana | 0:23d1f73bf130 | 335 | * @retval None |
| vladvana | 0:23d1f73bf130 | 336 | */ |
| vladvana | 0:23d1f73bf130 | 337 | #define __HAL_AFIO_REMAP_PD01_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_PD01_REMAP) |
| vladvana | 0:23d1f73bf130 | 338 | |
| vladvana | 0:23d1f73bf130 | 339 | /** |
| vladvana | 0:23d1f73bf130 | 340 | * @brief Disable the remapping of PD0 and PD1. When the HSE oscillator is not used |
| vladvana | 0:23d1f73bf130 | 341 | * (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and |
| vladvana | 0:23d1f73bf130 | 342 | * OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available |
| vladvana | 0:23d1f73bf130 | 343 | * on 100-pin and 144-pin packages, no need for remapping). |
| vladvana | 0:23d1f73bf130 | 344 | * @note DISABLE: No remapping of PD0 and PD1 |
| vladvana | 0:23d1f73bf130 | 345 | * @retval None |
| vladvana | 0:23d1f73bf130 | 346 | */ |
| vladvana | 0:23d1f73bf130 | 347 | #define __HAL_AFIO_REMAP_PD01_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_PD01_REMAP) |
| vladvana | 0:23d1f73bf130 | 348 | |
| vladvana | 0:23d1f73bf130 | 349 | #if defined(AFIO_MAPR_TIM5CH4_IREMAP) |
| vladvana | 0:23d1f73bf130 | 350 | /** |
| vladvana | 0:23d1f73bf130 | 351 | * @brief Enable the remapping of TIM5CH4. |
| vladvana | 0:23d1f73bf130 | 352 | * @note ENABLE: LSI internal clock is connected to TIM5_CH4 input for calibration purpose. |
| vladvana | 0:23d1f73bf130 | 353 | * @note This function is available only in high density value line devices. |
| vladvana | 0:23d1f73bf130 | 354 | * @retval None |
| vladvana | 0:23d1f73bf130 | 355 | */ |
| vladvana | 0:23d1f73bf130 | 356 | #define __HAL_AFIO_REMAP_TIM5CH4_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM5CH4_IREMAP) |
| vladvana | 0:23d1f73bf130 | 357 | |
| vladvana | 0:23d1f73bf130 | 358 | /** |
| vladvana | 0:23d1f73bf130 | 359 | * @brief Disable the remapping of TIM5CH4. |
| vladvana | 0:23d1f73bf130 | 360 | * @note DISABLE: TIM5_CH4 is connected to PA3 |
| vladvana | 0:23d1f73bf130 | 361 | * @note This function is available only in high density value line devices. |
| vladvana | 0:23d1f73bf130 | 362 | * @retval None |
| vladvana | 0:23d1f73bf130 | 363 | */ |
| vladvana | 0:23d1f73bf130 | 364 | #define __HAL_AFIO_REMAP_TIM5CH4_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM5CH4_IREMAP) |
| vladvana | 0:23d1f73bf130 | 365 | #endif |
| vladvana | 0:23d1f73bf130 | 366 | |
| vladvana | 0:23d1f73bf130 | 367 | #if defined(AFIO_MAPR_ETH_REMAP) |
| vladvana | 0:23d1f73bf130 | 368 | /** |
| vladvana | 0:23d1f73bf130 | 369 | * @brief Enable the remapping of Ethernet MAC connections with the PHY. |
| vladvana | 0:23d1f73bf130 | 370 | * @note ENABLE: Remap (RX_DV-CRS_DV/PD8, RXD0/PD9, RXD1/PD10, RXD2/PD11, RXD3/PD12) |
| vladvana | 0:23d1f73bf130 | 371 | * @note This bit is available only in connectivity line devices and is reserved otherwise. |
| vladvana | 0:23d1f73bf130 | 372 | * @retval None |
| vladvana | 0:23d1f73bf130 | 373 | */ |
| vladvana | 0:23d1f73bf130 | 374 | #define __HAL_AFIO_REMAP_ETH_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_ETH_REMAP) |
| vladvana | 0:23d1f73bf130 | 375 | |
| vladvana | 0:23d1f73bf130 | 376 | /** |
| vladvana | 0:23d1f73bf130 | 377 | * @brief Disable the remapping of Ethernet MAC connections with the PHY. |
| vladvana | 0:23d1f73bf130 | 378 | * @note DISABLE: No remap (RX_DV-CRS_DV/PA7, RXD0/PC4, RXD1/PC5, RXD2/PB0, RXD3/PB1) |
| vladvana | 0:23d1f73bf130 | 379 | * @note This bit is available only in connectivity line devices and is reserved otherwise. |
| vladvana | 0:23d1f73bf130 | 380 | * @retval None |
| vladvana | 0:23d1f73bf130 | 381 | */ |
| vladvana | 0:23d1f73bf130 | 382 | #define __HAL_AFIO_REMAP_ETH_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ETH_REMAP) |
| vladvana | 0:23d1f73bf130 | 383 | #endif |
| vladvana | 0:23d1f73bf130 | 384 | |
| vladvana | 0:23d1f73bf130 | 385 | #if defined(AFIO_MAPR_CAN2_REMAP) |
| vladvana | 0:23d1f73bf130 | 386 | |
| vladvana | 0:23d1f73bf130 | 387 | /** |
| vladvana | 0:23d1f73bf130 | 388 | * @brief Enable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX. |
| vladvana | 0:23d1f73bf130 | 389 | * @note ENABLE: Remap (CAN2_RX/PB5, CAN2_TX/PB6) |
| vladvana | 0:23d1f73bf130 | 390 | * @note This bit is available only in connectivity line devices and is reserved otherwise. |
| vladvana | 0:23d1f73bf130 | 391 | * @retval None |
| vladvana | 0:23d1f73bf130 | 392 | */ |
| vladvana | 0:23d1f73bf130 | 393 | #define __HAL_AFIO_REMAP_CAN2_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_CAN2_REMAP) |
| vladvana | 0:23d1f73bf130 | 394 | |
| vladvana | 0:23d1f73bf130 | 395 | /** |
| vladvana | 0:23d1f73bf130 | 396 | * @brief Disable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX. |
| vladvana | 0:23d1f73bf130 | 397 | * @note DISABLE: No remap (CAN2_RX/PB12, CAN2_TX/PB13) |
| vladvana | 0:23d1f73bf130 | 398 | * @note This bit is available only in connectivity line devices and is reserved otherwise. |
| vladvana | 0:23d1f73bf130 | 399 | * @retval None |
| vladvana | 0:23d1f73bf130 | 400 | */ |
| vladvana | 0:23d1f73bf130 | 401 | #define __HAL_AFIO_REMAP_CAN2_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_CAN2_REMAP) |
| vladvana | 0:23d1f73bf130 | 402 | #endif |
| vladvana | 0:23d1f73bf130 | 403 | |
| vladvana | 0:23d1f73bf130 | 404 | #if defined(AFIO_MAPR_MII_RMII_SEL) |
| vladvana | 0:23d1f73bf130 | 405 | /** |
| vladvana | 0:23d1f73bf130 | 406 | * @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY. |
| vladvana | 0:23d1f73bf130 | 407 | * @note ETH_RMII: Configure Ethernet MAC for connection with an RMII PHY |
| vladvana | 0:23d1f73bf130 | 408 | * @note This bit is available only in connectivity line devices and is reserved otherwise. |
| vladvana | 0:23d1f73bf130 | 409 | * @retval None |
| vladvana | 0:23d1f73bf130 | 410 | */ |
| vladvana | 0:23d1f73bf130 | 411 | #define __HAL_AFIO_ETH_RMII() SET_BIT(AFIO->MAPR, AFIO_MAPR_MII_RMII_SEL) |
| vladvana | 0:23d1f73bf130 | 412 | |
| vladvana | 0:23d1f73bf130 | 413 | /** |
| vladvana | 0:23d1f73bf130 | 414 | * @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY. |
| vladvana | 0:23d1f73bf130 | 415 | * @note ETH_MII: Configure Ethernet MAC for connection with an MII PHY |
| vladvana | 0:23d1f73bf130 | 416 | * @note This bit is available only in connectivity line devices and is reserved otherwise. |
| vladvana | 0:23d1f73bf130 | 417 | * @retval None |
| vladvana | 0:23d1f73bf130 | 418 | */ |
| vladvana | 0:23d1f73bf130 | 419 | #define __HAL_AFIO_ETH_MII() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_MII_RMII_SEL) |
| vladvana | 0:23d1f73bf130 | 420 | #endif |
| vladvana | 0:23d1f73bf130 | 421 | |
| vladvana | 0:23d1f73bf130 | 422 | /** |
| vladvana | 0:23d1f73bf130 | 423 | * @brief Enable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion). |
| vladvana | 0:23d1f73bf130 | 424 | * @note ENABLE: ADC1 External Event injected conversion is connected to TIM8 Channel4. |
| vladvana | 0:23d1f73bf130 | 425 | * @retval None |
| vladvana | 0:23d1f73bf130 | 426 | */ |
| vladvana | 0:23d1f73bf130 | 427 | #define __HAL_AFIO_REMAP_ADC1_ETRGINJ_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGINJ_REMAP) |
| vladvana | 0:23d1f73bf130 | 428 | |
| vladvana | 0:23d1f73bf130 | 429 | /** |
| vladvana | 0:23d1f73bf130 | 430 | * @brief Disable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion). |
| vladvana | 0:23d1f73bf130 | 431 | * @note DISABLE: ADC1 External trigger injected conversion is connected to EXTI15 |
| vladvana | 0:23d1f73bf130 | 432 | * @retval None |
| vladvana | 0:23d1f73bf130 | 433 | */ |
| vladvana | 0:23d1f73bf130 | 434 | #define __HAL_AFIO_REMAP_ADC1_ETRGINJ_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGINJ_REMAP) |
| vladvana | 0:23d1f73bf130 | 435 | |
| vladvana | 0:23d1f73bf130 | 436 | /** |
| vladvana | 0:23d1f73bf130 | 437 | * @brief Enable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion). |
| vladvana | 0:23d1f73bf130 | 438 | * @note ENABLE: ADC1 External Event regular conversion is connected to TIM8 TRG0. |
| vladvana | 0:23d1f73bf130 | 439 | * @retval None |
| vladvana | 0:23d1f73bf130 | 440 | */ |
| vladvana | 0:23d1f73bf130 | 441 | #define __HAL_AFIO_REMAP_ADC1_ETRGREG_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGREG_REMAP) |
| vladvana | 0:23d1f73bf130 | 442 | |
| vladvana | 0:23d1f73bf130 | 443 | /** |
| vladvana | 0:23d1f73bf130 | 444 | * @brief Disable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion). |
| vladvana | 0:23d1f73bf130 | 445 | * @note DISABLE: ADC1 External trigger regular conversion is connected to EXTI11 |
| vladvana | 0:23d1f73bf130 | 446 | * @retval None |
| vladvana | 0:23d1f73bf130 | 447 | */ |
| vladvana | 0:23d1f73bf130 | 448 | #define __HAL_AFIO_REMAP_ADC1_ETRGREG_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGREG_REMAP) |
| vladvana | 0:23d1f73bf130 | 449 | |
| vladvana | 0:23d1f73bf130 | 450 | #if defined(AFIO_MAPR_ADC2_ETRGINJ_REMAP) |
| vladvana | 0:23d1f73bf130 | 451 | |
| vladvana | 0:23d1f73bf130 | 452 | /** |
| vladvana | 0:23d1f73bf130 | 453 | * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion). |
| vladvana | 0:23d1f73bf130 | 454 | * @note ENABLE: ADC2 External Event injected conversion is connected to TIM8 Channel4. |
| vladvana | 0:23d1f73bf130 | 455 | * @retval None |
| vladvana | 0:23d1f73bf130 | 456 | */ |
| vladvana | 0:23d1f73bf130 | 457 | #define __HAL_AFIO_REMAP_ADC2_ETRGINJ_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGINJ_REMAP) |
| vladvana | 0:23d1f73bf130 | 458 | |
| vladvana | 0:23d1f73bf130 | 459 | /** |
| vladvana | 0:23d1f73bf130 | 460 | * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion). |
| vladvana | 0:23d1f73bf130 | 461 | * @note DISABLE: ADC2 External trigger injected conversion is connected to EXTI15 |
| vladvana | 0:23d1f73bf130 | 462 | * @retval None |
| vladvana | 0:23d1f73bf130 | 463 | */ |
| vladvana | 0:23d1f73bf130 | 464 | #define __HAL_AFIO_REMAP_ADC2_ETRGINJ_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGINJ_REMAP) |
| vladvana | 0:23d1f73bf130 | 465 | #endif |
| vladvana | 0:23d1f73bf130 | 466 | |
| vladvana | 0:23d1f73bf130 | 467 | #if defined (AFIO_MAPR_ADC2_ETRGREG_REMAP) |
| vladvana | 0:23d1f73bf130 | 468 | |
| vladvana | 0:23d1f73bf130 | 469 | /** |
| vladvana | 0:23d1f73bf130 | 470 | * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion). |
| vladvana | 0:23d1f73bf130 | 471 | * @note ENABLE: ADC2 External Event regular conversion is connected to TIM8 TRG0. |
| vladvana | 0:23d1f73bf130 | 472 | * @retval None |
| vladvana | 0:23d1f73bf130 | 473 | */ |
| vladvana | 0:23d1f73bf130 | 474 | #define __HAL_AFIO_REMAP_ADC2_ETRGREG_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGREG_REMAP) |
| vladvana | 0:23d1f73bf130 | 475 | |
| vladvana | 0:23d1f73bf130 | 476 | /** |
| vladvana | 0:23d1f73bf130 | 477 | * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion). |
| vladvana | 0:23d1f73bf130 | 478 | * @note DISABLE: ADC2 External trigger regular conversion is connected to EXTI11 |
| vladvana | 0:23d1f73bf130 | 479 | * @retval None |
| vladvana | 0:23d1f73bf130 | 480 | */ |
| vladvana | 0:23d1f73bf130 | 481 | #define __HAL_AFIO_REMAP_ADC2_ETRGREG_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGREG_REMAP) |
| vladvana | 0:23d1f73bf130 | 482 | #endif |
| vladvana | 0:23d1f73bf130 | 483 | |
| vladvana | 0:23d1f73bf130 | 484 | /** |
| vladvana | 0:23d1f73bf130 | 485 | * @brief Enable the Serial wire JTAG configuration |
| vladvana | 0:23d1f73bf130 | 486 | * @note ENABLE: Full SWJ (JTAG-DP + SW-DP): Reset State |
| vladvana | 0:23d1f73bf130 | 487 | * @retval None |
| vladvana | 0:23d1f73bf130 | 488 | */ |
| vladvana | 0:23d1f73bf130 | 489 | #define __HAL_AFIO_REMAP_SWJ_ENABLE() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_SWJ_CFG, AFIO_MAPR_SWJ_CFG_RESET) |
| vladvana | 0:23d1f73bf130 | 490 | |
| vladvana | 0:23d1f73bf130 | 491 | /** |
| vladvana | 0:23d1f73bf130 | 492 | * @brief Enable the Serial wire JTAG configuration |
| vladvana | 0:23d1f73bf130 | 493 | * @note NONJTRST: Full SWJ (JTAG-DP + SW-DP) but without NJTRST |
| vladvana | 0:23d1f73bf130 | 494 | * @retval None |
| vladvana | 0:23d1f73bf130 | 495 | */ |
| vladvana | 0:23d1f73bf130 | 496 | #define __HAL_AFIO_REMAP_SWJ_NONJTRST() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_SWJ_CFG, AFIO_MAPR_SWJ_CFG_NOJNTRST) |
| vladvana | 0:23d1f73bf130 | 497 | |
| vladvana | 0:23d1f73bf130 | 498 | /** |
| vladvana | 0:23d1f73bf130 | 499 | * @brief Enable the Serial wire JTAG configuration |
| vladvana | 0:23d1f73bf130 | 500 | * @note NOJTAG: JTAG-DP Disabled and SW-DP Enabled |
| vladvana | 0:23d1f73bf130 | 501 | * @retval None |
| vladvana | 0:23d1f73bf130 | 502 | */ |
| vladvana | 0:23d1f73bf130 | 503 | #define __HAL_AFIO_REMAP_SWJ_NOJTAG() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_SWJ_CFG, AFIO_MAPR_SWJ_CFG_JTAGDISABLE) |
| vladvana | 0:23d1f73bf130 | 504 | |
| vladvana | 0:23d1f73bf130 | 505 | /** |
| vladvana | 0:23d1f73bf130 | 506 | * @brief Disable the Serial wire JTAG configuration |
| vladvana | 0:23d1f73bf130 | 507 | * @note DISABLE: JTAG-DP Disabled and SW-DP Disabled |
| vladvana | 0:23d1f73bf130 | 508 | * @retval None |
| vladvana | 0:23d1f73bf130 | 509 | */ |
| vladvana | 0:23d1f73bf130 | 510 | #define __HAL_AFIO_REMAP_SWJ_DISABLE() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_SWJ_CFG, AFIO_MAPR_SWJ_CFG_DISABLE) |
| vladvana | 0:23d1f73bf130 | 511 | |
| vladvana | 0:23d1f73bf130 | 512 | #if defined(AFIO_MAPR_SPI3_REMAP) |
| vladvana | 0:23d1f73bf130 | 513 | |
| vladvana | 0:23d1f73bf130 | 514 | /** |
| vladvana | 0:23d1f73bf130 | 515 | * @brief Enable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD. |
| vladvana | 0:23d1f73bf130 | 516 | * @note ENABLE: Remap (SPI3_NSS-I2S3_WS/PA4, SPI3_SCK-I2S3_CK/PC10, SPI3_MISO/PC11, SPI3_MOSI-I2S3_SD/PC12) |
| vladvana | 0:23d1f73bf130 | 517 | * @note This bit is available only in connectivity line devices and is reserved otherwise. |
| vladvana | 0:23d1f73bf130 | 518 | * @retval None |
| vladvana | 0:23d1f73bf130 | 519 | */ |
| vladvana | 0:23d1f73bf130 | 520 | #define __HAL_AFIO_REMAP_SPI3_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_SPI3_REMAP) |
| vladvana | 0:23d1f73bf130 | 521 | |
| vladvana | 0:23d1f73bf130 | 522 | /** |
| vladvana | 0:23d1f73bf130 | 523 | * @brief Disable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD. |
| vladvana | 0:23d1f73bf130 | 524 | * @note DISABLE: No remap (SPI3_NSS-I2S3_WS/PA15, SPI3_SCK-I2S3_CK/PB3, SPI3_MISO/PB4, SPI3_MOSI-I2S3_SD/PB5). |
| vladvana | 0:23d1f73bf130 | 525 | * @note This bit is available only in connectivity line devices and is reserved otherwise. |
| vladvana | 0:23d1f73bf130 | 526 | * @retval None |
| vladvana | 0:23d1f73bf130 | 527 | */ |
| vladvana | 0:23d1f73bf130 | 528 | #define __HAL_AFIO_REMAP_SPI3_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_SPI3_REMAP) |
| vladvana | 0:23d1f73bf130 | 529 | #endif |
| vladvana | 0:23d1f73bf130 | 530 | |
| vladvana | 0:23d1f73bf130 | 531 | #if defined(AFIO_MAPR_TIM2ITR1_IREMAP) |
| vladvana | 0:23d1f73bf130 | 532 | |
| vladvana | 0:23d1f73bf130 | 533 | /** |
| vladvana | 0:23d1f73bf130 | 534 | * @brief Control of TIM2_ITR1 internal mapping. |
| vladvana | 0:23d1f73bf130 | 535 | * @note TO_USB: Connect USB OTG SOF (Start of Frame) output to TIM2_ITR1 for calibration purposes. |
| vladvana | 0:23d1f73bf130 | 536 | * @note This bit is available only in connectivity line devices and is reserved otherwise. |
| vladvana | 0:23d1f73bf130 | 537 | * @retval None |
| vladvana | 0:23d1f73bf130 | 538 | */ |
| vladvana | 0:23d1f73bf130 | 539 | #define __HAL_AFIO_TIM2ITR1_TO_USB() SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2ITR1_IREMAP) |
| vladvana | 0:23d1f73bf130 | 540 | |
| vladvana | 0:23d1f73bf130 | 541 | /** |
| vladvana | 0:23d1f73bf130 | 542 | * @brief Control of TIM2_ITR1 internal mapping. |
| vladvana | 0:23d1f73bf130 | 543 | * @note TO_ETH: Connect TIM2_ITR1 internally to the Ethernet PTP output for calibration purposes. |
| vladvana | 0:23d1f73bf130 | 544 | * @note This bit is available only in connectivity line devices and is reserved otherwise. |
| vladvana | 0:23d1f73bf130 | 545 | * @retval None |
| vladvana | 0:23d1f73bf130 | 546 | */ |
| vladvana | 0:23d1f73bf130 | 547 | #define __HAL_AFIO_TIM2ITR1_TO_ETH() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM2ITR1_IREMAP) |
| vladvana | 0:23d1f73bf130 | 548 | #endif |
| vladvana | 0:23d1f73bf130 | 549 | |
| vladvana | 0:23d1f73bf130 | 550 | #if defined(AFIO_MAPR_PTP_PPS_REMAP) |
| vladvana | 0:23d1f73bf130 | 551 | |
| vladvana | 0:23d1f73bf130 | 552 | /** |
| vladvana | 0:23d1f73bf130 | 553 | * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion). |
| vladvana | 0:23d1f73bf130 | 554 | * @note ENABLE: PTP_PPS is output on PB5 pin. |
| vladvana | 0:23d1f73bf130 | 555 | * @note This bit is available only in connectivity line devices and is reserved otherwise. |
| vladvana | 0:23d1f73bf130 | 556 | * @retval None |
| vladvana | 0:23d1f73bf130 | 557 | */ |
| vladvana | 0:23d1f73bf130 | 558 | #define __HAL_AFIO_ETH_PTP_PPS_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_PTP_PPS_REMAP) |
| vladvana | 0:23d1f73bf130 | 559 | |
| vladvana | 0:23d1f73bf130 | 560 | /** |
| vladvana | 0:23d1f73bf130 | 561 | * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion). |
| vladvana | 0:23d1f73bf130 | 562 | * @note DISABLE: PTP_PPS not output on PB5 pin. |
| vladvana | 0:23d1f73bf130 | 563 | * @note This bit is available only in connectivity line devices and is reserved otherwise. |
| vladvana | 0:23d1f73bf130 | 564 | * @retval None |
| vladvana | 0:23d1f73bf130 | 565 | */ |
| vladvana | 0:23d1f73bf130 | 566 | #define __HAL_AFIO_ETH_PTP_PPS_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_PTP_PPS_REMAP) |
| vladvana | 0:23d1f73bf130 | 567 | #endif |
| vladvana | 0:23d1f73bf130 | 568 | |
| vladvana | 0:23d1f73bf130 | 569 | #if defined(AFIO_MAPR2_TIM9_REMAP) |
| vladvana | 0:23d1f73bf130 | 570 | |
| vladvana | 0:23d1f73bf130 | 571 | /** |
| vladvana | 0:23d1f73bf130 | 572 | * @brief Enable the remapping of TIM9_CH1 and TIM9_CH2. |
| vladvana | 0:23d1f73bf130 | 573 | * @note ENABLE: Remap (TIM9_CH1 on PE5 and TIM9_CH2 on PE6). |
| vladvana | 0:23d1f73bf130 | 574 | * @retval None |
| vladvana | 0:23d1f73bf130 | 575 | */ |
| vladvana | 0:23d1f73bf130 | 576 | #define __HAL_AFIO_REMAP_TIM9_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP) |
| vladvana | 0:23d1f73bf130 | 577 | |
| vladvana | 0:23d1f73bf130 | 578 | /** |
| vladvana | 0:23d1f73bf130 | 579 | * @brief Disable the remapping of TIM9_CH1 and TIM9_CH2. |
| vladvana | 0:23d1f73bf130 | 580 | * @note DISABLE: No remap (TIM9_CH1 on PA2 and TIM9_CH2 on PA3). |
| vladvana | 0:23d1f73bf130 | 581 | * @retval None |
| vladvana | 0:23d1f73bf130 | 582 | */ |
| vladvana | 0:23d1f73bf130 | 583 | #define __HAL_AFIO_REMAP_TIM9_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP) |
| vladvana | 0:23d1f73bf130 | 584 | #endif |
| vladvana | 0:23d1f73bf130 | 585 | |
| vladvana | 0:23d1f73bf130 | 586 | #if defined(AFIO_MAPR2_TIM10_REMAP) |
| vladvana | 0:23d1f73bf130 | 587 | |
| vladvana | 0:23d1f73bf130 | 588 | /** |
| vladvana | 0:23d1f73bf130 | 589 | * @brief Enable the remapping of TIM10_CH1. |
| vladvana | 0:23d1f73bf130 | 590 | * @note ENABLE: Remap (TIM10_CH1 on PF6). |
| vladvana | 0:23d1f73bf130 | 591 | * @retval None |
| vladvana | 0:23d1f73bf130 | 592 | */ |
| vladvana | 0:23d1f73bf130 | 593 | #define __HAL_AFIO_REMAP_TIM10_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP) |
| vladvana | 0:23d1f73bf130 | 594 | |
| vladvana | 0:23d1f73bf130 | 595 | /** |
| vladvana | 0:23d1f73bf130 | 596 | * @brief Disable the remapping of TIM10_CH1. |
| vladvana | 0:23d1f73bf130 | 597 | * @note DISABLE: No remap (TIM10_CH1 on PB8). |
| vladvana | 0:23d1f73bf130 | 598 | * @retval None |
| vladvana | 0:23d1f73bf130 | 599 | */ |
| vladvana | 0:23d1f73bf130 | 600 | #define __HAL_AFIO_REMAP_TIM10_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP) |
| vladvana | 0:23d1f73bf130 | 601 | #endif |
| vladvana | 0:23d1f73bf130 | 602 | |
| vladvana | 0:23d1f73bf130 | 603 | #if defined(AFIO_MAPR2_TIM11_REMAP) |
| vladvana | 0:23d1f73bf130 | 604 | /** |
| vladvana | 0:23d1f73bf130 | 605 | * @brief Enable the remapping of TIM11_CH1. |
| vladvana | 0:23d1f73bf130 | 606 | * @note ENABLE: Remap (TIM11_CH1 on PF7). |
| vladvana | 0:23d1f73bf130 | 607 | * @retval None |
| vladvana | 0:23d1f73bf130 | 608 | */ |
| vladvana | 0:23d1f73bf130 | 609 | #define __HAL_AFIO_REMAP_TIM11_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP) |
| vladvana | 0:23d1f73bf130 | 610 | |
| vladvana | 0:23d1f73bf130 | 611 | /** |
| vladvana | 0:23d1f73bf130 | 612 | * @brief Disable the remapping of TIM11_CH1. |
| vladvana | 0:23d1f73bf130 | 613 | * @note DISABLE: No remap (TIM11_CH1 on PB9). |
| vladvana | 0:23d1f73bf130 | 614 | * @retval None |
| vladvana | 0:23d1f73bf130 | 615 | */ |
| vladvana | 0:23d1f73bf130 | 616 | #define __HAL_AFIO_REMAP_TIM11_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP) |
| vladvana | 0:23d1f73bf130 | 617 | #endif |
| vladvana | 0:23d1f73bf130 | 618 | |
| vladvana | 0:23d1f73bf130 | 619 | #if defined(AFIO_MAPR2_TIM13_REMAP) |
| vladvana | 0:23d1f73bf130 | 620 | |
| vladvana | 0:23d1f73bf130 | 621 | /** |
| vladvana | 0:23d1f73bf130 | 622 | * @brief Enable the remapping of TIM13_CH1. |
| vladvana | 0:23d1f73bf130 | 623 | * @note ENABLE: Remap STM32F100:(TIM13_CH1 on PF8). Others:(TIM13_CH1 on PB0). |
| vladvana | 0:23d1f73bf130 | 624 | * @retval None |
| vladvana | 0:23d1f73bf130 | 625 | */ |
| vladvana | 0:23d1f73bf130 | 626 | #define __HAL_AFIO_REMAP_TIM13_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP) |
| vladvana | 0:23d1f73bf130 | 627 | |
| vladvana | 0:23d1f73bf130 | 628 | /** |
| vladvana | 0:23d1f73bf130 | 629 | * @brief Disable the remapping of TIM13_CH1. |
| vladvana | 0:23d1f73bf130 | 630 | * @note DISABLE: No remap STM32F100:(TIM13_CH1 on PA6). Others:(TIM13_CH1 on PC8). |
| vladvana | 0:23d1f73bf130 | 631 | * @retval None |
| vladvana | 0:23d1f73bf130 | 632 | */ |
| vladvana | 0:23d1f73bf130 | 633 | #define __HAL_AFIO_REMAP_TIM13_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP) |
| vladvana | 0:23d1f73bf130 | 634 | #endif |
| vladvana | 0:23d1f73bf130 | 635 | |
| vladvana | 0:23d1f73bf130 | 636 | #if defined(AFIO_MAPR2_TIM14_REMAP) |
| vladvana | 0:23d1f73bf130 | 637 | |
| vladvana | 0:23d1f73bf130 | 638 | /** |
| vladvana | 0:23d1f73bf130 | 639 | * @brief Enable the remapping of TIM14_CH1. |
| vladvana | 0:23d1f73bf130 | 640 | * @note ENABLE: Remap STM32F100:(TIM14_CH1 on PB1). Others:(TIM14_CH1 on PF9). |
| vladvana | 0:23d1f73bf130 | 641 | * @retval None |
| vladvana | 0:23d1f73bf130 | 642 | */ |
| vladvana | 0:23d1f73bf130 | 643 | #define __HAL_AFIO_REMAP_TIM14_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP) |
| vladvana | 0:23d1f73bf130 | 644 | |
| vladvana | 0:23d1f73bf130 | 645 | /** |
| vladvana | 0:23d1f73bf130 | 646 | * @brief Disable the remapping of TIM14_CH1. |
| vladvana | 0:23d1f73bf130 | 647 | * @note DISABLE: No remap STM32F100:(TIM14_CH1 on PC9). Others:(TIM14_CH1 on PA7). |
| vladvana | 0:23d1f73bf130 | 648 | * @retval None |
| vladvana | 0:23d1f73bf130 | 649 | */ |
| vladvana | 0:23d1f73bf130 | 650 | #define __HAL_AFIO_REMAP_TIM14_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP) |
| vladvana | 0:23d1f73bf130 | 651 | #endif |
| vladvana | 0:23d1f73bf130 | 652 | |
| vladvana | 0:23d1f73bf130 | 653 | #if defined(AFIO_MAPR2_FSMC_NADV_REMAP) |
| vladvana | 0:23d1f73bf130 | 654 | |
| vladvana | 0:23d1f73bf130 | 655 | /** |
| vladvana | 0:23d1f73bf130 | 656 | * @brief Controls the use of the optional FSMC_NADV signal. |
| vladvana | 0:23d1f73bf130 | 657 | * @note DISCONNECTED: The NADV signal is not connected. The I/O pin can be used by another peripheral. |
| vladvana | 0:23d1f73bf130 | 658 | * @retval None |
| vladvana | 0:23d1f73bf130 | 659 | */ |
| vladvana | 0:23d1f73bf130 | 660 | #define __HAL_AFIO_FSMCNADV_DISCONNECTED() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP) |
| vladvana | 0:23d1f73bf130 | 661 | |
| vladvana | 0:23d1f73bf130 | 662 | /** |
| vladvana | 0:23d1f73bf130 | 663 | * @brief Controls the use of the optional FSMC_NADV signal. |
| vladvana | 0:23d1f73bf130 | 664 | * @note CONNECTED: The NADV signal is connected to the output (default). |
| vladvana | 0:23d1f73bf130 | 665 | * @retval None |
| vladvana | 0:23d1f73bf130 | 666 | */ |
| vladvana | 0:23d1f73bf130 | 667 | #define __HAL_AFIO_FSMCNADV_CONNECTED() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP) |
| vladvana | 0:23d1f73bf130 | 668 | #endif |
| vladvana | 0:23d1f73bf130 | 669 | |
| vladvana | 0:23d1f73bf130 | 670 | #if defined(AFIO_MAPR2_TIM15_REMAP) |
| vladvana | 0:23d1f73bf130 | 671 | |
| vladvana | 0:23d1f73bf130 | 672 | /** |
| vladvana | 0:23d1f73bf130 | 673 | * @brief Enable the remapping of TIM15_CH1 and TIM15_CH2. |
| vladvana | 0:23d1f73bf130 | 674 | * @note ENABLE: Remap (TIM15_CH1 on PB14 and TIM15_CH2 on PB15). |
| vladvana | 0:23d1f73bf130 | 675 | * @retval None |
| vladvana | 0:23d1f73bf130 | 676 | */ |
| vladvana | 0:23d1f73bf130 | 677 | #define __HAL_AFIO_REMAP_TIM15_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP) |
| vladvana | 0:23d1f73bf130 | 678 | |
| vladvana | 0:23d1f73bf130 | 679 | /** |
| vladvana | 0:23d1f73bf130 | 680 | * @brief Disable the remapping of TIM15_CH1 and TIM15_CH2. |
| vladvana | 0:23d1f73bf130 | 681 | * @note DISABLE: No remap (TIM15_CH1 on PA2 and TIM15_CH2 on PA3). |
| vladvana | 0:23d1f73bf130 | 682 | * @retval None |
| vladvana | 0:23d1f73bf130 | 683 | */ |
| vladvana | 0:23d1f73bf130 | 684 | #define __HAL_AFIO_REMAP_TIM15_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP) |
| vladvana | 0:23d1f73bf130 | 685 | #endif |
| vladvana | 0:23d1f73bf130 | 686 | |
| vladvana | 0:23d1f73bf130 | 687 | #if defined(AFIO_MAPR2_TIM16_REMAP) |
| vladvana | 0:23d1f73bf130 | 688 | |
| vladvana | 0:23d1f73bf130 | 689 | /** |
| vladvana | 0:23d1f73bf130 | 690 | * @brief Enable the remapping of TIM16_CH1. |
| vladvana | 0:23d1f73bf130 | 691 | * @note ENABLE: Remap (TIM16_CH1 on PA6). |
| vladvana | 0:23d1f73bf130 | 692 | * @retval None |
| vladvana | 0:23d1f73bf130 | 693 | */ |
| vladvana | 0:23d1f73bf130 | 694 | #define __HAL_AFIO_REMAP_TIM16_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP) |
| vladvana | 0:23d1f73bf130 | 695 | |
| vladvana | 0:23d1f73bf130 | 696 | /** |
| vladvana | 0:23d1f73bf130 | 697 | * @brief Disable the remapping of TIM16_CH1. |
| vladvana | 0:23d1f73bf130 | 698 | * @note DISABLE: No remap (TIM16_CH1 on PB8). |
| vladvana | 0:23d1f73bf130 | 699 | * @retval None |
| vladvana | 0:23d1f73bf130 | 700 | */ |
| vladvana | 0:23d1f73bf130 | 701 | #define __HAL_AFIO_REMAP_TIM16_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP) |
| vladvana | 0:23d1f73bf130 | 702 | #endif |
| vladvana | 0:23d1f73bf130 | 703 | |
| vladvana | 0:23d1f73bf130 | 704 | #if defined(AFIO_MAPR2_TIM17_REMAP) |
| vladvana | 0:23d1f73bf130 | 705 | |
| vladvana | 0:23d1f73bf130 | 706 | /** |
| vladvana | 0:23d1f73bf130 | 707 | * @brief Enable the remapping of TIM17_CH1. |
| vladvana | 0:23d1f73bf130 | 708 | * @note ENABLE: Remap (TIM17_CH1 on PA7). |
| vladvana | 0:23d1f73bf130 | 709 | * @retval None |
| vladvana | 0:23d1f73bf130 | 710 | */ |
| vladvana | 0:23d1f73bf130 | 711 | #define __HAL_AFIO_REMAP_TIM17_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP) |
| vladvana | 0:23d1f73bf130 | 712 | |
| vladvana | 0:23d1f73bf130 | 713 | /** |
| vladvana | 0:23d1f73bf130 | 714 | * @brief Disable the remapping of TIM17_CH1. |
| vladvana | 0:23d1f73bf130 | 715 | * @note DISABLE: No remap (TIM17_CH1 on PB9). |
| vladvana | 0:23d1f73bf130 | 716 | * @retval None |
| vladvana | 0:23d1f73bf130 | 717 | */ |
| vladvana | 0:23d1f73bf130 | 718 | #define __HAL_AFIO_REMAP_TIM17_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP) |
| vladvana | 0:23d1f73bf130 | 719 | #endif |
| vladvana | 0:23d1f73bf130 | 720 | |
| vladvana | 0:23d1f73bf130 | 721 | #if defined(AFIO_MAPR2_CEC_REMAP) |
| vladvana | 0:23d1f73bf130 | 722 | |
| vladvana | 0:23d1f73bf130 | 723 | /** |
| vladvana | 0:23d1f73bf130 | 724 | * @brief Enable the remapping of CEC. |
| vladvana | 0:23d1f73bf130 | 725 | * @note ENABLE: Remap (CEC on PB10). |
| vladvana | 0:23d1f73bf130 | 726 | * @retval None |
| vladvana | 0:23d1f73bf130 | 727 | */ |
| vladvana | 0:23d1f73bf130 | 728 | #define __HAL_AFIO_REMAP_CEC_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP) |
| vladvana | 0:23d1f73bf130 | 729 | |
| vladvana | 0:23d1f73bf130 | 730 | /** |
| vladvana | 0:23d1f73bf130 | 731 | * @brief Disable the remapping of CEC. |
| vladvana | 0:23d1f73bf130 | 732 | * @note DISABLE: No remap (CEC on PB8). |
| vladvana | 0:23d1f73bf130 | 733 | * @retval None |
| vladvana | 0:23d1f73bf130 | 734 | */ |
| vladvana | 0:23d1f73bf130 | 735 | #define __HAL_AFIO_REMAP_CEC_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP) |
| vladvana | 0:23d1f73bf130 | 736 | #endif |
| vladvana | 0:23d1f73bf130 | 737 | |
| vladvana | 0:23d1f73bf130 | 738 | #if defined(AFIO_MAPR2_TIM1_DMA_REMAP) |
| vladvana | 0:23d1f73bf130 | 739 | |
| vladvana | 0:23d1f73bf130 | 740 | /** |
| vladvana | 0:23d1f73bf130 | 741 | * @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels. |
| vladvana | 0:23d1f73bf130 | 742 | * @note ENABLE: Remap (TIM1_CH1 DMA request/DMA1 Channel6, TIM1_CH2 DMA request/DMA1 Channel6) |
| vladvana | 0:23d1f73bf130 | 743 | * @retval None |
| vladvana | 0:23d1f73bf130 | 744 | */ |
| vladvana | 0:23d1f73bf130 | 745 | #define __HAL_AFIO_REMAP_TIM1DMA_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP) |
| vladvana | 0:23d1f73bf130 | 746 | |
| vladvana | 0:23d1f73bf130 | 747 | /** |
| vladvana | 0:23d1f73bf130 | 748 | * @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels. |
| vladvana | 0:23d1f73bf130 | 749 | * @note DISABLE: No remap (TIM1_CH1 DMA request/DMA1 Channel2, TIM1_CH2 DMA request/DMA1 Channel3). |
| vladvana | 0:23d1f73bf130 | 750 | * @retval None |
| vladvana | 0:23d1f73bf130 | 751 | */ |
| vladvana | 0:23d1f73bf130 | 752 | #define __HAL_AFIO_REMAP_TIM1DMA_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP) |
| vladvana | 0:23d1f73bf130 | 753 | #endif |
| vladvana | 0:23d1f73bf130 | 754 | |
| vladvana | 0:23d1f73bf130 | 755 | #if defined(AFIO_MAPR2_TIM67_DAC_DMA_REMAP) |
| vladvana | 0:23d1f73bf130 | 756 | |
| vladvana | 0:23d1f73bf130 | 757 | /** |
| vladvana | 0:23d1f73bf130 | 758 | * @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels. |
| vladvana | 0:23d1f73bf130 | 759 | * @note ENABLE: Remap (TIM6_DAC1 DMA request/DMA1 Channel3, TIM7_DAC2 DMA request/DMA1 Channel4) |
| vladvana | 0:23d1f73bf130 | 760 | * @retval None |
| vladvana | 0:23d1f73bf130 | 761 | */ |
| vladvana | 0:23d1f73bf130 | 762 | #define __HAL_AFIO_REMAP_TIM67DACDMA_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP) |
| vladvana | 0:23d1f73bf130 | 763 | |
| vladvana | 0:23d1f73bf130 | 764 | /** |
| vladvana | 0:23d1f73bf130 | 765 | * @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels. |
| vladvana | 0:23d1f73bf130 | 766 | * @note DISABLE: No remap (TIM6_DAC1 DMA request/DMA2 Channel3, TIM7_DAC2 DMA request/DMA2 Channel4) |
| vladvana | 0:23d1f73bf130 | 767 | * @retval None |
| vladvana | 0:23d1f73bf130 | 768 | */ |
| vladvana | 0:23d1f73bf130 | 769 | #define __HAL_AFIO_REMAP_TIM67DACDMA_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP) |
| vladvana | 0:23d1f73bf130 | 770 | #endif |
| vladvana | 0:23d1f73bf130 | 771 | |
| vladvana | 0:23d1f73bf130 | 772 | #if defined(AFIO_MAPR2_TIM12_REMAP) |
| vladvana | 0:23d1f73bf130 | 773 | |
| vladvana | 0:23d1f73bf130 | 774 | /** |
| vladvana | 0:23d1f73bf130 | 775 | * @brief Enable the remapping of TIM12_CH1 and TIM12_CH2. |
| vladvana | 0:23d1f73bf130 | 776 | * @note ENABLE: Remap (TIM12_CH1 on PB12 and TIM12_CH2 on PB13). |
| vladvana | 0:23d1f73bf130 | 777 | * @note This bit is available only in high density value line devices. |
| vladvana | 0:23d1f73bf130 | 778 | * @retval None |
| vladvana | 0:23d1f73bf130 | 779 | */ |
| vladvana | 0:23d1f73bf130 | 780 | #define __HAL_AFIO_REMAP_TIM12_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP) |
| vladvana | 0:23d1f73bf130 | 781 | |
| vladvana | 0:23d1f73bf130 | 782 | /** |
| vladvana | 0:23d1f73bf130 | 783 | * @brief Disable the remapping of TIM12_CH1 and TIM12_CH2. |
| vladvana | 0:23d1f73bf130 | 784 | * @note DISABLE: No remap (TIM12_CH1 on PC4 and TIM12_CH2 on PC5). |
| vladvana | 0:23d1f73bf130 | 785 | * @note This bit is available only in high density value line devices. |
| vladvana | 0:23d1f73bf130 | 786 | * @retval None |
| vladvana | 0:23d1f73bf130 | 787 | */ |
| vladvana | 0:23d1f73bf130 | 788 | #define __HAL_AFIO_REMAP_TIM12_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP) |
| vladvana | 0:23d1f73bf130 | 789 | #endif |
| vladvana | 0:23d1f73bf130 | 790 | |
| vladvana | 0:23d1f73bf130 | 791 | #if defined(AFIO_MAPR2_MISC_REMAP) |
| vladvana | 0:23d1f73bf130 | 792 | |
| vladvana | 0:23d1f73bf130 | 793 | /** |
| vladvana | 0:23d1f73bf130 | 794 | * @brief Miscellaneous features remapping. |
| vladvana | 0:23d1f73bf130 | 795 | * This bit is set and cleared by software. It controls miscellaneous features. |
| vladvana | 0:23d1f73bf130 | 796 | * The DMA2 channel 5 interrupt position in the vector table. |
| vladvana | 0:23d1f73bf130 | 797 | * The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register). |
| vladvana | 0:23d1f73bf130 | 798 | * @note ENABLE: DMA2 channel 5 interrupt is mapped separately at position 60 and TIM15 TRGO event is |
| vladvana | 0:23d1f73bf130 | 799 | * selected as DAC Trigger 3, TIM15 triggers TIM1/3. |
| vladvana | 0:23d1f73bf130 | 800 | * @note This bit is available only in high density value line devices. |
| vladvana | 0:23d1f73bf130 | 801 | * @retval None |
| vladvana | 0:23d1f73bf130 | 802 | */ |
| vladvana | 0:23d1f73bf130 | 803 | #define __HAL_AFIO_REMAP_MISC_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP) |
| vladvana | 0:23d1f73bf130 | 804 | |
| vladvana | 0:23d1f73bf130 | 805 | /** |
| vladvana | 0:23d1f73bf130 | 806 | * @brief Miscellaneous features remapping. |
| vladvana | 0:23d1f73bf130 | 807 | * This bit is set and cleared by software. It controls miscellaneous features. |
| vladvana | 0:23d1f73bf130 | 808 | * The DMA2 channel 5 interrupt position in the vector table. |
| vladvana | 0:23d1f73bf130 | 809 | * The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register). |
| vladvana | 0:23d1f73bf130 | 810 | * @note DISABLE: DMA2 channel 5 interrupt is mapped with DMA2 channel 4 at position 59, TIM5 TRGO |
| vladvana | 0:23d1f73bf130 | 811 | * event is selected as DAC Trigger 3, TIM5 triggers TIM1/3. |
| vladvana | 0:23d1f73bf130 | 812 | * @note This bit is available only in high density value line devices. |
| vladvana | 0:23d1f73bf130 | 813 | * @retval None |
| vladvana | 0:23d1f73bf130 | 814 | */ |
| vladvana | 0:23d1f73bf130 | 815 | #define __HAL_AFIO_REMAP_MISC_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP) |
| vladvana | 0:23d1f73bf130 | 816 | #endif |
| vladvana | 0:23d1f73bf130 | 817 | |
| vladvana | 0:23d1f73bf130 | 818 | /** |
| vladvana | 0:23d1f73bf130 | 819 | * @} |
| vladvana | 0:23d1f73bf130 | 820 | */ |
| vladvana | 0:23d1f73bf130 | 821 | |
| vladvana | 0:23d1f73bf130 | 822 | /** |
| vladvana | 0:23d1f73bf130 | 823 | * @} |
| vladvana | 0:23d1f73bf130 | 824 | */ |
| vladvana | 0:23d1f73bf130 | 825 | |
| vladvana | 0:23d1f73bf130 | 826 | /** @defgroup GPIOEx_Private_Macros GPIOEx Private Macros |
| vladvana | 0:23d1f73bf130 | 827 | * @{ |
| vladvana | 0:23d1f73bf130 | 828 | */ |
| vladvana | 0:23d1f73bf130 | 829 | #if defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) |
| vladvana | 0:23d1f73bf130 | 830 | #define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ |
| vladvana | 0:23d1f73bf130 | 831 | ((__GPIOx__) == (GPIOB))? 1U :\ |
| vladvana | 0:23d1f73bf130 | 832 | ((__GPIOx__) == (GPIOC))? 2U :3U) |
| vladvana | 0:23d1f73bf130 | 833 | #elif defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) |
| vladvana | 0:23d1f73bf130 | 834 | #define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ |
| vladvana | 0:23d1f73bf130 | 835 | ((__GPIOx__) == (GPIOB))? 1U :\ |
| vladvana | 0:23d1f73bf130 | 836 | ((__GPIOx__) == (GPIOC))? 2U :\ |
| vladvana | 0:23d1f73bf130 | 837 | ((__GPIOx__) == (GPIOD))? 3U :4U) |
| vladvana | 0:23d1f73bf130 | 838 | #elif defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) |
| vladvana | 0:23d1f73bf130 | 839 | #define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ |
| vladvana | 0:23d1f73bf130 | 840 | ((__GPIOx__) == (GPIOB))? 1U :\ |
| vladvana | 0:23d1f73bf130 | 841 | ((__GPIOx__) == (GPIOC))? 2U :\ |
| vladvana | 0:23d1f73bf130 | 842 | ((__GPIOx__) == (GPIOD))? 3U :\ |
| vladvana | 0:23d1f73bf130 | 843 | ((__GPIOx__) == (GPIOE))? 4U :\ |
| vladvana | 0:23d1f73bf130 | 844 | ((__GPIOx__) == (GPIOF))? 5U :6U) |
| vladvana | 0:23d1f73bf130 | 845 | #endif |
| vladvana | 0:23d1f73bf130 | 846 | |
| vladvana | 0:23d1f73bf130 | 847 | /** |
| vladvana | 0:23d1f73bf130 | 848 | * @} |
| vladvana | 0:23d1f73bf130 | 849 | */ |
| vladvana | 0:23d1f73bf130 | 850 | |
| vladvana | 0:23d1f73bf130 | 851 | /* Exported macro ------------------------------------------------------------*/ |
| vladvana | 0:23d1f73bf130 | 852 | /* Exported functions --------------------------------------------------------*/ |
| vladvana | 0:23d1f73bf130 | 853 | |
| vladvana | 0:23d1f73bf130 | 854 | /** @addtogroup GPIOEx_Exported_Functions |
| vladvana | 0:23d1f73bf130 | 855 | * @{ |
| vladvana | 0:23d1f73bf130 | 856 | */ |
| vladvana | 0:23d1f73bf130 | 857 | |
| vladvana | 0:23d1f73bf130 | 858 | /** @addtogroup GPIOEx_Exported_Functions_Group1 |
| vladvana | 0:23d1f73bf130 | 859 | * @{ |
| vladvana | 0:23d1f73bf130 | 860 | */ |
| vladvana | 0:23d1f73bf130 | 861 | void HAL_GPIOEx_ConfigEventout(uint32_t GPIO_PortSource, uint32_t GPIO_PinSource); |
| vladvana | 0:23d1f73bf130 | 862 | void HAL_GPIOEx_EnableEventout(void); |
| vladvana | 0:23d1f73bf130 | 863 | void HAL_GPIOEx_DisableEventout(void); |
| vladvana | 0:23d1f73bf130 | 864 | |
| vladvana | 0:23d1f73bf130 | 865 | /** |
| vladvana | 0:23d1f73bf130 | 866 | * @} |
| vladvana | 0:23d1f73bf130 | 867 | */ |
| vladvana | 0:23d1f73bf130 | 868 | |
| vladvana | 0:23d1f73bf130 | 869 | /** |
| vladvana | 0:23d1f73bf130 | 870 | * @} |
| vladvana | 0:23d1f73bf130 | 871 | */ |
| vladvana | 0:23d1f73bf130 | 872 | |
| vladvana | 0:23d1f73bf130 | 873 | /** |
| vladvana | 0:23d1f73bf130 | 874 | * @} |
| vladvana | 0:23d1f73bf130 | 875 | */ |
| vladvana | 0:23d1f73bf130 | 876 | |
| vladvana | 0:23d1f73bf130 | 877 | /** |
| vladvana | 0:23d1f73bf130 | 878 | * @} |
| vladvana | 0:23d1f73bf130 | 879 | */ |
| vladvana | 0:23d1f73bf130 | 880 | |
| vladvana | 0:23d1f73bf130 | 881 | #ifdef __cplusplus |
| vladvana | 0:23d1f73bf130 | 882 | } |
| vladvana | 0:23d1f73bf130 | 883 | #endif |
| vladvana | 0:23d1f73bf130 | 884 | |
| vladvana | 0:23d1f73bf130 | 885 | #endif /* __STM32F1xx_HAL_GPIO_EX_H */ |
| vladvana | 0:23d1f73bf130 | 886 | |
| vladvana | 0:23d1f73bf130 | 887 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |