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TARGET_NUCLEO_F103RB/stm32f1xx_hal_eth.h@0:23d1f73bf130, 2017-09-24 (annotated)

Committer:: vladvana
Date:: Sun Sep 24 12:31:52 2017 +0000
Revision:: 0:23d1f73bf130

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User	Revision	Line number	New contents of line
vladvana	0:23d1f73bf130	1	/**
vladvana	0:23d1f73bf130	2	******************************************************************************
vladvana	0:23d1f73bf130	3	* @file stm32f1xx_hal_eth.h
vladvana	0:23d1f73bf130	4	* @author MCD Application Team
vladvana	0:23d1f73bf130	5	* @version V1.0.0
vladvana	0:23d1f73bf130	6	* @date 15-December-2014
vladvana	0:23d1f73bf130	7	* @brief Header file of ETH HAL module.
vladvana	0:23d1f73bf130	8	******************************************************************************
vladvana	0:23d1f73bf130	9	* @attention
vladvana	0:23d1f73bf130	10	*
vladvana	0:23d1f73bf130	11	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
vladvana	0:23d1f73bf130	12	*
vladvana	0:23d1f73bf130	13	* Redistribution and use in source and binary forms, with or without modification,
vladvana	0:23d1f73bf130	14	* are permitted provided that the following conditions are met:
vladvana	0:23d1f73bf130	15	* 1. Redistributions of source code must retain the above copyright notice,
vladvana	0:23d1f73bf130	16	* this list of conditions and the following disclaimer.
vladvana	0:23d1f73bf130	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
vladvana	0:23d1f73bf130	18	* this list of conditions and the following disclaimer in the documentation
vladvana	0:23d1f73bf130	19	* and/or other materials provided with the distribution.
vladvana	0:23d1f73bf130	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
vladvana	0:23d1f73bf130	21	* may be used to endorse or promote products derived from this software
vladvana	0:23d1f73bf130	22	* without specific prior written permission.
vladvana	0:23d1f73bf130	23	*
vladvana	0:23d1f73bf130	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
vladvana	0:23d1f73bf130	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
vladvana	0:23d1f73bf130	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
vladvana	0:23d1f73bf130	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
vladvana	0:23d1f73bf130	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
vladvana	0:23d1f73bf130	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
vladvana	0:23d1f73bf130	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
vladvana	0:23d1f73bf130	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
vladvana	0:23d1f73bf130	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
vladvana	0:23d1f73bf130	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
vladvana	0:23d1f73bf130	34	*
vladvana	0:23d1f73bf130	35	******************************************************************************
vladvana	0:23d1f73bf130	36	*/
vladvana	0:23d1f73bf130	37
vladvana	0:23d1f73bf130	38	/* Define to prevent recursive inclusion -------------------------------------*/
vladvana	0:23d1f73bf130	39	#ifndef __STM32F1xx_HAL_ETH_H
vladvana	0:23d1f73bf130	40	#define __STM32F1xx_HAL_ETH_H
vladvana	0:23d1f73bf130	41
vladvana	0:23d1f73bf130	42	#ifdef __cplusplus
vladvana	0:23d1f73bf130	43	extern "C" {
vladvana	0:23d1f73bf130	44	#endif
vladvana	0:23d1f73bf130	45
vladvana	0:23d1f73bf130	46	/* Includes ------------------------------------------------------------------*/
vladvana	0:23d1f73bf130	47	#include "stm32f1xx_hal_def.h"
vladvana	0:23d1f73bf130	48
vladvana	0:23d1f73bf130	49	/** @addtogroup STM32F1xx_HAL_Driver
vladvana	0:23d1f73bf130	50	* @{
vladvana	0:23d1f73bf130	51	*/
vladvana	0:23d1f73bf130	52	#if defined (STM32F107xC)
vladvana	0:23d1f73bf130	53
vladvana	0:23d1f73bf130	54	/** @addtogroup ETH
vladvana	0:23d1f73bf130	55	* @{
vladvana	0:23d1f73bf130	56	*/
vladvana	0:23d1f73bf130	57
vladvana	0:23d1f73bf130	58	/** @addtogroup ETH_Private_Macros
vladvana	0:23d1f73bf130	59	* @{
vladvana	0:23d1f73bf130	60	*/
vladvana	0:23d1f73bf130	61	#define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20)
vladvana	0:23d1f73bf130	62	#define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AUTONEGOTIATION_ENABLE) \|\| \
vladvana	0:23d1f73bf130	63	((CMD) == ETH_AUTONEGOTIATION_DISABLE))
vladvana	0:23d1f73bf130	64	#define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) \|\| \
vladvana	0:23d1f73bf130	65	((SPEED) == ETH_SPEED_100M))
vladvana	0:23d1f73bf130	66	#define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) \|\| \
vladvana	0:23d1f73bf130	67	((MODE) == ETH_MODE_HALFDUPLEX))
vladvana	0:23d1f73bf130	68	#define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) \|\| \
vladvana	0:23d1f73bf130	69	((MODE) == ETH_MODE_HALFDUPLEX))
vladvana	0:23d1f73bf130	70	#define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) \|\| \
vladvana	0:23d1f73bf130	71	((MODE) == ETH_RXINTERRUPT_MODE))
vladvana	0:23d1f73bf130	72	#define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) \|\| \
vladvana	0:23d1f73bf130	73	((MODE) == ETH_RXINTERRUPT_MODE))
vladvana	0:23d1f73bf130	74	#define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) \|\| \
vladvana	0:23d1f73bf130	75	((MODE) == ETH_RXINTERRUPT_MODE))
vladvana	0:23d1f73bf130	76	#define IS_ETH_CHECKSUM_MODE(MODE) (((MODE) == ETH_CHECKSUM_BY_HARDWARE) \|\| \
vladvana	0:23d1f73bf130	77	((MODE) == ETH_CHECKSUM_BY_SOFTWARE))
vladvana	0:23d1f73bf130	78	#define IS_ETH_MEDIA_INTERFACE(MODE) (((MODE) == ETH_MEDIA_INTERFACE_MII) \|\| \
vladvana	0:23d1f73bf130	79	((MODE) == ETH_MEDIA_INTERFACE_RMII))
vladvana	0:23d1f73bf130	80	#define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_WATCHDOG_ENABLE) \|\| \
vladvana	0:23d1f73bf130	81	((CMD) == ETH_WATCHDOG_DISABLE))
vladvana	0:23d1f73bf130	82	#define IS_ETH_JABBER(CMD) (((CMD) == ETH_JABBER_ENABLE) \|\| \
vladvana	0:23d1f73bf130	83	((CMD) == ETH_JABBER_DISABLE))
vladvana	0:23d1f73bf130	84	#define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_INTERFRAMEGAP_96BIT) \|\| \
vladvana	0:23d1f73bf130	85	((GAP) == ETH_INTERFRAMEGAP_88BIT) \|\| \
vladvana	0:23d1f73bf130	86	((GAP) == ETH_INTERFRAMEGAP_80BIT) \|\| \
vladvana	0:23d1f73bf130	87	((GAP) == ETH_INTERFRAMEGAP_72BIT) \|\| \
vladvana	0:23d1f73bf130	88	((GAP) == ETH_INTERFRAMEGAP_64BIT) \|\| \
vladvana	0:23d1f73bf130	89	((GAP) == ETH_INTERFRAMEGAP_56BIT) \|\| \
vladvana	0:23d1f73bf130	90	((GAP) == ETH_INTERFRAMEGAP_48BIT) \|\| \
vladvana	0:23d1f73bf130	91	((GAP) == ETH_INTERFRAMEGAP_40BIT))
vladvana	0:23d1f73bf130	92	#define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CARRIERSENCE_ENABLE) \|\| \
vladvana	0:23d1f73bf130	93	((CMD) == ETH_CARRIERSENCE_DISABLE))
vladvana	0:23d1f73bf130	94	#define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_RECEIVEOWN_ENABLE) \|\| \
vladvana	0:23d1f73bf130	95	((CMD) == ETH_RECEIVEOWN_DISABLE))
vladvana	0:23d1f73bf130	96	#define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LOOPBACKMODE_ENABLE) \|\| \
vladvana	0:23d1f73bf130	97	((CMD) == ETH_LOOPBACKMODE_DISABLE))
vladvana	0:23d1f73bf130	98	#define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_CHECKSUMOFFLAOD_ENABLE) \|\| \
vladvana	0:23d1f73bf130	99	((CMD) == ETH_CHECKSUMOFFLAOD_DISABLE))
vladvana	0:23d1f73bf130	100	#define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RETRYTRANSMISSION_ENABLE) \|\| \
vladvana	0:23d1f73bf130	101	((CMD) == ETH_RETRYTRANSMISSION_DISABLE))
vladvana	0:23d1f73bf130	102	#define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AUTOMATICPADCRCSTRIP_ENABLE) \|\| \
vladvana	0:23d1f73bf130	103	((CMD) == ETH_AUTOMATICPADCRCSTRIP_DISABLE))
vladvana	0:23d1f73bf130	104	#define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BACKOFFLIMIT_10) \|\| \
vladvana	0:23d1f73bf130	105	((LIMIT) == ETH_BACKOFFLIMIT_8) \|\| \
vladvana	0:23d1f73bf130	106	((LIMIT) == ETH_BACKOFFLIMIT_4) \|\| \
vladvana	0:23d1f73bf130	107	((LIMIT) == ETH_BACKOFFLIMIT_1))
vladvana	0:23d1f73bf130	108	#define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DEFFERRALCHECK_ENABLE) \|\| \
vladvana	0:23d1f73bf130	109	((CMD) == ETH_DEFFERRALCHECK_DISABLE))
vladvana	0:23d1f73bf130	110	#define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_RECEIVEALL_ENABLE) \|\| \
vladvana	0:23d1f73bf130	111	((CMD) == ETH_RECEIVEAll_DISABLE))
vladvana	0:23d1f73bf130	112	#define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SOURCEADDRFILTER_NORMAL_ENABLE) \|\| \
vladvana	0:23d1f73bf130	113	((CMD) == ETH_SOURCEADDRFILTER_INVERSE_ENABLE) \|\| \
vladvana	0:23d1f73bf130	114	((CMD) == ETH_SOURCEADDRFILTER_DISABLE))
vladvana	0:23d1f73bf130	115	#define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PASSCONTROLFRAMES_BLOCKALL) \|\| \
vladvana	0:23d1f73bf130	116	((PASS) == ETH_PASSCONTROLFRAMES_FORWARDALL) \|\| \
vladvana	0:23d1f73bf130	117	((PASS) == ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER))
vladvana	0:23d1f73bf130	118	#define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BROADCASTFRAMESRECEPTION_ENABLE) \|\| \
vladvana	0:23d1f73bf130	119	((CMD) == ETH_BROADCASTFRAMESRECEPTION_DISABLE))
vladvana	0:23d1f73bf130	120	#define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DESTINATIONADDRFILTER_NORMAL) \|\| \
vladvana	0:23d1f73bf130	121	((FILTER) == ETH_DESTINATIONADDRFILTER_INVERSE))
vladvana	0:23d1f73bf130	122	#define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PROMISCUOUS_MODE_ENABLE) \|\| \
vladvana	0:23d1f73bf130	123	((CMD) == ETH_PROMISCUOUS_MODE_DISABLE))
vladvana	0:23d1f73bf130	124	#define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE) \|\| \
vladvana	0:23d1f73bf130	125	((FILTER) == ETH_MULTICASTFRAMESFILTER_HASHTABLE) \|\| \
vladvana	0:23d1f73bf130	126	((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECT) \|\| \
vladvana	0:23d1f73bf130	127	((FILTER) == ETH_MULTICASTFRAMESFILTER_NONE))
vladvana	0:23d1f73bf130	128	#define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) \|\| \
vladvana	0:23d1f73bf130	129	((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) \|\| \
vladvana	0:23d1f73bf130	130	((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT))
vladvana	0:23d1f73bf130	131	#define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFF)
vladvana	0:23d1f73bf130	132	#define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) \|\| \
vladvana	0:23d1f73bf130	133	((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE))
vladvana	0:23d1f73bf130	134	#define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) \|\| \
vladvana	0:23d1f73bf130	135	((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS28) \|\| \
vladvana	0:23d1f73bf130	136	((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS144) \|\| \
vladvana	0:23d1f73bf130	137	((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS256))
vladvana	0:23d1f73bf130	138	#define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_ENABLE) \|\| \
vladvana	0:23d1f73bf130	139	((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_DISABLE))
vladvana	0:23d1f73bf130	140	#define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_RECEIVEFLOWCONTROL_ENABLE) \|\| \
vladvana	0:23d1f73bf130	141	((CMD) == ETH_RECEIVEFLOWCONTROL_DISABLE))
vladvana	0:23d1f73bf130	142	#define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TRANSMITFLOWCONTROL_ENABLE) \|\| \
vladvana	0:23d1f73bf130	143	((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE))
vladvana	0:23d1f73bf130	144	#define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) \|\| \
vladvana	0:23d1f73bf130	145	((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT))
vladvana	0:23d1f73bf130	146	#define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFF)
vladvana	0:23d1f73bf130	147	#define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS0) \|\| \
vladvana	0:23d1f73bf130	148	((ADDRESS) == ETH_MAC_ADDRESS1) \|\| \
vladvana	0:23d1f73bf130	149	((ADDRESS) == ETH_MAC_ADDRESS2) \|\| \
vladvana	0:23d1f73bf130	150	((ADDRESS) == ETH_MAC_ADDRESS3))
vladvana	0:23d1f73bf130	151	#define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS1) \|\| \
vladvana	0:23d1f73bf130	152	((ADDRESS) == ETH_MAC_ADDRESS2) \|\| \
vladvana	0:23d1f73bf130	153	((ADDRESS) == ETH_MAC_ADDRESS3))
vladvana	0:23d1f73bf130	154	#define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_ADDRESSFILTER_SA) \|\| \
vladvana	0:23d1f73bf130	155	((FILTER) == ETH_MAC_ADDRESSFILTER_DA))
vladvana	0:23d1f73bf130	156	#define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_ADDRESSMASK_BYTE6) \|\| \
vladvana	0:23d1f73bf130	157	((MASK) == ETH_MAC_ADDRESSMASK_BYTE5) \|\| \
vladvana	0:23d1f73bf130	158	((MASK) == ETH_MAC_ADDRESSMASK_BYTE4) \|\| \
vladvana	0:23d1f73bf130	159	((MASK) == ETH_MAC_ADDRESSMASK_BYTE3) \|\| \
vladvana	0:23d1f73bf130	160	((MASK) == ETH_MAC_ADDRESSMASK_BYTE2) \|\| \
vladvana	0:23d1f73bf130	161	((MASK) == ETH_MAC_ADDRESSMASK_BYTE1))
vladvana	0:23d1f73bf130	162	#define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE) \|\| \
vladvana	0:23d1f73bf130	163	((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE))
vladvana	0:23d1f73bf130	164	#define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_RECEIVESTOREFORWARD_ENABLE) \|\| \
vladvana	0:23d1f73bf130	165	((CMD) == ETH_RECEIVESTOREFORWARD_DISABLE))
vladvana	0:23d1f73bf130	166	#define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FLUSHRECEIVEDFRAME_ENABLE) \|\| \
vladvana	0:23d1f73bf130	167	((CMD) == ETH_FLUSHRECEIVEDFRAME_DISABLE))
vladvana	0:23d1f73bf130	168	#define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TRANSMITSTOREFORWARD_ENABLE) \|\| \
vladvana	0:23d1f73bf130	169	((CMD) == ETH_TRANSMITSTOREFORWARD_DISABLE))
vladvana	0:23d1f73bf130	170	#define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_64BYTES) \|\| \
vladvana	0:23d1f73bf130	171	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_128BYTES) \|\| \
vladvana	0:23d1f73bf130	172	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_192BYTES) \|\| \
vladvana	0:23d1f73bf130	173	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_256BYTES) \|\| \
vladvana	0:23d1f73bf130	174	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_40BYTES) \|\| \
vladvana	0:23d1f73bf130	175	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_32BYTES) \|\| \
vladvana	0:23d1f73bf130	176	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_24BYTES) \|\| \
vladvana	0:23d1f73bf130	177	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_16BYTES))
vladvana	0:23d1f73bf130	178	#define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_FORWARDERRORFRAMES_ENABLE) \|\| \
vladvana	0:23d1f73bf130	179	((CMD) == ETH_FORWARDERRORFRAMES_DISABLE))
vladvana	0:23d1f73bf130	180	#define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE) \|\| \
vladvana	0:23d1f73bf130	181	((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE))
vladvana	0:23d1f73bf130	182	#define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES) \|\| \
vladvana	0:23d1f73bf130	183	((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES) \|\| \
vladvana	0:23d1f73bf130	184	((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES) \|\| \
vladvana	0:23d1f73bf130	185	((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES))
vladvana	0:23d1f73bf130	186	#define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SECONDFRAMEOPERARTE_ENABLE) \|\| \
vladvana	0:23d1f73bf130	187	((CMD) == ETH_SECONDFRAMEOPERARTE_DISABLE))
vladvana	0:23d1f73bf130	188	#define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_ADDRESSALIGNEDBEATS_ENABLE) \|\| \
vladvana	0:23d1f73bf130	189	((CMD) == ETH_ADDRESSALIGNEDBEATS_DISABLE))
vladvana	0:23d1f73bf130	190	#define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FIXEDBURST_ENABLE) \|\| \
vladvana	0:23d1f73bf130	191	((CMD) == ETH_FIXEDBURST_DISABLE))
vladvana	0:23d1f73bf130	192	#define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RXDMABURSTLENGTH_1BEAT) \|\| \
vladvana	0:23d1f73bf130	193	((LENGTH) == ETH_RXDMABURSTLENGTH_2BEAT) \|\| \
vladvana	0:23d1f73bf130	194	((LENGTH) == ETH_RXDMABURSTLENGTH_4BEAT) \|\| \
vladvana	0:23d1f73bf130	195	((LENGTH) == ETH_RXDMABURSTLENGTH_8BEAT) \|\| \
vladvana	0:23d1f73bf130	196	((LENGTH) == ETH_RXDMABURSTLENGTH_16BEAT) \|\| \
vladvana	0:23d1f73bf130	197	((LENGTH) == ETH_RXDMABURSTLENGTH_32BEAT) \|\| \
vladvana	0:23d1f73bf130	198	((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_4BEAT) \|\| \
vladvana	0:23d1f73bf130	199	((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_8BEAT) \|\| \
vladvana	0:23d1f73bf130	200	((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_16BEAT) \|\| \
vladvana	0:23d1f73bf130	201	((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_32BEAT) \|\| \
vladvana	0:23d1f73bf130	202	((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_64BEAT) \|\| \
vladvana	0:23d1f73bf130	203	((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_128BEAT))
vladvana	0:23d1f73bf130	204	#define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TXDMABURSTLENGTH_1BEAT) \|\| \
vladvana	0:23d1f73bf130	205	((LENGTH) == ETH_TXDMABURSTLENGTH_2BEAT) \|\| \
vladvana	0:23d1f73bf130	206	((LENGTH) == ETH_TXDMABURSTLENGTH_4BEAT) \|\| \
vladvana	0:23d1f73bf130	207	((LENGTH) == ETH_TXDMABURSTLENGTH_8BEAT) \|\| \
vladvana	0:23d1f73bf130	208	((LENGTH) == ETH_TXDMABURSTLENGTH_16BEAT) \|\| \
vladvana	0:23d1f73bf130	209	((LENGTH) == ETH_TXDMABURSTLENGTH_32BEAT) \|\| \
vladvana	0:23d1f73bf130	210	((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_4BEAT) \|\| \
vladvana	0:23d1f73bf130	211	((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_8BEAT) \|\| \
vladvana	0:23d1f73bf130	212	((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_16BEAT) \|\| \
vladvana	0:23d1f73bf130	213	((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT) \|\| \
vladvana	0:23d1f73bf130	214	((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) \|\| \
vladvana	0:23d1f73bf130	215	((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT))
vladvana	0:23d1f73bf130	216	#define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1F)
vladvana	0:23d1f73bf130	217	#define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1) \|\| \
vladvana	0:23d1f73bf130	218	((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1) \|\| \
vladvana	0:23d1f73bf130	219	((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1) \|\| \
vladvana	0:23d1f73bf130	220	((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1) \|\| \
vladvana	0:23d1f73bf130	221	((RATIO) == ETH_DMAARBITRATION_RXPRIORTX))
vladvana	0:23d1f73bf130	222
vladvana	0:23d1f73bf130	223	#define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATXDESC_LASTSEGMENTS) \|\| \
vladvana	0:23d1f73bf130	224	((SEGMENT) == ETH_DMATXDESC_FIRSTSEGMENT))
vladvana	0:23d1f73bf130	225	#define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATXDESC_CHECKSUMBYPASS) \|\| \
vladvana	0:23d1f73bf130	226	((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) \|\| \
vladvana	0:23d1f73bf130	227	((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) \|\| \
vladvana	0:23d1f73bf130	228	((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL))
vladvana	0:23d1f73bf130	229	#define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFF)
vladvana	0:23d1f73bf130	230
vladvana	0:23d1f73bf130	231	#define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARXDESC_BUFFER1) \|\| \
vladvana	0:23d1f73bf130	232	((BUFFER) == ETH_DMARXDESC_BUFFER2))
vladvana	0:23d1f73bf130	233
vladvana	0:23d1f73bf130	234	#define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) \|\| \
vladvana	0:23d1f73bf130	235	((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER))
vladvana	0:23d1f73bf130	236
vladvana	0:23d1f73bf130	237	/**
vladvana	0:23d1f73bf130	238	* @}
vladvana	0:23d1f73bf130	239	*/
vladvana	0:23d1f73bf130	240
vladvana	0:23d1f73bf130	241	/** @addtogroup ETH_Private_Constants
vladvana	0:23d1f73bf130	242	* @{
vladvana	0:23d1f73bf130	243	*/
vladvana	0:23d1f73bf130	244	/* Delay to wait when writing to some Ethernet registers */
vladvana	0:23d1f73bf130	245	#define ETH_REG_WRITE_DELAY ((uint32_t)0x00000001)
vladvana	0:23d1f73bf130	246
vladvana	0:23d1f73bf130	247	/* ETHERNET Errors */
vladvana	0:23d1f73bf130	248	#define ETH_SUCCESS ((uint32_t)0)
vladvana	0:23d1f73bf130	249	#define ETH_ERROR ((uint32_t)1)
vladvana	0:23d1f73bf130	250
vladvana	0:23d1f73bf130	251	/* ETHERNET DMA Tx descriptors Collision Count Shift */
vladvana	0:23d1f73bf130	252	#define ETH_DMATXDESC_COLLISION_COUNTSHIFT ((uint32_t)3)
vladvana	0:23d1f73bf130	253
vladvana	0:23d1f73bf130	254	/* ETHERNET DMA Tx descriptors Buffer2 Size Shift */
vladvana	0:23d1f73bf130	255	#define ETH_DMATXDESC_BUFFER2_SIZESHIFT ((uint32_t)16)
vladvana	0:23d1f73bf130	256
vladvana	0:23d1f73bf130	257	/* ETHERNET DMA Rx descriptors Frame Length Shift */
vladvana	0:23d1f73bf130	258	#define ETH_DMARXDESC_FRAME_LENGTHSHIFT ((uint32_t)16)
vladvana	0:23d1f73bf130	259
vladvana	0:23d1f73bf130	260	/* ETHERNET DMA Rx descriptors Buffer2 Size Shift */
vladvana	0:23d1f73bf130	261	#define ETH_DMARXDESC_BUFFER2_SIZESHIFT ((uint32_t)16)
vladvana	0:23d1f73bf130	262
vladvana	0:23d1f73bf130	263	/* ETHERNET DMA Rx descriptors Frame length Shift */
vladvana	0:23d1f73bf130	264	#define ETH_DMARXDESC_FRAMELENGTHSHIFT ((uint32_t)16)
vladvana	0:23d1f73bf130	265
vladvana	0:23d1f73bf130	266	/* ETHERNET MAC address offsets */
vladvana	0:23d1f73bf130	267	#define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x40) /* ETHERNET MAC address high offset */
vladvana	0:23d1f73bf130	268	#define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x44) /* ETHERNET MAC address low offset */
vladvana	0:23d1f73bf130	269
vladvana	0:23d1f73bf130	270	/* ETHERNET MACMIIAR register Mask */
vladvana	0:23d1f73bf130	271	#define ETH_MACMIIAR_CR_MASK ((uint32_t)0xFFFFFFE3)
vladvana	0:23d1f73bf130	272
vladvana	0:23d1f73bf130	273	/* ETHERNET MACCR register Mask */
vladvana	0:23d1f73bf130	274	#define ETH_MACCR_CLEAR_MASK ((uint32_t)0xFF20810F)
vladvana	0:23d1f73bf130	275
vladvana	0:23d1f73bf130	276	/* ETHERNET MACFCR register Mask */
vladvana	0:23d1f73bf130	277	#define ETH_MACFCR_CLEAR_MASK ((uint32_t)0x0000FF41)
vladvana	0:23d1f73bf130	278
vladvana	0:23d1f73bf130	279	/* ETHERNET DMAOMR register Mask */
vladvana	0:23d1f73bf130	280	#define ETH_DMAOMR_CLEAR_MASK ((uint32_t)0xF8DE3F23)
vladvana	0:23d1f73bf130	281
vladvana	0:23d1f73bf130	282	/* ETHERNET Remote Wake-up frame register length */
vladvana	0:23d1f73bf130	283	#define ETH_WAKEUP_REGISTER_LENGTH 8
vladvana	0:23d1f73bf130	284
vladvana	0:23d1f73bf130	285	/* ETHERNET Missed frames counter Shift */
vladvana	0:23d1f73bf130	286	#define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17
vladvana	0:23d1f73bf130	287	/**
vladvana	0:23d1f73bf130	288	* @}
vladvana	0:23d1f73bf130	289	*/
vladvana	0:23d1f73bf130	290
vladvana	0:23d1f73bf130	291	/* Exported types ------------------------------------------------------------*/
vladvana	0:23d1f73bf130	292	/** @defgroup ETH_Exported_Types ETH Exported Types
vladvana	0:23d1f73bf130	293	* @{
vladvana	0:23d1f73bf130	294	*/
vladvana	0:23d1f73bf130	295
vladvana	0:23d1f73bf130	296	/**
vladvana	0:23d1f73bf130	297	* @brief HAL State structures definition
vladvana	0:23d1f73bf130	298	*/
vladvana	0:23d1f73bf130	299	typedef enum
vladvana	0:23d1f73bf130	300	{
vladvana	0:23d1f73bf130	301	HAL_ETH_STATE_RESET = 0x00, /!< Peripheral not yet Initialized or disabled /
vladvana	0:23d1f73bf130	302	HAL_ETH_STATE_READY = 0x01, /!< Peripheral Initialized and ready for use /
vladvana	0:23d1f73bf130	303	HAL_ETH_STATE_BUSY = 0x02, /!< an internal process is ongoing /
vladvana	0:23d1f73bf130	304	HAL_ETH_STATE_BUSY_TX = 0x12, /!< Data Transmission process is ongoing /
vladvana	0:23d1f73bf130	305	HAL_ETH_STATE_BUSY_RX = 0x22, /!< Data Reception process is ongoing /
vladvana	0:23d1f73bf130	306	HAL_ETH_STATE_BUSY_TX_RX = 0x32, /!< Data Transmission and Reception process is ongoing /
vladvana	0:23d1f73bf130	307	HAL_ETH_STATE_BUSY_WR = 0x42, /!< Write process is ongoing /
vladvana	0:23d1f73bf130	308	HAL_ETH_STATE_BUSY_RD = 0x82, /!< Read process is ongoing /
vladvana	0:23d1f73bf130	309	HAL_ETH_STATE_TIMEOUT = 0x03, /!< Timeout state /
vladvana	0:23d1f73bf130	310	HAL_ETH_STATE_ERROR = 0x04 /!< Reception process is ongoing /
vladvana	0:23d1f73bf130	311	}HAL_ETH_StateTypeDef;
vladvana	0:23d1f73bf130	312
vladvana	0:23d1f73bf130	313	/**
vladvana	0:23d1f73bf130	314	* @brief ETH Init Structure definition
vladvana	0:23d1f73bf130	315	*/
vladvana	0:23d1f73bf130	316
vladvana	0:23d1f73bf130	317	typedef struct
vladvana	0:23d1f73bf130	318	{
vladvana	0:23d1f73bf130	319	uint32_t AutoNegotiation; /*!< Selects or not the AutoNegotiation mode for the external PHY
vladvana	0:23d1f73bf130	320	The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps)
vladvana	0:23d1f73bf130	321	and the mode (half/full-duplex).
vladvana	0:23d1f73bf130	322	This parameter can be a value of @ref ETH_AutoNegotiation */
vladvana	0:23d1f73bf130	323
vladvana	0:23d1f73bf130	324	uint32_t Speed; /*!< Sets the Ethernet speed: 10/100 Mbps.
vladvana	0:23d1f73bf130	325	This parameter can be a value of @ref ETH_Speed */
vladvana	0:23d1f73bf130	326
vladvana	0:23d1f73bf130	327	uint32_t DuplexMode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode
vladvana	0:23d1f73bf130	328	This parameter can be a value of @ref ETH_Duplex_Mode */
vladvana	0:23d1f73bf130	329
vladvana	0:23d1f73bf130	330	uint16_t PhyAddress; /*!< Ethernet PHY address.
vladvana	0:23d1f73bf130	331	This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
vladvana	0:23d1f73bf130	332
vladvana	0:23d1f73bf130	333	uint8_t MACAddr; /!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */
vladvana	0:23d1f73bf130	334
vladvana	0:23d1f73bf130	335	uint32_t RxMode; /*!< Selects the Ethernet Rx mode: Polling mode, Interrupt mode.
vladvana	0:23d1f73bf130	336	This parameter can be a value of @ref ETH_Rx_Mode */
vladvana	0:23d1f73bf130	337
vladvana	0:23d1f73bf130	338	uint32_t ChecksumMode; /*!< Selects if the checksum is check by hardware or by software.
vladvana	0:23d1f73bf130	339	This parameter can be a value of @ref ETH_Checksum_Mode */
vladvana	0:23d1f73bf130	340
vladvana	0:23d1f73bf130	341	uint32_t MediaInterface ; /*!< Selects the media-independent interface or the reduced media-independent interface.
vladvana	0:23d1f73bf130	342	This parameter can be a value of @ref ETH_Media_Interface */
vladvana	0:23d1f73bf130	343
vladvana	0:23d1f73bf130	344	} ETH_InitTypeDef;
vladvana	0:23d1f73bf130	345
vladvana	0:23d1f73bf130	346
vladvana	0:23d1f73bf130	347	/**
vladvana	0:23d1f73bf130	348	* @brief ETH MAC Configuration Structure definition
vladvana	0:23d1f73bf130	349	*/
vladvana	0:23d1f73bf130	350
vladvana	0:23d1f73bf130	351	typedef struct
vladvana	0:23d1f73bf130	352	{
vladvana	0:23d1f73bf130	353	uint32_t Watchdog; /*!< Selects or not the Watchdog timer
vladvana	0:23d1f73bf130	354	When enabled, the MAC allows no more then 2048 bytes to be received.
vladvana	0:23d1f73bf130	355	When disabled, the MAC can receive up to 16384 bytes.
vladvana	0:23d1f73bf130	356	This parameter can be a value of @ref ETH_Watchdog */
vladvana	0:23d1f73bf130	357
vladvana	0:23d1f73bf130	358	uint32_t Jabber; /*!< Selects or not Jabber timer
vladvana	0:23d1f73bf130	359	When enabled, the MAC allows no more then 2048 bytes to be sent.
vladvana	0:23d1f73bf130	360	When disabled, the MAC can send up to 16384 bytes.
vladvana	0:23d1f73bf130	361	This parameter can be a value of @ref ETH_Jabber */
vladvana	0:23d1f73bf130	362
vladvana	0:23d1f73bf130	363	uint32_t InterFrameGap; /*!< Selects the minimum IFG between frames during transmission.
vladvana	0:23d1f73bf130	364	This parameter can be a value of @ref ETH_Inter_Frame_Gap */
vladvana	0:23d1f73bf130	365
vladvana	0:23d1f73bf130	366	uint32_t CarrierSense; /*!< Selects or not the Carrier Sense.
vladvana	0:23d1f73bf130	367	This parameter can be a value of @ref ETH_Carrier_Sense */
vladvana	0:23d1f73bf130	368
vladvana	0:23d1f73bf130	369	uint32_t ReceiveOwn; /*!< Selects or not the ReceiveOwn,
vladvana	0:23d1f73bf130	370	ReceiveOwn allows the reception of frames when the TX_EN signal is asserted
vladvana	0:23d1f73bf130	371	in Half-Duplex mode.
vladvana	0:23d1f73bf130	372	This parameter can be a value of @ref ETH_Receive_Own */
vladvana	0:23d1f73bf130	373
vladvana	0:23d1f73bf130	374	uint32_t LoopbackMode; /*!< Selects or not the internal MAC MII Loopback mode.
vladvana	0:23d1f73bf130	375	This parameter can be a value of @ref ETH_Loop_Back_Mode */
vladvana	0:23d1f73bf130	376
vladvana	0:23d1f73bf130	377	uint32_t ChecksumOffload; /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers.
vladvana	0:23d1f73bf130	378	This parameter can be a value of @ref ETH_Checksum_Offload */
vladvana	0:23d1f73bf130	379
vladvana	0:23d1f73bf130	380	uint32_t RetryTransmission; /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL,
vladvana	0:23d1f73bf130	381	when a collision occurs (Half-Duplex mode).
vladvana	0:23d1f73bf130	382	This parameter can be a value of @ref ETH_Retry_Transmission */
vladvana	0:23d1f73bf130	383
vladvana	0:23d1f73bf130	384	uint32_t AutomaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping.
vladvana	0:23d1f73bf130	385	This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */
vladvana	0:23d1f73bf130	386
vladvana	0:23d1f73bf130	387	uint32_t BackOffLimit; /*!< Selects the BackOff limit value.
vladvana	0:23d1f73bf130	388	This parameter can be a value of @ref ETH_Back_Off_Limit */
vladvana	0:23d1f73bf130	389
vladvana	0:23d1f73bf130	390	uint32_t DeferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode).
vladvana	0:23d1f73bf130	391	This parameter can be a value of @ref ETH_Deferral_Check */
vladvana	0:23d1f73bf130	392
vladvana	0:23d1f73bf130	393	uint32_t ReceiveAll; /*!< Selects or not all frames reception by the MAC (No filtering).
vladvana	0:23d1f73bf130	394	This parameter can be a value of @ref ETH_Receive_All */
vladvana	0:23d1f73bf130	395
vladvana	0:23d1f73bf130	396	uint32_t SourceAddrFilter; /*!< Selects the Source Address Filter mode.
vladvana	0:23d1f73bf130	397	This parameter can be a value of @ref ETH_Source_Addr_Filter */
vladvana	0:23d1f73bf130	398
vladvana	0:23d1f73bf130	399	uint32_t PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames)
vladvana	0:23d1f73bf130	400	This parameter can be a value of @ref ETH_Pass_Control_Frames */
vladvana	0:23d1f73bf130	401
vladvana	0:23d1f73bf130	402	uint32_t BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames.
vladvana	0:23d1f73bf130	403	This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */
vladvana	0:23d1f73bf130	404
vladvana	0:23d1f73bf130	405	uint32_t DestinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames.
vladvana	0:23d1f73bf130	406	This parameter can be a value of @ref ETH_Destination_Addr_Filter */
vladvana	0:23d1f73bf130	407
vladvana	0:23d1f73bf130	408	uint32_t PromiscuousMode; /*!< Selects or not the Promiscuous Mode
vladvana	0:23d1f73bf130	409	This parameter can be a value of @ref ETH_Promiscuous_Mode */
vladvana	0:23d1f73bf130	410
vladvana	0:23d1f73bf130	411	uint32_t MulticastFramesFilter; /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter.
vladvana	0:23d1f73bf130	412	This parameter can be a value of @ref ETH_Multicast_Frames_Filter */
vladvana	0:23d1f73bf130	413
vladvana	0:23d1f73bf130	414	uint32_t UnicastFramesFilter; /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter.
vladvana	0:23d1f73bf130	415	This parameter can be a value of @ref ETH_Unicast_Frames_Filter */
vladvana	0:23d1f73bf130	416
vladvana	0:23d1f73bf130	417	uint32_t HashTableHigh; /*!< This field holds the higher 32 bits of Hash table.
vladvana	0:23d1f73bf130	418	This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */
vladvana	0:23d1f73bf130	419
vladvana	0:23d1f73bf130	420	uint32_t HashTableLow; /*!< This field holds the lower 32 bits of Hash table.
vladvana	0:23d1f73bf130	421	This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */
vladvana	0:23d1f73bf130	422
vladvana	0:23d1f73bf130	423	uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control frame.
vladvana	0:23d1f73bf130	424	This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */
vladvana	0:23d1f73bf130	425
vladvana	0:23d1f73bf130	426	uint32_t ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames.
vladvana	0:23d1f73bf130	427	This parameter can be a value of @ref ETH_Zero_Quanta_Pause */
vladvana	0:23d1f73bf130	428
vladvana	0:23d1f73bf130	429	uint32_t PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for
vladvana	0:23d1f73bf130	430	automatic retransmission of PAUSE Frame.
vladvana	0:23d1f73bf130	431	This parameter can be a value of @ref ETH_Pause_Low_Threshold */
vladvana	0:23d1f73bf130	432
vladvana	0:23d1f73bf130	433	uint32_t UnicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0
vladvana	0:23d1f73bf130	434	unicast address and unique multicast address).
vladvana	0:23d1f73bf130	435	This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */
vladvana	0:23d1f73bf130	436
vladvana	0:23d1f73bf130	437	uint32_t ReceiveFlowControl; /*!< Enables or disables the MAC to decode the received Pause frame and
vladvana	0:23d1f73bf130	438	disable its transmitter for a specified time (Pause Time)
vladvana	0:23d1f73bf130	439	This parameter can be a value of @ref ETH_Receive_Flow_Control */
vladvana	0:23d1f73bf130	440
vladvana	0:23d1f73bf130	441	uint32_t TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode)
vladvana	0:23d1f73bf130	442	or the MAC back-pressure operation (Half-Duplex mode)
vladvana	0:23d1f73bf130	443	This parameter can be a value of @ref ETH_Transmit_Flow_Control */
vladvana	0:23d1f73bf130	444
vladvana	0:23d1f73bf130	445	uint32_t VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for
vladvana	0:23d1f73bf130	446	comparison and filtering.
vladvana	0:23d1f73bf130	447	This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */
vladvana	0:23d1f73bf130	448
vladvana	0:23d1f73bf130	449	uint32_t VLANTagIdentifier; /!< Holds the VLAN tag identifier for receive frames /
vladvana	0:23d1f73bf130	450
vladvana	0:23d1f73bf130	451	} ETH_MACInitTypeDef;
vladvana	0:23d1f73bf130	452
vladvana	0:23d1f73bf130	453
vladvana	0:23d1f73bf130	454	/**
vladvana	0:23d1f73bf130	455	* @brief ETH DMA Configuration Structure definition
vladvana	0:23d1f73bf130	456	*/
vladvana	0:23d1f73bf130	457
vladvana	0:23d1f73bf130	458	typedef struct
vladvana	0:23d1f73bf130	459	{
vladvana	0:23d1f73bf130	460	uint32_t DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames.
vladvana	0:23d1f73bf130	461	This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */
vladvana	0:23d1f73bf130	462
vladvana	0:23d1f73bf130	463	uint32_t ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode.
vladvana	0:23d1f73bf130	464	This parameter can be a value of @ref ETH_Receive_Store_Forward */
vladvana	0:23d1f73bf130	465
vladvana	0:23d1f73bf130	466	uint32_t FlushReceivedFrame; /*!< Enables or disables the flushing of received frames.
vladvana	0:23d1f73bf130	467	This parameter can be a value of @ref ETH_Flush_Received_Frame */
vladvana	0:23d1f73bf130	468
vladvana	0:23d1f73bf130	469	uint32_t TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode.
vladvana	0:23d1f73bf130	470	This parameter can be a value of @ref ETH_Transmit_Store_Forward */
vladvana	0:23d1f73bf130	471
vladvana	0:23d1f73bf130	472	uint32_t TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control.
vladvana	0:23d1f73bf130	473	This parameter can be a value of @ref ETH_Transmit_Threshold_Control */
vladvana	0:23d1f73bf130	474
vladvana	0:23d1f73bf130	475	uint32_t ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames.
vladvana	0:23d1f73bf130	476	This parameter can be a value of @ref ETH_Forward_Error_Frames */
vladvana	0:23d1f73bf130	477
vladvana	0:23d1f73bf130	478	uint32_t ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error
vladvana	0:23d1f73bf130	479	and length less than 64 bytes) including pad-bytes and CRC)
vladvana	0:23d1f73bf130	480	This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */
vladvana	0:23d1f73bf130	481
vladvana	0:23d1f73bf130	482	uint32_t ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO.
vladvana	0:23d1f73bf130	483	This parameter can be a value of @ref ETH_Receive_Threshold_Control */
vladvana	0:23d1f73bf130	484
vladvana	0:23d1f73bf130	485	uint32_t SecondFrameOperate; /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second
vladvana	0:23d1f73bf130	486	frame of Transmit data even before obtaining the status for the first frame.
vladvana	0:23d1f73bf130	487	This parameter can be a value of @ref ETH_Second_Frame_Operate */
vladvana	0:23d1f73bf130	488
vladvana	0:23d1f73bf130	489	uint32_t AddressAlignedBeats; /*!< Enables or disables the Address Aligned Beats.
vladvana	0:23d1f73bf130	490	This parameter can be a value of @ref ETH_Address_Aligned_Beats */
vladvana	0:23d1f73bf130	491
vladvana	0:23d1f73bf130	492	uint32_t FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers.
vladvana	0:23d1f73bf130	493	This parameter can be a value of @ref ETH_Fixed_Burst */
vladvana	0:23d1f73bf130	494
vladvana	0:23d1f73bf130	495	uint32_t RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction.
vladvana	0:23d1f73bf130	496	This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */
vladvana	0:23d1f73bf130	497
vladvana	0:23d1f73bf130	498	uint32_t TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction.
vladvana	0:23d1f73bf130	499	This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */
vladvana	0:23d1f73bf130	500
vladvana	0:23d1f73bf130	501	uint32_t DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode)
vladvana	0:23d1f73bf130	502	This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
vladvana	0:23d1f73bf130	503
vladvana	0:23d1f73bf130	504	uint32_t DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration.
vladvana	0:23d1f73bf130	505	This parameter can be a value of @ref ETH_DMA_Arbitration */
vladvana	0:23d1f73bf130	506	} ETH_DMAInitTypeDef;
vladvana	0:23d1f73bf130	507
vladvana	0:23d1f73bf130	508
vladvana	0:23d1f73bf130	509	/**
vladvana	0:23d1f73bf130	510	* @brief ETH DMA Descriptors data structure definition
vladvana	0:23d1f73bf130	511	*/
vladvana	0:23d1f73bf130	512
vladvana	0:23d1f73bf130	513	typedef struct
vladvana	0:23d1f73bf130	514	{
vladvana	0:23d1f73bf130	515	__IO uint32_t Status; /!< Status /
vladvana	0:23d1f73bf130	516
vladvana	0:23d1f73bf130	517	uint32_t ControlBufferSize; /!< Control and Buffer1, Buffer2 lengths /
vladvana	0:23d1f73bf130	518
vladvana	0:23d1f73bf130	519	uint32_t Buffer1Addr; /!< Buffer1 address pointer /
vladvana	0:23d1f73bf130	520
vladvana	0:23d1f73bf130	521	uint32_t Buffer2NextDescAddr; /!< Buffer2 or next descriptor address pointer /
vladvana	0:23d1f73bf130	522
vladvana	0:23d1f73bf130	523	} ETH_DMADescTypeDef;
vladvana	0:23d1f73bf130	524
vladvana	0:23d1f73bf130	525
vladvana	0:23d1f73bf130	526	/**
vladvana	0:23d1f73bf130	527	* @brief Received Frame Informations structure definition
vladvana	0:23d1f73bf130	528	*/
vladvana	0:23d1f73bf130	529	typedef struct
vladvana	0:23d1f73bf130	530	{
vladvana	0:23d1f73bf130	531	ETH_DMADescTypeDef FSRxDesc; /!< First Segment Rx Desc */
vladvana	0:23d1f73bf130	532
vladvana	0:23d1f73bf130	533	ETH_DMADescTypeDef LSRxDesc; /!< Last Segment Rx Desc */
vladvana	0:23d1f73bf130	534
vladvana	0:23d1f73bf130	535	uint32_t SegCount; /!< Segment count /
vladvana	0:23d1f73bf130	536
vladvana	0:23d1f73bf130	537	uint32_t length; /!< Frame length /
vladvana	0:23d1f73bf130	538
vladvana	0:23d1f73bf130	539	uint32_t buffer; /!< Frame buffer /
vladvana	0:23d1f73bf130	540
vladvana	0:23d1f73bf130	541	} ETH_DMARxFrameInfos;
vladvana	0:23d1f73bf130	542
vladvana	0:23d1f73bf130	543
vladvana	0:23d1f73bf130	544	/**
vladvana	0:23d1f73bf130	545	* @brief ETH Handle Structure definition
vladvana	0:23d1f73bf130	546	*/
vladvana	0:23d1f73bf130	547
vladvana	0:23d1f73bf130	548	typedef struct
vladvana	0:23d1f73bf130	549	{
vladvana	0:23d1f73bf130	550	ETH_TypeDef Instance; /!< Register base address */
vladvana	0:23d1f73bf130	551
vladvana	0:23d1f73bf130	552	ETH_InitTypeDef Init; /!< Ethernet Init Configuration /
vladvana	0:23d1f73bf130	553
vladvana	0:23d1f73bf130	554	uint32_t LinkStatus; /!< Ethernet link status /
vladvana	0:23d1f73bf130	555
vladvana	0:23d1f73bf130	556	ETH_DMADescTypeDef RxDesc; /!< Rx descriptor to Get */
vladvana	0:23d1f73bf130	557
vladvana	0:23d1f73bf130	558	ETH_DMADescTypeDef TxDesc; /!< Tx descriptor to Set */
vladvana	0:23d1f73bf130	559
vladvana	0:23d1f73bf130	560	ETH_DMARxFrameInfos RxFrameInfos; /!< last Rx frame infos /
vladvana	0:23d1f73bf130	561
vladvana	0:23d1f73bf130	562	__IO HAL_ETH_StateTypeDef State; /!< ETH communication state /
vladvana	0:23d1f73bf130	563
vladvana	0:23d1f73bf130	564	HAL_LockTypeDef Lock; /!< ETH Lock /
vladvana	0:23d1f73bf130	565
vladvana	0:23d1f73bf130	566	} ETH_HandleTypeDef;
vladvana	0:23d1f73bf130	567
vladvana	0:23d1f73bf130	568	/**
vladvana	0:23d1f73bf130	569	* @}
vladvana	0:23d1f73bf130	570	*/
vladvana	0:23d1f73bf130	571
vladvana	0:23d1f73bf130	572	/* Exported constants --------------------------------------------------------*/
vladvana	0:23d1f73bf130	573	/** @defgroup ETH_Exported_Constants ETH Exported Constants
vladvana	0:23d1f73bf130	574	* @{
vladvana	0:23d1f73bf130	575	*/
vladvana	0:23d1f73bf130	576
vladvana	0:23d1f73bf130	577	/** @defgroup ETH_Buffers_setting ETH Buffers setting
vladvana	0:23d1f73bf130	578	* @{
vladvana	0:23d1f73bf130	579	*/
vladvana	0:23d1f73bf130	580	#define ETH_MAX_PACKET_SIZE ((uint32_t)1524) /!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC /
vladvana	0:23d1f73bf130	581	#define ETH_HEADER ((uint32_t)14) /!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type /
vladvana	0:23d1f73bf130	582	#define ETH_CRC ((uint32_t)4) /!< Ethernet CRC /
vladvana	0:23d1f73bf130	583	#define ETH_EXTRA ((uint32_t)2) /!< Extra bytes in some cases /
vladvana	0:23d1f73bf130	584	#define ETH_VLAN_TAG ((uint32_t)4) /!< optional 802.1q VLAN Tag /
vladvana	0:23d1f73bf130	585	#define ETH_MIN_ETH_PAYLOAD ((uint32_t)46) /!< Minimum Ethernet payload size /
vladvana	0:23d1f73bf130	586	#define ETH_MAX_ETH_PAYLOAD ((uint32_t)1500) /!< Maximum Ethernet payload size /
vladvana	0:23d1f73bf130	587	#define ETH_JUMBO_FRAME_PAYLOAD ((uint32_t)9000) /!< Jumbo frame payload size /
vladvana	0:23d1f73bf130	588
vladvana	0:23d1f73bf130	589	/* Ethernet driver receive buffers are organized in a chained linked-list, when
vladvana	0:23d1f73bf130	590	an ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO
vladvana	0:23d1f73bf130	591	to the driver receive buffers memory.
vladvana	0:23d1f73bf130	592
vladvana	0:23d1f73bf130	593	Depending on the size of the received ethernet packet and the size of
vladvana	0:23d1f73bf130	594	each ethernet driver receive buffer, the received packet can take one or more
vladvana	0:23d1f73bf130	595	ethernet driver receive buffer.
vladvana	0:23d1f73bf130	596
vladvana	0:23d1f73bf130	597	In below are defined the size of one ethernet driver receive buffer ETH_RX_BUF_SIZE
vladvana	0:23d1f73bf130	598	and the total count of the driver receive buffers ETH_RXBUFNB.
vladvana	0:23d1f73bf130	599
vladvana	0:23d1f73bf130	600	The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as
vladvana	0:23d1f73bf130	601	example, they can be reconfigured in the application layer to fit the application
vladvana	0:23d1f73bf130	602	needs */
vladvana	0:23d1f73bf130	603
vladvana	0:23d1f73bf130	604	/* Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet
vladvana	0:23d1f73bf130	605	packet */
vladvana	0:23d1f73bf130	606	#ifndef ETH_RX_BUF_SIZE
vladvana	0:23d1f73bf130	607	#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE
vladvana	0:23d1f73bf130	608	#endif
vladvana	0:23d1f73bf130	609
vladvana	0:23d1f73bf130	610	/* 5 Ethernet driver receive buffers are used (in a chained linked list)*/
vladvana	0:23d1f73bf130	611	#ifndef ETH_RXBUFNB
vladvana	0:23d1f73bf130	612	#define ETH_RXBUFNB ((uint32_t)5 /* 5 Rx buffers of size ETH_RX_BUF_SIZE */
vladvana	0:23d1f73bf130	613	#endif
vladvana	0:23d1f73bf130	614
vladvana	0:23d1f73bf130	615
vladvana	0:23d1f73bf130	616	/* Ethernet driver transmit buffers are organized in a chained linked-list, when
vladvana	0:23d1f73bf130	617	an ethernet packet is transmitted, Tx-DMA will transfer the packet from the
vladvana	0:23d1f73bf130	618	driver transmit buffers memory to the TxFIFO.
vladvana	0:23d1f73bf130	619
vladvana	0:23d1f73bf130	620	Depending on the size of the Ethernet packet to be transmitted and the size of
vladvana	0:23d1f73bf130	621	each ethernet driver transmit buffer, the packet to be transmitted can take
vladvana	0:23d1f73bf130	622	one or more ethernet driver transmit buffer.
vladvana	0:23d1f73bf130	623
vladvana	0:23d1f73bf130	624	In below are defined the size of one ethernet driver transmit buffer ETH_TX_BUF_SIZE
vladvana	0:23d1f73bf130	625	and the total count of the driver transmit buffers ETH_TXBUFNB.
vladvana	0:23d1f73bf130	626
vladvana	0:23d1f73bf130	627	The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as
vladvana	0:23d1f73bf130	628	example, they can be reconfigured in the application layer to fit the application
vladvana	0:23d1f73bf130	629	needs */
vladvana	0:23d1f73bf130	630
vladvana	0:23d1f73bf130	631	/* Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet
vladvana	0:23d1f73bf130	632	packet */
vladvana	0:23d1f73bf130	633	#ifndef ETH_TX_BUF_SIZE
vladvana	0:23d1f73bf130	634	#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE
vladvana	0:23d1f73bf130	635	#endif
vladvana	0:23d1f73bf130	636
vladvana	0:23d1f73bf130	637	/* 5 ethernet driver transmit buffers are used (in a chained linked list)*/
vladvana	0:23d1f73bf130	638	#ifndef ETH_TXBUFNB
vladvana	0:23d1f73bf130	639	#define ETH_TXBUFNB ((uint32_t)5 /* 5 Tx buffers of size ETH_TX_BUF_SIZE */
vladvana	0:23d1f73bf130	640	#endif
vladvana	0:23d1f73bf130	641
vladvana	0:23d1f73bf130	642	/**
vladvana	0:23d1f73bf130	643	* @}
vladvana	0:23d1f73bf130	644	*/
vladvana	0:23d1f73bf130	645
vladvana	0:23d1f73bf130	646	/** @defgroup ETH_DMA_TX_Descriptor ETH DMA TX Descriptor
vladvana	0:23d1f73bf130	647	* @{
vladvana	0:23d1f73bf130	648	*/
vladvana	0:23d1f73bf130	649
vladvana	0:23d1f73bf130	650	/*
vladvana	0:23d1f73bf130	651	DMA Tx Desciptor
vladvana	0:23d1f73bf130	652	-----------------------------------------------------------------------------------------------
vladvana	0:23d1f73bf130	653	TDES0 \| OWN(31) \| CTRL[30:26] \| Reserved[25:24] \| CTRL[23:20] \| Reserved[19:17] \| Status[16:0] \|
vladvana	0:23d1f73bf130	654	-----------------------------------------------------------------------------------------------
vladvana	0:23d1f73bf130	655	TDES1 \| Reserved[31:29] \| Buffer2 ByteCount[28:16] \| Reserved[15:13] \| Buffer1 ByteCount[12:0] \|
vladvana	0:23d1f73bf130	656	-----------------------------------------------------------------------------------------------
vladvana	0:23d1f73bf130	657	TDES2 \| Buffer1 Address [31:0] \|
vladvana	0:23d1f73bf130	658	-----------------------------------------------------------------------------------------------
vladvana	0:23d1f73bf130	659	TDES3 \| Buffer2 Address [31:0] / Next Descriptor Address [31:0] \|
vladvana	0:23d1f73bf130	660	-----------------------------------------------------------------------------------------------
vladvana	0:23d1f73bf130	661	*/
vladvana	0:23d1f73bf130	662
vladvana	0:23d1f73bf130	663	/**
vladvana	0:23d1f73bf130	664	* @brief Bit definition of TDES0 register: DMA Tx descriptor status register
vladvana	0:23d1f73bf130	665	*/
vladvana	0:23d1f73bf130	666	#define ETH_DMATXDESC_OWN ((uint32_t)0x80000000) /!< OWN bit: descriptor is owned by DMA engine /
vladvana	0:23d1f73bf130	667	#define ETH_DMATXDESC_IC ((uint32_t)0x40000000) /!< Interrupt on Completion /
vladvana	0:23d1f73bf130	668	#define ETH_DMATXDESC_LS ((uint32_t)0x20000000) /!< Last Segment /
vladvana	0:23d1f73bf130	669	#define ETH_DMATXDESC_FS ((uint32_t)0x10000000) /!< First Segment /
vladvana	0:23d1f73bf130	670	#define ETH_DMATXDESC_DC ((uint32_t)0x08000000) /!< Disable CRC /
vladvana	0:23d1f73bf130	671	#define ETH_DMATXDESC_DP ((uint32_t)0x04000000) /!< Disable Padding /
vladvana	0:23d1f73bf130	672	#define ETH_DMATXDESC_TTSE ((uint32_t)0x02000000) /!< Transmit Time Stamp Enable /
vladvana	0:23d1f73bf130	673	#define ETH_DMATXDESC_CIC ((uint32_t)0x00C00000) /!< Checksum Insertion Control: 4 cases /
vladvana	0:23d1f73bf130	674	#define ETH_DMATXDESC_CIC_BYPASS ((uint32_t)0x00000000) /!< Do Nothing: Checksum Engine is bypassed /
vladvana	0:23d1f73bf130	675	#define ETH_DMATXDESC_CIC_IPV4HEADER ((uint32_t)0x00400000) /!< IPV4 header Checksum Insertion /
vladvana	0:23d1f73bf130	676	#define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT ((uint32_t)0x00800000) /!< TCP/UDP/ICMP Checksum Insertion calculated over segment only /
vladvana	0:23d1f73bf130	677	#define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL ((uint32_t)0x00C00000) /!< TCP/UDP/ICMP Checksum Insertion fully calculated /
vladvana	0:23d1f73bf130	678	#define ETH_DMATXDESC_TER ((uint32_t)0x00200000) /!< Transmit End of Ring /
vladvana	0:23d1f73bf130	679	#define ETH_DMATXDESC_TCH ((uint32_t)0x00100000) /!< Second Address Chained /
vladvana	0:23d1f73bf130	680	#define ETH_DMATXDESC_TTSS ((uint32_t)0x00020000) /!< Tx Time Stamp Status /
vladvana	0:23d1f73bf130	681	#define ETH_DMATXDESC_IHE ((uint32_t)0x00010000) /!< IP Header Error /
vladvana	0:23d1f73bf130	682	#define ETH_DMATXDESC_ES ((uint32_t)0x00008000) /!< Error summary: OR of the following bits: UE \|\| ED \|\| EC \|\| LCO \|\| NC \|\| LCA \|\| FF \|\| JT /
vladvana	0:23d1f73bf130	683	#define ETH_DMATXDESC_JT ((uint32_t)0x00004000) /!< Jabber Timeout /
vladvana	0:23d1f73bf130	684	#define ETH_DMATXDESC_FF ((uint32_t)0x00002000) /!< Frame Flushed: DMA/MTL flushed the frame due to SW flush /
vladvana	0:23d1f73bf130	685	#define ETH_DMATXDESC_PCE ((uint32_t)0x00001000) /!< Payload Checksum Error /
vladvana	0:23d1f73bf130	686	#define ETH_DMATXDESC_LCA ((uint32_t)0x00000800) /!< Loss of Carrier: carrier lost during transmission /
vladvana	0:23d1f73bf130	687	#define ETH_DMATXDESC_NC ((uint32_t)0x00000400) /!< No Carrier: no carrier signal from the transceiver /
vladvana	0:23d1f73bf130	688	#define ETH_DMATXDESC_LCO ((uint32_t)0x00000200) /!< Late Collision: transmission aborted due to collision /
vladvana	0:23d1f73bf130	689	#define ETH_DMATXDESC_EC ((uint32_t)0x00000100) /!< Excessive Collision: transmission aborted after 16 collisions /
vladvana	0:23d1f73bf130	690	#define ETH_DMATXDESC_VF ((uint32_t)0x00000080) /!< VLAN Frame /
vladvana	0:23d1f73bf130	691	#define ETH_DMATXDESC_CC ((uint32_t)0x00000078) /!< Collision Count /
vladvana	0:23d1f73bf130	692	#define ETH_DMATXDESC_ED ((uint32_t)0x00000004) /!< Excessive Deferral /
vladvana	0:23d1f73bf130	693	#define ETH_DMATXDESC_UF ((uint32_t)0x00000002) /!< Underflow Error: late data arrival from the memory /
vladvana	0:23d1f73bf130	694	#define ETH_DMATXDESC_DB ((uint32_t)0x00000001) /!< Deferred Bit /
vladvana	0:23d1f73bf130	695
vladvana	0:23d1f73bf130	696	/**
vladvana	0:23d1f73bf130	697	* @brief Bit definition of TDES1 register
vladvana	0:23d1f73bf130	698	*/
vladvana	0:23d1f73bf130	699	#define ETH_DMATXDESC_TBS2 ((uint32_t)0x1FFF0000) /!< Transmit Buffer2 Size /
vladvana	0:23d1f73bf130	700	#define ETH_DMATXDESC_TBS1 ((uint32_t)0x00001FFF) /!< Transmit Buffer1 Size /
vladvana	0:23d1f73bf130	701
vladvana	0:23d1f73bf130	702	/**
vladvana	0:23d1f73bf130	703	* @brief Bit definition of TDES2 register
vladvana	0:23d1f73bf130	704	*/
vladvana	0:23d1f73bf130	705	#define ETH_DMATXDESC_B1AP ((uint32_t)0xFFFFFFFF) /!< Buffer1 Address Pointer /
vladvana	0:23d1f73bf130	706
vladvana	0:23d1f73bf130	707	/**
vladvana	0:23d1f73bf130	708	* @brief Bit definition of TDES3 register
vladvana	0:23d1f73bf130	709	*/
vladvana	0:23d1f73bf130	710	#define ETH_DMATXDESC_B2AP ((uint32_t)0xFFFFFFFF) /!< Buffer2 Address Pointer /
vladvana	0:23d1f73bf130	711
vladvana	0:23d1f73bf130	712	/**
vladvana	0:23d1f73bf130	713	* @}
vladvana	0:23d1f73bf130	714	*/
vladvana	0:23d1f73bf130	715	/** @defgroup ETH_DMA_RX_Descriptor ETH DMA RX Descriptor
vladvana	0:23d1f73bf130	716	* @{
vladvana	0:23d1f73bf130	717	*/
vladvana	0:23d1f73bf130	718
vladvana	0:23d1f73bf130	719	/*
vladvana	0:23d1f73bf130	720	DMA Rx Descriptor
vladvana	0:23d1f73bf130	721	--------------------------------------------------------------------------------------------------------------------
vladvana	0:23d1f73bf130	722	RDES0 \| OWN(31) \| Status [30:0] \|
vladvana	0:23d1f73bf130	723	---------------------------------------------------------------------------------------------------------------------
vladvana	0:23d1f73bf130	724	RDES1 \| CTRL(31) \| Reserved[30:29] \| Buffer2 ByteCount[28:16] \| CTRL[15:14] \| Reserved(13) \| Buffer1 ByteCount[12:0] \|
vladvana	0:23d1f73bf130	725	---------------------------------------------------------------------------------------------------------------------
vladvana	0:23d1f73bf130	726	RDES2 \| Buffer1 Address [31:0] \|
vladvana	0:23d1f73bf130	727	---------------------------------------------------------------------------------------------------------------------
vladvana	0:23d1f73bf130	728	RDES3 \| Buffer2 Address [31:0] / Next Descriptor Address [31:0] \|
vladvana	0:23d1f73bf130	729	---------------------------------------------------------------------------------------------------------------------
vladvana	0:23d1f73bf130	730	*/
vladvana	0:23d1f73bf130	731
vladvana	0:23d1f73bf130	732	/**
vladvana	0:23d1f73bf130	733	* @brief Bit definition of RDES0 register: DMA Rx descriptor status register
vladvana	0:23d1f73bf130	734	*/
vladvana	0:23d1f73bf130	735	#define ETH_DMARXDESC_OWN ((uint32_t)0x80000000) /!< OWN bit: descriptor is owned by DMA engine /
vladvana	0:23d1f73bf130	736	#define ETH_DMARXDESC_AFM ((uint32_t)0x40000000) /!< DA Filter Fail for the rx frame /
vladvana	0:23d1f73bf130	737	#define ETH_DMARXDESC_FL ((uint32_t)0x3FFF0000) /!< Receive descriptor frame length /
vladvana	0:23d1f73bf130	738	#define ETH_DMARXDESC_ES ((uint32_t)0x00008000) /!< Error summary: OR of the following bits: DE \|\| OE \|\| IPC \|\| LC \|\| RWT \|\| RE \|\| CE /
vladvana	0:23d1f73bf130	739	#define ETH_DMARXDESC_DE ((uint32_t)0x00004000) /!< Descriptor error: no more descriptors for receive frame /
vladvana	0:23d1f73bf130	740	#define ETH_DMARXDESC_SAF ((uint32_t)0x00002000) /!< SA Filter Fail for the received frame /
vladvana	0:23d1f73bf130	741	#define ETH_DMARXDESC_LE ((uint32_t)0x00001000) /!< Frame size not matching with length field /
vladvana	0:23d1f73bf130	742	#define ETH_DMARXDESC_OE ((uint32_t)0x00000800) /!< Overflow Error: Frame was damaged due to buffer overflow /
vladvana	0:23d1f73bf130	743	#define ETH_DMARXDESC_VLAN ((uint32_t)0x00000400) /!< VLAN Tag: received frame is a VLAN frame /
vladvana	0:23d1f73bf130	744	#define ETH_DMARXDESC_FS ((uint32_t)0x00000200) /!< First descriptor of the frame /
vladvana	0:23d1f73bf130	745	#define ETH_DMARXDESC_LS ((uint32_t)0x00000100) /!< Last descriptor of the frame /
vladvana	0:23d1f73bf130	746	#define ETH_DMARXDESC_IPV4HCE ((uint32_t)0x00000080) /!< IPC Checksum Error: Rx Ipv4 header checksum error /
vladvana	0:23d1f73bf130	747	#define ETH_DMARXDESC_LC ((uint32_t)0x00000040) /!< Late collision occurred during reception /
vladvana	0:23d1f73bf130	748	#define ETH_DMARXDESC_FT ((uint32_t)0x00000020) /!< Frame type - Ethernet, otherwise 802.3 /
vladvana	0:23d1f73bf130	749	#define ETH_DMARXDESC_RWT ((uint32_t)0x00000010) /!< Receive Watchdog Timeout: watchdog timer expired during reception /
vladvana	0:23d1f73bf130	750	#define ETH_DMARXDESC_RE ((uint32_t)0x00000008) /!< Receive error: error reported by MII interface /
vladvana	0:23d1f73bf130	751	#define ETH_DMARXDESC_DBE ((uint32_t)0x00000004) /!< Dribble bit error: frame contains non int multiple of 8 bits /
vladvana	0:23d1f73bf130	752	#define ETH_DMARXDESC_CE ((uint32_t)0x00000002) /!< CRC error /
vladvana	0:23d1f73bf130	753	#define ETH_DMARXDESC_MAMPCE ((uint32_t)0x00000001) /!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error /
vladvana	0:23d1f73bf130	754
vladvana	0:23d1f73bf130	755	/**
vladvana	0:23d1f73bf130	756	* @brief Bit definition of RDES1 register
vladvana	0:23d1f73bf130	757	*/
vladvana	0:23d1f73bf130	758	#define ETH_DMARXDESC_DIC ((uint32_t)0x80000000) /!< Disable Interrupt on Completion /
vladvana	0:23d1f73bf130	759	#define ETH_DMARXDESC_RBS2 ((uint32_t)0x1FFF0000) /!< Receive Buffer2 Size /
vladvana	0:23d1f73bf130	760	#define ETH_DMARXDESC_RER ((uint32_t)0x00008000) /!< Receive End of Ring /
vladvana	0:23d1f73bf130	761	#define ETH_DMARXDESC_RCH ((uint32_t)0x00004000) /!< Second Address Chained /
vladvana	0:23d1f73bf130	762	#define ETH_DMARXDESC_RBS1 ((uint32_t)0x00001FFF) /!< Receive Buffer1 Size /
vladvana	0:23d1f73bf130	763
vladvana	0:23d1f73bf130	764	/**
vladvana	0:23d1f73bf130	765	* @brief Bit definition of RDES2 register
vladvana	0:23d1f73bf130	766	*/
vladvana	0:23d1f73bf130	767	#define ETH_DMARXDESC_B1AP ((uint32_t)0xFFFFFFFF) /!< Buffer1 Address Pointer /
vladvana	0:23d1f73bf130	768
vladvana	0:23d1f73bf130	769	/**
vladvana	0:23d1f73bf130	770	* @brief Bit definition of RDES3 register
vladvana	0:23d1f73bf130	771	*/
vladvana	0:23d1f73bf130	772	#define ETH_DMARXDESC_B2AP ((uint32_t)0xFFFFFFFF) /!< Buffer2 Address Pointer /
vladvana	0:23d1f73bf130	773
vladvana	0:23d1f73bf130	774	/**
vladvana	0:23d1f73bf130	775	* @}
vladvana	0:23d1f73bf130	776	*/
vladvana	0:23d1f73bf130	777	/** @defgroup ETH_AutoNegotiation ETH AutoNegotiation
vladvana	0:23d1f73bf130	778	* @{
vladvana	0:23d1f73bf130	779	*/
vladvana	0:23d1f73bf130	780	#define ETH_AUTONEGOTIATION_ENABLE ((uint32_t)0x00000001)
vladvana	0:23d1f73bf130	781	#define ETH_AUTONEGOTIATION_DISABLE ((uint32_t)0x00000000)
vladvana	0:23d1f73bf130	782
vladvana	0:23d1f73bf130	783	/**
vladvana	0:23d1f73bf130	784	* @}
vladvana	0:23d1f73bf130	785	*/
vladvana	0:23d1f73bf130	786	/** @defgroup ETH_Speed ETH Speed
vladvana	0:23d1f73bf130	787	* @{
vladvana	0:23d1f73bf130	788	*/
vladvana	0:23d1f73bf130	789	#define ETH_SPEED_10M ((uint32_t)0x00000000)
vladvana	0:23d1f73bf130	790	#define ETH_SPEED_100M ((uint32_t)0x00004000)
vladvana	0:23d1f73bf130	791
vladvana	0:23d1f73bf130	792	/**
vladvana	0:23d1f73bf130	793	* @}
vladvana	0:23d1f73bf130	794	*/
vladvana	0:23d1f73bf130	795	/** @defgroup ETH_Duplex_Mode ETH Duplex Mode
vladvana	0:23d1f73bf130	796	* @{
vladvana	0:23d1f73bf130	797	*/
vladvana	0:23d1f73bf130	798	#define ETH_MODE_FULLDUPLEX ((uint32_t)0x00000800)
vladvana	0:23d1f73bf130	799	#define ETH_MODE_HALFDUPLEX ((uint32_t)0x00000000)
vladvana	0:23d1f73bf130	800	/**
vladvana	0:23d1f73bf130	801	* @}
vladvana	0:23d1f73bf130	802	*/
vladvana	0:23d1f73bf130	803	/** @defgroup ETH_Rx_Mode ETH Rx Mode
vladvana	0:23d1f73bf130	804	* @{
vladvana	0:23d1f73bf130	805	*/
vladvana	0:23d1f73bf130	806	#define ETH_RXPOLLING_MODE ((uint32_t)0x00000000)
vladvana	0:23d1f73bf130	807	#define ETH_RXINTERRUPT_MODE ((uint32_t)0x00000001)
vladvana	0:23d1f73bf130	808	/**
vladvana	0:23d1f73bf130	809	* @}
vladvana	0:23d1f73bf130	810	*/
vladvana	0:23d1f73bf130	811
vladvana	0:23d1f73bf130	812	/** @defgroup ETH_Checksum_Mode ETH Checksum Mode
vladvana	0:23d1f73bf130	813	* @{
vladvana	0:23d1f73bf130	814	*/
vladvana	0:23d1f73bf130	815	#define ETH_CHECKSUM_BY_HARDWARE ((uint32_t)0x00000000)
vladvana	0:23d1f73bf130	816	#define ETH_CHECKSUM_BY_SOFTWARE ((uint32_t)0x00000001)
vladvana	0:23d1f73bf130	817	/**
vladvana	0:23d1f73bf130	818	* @}
vladvana	0:23d1f73bf130	819	*/
vladvana	0:23d1f73bf130	820
vladvana	0:23d1f73bf130	821	/** @defgroup ETH_Media_Interface ETH Media Interface
vladvana	0:23d1f73bf130	822	* @{
vladvana	0:23d1f73bf130	823	*/
vladvana	0:23d1f73bf130	824	#define ETH_MEDIA_INTERFACE_MII ((uint32_t)0x00000000)
vladvana	0:23d1f73bf130	825	#define ETH_MEDIA_INTERFACE_RMII ((uint32_t)AFIO_MAPR_MII_RMII_SEL)
vladvana	0:23d1f73bf130	826
vladvana	0:23d1f73bf130	827	/**
vladvana	0:23d1f73bf130	828	* @}
vladvana	0:23d1f73bf130	829	*/
vladvana	0:23d1f73bf130	830
vladvana	0:23d1f73bf130	831	/** @defgroup ETH_Watchdog ETH Watchdog
vladvana	0:23d1f73bf130	832	* @{
vladvana	0:23d1f73bf130	833	*/
vladvana	0:23d1f73bf130	834	#define ETH_WATCHDOG_ENABLE ((uint32_t)0x00000000)
vladvana	0:23d1f73bf130	835	#define ETH_WATCHDOG_DISABLE ((uint32_t)0x00800000)
vladvana	0:23d1f73bf130	836
vladvana	0:23d1f73bf130	837	/**
vladvana	0:23d1f73bf130	838	* @}
vladvana	0:23d1f73bf130	839	*/
vladvana	0:23d1f73bf130	840
vladvana	0:23d1f73bf130	841	/** @defgroup ETH_Jabber ETH Jabber
vladvana	0:23d1f73bf130	842	* @{
vladvana	0:23d1f73bf130	843	*/
vladvana	0:23d1f73bf130	844	#define ETH_JABBER_ENABLE ((uint32_t)0x00000000)
vladvana	0:23d1f73bf130	845	#define ETH_JABBER_DISABLE ((uint32_t)0x00400000)
vladvana	0:23d1f73bf130	846
vladvana	0:23d1f73bf130	847	/**
vladvana	0:23d1f73bf130	848	* @}
vladvana	0:23d1f73bf130	849	*/
vladvana	0:23d1f73bf130	850
vladvana	0:23d1f73bf130	851	/** @defgroup ETH_Inter_Frame_Gap ETH Inter Frame Gap
vladvana	0:23d1f73bf130	852	* @{
vladvana	0:23d1f73bf130	853	*/
vladvana	0:23d1f73bf130	854	#define ETH_INTERFRAMEGAP_96BIT ((uint32_t)0x00000000) /!< minimum IFG between frames during transmission is 96Bit /
vladvana	0:23d1f73bf130	855	#define ETH_INTERFRAMEGAP_88BIT ((uint32_t)0x00020000) /!< minimum IFG between frames during transmission is 88Bit /
vladvana	0:23d1f73bf130	856	#define ETH_INTERFRAMEGAP_80BIT ((uint32_t)0x00040000) /!< minimum IFG between frames during transmission is 80Bit /
vladvana	0:23d1f73bf130	857	#define ETH_INTERFRAMEGAP_72BIT ((uint32_t)0x00060000) /!< minimum IFG between frames during transmission is 72Bit /
vladvana	0:23d1f73bf130	858	#define ETH_INTERFRAMEGAP_64BIT ((uint32_t)0x00080000) /!< minimum IFG between frames during transmission is 64Bit /
vladvana	0:23d1f73bf130	859	#define ETH_INTERFRAMEGAP_56BIT ((uint32_t)0x000A0000) /!< minimum IFG between frames during transmission is 56Bit /
vladvana	0:23d1f73bf130	860	#define ETH_INTERFRAMEGAP_48BIT ((uint32_t)0x000C0000) /!< minimum IFG between frames during transmission is 48Bit /
vladvana	0:23d1f73bf130	861	#define ETH_INTERFRAMEGAP_40BIT ((uint32_t)0x000E0000) /!< minimum IFG between frames during transmission is 40Bit /
vladvana	0:23d1f73bf130	862
vladvana	0:23d1f73bf130	863	/**
vladvana	0:23d1f73bf130	864	* @}
vladvana	0:23d1f73bf130	865	*/
vladvana	0:23d1f73bf130	866
vladvana	0:23d1f73bf130	867	/** @defgroup ETH_Carrier_Sense ETH Carrier Sense
vladvana	0:23d1f73bf130	868	* @{
vladvana	0:23d1f73bf130	869	*/
vladvana	0:23d1f73bf130	870	#define ETH_CARRIERSENCE_ENABLE ((uint32_t)0x00000000)
vladvana	0:23d1f73bf130	871	#define ETH_CARRIERSENCE_DISABLE ((uint32_t)0x00010000)
vladvana	0:23d1f73bf130	872
vladvana	0:23d1f73bf130	873	/**
vladvana	0:23d1f73bf130	874	* @}
vladvana	0:23d1f73bf130	875	*/
vladvana	0:23d1f73bf130	876
vladvana	0:23d1f73bf130	877	/** @defgroup ETH_Receive_Own ETH Receive Own
vladvana	0:23d1f73bf130	878	* @{
vladvana	0:23d1f73bf130	879	*/
vladvana	0:23d1f73bf130	880	#define ETH_RECEIVEOWN_ENABLE ((uint32_t)0x00000000)
vladvana	0:23d1f73bf130	881	#define ETH_RECEIVEOWN_DISABLE ((uint32_t)0x00002000)
vladvana	0:23d1f73bf130	882
vladvana	0:23d1f73bf130	883	/**
vladvana	0:23d1f73bf130	884	* @}
vladvana	0:23d1f73bf130	885	*/
vladvana	0:23d1f73bf130	886
vladvana	0:23d1f73bf130	887	/** @defgroup ETH_Loop_Back_Mode ETH Loop Back Mode
vladvana	0:23d1f73bf130	888	* @{
vladvana	0:23d1f73bf130	889	*/
vladvana	0:23d1f73bf130	890	#define ETH_LOOPBACKMODE_ENABLE ((uint32_t)0x00001000)
vladvana	0:23d1f73bf130	891	#define ETH_LOOPBACKMODE_DISABLE ((uint32_t)0x00000000)
vladvana	0:23d1f73bf130	892
vladvana	0:23d1f73bf130	893	/**
vladvana	0:23d1f73bf130	894	* @}
vladvana	0:23d1f73bf130	895	*/
vladvana	0:23d1f73bf130	896
vladvana	0:23d1f73bf130	897	/** @defgroup ETH_Checksum_Offload ETH Checksum Offload
vladvana	0:23d1f73bf130	898	* @{
vladvana	0:23d1f73bf130	899	*/
vladvana	0:23d1f73bf130	900	#define ETH_CHECKSUMOFFLAOD_ENABLE ((uint32_t)0x00000400)
vladvana	0:23d1f73bf130	901	#define ETH_CHECKSUMOFFLAOD_DISABLE ((uint32_t)0x00000000)
vladvana	0:23d1f73bf130	902
vladvana	0:23d1f73bf130	903	/**
vladvana	0:23d1f73bf130	904	* @}
vladvana	0:23d1f73bf130	905	*/
vladvana	0:23d1f73bf130	906
vladvana	0:23d1f73bf130	907	/** @defgroup ETH_Retry_Transmission ETH Retry Transmission
vladvana	0:23d1f73bf130	908	* @{
vladvana	0:23d1f73bf130	909	*/
vladvana	0:23d1f73bf130	910	#define ETH_RETRYTRANSMISSION_ENABLE ((uint32_t)0x00000000)
vladvana	0:23d1f73bf130	911	#define ETH_RETRYTRANSMISSION_DISABLE ((uint32_t)0x00000200)
vladvana	0:23d1f73bf130	912
vladvana	0:23d1f73bf130	913	/**
vladvana	0:23d1f73bf130	914	* @}
vladvana	0:23d1f73bf130	915	*/
vladvana	0:23d1f73bf130	916
vladvana	0:23d1f73bf130	917	/** @defgroup ETH_Automatic_Pad_CRC_Strip ETH Automatic Pad CRC Strip
vladvana	0:23d1f73bf130	918	* @{
vladvana	0:23d1f73bf130	919	*/
vladvana	0:23d1f73bf130	920	#define ETH_AUTOMATICPADCRCSTRIP_ENABLE ((uint32_t)0x00000080)
vladvana	0:23d1f73bf130	921	#define ETH_AUTOMATICPADCRCSTRIP_DISABLE ((uint32_t)0x00000000)
vladvana	0:23d1f73bf130	922
vladvana	0:23d1f73bf130	923	/**
vladvana	0:23d1f73bf130	924	* @}
vladvana	0:23d1f73bf130	925	*/
vladvana	0:23d1f73bf130	926
vladvana	0:23d1f73bf130	927	/** @defgroup ETH_Back_Off_Limit ETH Back Off Limit
vladvana	0:23d1f73bf130	928	* @{
vladvana	0:23d1f73bf130	929	*/
vladvana	0:23d1f73bf130	930	#define ETH_BACKOFFLIMIT_10 ((uint32_t)0x00000000)
vladvana	0:23d1f73bf130	931	#define ETH_BACKOFFLIMIT_8 ((uint32_t)0x00000020)
vladvana	0:23d1f73bf130	932	#define ETH_BACKOFFLIMIT_4 ((uint32_t)0x00000040)
vladvana	0:23d1f73bf130	933	#define ETH_BACKOFFLIMIT_1 ((uint32_t)0x00000060)
vladvana	0:23d1f73bf130	934
vladvana	0:23d1f73bf130	935	/**
vladvana	0:23d1f73bf130	936	* @}
vladvana	0:23d1f73bf130	937	*/
vladvana	0:23d1f73bf130	938
vladvana	0:23d1f73bf130	939	/** @defgroup ETH_Deferral_Check ETH Deferral Check
vladvana	0:23d1f73bf130	940	* @{
vladvana	0:23d1f73bf130	941	*/
vladvana	0:23d1f73bf130	942	#define ETH_DEFFERRALCHECK_ENABLE ((uint32_t)0x00000010)
vladvana	0:23d1f73bf130	943	#define ETH_DEFFERRALCHECK_DISABLE ((uint32_t)0x00000000)
vladvana	0:23d1f73bf130	944
vladvana	0:23d1f73bf130	945	/**
vladvana	0:23d1f73bf130	946	* @}
vladvana	0:23d1f73bf130	947	*/
vladvana	0:23d1f73bf130	948
vladvana	0:23d1f73bf130	949	/** @defgroup ETH_Receive_All ETH Receive All
vladvana	0:23d1f73bf130	950	* @{
vladvana	0:23d1f73bf130	951	*/
vladvana	0:23d1f73bf130	952	#define ETH_RECEIVEALL_ENABLE ((uint32_t)0x80000000)
vladvana	0:23d1f73bf130	953	#define ETH_RECEIVEAll_DISABLE ((uint32_t)0x00000000)
vladvana	0:23d1f73bf130	954
vladvana	0:23d1f73bf130	955	/**
vladvana	0:23d1f73bf130	956	* @}
vladvana	0:23d1f73bf130	957	*/
vladvana	0:23d1f73bf130	958
vladvana	0:23d1f73bf130	959	/** @defgroup ETH_Source_Addr_Filter ETH Source Addr Filter
vladvana	0:23d1f73bf130	960	* @{
vladvana	0:23d1f73bf130	961	*/
vladvana	0:23d1f73bf130	962	#define ETH_SOURCEADDRFILTER_NORMAL_ENABLE ((uint32_t)0x00000200)
vladvana	0:23d1f73bf130	963	#define ETH_SOURCEADDRFILTER_INVERSE_ENABLE ((uint32_t)0x00000300)
vladvana	0:23d1f73bf130	964	#define ETH_SOURCEADDRFILTER_DISABLE ((uint32_t)0x00000000)
vladvana	0:23d1f73bf130	965
vladvana	0:23d1f73bf130	966	/**
vladvana	0:23d1f73bf130	967	* @}
vladvana	0:23d1f73bf130	968	*/
vladvana	0:23d1f73bf130	969
vladvana	0:23d1f73bf130	970	/** @defgroup ETH_Pass_Control_Frames ETH Pass Control Frames
vladvana	0:23d1f73bf130	971	* @{
vladvana	0:23d1f73bf130	972	*/
vladvana	0:23d1f73bf130	973	#define ETH_PASSCONTROLFRAMES_BLOCKALL ((uint32_t)0x00000040) /!< MAC filters all control frames from reaching the application /
vladvana	0:23d1f73bf130	974	#define ETH_PASSCONTROLFRAMES_FORWARDALL ((uint32_t)0x00000080) /!< MAC forwards all control frames to application even if they fail the Address Filter /
vladvana	0:23d1f73bf130	975	#define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER ((uint32_t)0x000000C0) /!< MAC forwards control frames that pass the Address Filter. /
vladvana	0:23d1f73bf130	976
vladvana	0:23d1f73bf130	977	/**
vladvana	0:23d1f73bf130	978	* @}
vladvana	0:23d1f73bf130	979	*/
vladvana	0:23d1f73bf130	980
vladvana	0:23d1f73bf130	981	/** @defgroup ETH_Broadcast_Frames_Reception ETH Broadcast Frames Reception
vladvana	0:23d1f73bf130	982	* @{
vladvana	0:23d1f73bf130	983	*/
vladvana	0:23d1f73bf130	984	#define ETH_BROADCASTFRAMESRECEPTION_ENABLE ((uint32_t)0x00000000)
vladvana	0:23d1f73bf130	985	#define ETH_BROADCASTFRAMESRECEPTION_DISABLE ((uint32_t)0x00000020)
vladvana	0:23d1f73bf130	986
vladvana	0:23d1f73bf130	987	/**
vladvana	0:23d1f73bf130	988	* @}
vladvana	0:23d1f73bf130	989	*/
vladvana	0:23d1f73bf130	990
vladvana	0:23d1f73bf130	991	/** @defgroup ETH_Destination_Addr_Filter ETH Destination Addr Filter
vladvana	0:23d1f73bf130	992	* @{
vladvana	0:23d1f73bf130	993	*/
vladvana	0:23d1f73bf130	994	#define ETH_DESTINATIONADDRFILTER_NORMAL ((uint32_t)0x00000000)
vladvana	0:23d1f73bf130	995	#define ETH_DESTINATIONADDRFILTER_INVERSE ((uint32_t)0x00000008)
vladvana	0:23d1f73bf130	996
vladvana	0:23d1f73bf130	997	/**
vladvana	0:23d1f73bf130	998	* @}
vladvana	0:23d1f73bf130	999	*/
vladvana	0:23d1f73bf130	1000
vladvana	0:23d1f73bf130	1001	/** @defgroup ETH_Promiscuous_Mode ETH Promiscuous Mode
vladvana	0:23d1f73bf130	1002	* @{
vladvana	0:23d1f73bf130	1003	*/
vladvana	0:23d1f73bf130	1004	#define ETH_PROMISCUOUS_MODE_ENABLE ((uint32_t)0x00000001)
vladvana	0:23d1f73bf130	1005	#define ETH_PROMISCUOUS_MODE_DISABLE ((uint32_t)0x00000000)
vladvana	0:23d1f73bf130	1006
vladvana	0:23d1f73bf130	1007	/**
vladvana	0:23d1f73bf130	1008	* @}
vladvana	0:23d1f73bf130	1009	*/
vladvana	0:23d1f73bf130	1010
vladvana	0:23d1f73bf130	1011	/** @defgroup ETH_Multicast_Frames_Filter ETH Multicast Frames Filter
vladvana	0:23d1f73bf130	1012	* @{
vladvana	0:23d1f73bf130	1013	*/
vladvana	0:23d1f73bf130	1014	#define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000404)
vladvana	0:23d1f73bf130	1015	#define ETH_MULTICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000004)
vladvana	0:23d1f73bf130	1016	#define ETH_MULTICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000)
vladvana	0:23d1f73bf130	1017	#define ETH_MULTICASTFRAMESFILTER_NONE ((uint32_t)0x00000010)
vladvana	0:23d1f73bf130	1018
vladvana	0:23d1f73bf130	1019	/**
vladvana	0:23d1f73bf130	1020	* @}
vladvana	0:23d1f73bf130	1021	*/
vladvana	0:23d1f73bf130	1022
vladvana	0:23d1f73bf130	1023	/** @defgroup ETH_Unicast_Frames_Filter ETH Unicast Frames Filter
vladvana	0:23d1f73bf130	1024	* @{
vladvana	0:23d1f73bf130	1025	*/
vladvana	0:23d1f73bf130	1026	#define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000402)
vladvana	0:23d1f73bf130	1027	#define ETH_UNICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000002)
vladvana	0:23d1f73bf130	1028	#define ETH_UNICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000)
vladvana	0:23d1f73bf130	1029
vladvana	0:23d1f73bf130	1030	/**
vladvana	0:23d1f73bf130	1031	* @}
vladvana	0:23d1f73bf130	1032	*/
vladvana	0:23d1f73bf130	1033
vladvana	0:23d1f73bf130	1034	/** @defgroup ETH_Zero_Quanta_Pause ETH Zero Quanta Pause
vladvana	0:23d1f73bf130	1035	* @{
vladvana	0:23d1f73bf130	1036	*/
vladvana	0:23d1f73bf130	1037	#define ETH_ZEROQUANTAPAUSE_ENABLE ((uint32_t)0x00000000)
vladvana	0:23d1f73bf130	1038	#define ETH_ZEROQUANTAPAUSE_DISABLE ((uint32_t)0x00000080)
vladvana	0:23d1f73bf130	1039
vladvana	0:23d1f73bf130	1040	/**
vladvana	0:23d1f73bf130	1041	* @}
vladvana	0:23d1f73bf130	1042	*/
vladvana	0:23d1f73bf130	1043
vladvana	0:23d1f73bf130	1044	/** @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold
vladvana	0:23d1f73bf130	1045	* @{
vladvana	0:23d1f73bf130	1046	*/
vladvana	0:23d1f73bf130	1047	#define ETH_PAUSELOWTHRESHOLD_MINUS4 ((uint32_t)0x00000000) /!< Pause time minus 4 slot times /
vladvana	0:23d1f73bf130	1048	#define ETH_PAUSELOWTHRESHOLD_MINUS28 ((uint32_t)0x00000010) /!< Pause time minus 28 slot times /
vladvana	0:23d1f73bf130	1049	#define ETH_PAUSELOWTHRESHOLD_MINUS144 ((uint32_t)0x00000020) /!< Pause time minus 144 slot times /
vladvana	0:23d1f73bf130	1050	#define ETH_PAUSELOWTHRESHOLD_MINUS256 ((uint32_t)0x00000030) /!< Pause time minus 256 slot times /
vladvana	0:23d1f73bf130	1051
vladvana	0:23d1f73bf130	1052	/**
vladvana	0:23d1f73bf130	1053	* @}
vladvana	0:23d1f73bf130	1054	*/
vladvana	0:23d1f73bf130	1055
vladvana	0:23d1f73bf130	1056	/** @defgroup ETH_Unicast_Pause_Frame_Detect ETH Unicast Pause Frame Detect
vladvana	0:23d1f73bf130	1057	* @{
vladvana	0:23d1f73bf130	1058	*/
vladvana	0:23d1f73bf130	1059	#define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE ((uint32_t)0x00000008)
vladvana	0:23d1f73bf130	1060	#define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE ((uint32_t)0x00000000)
vladvana	0:23d1f73bf130	1061
vladvana	0:23d1f73bf130	1062	/**
vladvana	0:23d1f73bf130	1063	* @}
vladvana	0:23d1f73bf130	1064	*/
vladvana	0:23d1f73bf130	1065
vladvana	0:23d1f73bf130	1066	/** @defgroup ETH_Receive_Flow_Control ETH Receive Flow Control
vladvana	0:23d1f73bf130	1067	* @{
vladvana	0:23d1f73bf130	1068	*/
vladvana	0:23d1f73bf130	1069	#define ETH_RECEIVEFLOWCONTROL_ENABLE ((uint32_t)0x00000004)
vladvana	0:23d1f73bf130	1070	#define ETH_RECEIVEFLOWCONTROL_DISABLE ((uint32_t)0x00000000)
vladvana	0:23d1f73bf130	1071
vladvana	0:23d1f73bf130	1072	/**
vladvana	0:23d1f73bf130	1073	* @}
vladvana	0:23d1f73bf130	1074	*/
vladvana	0:23d1f73bf130	1075
vladvana	0:23d1f73bf130	1076	/** @defgroup ETH_Transmit_Flow_Control ETH Transmit Flow Control
vladvana	0:23d1f73bf130	1077	* @{
vladvana	0:23d1f73bf130	1078	*/
vladvana	0:23d1f73bf130	1079	#define ETH_TRANSMITFLOWCONTROL_ENABLE ((uint32_t)0x00000002)
vladvana	0:23d1f73bf130	1080	#define ETH_TRANSMITFLOWCONTROL_DISABLE ((uint32_t)0x00000000)
vladvana	0:23d1f73bf130	1081
vladvana	0:23d1f73bf130	1082	/**
vladvana	0:23d1f73bf130	1083	* @}
vladvana	0:23d1f73bf130	1084	*/
vladvana	0:23d1f73bf130	1085
vladvana	0:23d1f73bf130	1086	/** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison
vladvana	0:23d1f73bf130	1087	* @{
vladvana	0:23d1f73bf130	1088	*/
vladvana	0:23d1f73bf130	1089	#define ETH_VLANTAGCOMPARISON_12BIT ((uint32_t)0x00010000)
vladvana	0:23d1f73bf130	1090	#define ETH_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000)
vladvana	0:23d1f73bf130	1091
vladvana	0:23d1f73bf130	1092	/**
vladvana	0:23d1f73bf130	1093	* @}
vladvana	0:23d1f73bf130	1094	*/
vladvana	0:23d1f73bf130	1095
vladvana	0:23d1f73bf130	1096	/** @defgroup ETH_MAC_addresses ETH MAC addresses
vladvana	0:23d1f73bf130	1097	* @{
vladvana	0:23d1f73bf130	1098	*/
vladvana	0:23d1f73bf130	1099	#define ETH_MAC_ADDRESS0 ((uint32_t)0x00000000)
vladvana	0:23d1f73bf130	1100	#define ETH_MAC_ADDRESS1 ((uint32_t)0x00000008)
vladvana	0:23d1f73bf130	1101	#define ETH_MAC_ADDRESS2 ((uint32_t)0x00000010)
vladvana	0:23d1f73bf130	1102	#define ETH_MAC_ADDRESS3 ((uint32_t)0x00000018)
vladvana	0:23d1f73bf130	1103
vladvana	0:23d1f73bf130	1104	/**
vladvana	0:23d1f73bf130	1105	* @}
vladvana	0:23d1f73bf130	1106	*/
vladvana	0:23d1f73bf130	1107
vladvana	0:23d1f73bf130	1108	/** @defgroup ETH_MAC_Addresses_Filter_SA_DA ETH MAC Addresses Filter SA DA
vladvana	0:23d1f73bf130	1109	* @{
vladvana	0:23d1f73bf130	1110	*/
vladvana	0:23d1f73bf130	1111	#define ETH_MAC_ADDRESSFILTER_SA ((uint32_t)0x00000000)
vladvana	0:23d1f73bf130	1112	#define ETH_MAC_ADDRESSFILTER_DA ((uint32_t)0x00000008)
vladvana	0:23d1f73bf130	1113	/**
vladvana	0:23d1f73bf130	1114	* @}
vladvana	0:23d1f73bf130	1115	*/
vladvana	0:23d1f73bf130	1116
vladvana	0:23d1f73bf130	1117	/** @defgroup ETH_MAC_Addresses_Filter_Mask_Bytes ETH_MAC Addresses Filter Mask Bytes
vladvana	0:23d1f73bf130	1118	* @{
vladvana	0:23d1f73bf130	1119	*/
vladvana	0:23d1f73bf130	1120	#define ETH_MAC_ADDRESSMASK_BYTE6 ((uint32_t)0x20000000) /!< Mask MAC Address high reg bits [15:8] /
vladvana	0:23d1f73bf130	1121	#define ETH_MAC_ADDRESSMASK_BYTE5 ((uint32_t)0x10000000) /!< Mask MAC Address high reg bits [7:0] /
vladvana	0:23d1f73bf130	1122	#define ETH_MAC_ADDRESSMASK_BYTE4 ((uint32_t)0x08000000) /!< Mask MAC Address low reg bits [31:24] /
vladvana	0:23d1f73bf130	1123	#define ETH_MAC_ADDRESSMASK_BYTE3 ((uint32_t)0x04000000) /!< Mask MAC Address low reg bits [23:16] /
vladvana	0:23d1f73bf130	1124	#define ETH_MAC_ADDRESSMASK_BYTE2 ((uint32_t)0x02000000) /!< Mask MAC Address low reg bits [15:8] /
vladvana	0:23d1f73bf130	1125	#define ETH_MAC_ADDRESSMASK_BYTE1 ((uint32_t)0x01000000) /!< Mask MAC Address low reg bits [70] /
vladvana	0:23d1f73bf130	1126
vladvana	0:23d1f73bf130	1127	/**
vladvana	0:23d1f73bf130	1128	* @}
vladvana	0:23d1f73bf130	1129	*/
vladvana	0:23d1f73bf130	1130
vladvana	0:23d1f73bf130	1131	/** @defgroup ETH_MAC_Debug_Flags ETH MAC Debug Flags
vladvana	0:23d1f73bf130	1132	* @{
vladvana	0:23d1f73bf130	1133	*/
vladvana	0:23d1f73bf130	1134	#define ETH_MAC_TXFIFO_FULL ((uint32_t)0x02000000) /* Tx FIFO full */
vladvana	0:23d1f73bf130	1135	#define ETH_MAC_TXFIFONOT_EMPTY ((uint32_t)0x01000000) /* Tx FIFO not empty */
vladvana	0:23d1f73bf130	1136	#define ETH_MAC_TXFIFO_WRITE_ACTIVE ((uint32_t)0x00400000) /* Tx FIFO write active */
vladvana	0:23d1f73bf130	1137	#define ETH_MAC_TXFIFO_IDLE ((uint32_t)0x00000000) /* Tx FIFO read status: Idle */
vladvana	0:23d1f73bf130	1138	#define ETH_MAC_TXFIFO_READ ((uint32_t)0x00100000) /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
vladvana	0:23d1f73bf130	1139	#define ETH_MAC_TXFIFO_WAITING ((uint32_t)0x00200000) /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
vladvana	0:23d1f73bf130	1140	#define ETH_MAC_TXFIFO_WRITING ((uint32_t)0x00300000) /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
vladvana	0:23d1f73bf130	1141	#define ETH_MAC_TRANSMISSION_PAUSE ((uint32_t)0x00080000) /* MAC transmitter in pause */
vladvana	0:23d1f73bf130	1142	#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE ((uint32_t)0x00000000) /* MAC transmit frame controller: Idle */
vladvana	0:23d1f73bf130	1143	#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING ((uint32_t)0x00020000) /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
vladvana	0:23d1f73bf130	1144	#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF ((uint32_t)0x00040000) /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
vladvana	0:23d1f73bf130	1145	#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING ((uint32_t)0x00060000) /* MAC transmit frame controller: Transferring input frame for transmission */
vladvana	0:23d1f73bf130	1146	#define ETH_MAC_MII_TRANSMIT_ACTIVE ((uint32_t)0x00010000) /* MAC MII transmit engine active */
vladvana	0:23d1f73bf130	1147	#define ETH_MAC_RXFIFO_EMPTY ((uint32_t)0x00000000) /* Rx FIFO fill level: empty */
vladvana	0:23d1f73bf130	1148	#define ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
vladvana	0:23d1f73bf130	1149	#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) /* Rx FIFO fill level: fill-level above flow-control activate threshold */
vladvana	0:23d1f73bf130	1150	#define ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) /* Rx FIFO fill level: full */
vladvana	0:23d1f73bf130	1151	#define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000060) /* Rx FIFO read controller IDLE state */
vladvana	0:23d1f73bf130	1152	#define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000060) /* Rx FIFO read controller Reading frame data */
vladvana	0:23d1f73bf130	1153	#define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000060) /* Rx FIFO read controller Reading frame status (or time-stamp) */
vladvana	0:23d1f73bf130	1154	#define ETH_MAC_READCONTROLLER_ FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */
vladvana	0:23d1f73bf130	1155	#define ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) /* Rx FIFO write controller active */
vladvana	0:23d1f73bf130	1156	#define ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) /* MAC small FIFO read / write controllers not active */
vladvana	0:23d1f73bf130	1157	#define ETH_MAC_SMALL_FIFO_READ_ACTIVE ((uint32_t)0x00000002) /* MAC small FIFO read controller active */
vladvana	0:23d1f73bf130	1158	#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004) /* MAC small FIFO write controller active */
vladvana	0:23d1f73bf130	1159	#define ETH_MAC_SMALL_FIFO_RW_ACTIVE ((uint32_t)0x00000006) /* MAC small FIFO read / write controllers active */
vladvana	0:23d1f73bf130	1160	#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE ((uint32_t)0x00000001) /* MAC MII receive protocol engine active */
vladvana	0:23d1f73bf130	1161
vladvana	0:23d1f73bf130	1162	/**
vladvana	0:23d1f73bf130	1163	* @}
vladvana	0:23d1f73bf130	1164	*/
vladvana	0:23d1f73bf130	1165
vladvana	0:23d1f73bf130	1166	/** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame ETH Drop TCP IP Checksum Error Frame
vladvana	0:23d1f73bf130	1167	* @{
vladvana	0:23d1f73bf130	1168	*/
vladvana	0:23d1f73bf130	1169	#define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE ((uint32_t)0x00000000)
vladvana	0:23d1f73bf130	1170	#define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE ((uint32_t)0x04000000)
vladvana	0:23d1f73bf130	1171
vladvana	0:23d1f73bf130	1172	/**
vladvana	0:23d1f73bf130	1173	* @}
vladvana	0:23d1f73bf130	1174	*/
vladvana	0:23d1f73bf130	1175
vladvana	0:23d1f73bf130	1176	/** @defgroup ETH_Receive_Store_Forward ETH Receive Store Forward
vladvana	0:23d1f73bf130	1177	* @{
vladvana	0:23d1f73bf130	1178	*/
vladvana	0:23d1f73bf130	1179	#define ETH_RECEIVESTOREFORWARD_ENABLE ((uint32_t)0x02000000)
vladvana	0:23d1f73bf130	1180	#define ETH_RECEIVESTOREFORWARD_DISABLE ((uint32_t)0x00000000)
vladvana	0:23d1f73bf130	1181
vladvana	0:23d1f73bf130	1182	/**
vladvana	0:23d1f73bf130	1183	* @}
vladvana	0:23d1f73bf130	1184	*/
vladvana	0:23d1f73bf130	1185
vladvana	0:23d1f73bf130	1186	/** @defgroup ETH_Flush_Received_Frame ETH Flush Received Frame
vladvana	0:23d1f73bf130	1187	* @{
vladvana	0:23d1f73bf130	1188	*/
vladvana	0:23d1f73bf130	1189	#define ETH_FLUSHRECEIVEDFRAME_ENABLE ((uint32_t)0x00000000)
vladvana	0:23d1f73bf130	1190	#define ETH_FLUSHRECEIVEDFRAME_DISABLE ((uint32_t)0x01000000)
vladvana	0:23d1f73bf130	1191
vladvana	0:23d1f73bf130	1192	/**
vladvana	0:23d1f73bf130	1193	* @}
vladvana	0:23d1f73bf130	1194	*/
vladvana	0:23d1f73bf130	1195
vladvana	0:23d1f73bf130	1196	/** @defgroup ETH_Transmit_Store_Forward ETH Transmit Store Forward
vladvana	0:23d1f73bf130	1197	* @{
vladvana	0:23d1f73bf130	1198	*/
vladvana	0:23d1f73bf130	1199	#define ETH_TRANSMITSTOREFORWARD_ENABLE ((uint32_t)0x00200000)
vladvana	0:23d1f73bf130	1200	#define ETH_TRANSMITSTOREFORWARD_DISABLE ((uint32_t)0x00000000)
vladvana	0:23d1f73bf130	1201
vladvana	0:23d1f73bf130	1202	/**
vladvana	0:23d1f73bf130	1203	* @}
vladvana	0:23d1f73bf130	1204	*/
vladvana	0:23d1f73bf130	1205
vladvana	0:23d1f73bf130	1206	/** @defgroup ETH_Transmit_Threshold_Control ETH Transmit Threshold Control
vladvana	0:23d1f73bf130	1207	* @{
vladvana	0:23d1f73bf130	1208	*/
vladvana	0:23d1f73bf130	1209	#define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000) /!< threshold level of the MTL Transmit FIFO is 64 Bytes /
vladvana	0:23d1f73bf130	1210	#define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00004000) /!< threshold level of the MTL Transmit FIFO is 128 Bytes /
vladvana	0:23d1f73bf130	1211	#define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES ((uint32_t)0x00008000) /!< threshold level of the MTL Transmit FIFO is 192 Bytes /
vladvana	0:23d1f73bf130	1212	#define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES ((uint32_t)0x0000C000) /!< threshold level of the MTL Transmit FIFO is 256 Bytes /
vladvana	0:23d1f73bf130	1213	#define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES ((uint32_t)0x00010000) /!< threshold level of the MTL Transmit FIFO is 40 Bytes /
vladvana	0:23d1f73bf130	1214	#define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00014000) /!< threshold level of the MTL Transmit FIFO is 32 Bytes /
vladvana	0:23d1f73bf130	1215	#define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES ((uint32_t)0x00018000) /!< threshold level of the MTL Transmit FIFO is 24 Bytes /
vladvana	0:23d1f73bf130	1216	#define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES ((uint32_t)0x0001C000) /!< threshold level of the MTL Transmit FIFO is 16 Bytes /
vladvana	0:23d1f73bf130	1217
vladvana	0:23d1f73bf130	1218	/**
vladvana	0:23d1f73bf130	1219	* @}
vladvana	0:23d1f73bf130	1220	*/
vladvana	0:23d1f73bf130	1221
vladvana	0:23d1f73bf130	1222	/** @defgroup ETH_Forward_Error_Frames ETH Forward Error Frames
vladvana	0:23d1f73bf130	1223	* @{
vladvana	0:23d1f73bf130	1224	*/
vladvana	0:23d1f73bf130	1225	#define ETH_FORWARDERRORFRAMES_ENABLE ((uint32_t)0x00000080)
vladvana	0:23d1f73bf130	1226	#define ETH_FORWARDERRORFRAMES_DISABLE ((uint32_t)0x00000000)
vladvana	0:23d1f73bf130	1227
vladvana	0:23d1f73bf130	1228	/**
vladvana	0:23d1f73bf130	1229	* @}
vladvana	0:23d1f73bf130	1230	*/
vladvana	0:23d1f73bf130	1231
vladvana	0:23d1f73bf130	1232	/** @defgroup ETH_Forward_Undersized_Good_Frames ETH Forward Undersized Good Frames
vladvana	0:23d1f73bf130	1233	* @{
vladvana	0:23d1f73bf130	1234	*/
vladvana	0:23d1f73bf130	1235	#define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE ((uint32_t)0x00000040)
vladvana	0:23d1f73bf130	1236	#define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE ((uint32_t)0x00000000)
vladvana	0:23d1f73bf130	1237
vladvana	0:23d1f73bf130	1238	/**
vladvana	0:23d1f73bf130	1239	* @}
vladvana	0:23d1f73bf130	1240	*/
vladvana	0:23d1f73bf130	1241
vladvana	0:23d1f73bf130	1242	/** @defgroup ETH_Receive_Threshold_Control ETH Receive Threshold Control
vladvana	0:23d1f73bf130	1243	* @{
vladvana	0:23d1f73bf130	1244	*/
vladvana	0:23d1f73bf130	1245	#define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000) /!< threshold level of the MTL Receive FIFO is 64 Bytes /
vladvana	0:23d1f73bf130	1246	#define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00000008) /!< threshold level of the MTL Receive FIFO is 32 Bytes /
vladvana	0:23d1f73bf130	1247	#define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES ((uint32_t)0x00000010) /!< threshold level of the MTL Receive FIFO is 96 Bytes /
vladvana	0:23d1f73bf130	1248	#define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00000018) /!< threshold level of the MTL Receive FIFO is 128 Bytes /
vladvana	0:23d1f73bf130	1249
vladvana	0:23d1f73bf130	1250	/**
vladvana	0:23d1f73bf130	1251	* @}
vladvana	0:23d1f73bf130	1252	*/
vladvana	0:23d1f73bf130	1253
vladvana	0:23d1f73bf130	1254	/** @defgroup ETH_Second_Frame_Operate ETH Second Frame Operate
vladvana	0:23d1f73bf130	1255	* @{
vladvana	0:23d1f73bf130	1256	*/
vladvana	0:23d1f73bf130	1257	#define ETH_SECONDFRAMEOPERARTE_ENABLE ((uint32_t)0x00000004)
vladvana	0:23d1f73bf130	1258	#define ETH_SECONDFRAMEOPERARTE_DISABLE ((uint32_t)0x00000000)
vladvana	0:23d1f73bf130	1259
vladvana	0:23d1f73bf130	1260	/**
vladvana	0:23d1f73bf130	1261	* @}
vladvana	0:23d1f73bf130	1262	*/
vladvana	0:23d1f73bf130	1263
vladvana	0:23d1f73bf130	1264	/** @defgroup ETH_Address_Aligned_Beats ETH Address Aligned Beats
vladvana	0:23d1f73bf130	1265	* @{
vladvana	0:23d1f73bf130	1266	*/
vladvana	0:23d1f73bf130	1267	#define ETH_ADDRESSALIGNEDBEATS_ENABLE ((uint32_t)0x02000000)
vladvana	0:23d1f73bf130	1268	#define ETH_ADDRESSALIGNEDBEATS_DISABLE ((uint32_t)0x00000000)
vladvana	0:23d1f73bf130	1269
vladvana	0:23d1f73bf130	1270	/**
vladvana	0:23d1f73bf130	1271	* @}
vladvana	0:23d1f73bf130	1272	*/
vladvana	0:23d1f73bf130	1273
vladvana	0:23d1f73bf130	1274	/** @defgroup ETH_Fixed_Burst ETH Fixed Burst
vladvana	0:23d1f73bf130	1275	* @{
vladvana	0:23d1f73bf130	1276	*/
vladvana	0:23d1f73bf130	1277	#define ETH_FIXEDBURST_ENABLE ((uint32_t)0x00010000)
vladvana	0:23d1f73bf130	1278	#define ETH_FIXEDBURST_DISABLE ((uint32_t)0x00000000)
vladvana	0:23d1f73bf130	1279
vladvana	0:23d1f73bf130	1280	/**
vladvana	0:23d1f73bf130	1281	* @}
vladvana	0:23d1f73bf130	1282	*/
vladvana	0:23d1f73bf130	1283
vladvana	0:23d1f73bf130	1284	/** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA_Burst Length
vladvana	0:23d1f73bf130	1285	* @{
vladvana	0:23d1f73bf130	1286	*/
vladvana	0:23d1f73bf130	1287	#define ETH_RXDMABURSTLENGTH_1BEAT ((uint32_t)0x00020000) /!< maximum number of beats to be transferred in one RxDMA transaction is 1 /
vladvana	0:23d1f73bf130	1288	#define ETH_RXDMABURSTLENGTH_2BEAT ((uint32_t)0x00040000) /!< maximum number of beats to be transferred in one RxDMA transaction is 2 /
vladvana	0:23d1f73bf130	1289	#define ETH_RXDMABURSTLENGTH_4BEAT ((uint32_t)0x00080000) /!< maximum number of beats to be transferred in one RxDMA transaction is 4 /
vladvana	0:23d1f73bf130	1290	#define ETH_RXDMABURSTLENGTH_8BEAT ((uint32_t)0x00100000) /!< maximum number of beats to be transferred in one RxDMA transaction is 8 /
vladvana	0:23d1f73bf130	1291	#define ETH_RXDMABURSTLENGTH_16BEAT ((uint32_t)0x00200000) /!< maximum number of beats to be transferred in one RxDMA transaction is 16 /
vladvana	0:23d1f73bf130	1292	#define ETH_RXDMABURSTLENGTH_32BEAT ((uint32_t)0x00400000) /!< maximum number of beats to be transferred in one RxDMA transaction is 32 /
vladvana	0:23d1f73bf130	1293	#define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01020000) /!< maximum number of beats to be transferred in one RxDMA transaction is 4 /
vladvana	0:23d1f73bf130	1294	#define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01040000) /!< maximum number of beats to be transferred in one RxDMA transaction is 8 /
vladvana	0:23d1f73bf130	1295	#define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01080000) /!< maximum number of beats to be transferred in one RxDMA transaction is 16 /
vladvana	0:23d1f73bf130	1296	#define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01100000) /!< maximum number of beats to be transferred in one RxDMA transaction is 32 /
vladvana	0:23d1f73bf130	1297	#define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01200000) /!< maximum number of beats to be transferred in one RxDMA transaction is 64 /
vladvana	0:23d1f73bf130	1298	#define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01400000) /!< maximum number of beats to be transferred in one RxDMA transaction is 128 /
vladvana	0:23d1f73bf130	1299
vladvana	0:23d1f73bf130	1300	/**
vladvana	0:23d1f73bf130	1301	* @}
vladvana	0:23d1f73bf130	1302	*/
vladvana	0:23d1f73bf130	1303
vladvana	0:23d1f73bf130	1304	/** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length
vladvana	0:23d1f73bf130	1305	* @{
vladvana	0:23d1f73bf130	1306	*/
vladvana	0:23d1f73bf130	1307	#define ETH_TXDMABURSTLENGTH_1BEAT ((uint32_t)0x00000100) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 /
vladvana	0:23d1f73bf130	1308	#define ETH_TXDMABURSTLENGTH_2BEAT ((uint32_t)0x00000200) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 /
vladvana	0:23d1f73bf130	1309	#define ETH_TXDMABURSTLENGTH_4BEAT ((uint32_t)0x00000400) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 /
vladvana	0:23d1f73bf130	1310	#define ETH_TXDMABURSTLENGTH_8BEAT ((uint32_t)0x00000800) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 /
vladvana	0:23d1f73bf130	1311	#define ETH_TXDMABURSTLENGTH_16BEAT ((uint32_t)0x00001000) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 /
vladvana	0:23d1f73bf130	1312	#define ETH_TXDMABURSTLENGTH_32BEAT ((uint32_t)0x00002000) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 /
vladvana	0:23d1f73bf130	1313	#define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01000100) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 /
vladvana	0:23d1f73bf130	1314	#define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01000200) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 /
vladvana	0:23d1f73bf130	1315	#define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01000400) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 /
vladvana	0:23d1f73bf130	1316	#define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01000800) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 /
vladvana	0:23d1f73bf130	1317	#define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01001000) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 /
vladvana	0:23d1f73bf130	1318	#define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01002000) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 /
vladvana	0:23d1f73bf130	1319
vladvana	0:23d1f73bf130	1320	/**
vladvana	0:23d1f73bf130	1321	* @}
vladvana	0:23d1f73bf130	1322	*/
vladvana	0:23d1f73bf130	1323
vladvana	0:23d1f73bf130	1324	/** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration
vladvana	0:23d1f73bf130	1325	* @{
vladvana	0:23d1f73bf130	1326	*/
vladvana	0:23d1f73bf130	1327	#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 ((uint32_t)0x00000000)
vladvana	0:23d1f73bf130	1328	#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 ((uint32_t)0x00004000)
vladvana	0:23d1f73bf130	1329	#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 ((uint32_t)0x00008000)
vladvana	0:23d1f73bf130	1330	#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 ((uint32_t)0x0000C000)
vladvana	0:23d1f73bf130	1331	#define ETH_DMAARBITRATION_RXPRIORTX ((uint32_t)0x00000002)
vladvana	0:23d1f73bf130	1332
vladvana	0:23d1f73bf130	1333	/**
vladvana	0:23d1f73bf130	1334	* @}
vladvana	0:23d1f73bf130	1335	*/
vladvana	0:23d1f73bf130	1336
vladvana	0:23d1f73bf130	1337	/** @defgroup ETH_DMA_Tx_Descriptor_Segment ETH DMA Tx Descriptor Segment
vladvana	0:23d1f73bf130	1338	* @{
vladvana	0:23d1f73bf130	1339	*/
vladvana	0:23d1f73bf130	1340	#define ETH_DMATXDESC_LASTSEGMENTS ((uint32_t)0x40000000) /!< Last Segment /
vladvana	0:23d1f73bf130	1341	#define ETH_DMATXDESC_FIRSTSEGMENT ((uint32_t)0x20000000) /!< First Segment /
vladvana	0:23d1f73bf130	1342
vladvana	0:23d1f73bf130	1343	/**
vladvana	0:23d1f73bf130	1344	* @}
vladvana	0:23d1f73bf130	1345	*/
vladvana	0:23d1f73bf130	1346
vladvana	0:23d1f73bf130	1347	/** @defgroup ETH_DMA_Tx_Descriptor_Checksum_Insertion_Control ETH DMA Tx Descriptor Checksum Insertion Control
vladvana	0:23d1f73bf130	1348	* @{
vladvana	0:23d1f73bf130	1349	*/
vladvana	0:23d1f73bf130	1350	#define ETH_DMATXDESC_CHECKSUMBYPASS ((uint32_t)0x00000000) /!< Checksum engine bypass /
vladvana	0:23d1f73bf130	1351	#define ETH_DMATXDESC_CHECKSUMIPV4HEADER ((uint32_t)0x00400000) /!< IPv4 header checksum insertion /
vladvana	0:23d1f73bf130	1352	#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT ((uint32_t)0x00800000) /!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present /
vladvana	0:23d1f73bf130	1353	#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL ((uint32_t)0x00C00000) /!< TCP/UDP/ICMP checksum fully in hardware including pseudo header /
vladvana	0:23d1f73bf130	1354
vladvana	0:23d1f73bf130	1355	/**
vladvana	0:23d1f73bf130	1356	* @}
vladvana	0:23d1f73bf130	1357	*/
vladvana	0:23d1f73bf130	1358
vladvana	0:23d1f73bf130	1359	/** @defgroup ETH_DMA_Rx_Descriptor_Buffers ETH DMA Rx Descriptor Buffers
vladvana	0:23d1f73bf130	1360	* @{
vladvana	0:23d1f73bf130	1361	*/
vladvana	0:23d1f73bf130	1362	#define ETH_DMARXDESC_BUFFER1 ((uint32_t)0x00000000) /!< DMA Rx Desc Buffer1 /
vladvana	0:23d1f73bf130	1363	#define ETH_DMARXDESC_BUFFER2 ((uint32_t)0x00000001) /!< DMA Rx Desc Buffer2 /
vladvana	0:23d1f73bf130	1364
vladvana	0:23d1f73bf130	1365	/**
vladvana	0:23d1f73bf130	1366	* @}
vladvana	0:23d1f73bf130	1367	*/
vladvana	0:23d1f73bf130	1368
vladvana	0:23d1f73bf130	1369	/** @defgroup ETH_PMT_Flags ETH PMT Flags
vladvana	0:23d1f73bf130	1370	* @{
vladvana	0:23d1f73bf130	1371	*/
vladvana	0:23d1f73bf130	1372	#define ETH_PMT_FLAG_WUFFRPR ((uint32_t)0x80000000) /!< Wake-Up Frame Filter Register Pointer Reset /
vladvana	0:23d1f73bf130	1373	#define ETH_PMT_FLAG_WUFR ((uint32_t)0x00000040) /!< Wake-Up Frame Received /
vladvana	0:23d1f73bf130	1374	#define ETH_PMT_FLAG_MPR ((uint32_t)0x00000020) /!< Magic Packet Received /
vladvana	0:23d1f73bf130	1375
vladvana	0:23d1f73bf130	1376	/**
vladvana	0:23d1f73bf130	1377	* @}
vladvana	0:23d1f73bf130	1378	*/
vladvana	0:23d1f73bf130	1379
vladvana	0:23d1f73bf130	1380	/** @defgroup ETH_MMC_Tx_Interrupts ETH MMC Tx Interrupts
vladvana	0:23d1f73bf130	1381	* @{
vladvana	0:23d1f73bf130	1382	*/
vladvana	0:23d1f73bf130	1383	#define ETH_MMC_IT_TGF ((uint32_t)0x00200000) /!< When Tx good frame counter reaches half the maximum value /
vladvana	0:23d1f73bf130	1384	#define ETH_MMC_IT_TGFMSC ((uint32_t)0x00008000) /!< When Tx good multi col counter reaches half the maximum value /
vladvana	0:23d1f73bf130	1385	#define ETH_MMC_IT_TGFSC ((uint32_t)0x00004000) /!< When Tx good single col counter reaches half the maximum value /
vladvana	0:23d1f73bf130	1386
vladvana	0:23d1f73bf130	1387	/**
vladvana	0:23d1f73bf130	1388	* @}
vladvana	0:23d1f73bf130	1389	*/
vladvana	0:23d1f73bf130	1390
vladvana	0:23d1f73bf130	1391	/** @defgroup ETH_MMC_Rx_Interrupts ETH MMC Rx Interrupts
vladvana	0:23d1f73bf130	1392	* @{
vladvana	0:23d1f73bf130	1393	*/
vladvana	0:23d1f73bf130	1394	#define ETH_MMC_IT_RGUF ((uint32_t)0x10020000) /!< When Rx good unicast frames counter reaches half the maximum value /
vladvana	0:23d1f73bf130	1395	#define ETH_MMC_IT_RFAE ((uint32_t)0x10000040) /!< When Rx alignment error counter reaches half the maximum value /
vladvana	0:23d1f73bf130	1396	#define ETH_MMC_IT_RFCE ((uint32_t)0x10000020) /!< When Rx crc error counter reaches half the maximum value /
vladvana	0:23d1f73bf130	1397
vladvana	0:23d1f73bf130	1398	/**
vladvana	0:23d1f73bf130	1399	* @}
vladvana	0:23d1f73bf130	1400	*/
vladvana	0:23d1f73bf130	1401
vladvana	0:23d1f73bf130	1402	/** @defgroup ETH_MAC_Flags ETH MAC Flags
vladvana	0:23d1f73bf130	1403	* @{
vladvana	0:23d1f73bf130	1404	*/
vladvana	0:23d1f73bf130	1405	#define ETH_MAC_FLAG_TST ((uint32_t)0x00000200) /!< Time stamp trigger flag (on MAC) /
vladvana	0:23d1f73bf130	1406	#define ETH_MAC_FLAG_MMCT ((uint32_t)0x00000040) /!< MMC transmit flag /
vladvana	0:23d1f73bf130	1407	#define ETH_MAC_FLAG_MMCR ((uint32_t)0x00000020) /!< MMC receive flag /
vladvana	0:23d1f73bf130	1408	#define ETH_MAC_FLAG_MMC ((uint32_t)0x00000010) /!< MMC flag (on MAC) /
vladvana	0:23d1f73bf130	1409	#define ETH_MAC_FLAG_PMT ((uint32_t)0x00000008) /!< PMT flag (on MAC) /
vladvana	0:23d1f73bf130	1410
vladvana	0:23d1f73bf130	1411	/**
vladvana	0:23d1f73bf130	1412	* @}
vladvana	0:23d1f73bf130	1413	*/
vladvana	0:23d1f73bf130	1414
vladvana	0:23d1f73bf130	1415	/** @defgroup ETH_DMA_Flags ETH DMA Flags
vladvana	0:23d1f73bf130	1416	* @{
vladvana	0:23d1f73bf130	1417	*/
vladvana	0:23d1f73bf130	1418	#define ETH_DMA_FLAG_TST ((uint32_t)0x20000000) /!< Time-stamp trigger interrupt (on DMA) /
vladvana	0:23d1f73bf130	1419	#define ETH_DMA_FLAG_PMT ((uint32_t)0x10000000) /!< PMT interrupt (on DMA) /
vladvana	0:23d1f73bf130	1420	#define ETH_DMA_FLAG_MMC ((uint32_t)0x08000000) /!< MMC interrupt (on DMA) /
vladvana	0:23d1f73bf130	1421	#define ETH_DMA_FLAG_DATATRANSFERERROR ((uint32_t)0x00800000) /!< Error bits 0-Rx DMA, 1-Tx DMA /
vladvana	0:23d1f73bf130	1422	#define ETH_DMA_FLAG_READWRITEERROR ((uint32_t)0x01000000) /!< Error bits 0-write trnsf, 1-read transfr /
vladvana	0:23d1f73bf130	1423	#define ETH_DMA_FLAG_ACCESSERROR ((uint32_t)0x02000000) /!< Error bits 0-data buffer, 1-desc. access /
vladvana	0:23d1f73bf130	1424	#define ETH_DMA_FLAG_NIS ((uint32_t)0x00010000) /!< Normal interrupt summary flag /
vladvana	0:23d1f73bf130	1425	#define ETH_DMA_FLAG_AIS ((uint32_t)0x00008000) /!< Abnormal interrupt summary flag /
vladvana	0:23d1f73bf130	1426	#define ETH_DMA_FLAG_ER ((uint32_t)0x00004000) /!< Early receive flag /
vladvana	0:23d1f73bf130	1427	#define ETH_DMA_FLAG_FBE ((uint32_t)0x00002000) /!< Fatal bus error flag /
vladvana	0:23d1f73bf130	1428	#define ETH_DMA_FLAG_ET ((uint32_t)0x00000400) /!< Early transmit flag /
vladvana	0:23d1f73bf130	1429	#define ETH_DMA_FLAG_RWT ((uint32_t)0x00000200) /!< Receive watchdog timeout flag /
vladvana	0:23d1f73bf130	1430	#define ETH_DMA_FLAG_RPS ((uint32_t)0x00000100) /!< Receive process stopped flag /
vladvana	0:23d1f73bf130	1431	#define ETH_DMA_FLAG_RBU ((uint32_t)0x00000080) /!< Receive buffer unavailable flag /
vladvana	0:23d1f73bf130	1432	#define ETH_DMA_FLAG_R ((uint32_t)0x00000040) /!< Receive flag /
vladvana	0:23d1f73bf130	1433	#define ETH_DMA_FLAG_TU ((uint32_t)0x00000020) /!< Underflow flag /
vladvana	0:23d1f73bf130	1434	#define ETH_DMA_FLAG_RO ((uint32_t)0x00000010) /!< Overflow flag /
vladvana	0:23d1f73bf130	1435	#define ETH_DMA_FLAG_TJT ((uint32_t)0x00000008) /!< Transmit jabber timeout flag /
vladvana	0:23d1f73bf130	1436	#define ETH_DMA_FLAG_TBU ((uint32_t)0x00000004) /!< Transmit buffer unavailable flag /
vladvana	0:23d1f73bf130	1437	#define ETH_DMA_FLAG_TPS ((uint32_t)0x00000002) /!< Transmit process stopped flag /
vladvana	0:23d1f73bf130	1438	#define ETH_DMA_FLAG_T ((uint32_t)0x00000001) /!< Transmit flag /
vladvana	0:23d1f73bf130	1439
vladvana	0:23d1f73bf130	1440	/**
vladvana	0:23d1f73bf130	1441	* @}
vladvana	0:23d1f73bf130	1442	*/
vladvana	0:23d1f73bf130	1443
vladvana	0:23d1f73bf130	1444	/** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts
vladvana	0:23d1f73bf130	1445	* @{
vladvana	0:23d1f73bf130	1446	*/
vladvana	0:23d1f73bf130	1447	#define ETH_MAC_IT_TST ((uint32_t)0x00000200) /!< Time stamp trigger interrupt (on MAC) /
vladvana	0:23d1f73bf130	1448	#define ETH_MAC_IT_MMCT ((uint32_t)0x00000040) /!< MMC transmit interrupt /
vladvana	0:23d1f73bf130	1449	#define ETH_MAC_IT_MMCR ((uint32_t)0x00000020) /!< MMC receive interrupt /
vladvana	0:23d1f73bf130	1450	#define ETH_MAC_IT_MMC ((uint32_t)0x00000010) /!< MMC interrupt (on MAC) /
vladvana	0:23d1f73bf130	1451	#define ETH_MAC_IT_PMT ((uint32_t)0x00000008) /!< PMT interrupt (on MAC) /
vladvana	0:23d1f73bf130	1452
vladvana	0:23d1f73bf130	1453	/**
vladvana	0:23d1f73bf130	1454	* @}
vladvana	0:23d1f73bf130	1455	*/
vladvana	0:23d1f73bf130	1456
vladvana	0:23d1f73bf130	1457	/** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts
vladvana	0:23d1f73bf130	1458	* @{
vladvana	0:23d1f73bf130	1459	*/
vladvana	0:23d1f73bf130	1460	#define ETH_DMA_IT_TST ((uint32_t)0x20000000) /!< Time-stamp trigger interrupt (on DMA) /
vladvana	0:23d1f73bf130	1461	#define ETH_DMA_IT_PMT ((uint32_t)0x10000000) /!< PMT interrupt (on DMA) /
vladvana	0:23d1f73bf130	1462	#define ETH_DMA_IT_MMC ((uint32_t)0x08000000) /!< MMC interrupt (on DMA) /
vladvana	0:23d1f73bf130	1463	#define ETH_DMA_IT_NIS ((uint32_t)0x00010000) /!< Normal interrupt summary /
vladvana	0:23d1f73bf130	1464	#define ETH_DMA_IT_AIS ((uint32_t)0x00008000) /!< Abnormal interrupt summary /
vladvana	0:23d1f73bf130	1465	#define ETH_DMA_IT_ER ((uint32_t)0x00004000) /!< Early receive interrupt /
vladvana	0:23d1f73bf130	1466	#define ETH_DMA_IT_FBE ((uint32_t)0x00002000) /!< Fatal bus error interrupt /
vladvana	0:23d1f73bf130	1467	#define ETH_DMA_IT_ET ((uint32_t)0x00000400) /!< Early transmit interrupt /
vladvana	0:23d1f73bf130	1468	#define ETH_DMA_IT_RWT ((uint32_t)0x00000200) /!< Receive watchdog timeout interrupt /
vladvana	0:23d1f73bf130	1469	#define ETH_DMA_IT_RPS ((uint32_t)0x00000100) /!< Receive process stopped interrupt /
vladvana	0:23d1f73bf130	1470	#define ETH_DMA_IT_RBU ((uint32_t)0x00000080) /!< Receive buffer unavailable interrupt /
vladvana	0:23d1f73bf130	1471	#define ETH_DMA_IT_R ((uint32_t)0x00000040) /!< Receive interrupt /
vladvana	0:23d1f73bf130	1472	#define ETH_DMA_IT_TU ((uint32_t)0x00000020) /!< Underflow interrupt /
vladvana	0:23d1f73bf130	1473	#define ETH_DMA_IT_RO ((uint32_t)0x00000010) /!< Overflow interrupt /
vladvana	0:23d1f73bf130	1474	#define ETH_DMA_IT_TJT ((uint32_t)0x00000008) /!< Transmit jabber timeout interrupt /
vladvana	0:23d1f73bf130	1475	#define ETH_DMA_IT_TBU ((uint32_t)0x00000004) /!< Transmit buffer unavailable interrupt /
vladvana	0:23d1f73bf130	1476	#define ETH_DMA_IT_TPS ((uint32_t)0x00000002) /!< Transmit process stopped interrupt /
vladvana	0:23d1f73bf130	1477	#define ETH_DMA_IT_T ((uint32_t)0x00000001) /!< Transmit interrupt /
vladvana	0:23d1f73bf130	1478
vladvana	0:23d1f73bf130	1479	/**
vladvana	0:23d1f73bf130	1480	* @}
vladvana	0:23d1f73bf130	1481	*/
vladvana	0:23d1f73bf130	1482
vladvana	0:23d1f73bf130	1483	/** @defgroup ETH_DMA_transmit_process_state ETH DMA transmit process state
vladvana	0:23d1f73bf130	1484	* @{
vladvana	0:23d1f73bf130	1485	*/
vladvana	0:23d1f73bf130	1486	#define ETH_DMA_TRANSMITPROCESS_STOPPED ((uint32_t)0x00000000) /!< Stopped - Reset or Stop Tx Command issued /
vladvana	0:23d1f73bf130	1487	#define ETH_DMA_TRANSMITPROCESS_FETCHING ((uint32_t)0x00100000) /!< Running - fetching the Tx descriptor /
vladvana	0:23d1f73bf130	1488	#define ETH_DMA_TRANSMITPROCESS_WAITING ((uint32_t)0x00200000) /!< Running - waiting for status /
vladvana	0:23d1f73bf130	1489	#define ETH_DMA_TRANSMITPROCESS_READING ((uint32_t)0x00300000) /!< Running - reading the data from host memory /
vladvana	0:23d1f73bf130	1490	#define ETH_DMA_TRANSMITPROCESS_SUSPENDED ((uint32_t)0x00600000) /!< Suspended - Tx Descriptor unavailable /
vladvana	0:23d1f73bf130	1491	#define ETH_DMA_TRANSMITPROCESS_CLOSING ((uint32_t)0x00700000) /!< Running - closing Rx descriptor /
vladvana	0:23d1f73bf130	1492
vladvana	0:23d1f73bf130	1493	/**
vladvana	0:23d1f73bf130	1494	* @}
vladvana	0:23d1f73bf130	1495	*/
vladvana	0:23d1f73bf130	1496
vladvana	0:23d1f73bf130	1497
vladvana	0:23d1f73bf130	1498	/** @defgroup ETH_DMA_receive_process_state ETH DMA receive process state
vladvana	0:23d1f73bf130	1499	* @{
vladvana	0:23d1f73bf130	1500	*/
vladvana	0:23d1f73bf130	1501	#define ETH_DMA_RECEIVEPROCESS_STOPPED ((uint32_t)0x00000000) /!< Stopped - Reset or Stop Rx Command issued /
vladvana	0:23d1f73bf130	1502	#define ETH_DMA_RECEIVEPROCESS_FETCHING ((uint32_t)0x00020000) /!< Running - fetching the Rx descriptor /
vladvana	0:23d1f73bf130	1503	#define ETH_DMA_RECEIVEPROCESS_WAITING ((uint32_t)0x00060000) /!< Running - waiting for packet /
vladvana	0:23d1f73bf130	1504	#define ETH_DMA_RECEIVEPROCESS_SUSPENDED ((uint32_t)0x00080000) /!< Suspended - Rx Descriptor unavailable /
vladvana	0:23d1f73bf130	1505	#define ETH_DMA_RECEIVEPROCESS_CLOSING ((uint32_t)0x000A0000) /!< Running - closing descriptor /
vladvana	0:23d1f73bf130	1506	#define ETH_DMA_RECEIVEPROCESS_QUEUING ((uint32_t)0x000E0000) /!< Running - queuing the receive frame into host memory /
vladvana	0:23d1f73bf130	1507
vladvana	0:23d1f73bf130	1508	/**
vladvana	0:23d1f73bf130	1509	* @}
vladvana	0:23d1f73bf130	1510	*/
vladvana	0:23d1f73bf130	1511
vladvana	0:23d1f73bf130	1512	/** @defgroup ETH_DMA_overflow ETH DMA overflow
vladvana	0:23d1f73bf130	1513	* @{
vladvana	0:23d1f73bf130	1514	*/
vladvana	0:23d1f73bf130	1515	#define ETH_DMA_OVERFLOW_RXFIFOCOUNTER ((uint32_t)0x10000000) /!< Overflow bit for FIFO overflow counter /
vladvana	0:23d1f73bf130	1516	#define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER ((uint32_t)0x00010000) /!< Overflow bit for missed frame counter /
vladvana	0:23d1f73bf130	1517
vladvana	0:23d1f73bf130	1518	/**
vladvana	0:23d1f73bf130	1519	* @}
vladvana	0:23d1f73bf130	1520	*/
vladvana	0:23d1f73bf130	1521
vladvana	0:23d1f73bf130	1522	/** @defgroup ETH_EXTI_LINE_WAKEUP ETH EXTI LINE WAKEUP
vladvana	0:23d1f73bf130	1523	* @{
vladvana	0:23d1f73bf130	1524	*/
vladvana	0:23d1f73bf130	1525	#define ETH_EXTI_LINE_WAKEUP ((uint32_t)0x00080000) /!< External interrupt line 19 Connected to the ETH EXTI Line /
vladvana	0:23d1f73bf130	1526
vladvana	0:23d1f73bf130	1527	/**
vladvana	0:23d1f73bf130	1528	* @}
vladvana	0:23d1f73bf130	1529	*/
vladvana	0:23d1f73bf130	1530
vladvana	0:23d1f73bf130	1531	/**
vladvana	0:23d1f73bf130	1532	* @}
vladvana	0:23d1f73bf130	1533	*/
vladvana	0:23d1f73bf130	1534
vladvana	0:23d1f73bf130	1535	/* Exported macro ------------------------------------------------------------*/
vladvana	0:23d1f73bf130	1536	/** @defgroup ETH_Exported_Macros ETH Exported Macros
vladvana	0:23d1f73bf130	1537	* @brief macros to handle interrupts and specific clock configurations
vladvana	0:23d1f73bf130	1538	* @{
vladvana	0:23d1f73bf130	1539	*/
vladvana	0:23d1f73bf130	1540
vladvana	0:23d1f73bf130	1541	/** @brief Reset ETH handle state
vladvana	0:23d1f73bf130	1542	* @param __HANDLE__: specifies the ETH handle.
vladvana	0:23d1f73bf130	1543	* @retval None
vladvana	0:23d1f73bf130	1544	*/
vladvana	0:23d1f73bf130	1545	#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET)
vladvana	0:23d1f73bf130	1546
vladvana	0:23d1f73bf130	1547	/**
vladvana	0:23d1f73bf130	1548	* @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not.
vladvana	0:23d1f73bf130	1549	* @param __HANDLE__: ETH Handle
vladvana	0:23d1f73bf130	1550	* @param __FLAG__: specifies the flag of TDES0 to check .
vladvana	0:23d1f73bf130	1551	* @retval the ETH_DMATxDescFlag (SET or RESET).
vladvana	0:23d1f73bf130	1552	*/
vladvana	0:23d1f73bf130	1553	#define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__))
vladvana	0:23d1f73bf130	1554
vladvana	0:23d1f73bf130	1555	/**
vladvana	0:23d1f73bf130	1556	* @brief Checks whether the specified ETHERNET DMA Rx Desc flag is set or not.
vladvana	0:23d1f73bf130	1557	* @param __HANDLE__: ETH Handle
vladvana	0:23d1f73bf130	1558	* @param __FLAG__: specifies the flag of RDES0 to check.
vladvana	0:23d1f73bf130	1559	* @retval the ETH_DMATxDescFlag (SET or RESET).
vladvana	0:23d1f73bf130	1560	*/
vladvana	0:23d1f73bf130	1561	#define __HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__))
vladvana	0:23d1f73bf130	1562
vladvana	0:23d1f73bf130	1563	/**
vladvana	0:23d1f73bf130	1564	* @brief Enables the specified DMA Rx Desc receive interrupt.
vladvana	0:23d1f73bf130	1565	* @param __HANDLE__: ETH Handle
vladvana	0:23d1f73bf130	1566	* @retval None
vladvana	0:23d1f73bf130	1567	*/
vladvana	0:23d1f73bf130	1568	#define __HAL_ETH_DMARXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DIC))
vladvana	0:23d1f73bf130	1569
vladvana	0:23d1f73bf130	1570	/**
vladvana	0:23d1f73bf130	1571	* @brief Disables the specified DMA Rx Desc receive interrupt.
vladvana	0:23d1f73bf130	1572	* @param __HANDLE__: ETH Handle
vladvana	0:23d1f73bf130	1573	* @retval None
vladvana	0:23d1f73bf130	1574	*/
vladvana	0:23d1f73bf130	1575	#define __HAL_ETH_DMARXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize \|= ETH_DMARXDESC_DIC)
vladvana	0:23d1f73bf130	1576
vladvana	0:23d1f73bf130	1577	/**
vladvana	0:23d1f73bf130	1578	* @brief Set the specified DMA Rx Desc Own bit.
vladvana	0:23d1f73bf130	1579	* @param __HANDLE__: ETH Handle
vladvana	0:23d1f73bf130	1580	* @retval None
vladvana	0:23d1f73bf130	1581	*/
vladvana	0:23d1f73bf130	1582	#define __HAL_ETH_DMARXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->RxDesc->Status \|= ETH_DMARXDESC_OWN)
vladvana	0:23d1f73bf130	1583
vladvana	0:23d1f73bf130	1584	/**
vladvana	0:23d1f73bf130	1585	* @brief Returns the specified ETHERNET DMA Tx Desc collision count.
vladvana	0:23d1f73bf130	1586	* @param __HANDLE__: ETH Handle
vladvana	0:23d1f73bf130	1587	* @retval The Transmit descriptor collision counter value.
vladvana	0:23d1f73bf130	1588	*/
vladvana	0:23d1f73bf130	1589	#define __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT(__HANDLE__) (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT)
vladvana	0:23d1f73bf130	1590
vladvana	0:23d1f73bf130	1591	/**
vladvana	0:23d1f73bf130	1592	* @brief Set the specified DMA Tx Desc Own bit.
vladvana	0:23d1f73bf130	1593	* @param __HANDLE__: ETH Handle
vladvana	0:23d1f73bf130	1594	* @retval None
vladvana	0:23d1f73bf130	1595	*/
vladvana	0:23d1f73bf130	1596	#define __HAL_ETH_DMATXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->TxDesc->Status \|= ETH_DMATXDESC_OWN)
vladvana	0:23d1f73bf130	1597
vladvana	0:23d1f73bf130	1598	/**
vladvana	0:23d1f73bf130	1599	* @brief Enables the specified DMA Tx Desc Transmit interrupt.
vladvana	0:23d1f73bf130	1600	* @param __HANDLE__: ETH Handle
vladvana	0:23d1f73bf130	1601	* @retval None
vladvana	0:23d1f73bf130	1602	*/
vladvana	0:23d1f73bf130	1603	#define __HAL_ETH_DMATXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status \|= ETH_DMATXDESC_IC)
vladvana	0:23d1f73bf130	1604
vladvana	0:23d1f73bf130	1605	/**
vladvana	0:23d1f73bf130	1606	* @brief Disables the specified DMA Tx Desc Transmit interrupt.
vladvana	0:23d1f73bf130	1607	* @param __HANDLE__: ETH Handle
vladvana	0:23d1f73bf130	1608	* @retval None
vladvana	0:23d1f73bf130	1609	*/
vladvana	0:23d1f73bf130	1610	#define __HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC)
vladvana	0:23d1f73bf130	1611
vladvana	0:23d1f73bf130	1612	/**
vladvana	0:23d1f73bf130	1613	* @brief Selects the specified ETHERNET DMA Tx Desc Checksum Insertion.
vladvana	0:23d1f73bf130	1614	* @param __HANDLE__: ETH Handle
vladvana	0:23d1f73bf130	1615	* @param __CHECKSUM__: specifies is the DMA Tx desc checksum insertion.
vladvana	0:23d1f73bf130	1616	* This parameter can be one of the following values:
vladvana	0:23d1f73bf130	1617	* @arg ETH_DMATXDESC_CHECKSUMBYPASS : Checksum bypass
vladvana	0:23d1f73bf130	1618	* @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER : IPv4 header checksum
vladvana	0:23d1f73bf130	1619	* @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present
vladvana	0:23d1f73bf130	1620	* @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : TCP/UDP/ICMP checksum fully in hardware including pseudo header
vladvana	0:23d1f73bf130	1621	* @retval None
vladvana	0:23d1f73bf130	1622	*/
vladvana	0:23d1f73bf130	1623	#define __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION(__HANDLE__, __CHECKSUM__) ((__HANDLE__)->TxDesc->Status \|= (__CHECKSUM__))
vladvana	0:23d1f73bf130	1624
vladvana	0:23d1f73bf130	1625	/**
vladvana	0:23d1f73bf130	1626	* @brief Enables the DMA Tx Desc CRC.
vladvana	0:23d1f73bf130	1627	* @param __HANDLE__: ETH Handle
vladvana	0:23d1f73bf130	1628	* @retval None
vladvana	0:23d1f73bf130	1629	*/
vladvana	0:23d1f73bf130	1630	#define __HAL_ETH_DMATXDESC_CRC_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC)
vladvana	0:23d1f73bf130	1631
vladvana	0:23d1f73bf130	1632	/**
vladvana	0:23d1f73bf130	1633	* @brief Disables the DMA Tx Desc CRC.
vladvana	0:23d1f73bf130	1634	* @param __HANDLE__: ETH Handle
vladvana	0:23d1f73bf130	1635	* @retval None
vladvana	0:23d1f73bf130	1636	*/
vladvana	0:23d1f73bf130	1637	#define __HAL_ETH_DMATXDESC_CRC_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status \|= ETH_DMATXDESC_DC)
vladvana	0:23d1f73bf130	1638
vladvana	0:23d1f73bf130	1639	/**
vladvana	0:23d1f73bf130	1640	* @brief Enables the DMA Tx Desc padding for frame shorter than 64 bytes.
vladvana	0:23d1f73bf130	1641	* @param __HANDLE__: ETH Handle
vladvana	0:23d1f73bf130	1642	* @retval None
vladvana	0:23d1f73bf130	1643	*/
vladvana	0:23d1f73bf130	1644	#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP)
vladvana	0:23d1f73bf130	1645
vladvana	0:23d1f73bf130	1646	/**
vladvana	0:23d1f73bf130	1647	* @brief Disables the DMA Tx Desc padding for frame shorter than 64 bytes.
vladvana	0:23d1f73bf130	1648	* @param __HANDLE__: ETH Handle
vladvana	0:23d1f73bf130	1649	* @retval None
vladvana	0:23d1f73bf130	1650	*/
vladvana	0:23d1f73bf130	1651	#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status \|= ETH_DMATXDESC_DP)
vladvana	0:23d1f73bf130	1652
vladvana	0:23d1f73bf130	1653	/**
vladvana	0:23d1f73bf130	1654	* @brief Enables the specified ETHERNET MAC interrupts.
vladvana	0:23d1f73bf130	1655	* @param __HANDLE__ : ETH Handle
vladvana	0:23d1f73bf130	1656	* @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
vladvana	0:23d1f73bf130	1657	* enabled or disabled.
vladvana	0:23d1f73bf130	1658	* This parameter can be any combination of the following values:
vladvana	0:23d1f73bf130	1659	* @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
vladvana	0:23d1f73bf130	1660	* @arg ETH_MAC_IT_PMT : PMT interrupt
vladvana	0:23d1f73bf130	1661	* @retval None
vladvana	0:23d1f73bf130	1662	*/
vladvana	0:23d1f73bf130	1663	#define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR \|= (__INTERRUPT__))
vladvana	0:23d1f73bf130	1664
vladvana	0:23d1f73bf130	1665	/**
vladvana	0:23d1f73bf130	1666	* @brief Disables the specified ETHERNET MAC interrupts.
vladvana	0:23d1f73bf130	1667	* @param __HANDLE__ : ETH Handle
vladvana	0:23d1f73bf130	1668	* @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
vladvana	0:23d1f73bf130	1669	* enabled or disabled.
vladvana	0:23d1f73bf130	1670	* This parameter can be any combination of the following values:
vladvana	0:23d1f73bf130	1671	* @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
vladvana	0:23d1f73bf130	1672	* @arg ETH_MAC_IT_PMT : PMT interrupt
vladvana	0:23d1f73bf130	1673	* @retval None
vladvana	0:23d1f73bf130	1674	*/
vladvana	0:23d1f73bf130	1675	#define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR &= ~(__INTERRUPT__))
vladvana	0:23d1f73bf130	1676
vladvana	0:23d1f73bf130	1677	/**
vladvana	0:23d1f73bf130	1678	* @brief Initiate a Pause Control Frame (Full-duplex only).
vladvana	0:23d1f73bf130	1679	* @param __HANDLE__: ETH Handle
vladvana	0:23d1f73bf130	1680	* @retval None
vladvana	0:23d1f73bf130	1681	*/
vladvana	0:23d1f73bf130	1682	#define __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME(__HANDLE__) ((__HANDLE__)->Instance->MACFCR \|= ETH_MACFCR_FCBBPA)
vladvana	0:23d1f73bf130	1683
vladvana	0:23d1f73bf130	1684	/**
vladvana	0:23d1f73bf130	1685	* @brief Checks whether the ETHERNET flow control busy bit is set or not.
vladvana	0:23d1f73bf130	1686	* @param __HANDLE__: ETH Handle
vladvana	0:23d1f73bf130	1687	* @retval The new state of flow control busy status bit (SET or RESET).
vladvana	0:23d1f73bf130	1688	*/
vladvana	0:23d1f73bf130	1689	#define __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS(__HANDLE__) (((__HANDLE__)->Instance->MACFCR & ETH_MACFCR_FCBBPA) == ETH_MACFCR_FCBBPA)
vladvana	0:23d1f73bf130	1690
vladvana	0:23d1f73bf130	1691	/**
vladvana	0:23d1f73bf130	1692	* @brief Enables the MAC Back Pressure operation activation (Half-duplex only).
vladvana	0:23d1f73bf130	1693	* @param __HANDLE__: ETH Handle
vladvana	0:23d1f73bf130	1694	* @retval None
vladvana	0:23d1f73bf130	1695	*/
vladvana	0:23d1f73bf130	1696	#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR \|= ETH_MACFCR_FCBBPA)
vladvana	0:23d1f73bf130	1697
vladvana	0:23d1f73bf130	1698	/**
vladvana	0:23d1f73bf130	1699	* @brief Disables the MAC BackPressure operation activation (Half-duplex only).
vladvana	0:23d1f73bf130	1700	* @param __HANDLE__: ETH Handle
vladvana	0:23d1f73bf130	1701	* @retval None
vladvana	0:23d1f73bf130	1702	*/
vladvana	0:23d1f73bf130	1703	#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA)
vladvana	0:23d1f73bf130	1704
vladvana	0:23d1f73bf130	1705	/**
vladvana	0:23d1f73bf130	1706	* @brief Checks whether the specified ETHERNET MAC flag is set or not.
vladvana	0:23d1f73bf130	1707	* @param __HANDLE__: ETH Handle
vladvana	0:23d1f73bf130	1708	* @param __FLAG__: specifies the flag to check.
vladvana	0:23d1f73bf130	1709	* This parameter can be one of the following values:
vladvana	0:23d1f73bf130	1710	* @arg ETH_MAC_FLAG_TST : Time stamp trigger flag
vladvana	0:23d1f73bf130	1711	* @arg ETH_MAC_FLAG_MMCT : MMC transmit flag
vladvana	0:23d1f73bf130	1712	* @arg ETH_MAC_FLAG_MMCR : MMC receive flag
vladvana	0:23d1f73bf130	1713	* @arg ETH_MAC_FLAG_MMC : MMC flag
vladvana	0:23d1f73bf130	1714	* @arg ETH_MAC_FLAG_PMT : PMT flag
vladvana	0:23d1f73bf130	1715	* @retval The state of ETHERNET MAC flag.
vladvana	0:23d1f73bf130	1716	*/
vladvana	0:23d1f73bf130	1717	#define __HAL_ETH_MAC_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__))
vladvana	0:23d1f73bf130	1718
vladvana	0:23d1f73bf130	1719	/**
vladvana	0:23d1f73bf130	1720	* @brief Enables the specified ETHERNET DMA interrupts.
vladvana	0:23d1f73bf130	1721	* @param __HANDLE__ : ETH Handle
vladvana	0:23d1f73bf130	1722	* @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
vladvana	0:23d1f73bf130	1723	* enabled @ref ETH_DMA_Interrupts
vladvana	0:23d1f73bf130	1724	* @retval None
vladvana	0:23d1f73bf130	1725	*/
vladvana	0:23d1f73bf130	1726	#define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER \|= (__INTERRUPT__))
vladvana	0:23d1f73bf130	1727
vladvana	0:23d1f73bf130	1728	/**
vladvana	0:23d1f73bf130	1729	* @brief Disables the specified ETHERNET DMA interrupts.
vladvana	0:23d1f73bf130	1730	* @param __HANDLE__ : ETH Handle
vladvana	0:23d1f73bf130	1731	* @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
vladvana	0:23d1f73bf130	1732	* disabled. @ref ETH_DMA_Interrupts
vladvana	0:23d1f73bf130	1733	* @retval None
vladvana	0:23d1f73bf130	1734	*/
vladvana	0:23d1f73bf130	1735	#define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER &= ~(__INTERRUPT__))
vladvana	0:23d1f73bf130	1736
vladvana	0:23d1f73bf130	1737	/**
vladvana	0:23d1f73bf130	1738	* @brief Clears the ETHERNET DMA IT pending bit.
vladvana	0:23d1f73bf130	1739	* @param __HANDLE__ : ETH Handle
vladvana	0:23d1f73bf130	1740	* @param __INTERRUPT__: specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts
vladvana	0:23d1f73bf130	1741	* @retval None
vladvana	0:23d1f73bf130	1742	*/
vladvana	0:23d1f73bf130	1743	#define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__))
vladvana	0:23d1f73bf130	1744
vladvana	0:23d1f73bf130	1745	/**
vladvana	0:23d1f73bf130	1746	* @brief Checks whether the specified ETHERNET DMA flag is set or not.
vladvana	0:23d1f73bf130	1747	* @param __HANDLE__: ETH Handle
vladvana	0:23d1f73bf130	1748	* @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Flags
vladvana	0:23d1f73bf130	1749	* @retval The new state of ETH_DMA_FLAG (SET or RESET).
vladvana	0:23d1f73bf130	1750	*/
vladvana	0:23d1f73bf130	1751	#define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__))
vladvana	0:23d1f73bf130	1752
vladvana	0:23d1f73bf130	1753	/**
vladvana	0:23d1f73bf130	1754	* @brief Checks whether the specified ETHERNET DMA flag is set or not.
vladvana	0:23d1f73bf130	1755	* @param __HANDLE__: ETH Handle
vladvana	0:23d1f73bf130	1756	* @param __FLAG__: specifies the flag to clear. @ref ETH_DMA_Flags
vladvana	0:23d1f73bf130	1757	* @retval The new state of ETH_DMA_FLAG (SET or RESET).
vladvana	0:23d1f73bf130	1758	*/
vladvana	0:23d1f73bf130	1759	#define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR = (__FLAG__))
vladvana	0:23d1f73bf130	1760
vladvana	0:23d1f73bf130	1761	/**
vladvana	0:23d1f73bf130	1762	* @brief Checks whether the specified ETHERNET DMA overflow flag is set or not.
vladvana	0:23d1f73bf130	1763	* @param __HANDLE__: ETH Handle
vladvana	0:23d1f73bf130	1764	* @param __OVERFLOW__: specifies the DMA overflow flag to check.
vladvana	0:23d1f73bf130	1765	* This parameter can be one of the following values:
vladvana	0:23d1f73bf130	1766	* @arg ETH_DMA_OVERFLOW_RXFIFOCOUNTER : Overflow for FIFO Overflows Counter
vladvana	0:23d1f73bf130	1767	* @arg ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER : Overflow for Buffer Unavailable Missed Frame Counter
vladvana	0:23d1f73bf130	1768	* @retval The state of ETHERNET DMA overflow Flag (SET or RESET).
vladvana	0:23d1f73bf130	1769	*/
vladvana	0:23d1f73bf130	1770	#define __HAL_ETH_GET_DMA_OVERFLOW_STATUS(__HANDLE__, __OVERFLOW__) (((__HANDLE__)->Instance->DMAMFBOCR & (__OVERFLOW__)) == (__OVERFLOW__))
vladvana	0:23d1f73bf130	1771
vladvana	0:23d1f73bf130	1772	/**
vladvana	0:23d1f73bf130	1773	* @brief Set the DMA Receive status watchdog timer register value
vladvana	0:23d1f73bf130	1774	* @param __HANDLE__: ETH Handle
vladvana	0:23d1f73bf130	1775	* @param __VALUE__: DMA Receive status watchdog timer register value
vladvana	0:23d1f73bf130	1776	* @retval None
vladvana	0:23d1f73bf130	1777	*/
vladvana	0:23d1f73bf130	1778	#define __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__))
vladvana	0:23d1f73bf130	1779
vladvana	0:23d1f73bf130	1780	/**
vladvana	0:23d1f73bf130	1781	* @brief Enables any unicast packet filtered by the MAC address
vladvana	0:23d1f73bf130	1782	* recognition to be a wake-up frame.
vladvana	0:23d1f73bf130	1783	* @param __HANDLE__: ETH Handle.
vladvana	0:23d1f73bf130	1784	* @retval None
vladvana	0:23d1f73bf130	1785	*/
vladvana	0:23d1f73bf130	1786	#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR \|= ETH_MACPMTCSR_GU)
vladvana	0:23d1f73bf130	1787
vladvana	0:23d1f73bf130	1788	/**
vladvana	0:23d1f73bf130	1789	* @brief Disables any unicast packet filtered by the MAC address
vladvana	0:23d1f73bf130	1790	* recognition to be a wake-up frame.
vladvana	0:23d1f73bf130	1791	* @param __HANDLE__: ETH Handle.
vladvana	0:23d1f73bf130	1792	* @retval None
vladvana	0:23d1f73bf130	1793	*/
vladvana	0:23d1f73bf130	1794	#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU)
vladvana	0:23d1f73bf130	1795
vladvana	0:23d1f73bf130	1796	/**
vladvana	0:23d1f73bf130	1797	* @brief Enables the MAC Wake-Up Frame Detection.
vladvana	0:23d1f73bf130	1798	* @param __HANDLE__: ETH Handle.
vladvana	0:23d1f73bf130	1799	* @retval None
vladvana	0:23d1f73bf130	1800	*/
vladvana	0:23d1f73bf130	1801	#define __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR \|= ETH_MACPMTCSR_WFE)
vladvana	0:23d1f73bf130	1802
vladvana	0:23d1f73bf130	1803	/**
vladvana	0:23d1f73bf130	1804	* @brief Disables the MAC Wake-Up Frame Detection.
vladvana	0:23d1f73bf130	1805	* @param __HANDLE__: ETH Handle.
vladvana	0:23d1f73bf130	1806	* @retval None
vladvana	0:23d1f73bf130	1807	*/
vladvana	0:23d1f73bf130	1808	#define __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
vladvana	0:23d1f73bf130	1809
vladvana	0:23d1f73bf130	1810	/**
vladvana	0:23d1f73bf130	1811	* @brief Enables the MAC Magic Packet Detection.
vladvana	0:23d1f73bf130	1812	* @param __HANDLE__: ETH Handle.
vladvana	0:23d1f73bf130	1813	* @retval None
vladvana	0:23d1f73bf130	1814	*/
vladvana	0:23d1f73bf130	1815	#define __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR \|= ETH_MACPMTCSR_MPE)
vladvana	0:23d1f73bf130	1816
vladvana	0:23d1f73bf130	1817	/**
vladvana	0:23d1f73bf130	1818	* @brief Disables the MAC Magic Packet Detection.
vladvana	0:23d1f73bf130	1819	* @param __HANDLE__: ETH Handle.
vladvana	0:23d1f73bf130	1820	* @retval None
vladvana	0:23d1f73bf130	1821	*/
vladvana	0:23d1f73bf130	1822	#define __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
vladvana	0:23d1f73bf130	1823
vladvana	0:23d1f73bf130	1824	/**
vladvana	0:23d1f73bf130	1825	* @brief Enables the MAC Power Down.
vladvana	0:23d1f73bf130	1826	* @param __HANDLE__: ETH Handle
vladvana	0:23d1f73bf130	1827	* @retval None
vladvana	0:23d1f73bf130	1828	*/
vladvana	0:23d1f73bf130	1829	#define __HAL_ETH_POWER_DOWN_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR \|= ETH_MACPMTCSR_PD)
vladvana	0:23d1f73bf130	1830
vladvana	0:23d1f73bf130	1831	/**
vladvana	0:23d1f73bf130	1832	* @brief Disables the MAC Power Down.
vladvana	0:23d1f73bf130	1833	* @param __HANDLE__: ETH Handle
vladvana	0:23d1f73bf130	1834	* @retval None
vladvana	0:23d1f73bf130	1835	*/
vladvana	0:23d1f73bf130	1836	#define __HAL_ETH_POWER_DOWN_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD)
vladvana	0:23d1f73bf130	1837
vladvana	0:23d1f73bf130	1838	/**
vladvana	0:23d1f73bf130	1839	* @brief Checks whether the specified ETHERNET PMT flag is set or not.
vladvana	0:23d1f73bf130	1840	* @param __HANDLE__: ETH Handle.
vladvana	0:23d1f73bf130	1841	* @param __FLAG__: specifies the flag to check.
vladvana	0:23d1f73bf130	1842	* This parameter can be one of the following values:
vladvana	0:23d1f73bf130	1843	* @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset
vladvana	0:23d1f73bf130	1844	* @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received
vladvana	0:23d1f73bf130	1845	* @arg ETH_PMT_FLAG_MPR : Magic Packet Received
vladvana	0:23d1f73bf130	1846	* @retval The new state of ETHERNET PMT Flag (SET or RESET).
vladvana	0:23d1f73bf130	1847	*/
vladvana	0:23d1f73bf130	1848	#define __HAL_ETH_GET_PMT_FLAG_STATUS(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACPMTCSR &( __FLAG__)) == ( __FLAG__))
vladvana	0:23d1f73bf130	1849
vladvana	0:23d1f73bf130	1850	/**
vladvana	0:23d1f73bf130	1851	* @brief Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16)
vladvana	0:23d1f73bf130	1852	* @param __HANDLE__: ETH Handle.
vladvana	0:23d1f73bf130	1853	* @retval None
vladvana	0:23d1f73bf130	1854	*/
vladvana	0:23d1f73bf130	1855	#define __HAL_ETH_MMC_COUNTER_FULL_PRESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR \|= (ETH_MMCCR_MCFHP \| ETH_MMCCR_MCP))
vladvana	0:23d1f73bf130	1856
vladvana	0:23d1f73bf130	1857	/**
vladvana	0:23d1f73bf130	1858	* @brief Preset and Initialize the MMC counters to almost-half value: 0x7FFF_FFF0 (half - 16)
vladvana	0:23d1f73bf130	1859	* @param __HANDLE__: ETH Handle.
vladvana	0:23d1f73bf130	1860	* @retval None
vladvana	0:23d1f73bf130	1861	*/
vladvana	0:23d1f73bf130	1862	#define __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__) do{(__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCFHP;\
vladvana	0:23d1f73bf130	1863	(__HANDLE__)->Instance->MMCCR \|= ETH_MMCCR_MCP;} while (0)
vladvana	0:23d1f73bf130	1864
vladvana	0:23d1f73bf130	1865	/**
vladvana	0:23d1f73bf130	1866	* @brief Enables the MMC Counter Freeze.
vladvana	0:23d1f73bf130	1867	* @param __HANDLE__: ETH Handle.
vladvana	0:23d1f73bf130	1868	* @retval None
vladvana	0:23d1f73bf130	1869	*/
vladvana	0:23d1f73bf130	1870	#define __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR \|= ETH_MMCCR_MCF)
vladvana	0:23d1f73bf130	1871
vladvana	0:23d1f73bf130	1872	/**
vladvana	0:23d1f73bf130	1873	* @brief Disables the MMC Counter Freeze.
vladvana	0:23d1f73bf130	1874	* @param __HANDLE__: ETH Handle.
vladvana	0:23d1f73bf130	1875	* @retval None
vladvana	0:23d1f73bf130	1876	*/
vladvana	0:23d1f73bf130	1877	#define __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCF)
vladvana	0:23d1f73bf130	1878
vladvana	0:23d1f73bf130	1879	/**
vladvana	0:23d1f73bf130	1880	* @brief Enables the MMC Reset On Read.
vladvana	0:23d1f73bf130	1881	* @param __HANDLE__: ETH Handle.
vladvana	0:23d1f73bf130	1882	* @retval None
vladvana	0:23d1f73bf130	1883	*/
vladvana	0:23d1f73bf130	1884	#define __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR \|= ETH_MMCCR_ROR)
vladvana	0:23d1f73bf130	1885
vladvana	0:23d1f73bf130	1886	/**
vladvana	0:23d1f73bf130	1887	* @brief Disables the MMC Reset On Read.
vladvana	0:23d1f73bf130	1888	* @param __HANDLE__: ETH Handle.
vladvana	0:23d1f73bf130	1889	* @retval None
vladvana	0:23d1f73bf130	1890	*/
vladvana	0:23d1f73bf130	1891	#define __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_ROR)
vladvana	0:23d1f73bf130	1892
vladvana	0:23d1f73bf130	1893	/**
vladvana	0:23d1f73bf130	1894	* @brief Enables the MMC Counter Stop Rollover.
vladvana	0:23d1f73bf130	1895	* @param __HANDLE__: ETH Handle.
vladvana	0:23d1f73bf130	1896	* @retval None
vladvana	0:23d1f73bf130	1897	*/
vladvana	0:23d1f73bf130	1898	#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_CSR)
vladvana	0:23d1f73bf130	1899
vladvana	0:23d1f73bf130	1900	/**
vladvana	0:23d1f73bf130	1901	* @brief Disables the MMC Counter Stop Rollover.
vladvana	0:23d1f73bf130	1902	* @param __HANDLE__: ETH Handle.
vladvana	0:23d1f73bf130	1903	* @retval None
vladvana	0:23d1f73bf130	1904	*/
vladvana	0:23d1f73bf130	1905	#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR \|= ETH_MMCCR_CSR)
vladvana	0:23d1f73bf130	1906
vladvana	0:23d1f73bf130	1907	/**
vladvana	0:23d1f73bf130	1908	* @brief Resets the MMC Counters.
vladvana	0:23d1f73bf130	1909	* @param __HANDLE__: ETH Handle.
vladvana	0:23d1f73bf130	1910	* @retval None
vladvana	0:23d1f73bf130	1911	*/
vladvana	0:23d1f73bf130	1912	#define __HAL_ETH_MMC_COUNTERS_RESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR \|= ETH_MMCCR_CR)
vladvana	0:23d1f73bf130	1913
vladvana	0:23d1f73bf130	1914	/**
vladvana	0:23d1f73bf130	1915	* @brief Enables the specified ETHERNET MMC Rx interrupts.
vladvana	0:23d1f73bf130	1916	* @param __HANDLE__: ETH Handle.
vladvana	0:23d1f73bf130	1917	* @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
vladvana	0:23d1f73bf130	1918	* This parameter can be one of the following values:
vladvana	0:23d1f73bf130	1919	* @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
vladvana	0:23d1f73bf130	1920	* @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
vladvana	0:23d1f73bf130	1921	* @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
vladvana	0:23d1f73bf130	1922	* @retval None
vladvana	0:23d1f73bf130	1923	*/
vladvana	0:23d1f73bf130	1924	#define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFF)
vladvana	0:23d1f73bf130	1925	/**
vladvana	0:23d1f73bf130	1926	* @brief Disables the specified ETHERNET MMC Rx interrupts.
vladvana	0:23d1f73bf130	1927	* @param __HANDLE__: ETH Handle.
vladvana	0:23d1f73bf130	1928	* @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
vladvana	0:23d1f73bf130	1929	* This parameter can be one of the following values:
vladvana	0:23d1f73bf130	1930	* @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
vladvana	0:23d1f73bf130	1931	* @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
vladvana	0:23d1f73bf130	1932	* @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
vladvana	0:23d1f73bf130	1933	* @retval None
vladvana	0:23d1f73bf130	1934	*/
vladvana	0:23d1f73bf130	1935	#define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR \|= ((__INTERRUPT__) & 0xEFFFFFFF)
vladvana	0:23d1f73bf130	1936	/**
vladvana	0:23d1f73bf130	1937	* @brief Enables the specified ETHERNET MMC Tx interrupts.
vladvana	0:23d1f73bf130	1938	* @param __HANDLE__: ETH Handle.
vladvana	0:23d1f73bf130	1939	* @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
vladvana	0:23d1f73bf130	1940	* This parameter can be one of the following values:
vladvana	0:23d1f73bf130	1941	* @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
vladvana	0:23d1f73bf130	1942	* @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
vladvana	0:23d1f73bf130	1943	* @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
vladvana	0:23d1f73bf130	1944	* @retval None
vladvana	0:23d1f73bf130	1945	*/
vladvana	0:23d1f73bf130	1946	#define __HAL_ETH_MMC_TX_IT_ENABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR &= ~ (__INTERRUPT__))
vladvana	0:23d1f73bf130	1947
vladvana	0:23d1f73bf130	1948	/**
vladvana	0:23d1f73bf130	1949	* @brief Disables the specified ETHERNET MMC Tx interrupts.
vladvana	0:23d1f73bf130	1950	* @param __HANDLE__: ETH Handle.
vladvana	0:23d1f73bf130	1951	* @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
vladvana	0:23d1f73bf130	1952	* This parameter can be one of the following values:
vladvana	0:23d1f73bf130	1953	* @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
vladvana	0:23d1f73bf130	1954	* @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
vladvana	0:23d1f73bf130	1955	* @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
vladvana	0:23d1f73bf130	1956	* @retval None
vladvana	0:23d1f73bf130	1957	*/
vladvana	0:23d1f73bf130	1958	#define __HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR \|= (__INTERRUPT__))
vladvana	0:23d1f73bf130	1959
vladvana	0:23d1f73bf130	1960	/**
vladvana	0:23d1f73bf130	1961	* @brief Enables the ETH External interrupt line.
vladvana	0:23d1f73bf130	1962	* @retval None
vladvana	0:23d1f73bf130	1963	*/
vladvana	0:23d1f73bf130	1964	#define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR \|= (ETH_EXTI_LINE_WAKEUP)
vladvana	0:23d1f73bf130	1965
vladvana	0:23d1f73bf130	1966	/**
vladvana	0:23d1f73bf130	1967	* @brief Disables the ETH External interrupt line.
vladvana	0:23d1f73bf130	1968	* @retval None
vladvana	0:23d1f73bf130	1969	*/
vladvana	0:23d1f73bf130	1970	#define __HAL_ETH_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(ETH_EXTI_LINE_WAKEUP)
vladvana	0:23d1f73bf130	1971
vladvana	0:23d1f73bf130	1972	/**
vladvana	0:23d1f73bf130	1973	* @brief Enable event on ETH External event line.
vladvana	0:23d1f73bf130	1974	* @retval None.
vladvana	0:23d1f73bf130	1975	*/
vladvana	0:23d1f73bf130	1976	#define __HAL_ETH_WAKEUP_EXTI_ENABLE_EVENT() EXTI->EMR \|= (ETH_EXTI_LINE_WAKEUP)
vladvana	0:23d1f73bf130	1977
vladvana	0:23d1f73bf130	1978	/**
vladvana	0:23d1f73bf130	1979	* @brief Disable event on ETH External event line
vladvana	0:23d1f73bf130	1980	* @retval None.
vladvana	0:23d1f73bf130	1981	*/
vladvana	0:23d1f73bf130	1982	#define __HAL_ETH_WAKEUP_EXTI_DISABLE_EVENT() EXTI->EMR &= ~(ETH_EXTI_LINE_WAKEUP)
vladvana	0:23d1f73bf130	1983
vladvana	0:23d1f73bf130	1984	/**
vladvana	0:23d1f73bf130	1985	* @brief Get flag of the ETH External interrupt line.
vladvana	0:23d1f73bf130	1986	* @retval None
vladvana	0:23d1f73bf130	1987	*/
vladvana	0:23d1f73bf130	1988	#define __HAL_ETH_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (ETH_EXTI_LINE_WAKEUP)
vladvana	0:23d1f73bf130	1989
vladvana	0:23d1f73bf130	1990	/**
vladvana	0:23d1f73bf130	1991	* @brief Clear flag of the ETH External interrupt line.
vladvana	0:23d1f73bf130	1992	* @retval None
vladvana	0:23d1f73bf130	1993	*/
vladvana	0:23d1f73bf130	1994	#define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (ETH_EXTI_LINE_WAKEUP)
vladvana	0:23d1f73bf130	1995
vladvana	0:23d1f73bf130	1996	/**
vladvana	0:23d1f73bf130	1997	* @brief Enables rising edge trigger to the ETH External interrupt line.
vladvana	0:23d1f73bf130	1998	* @retval None
vladvana	0:23d1f73bf130	1999	*/
vladvana	0:23d1f73bf130	2000	#define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER() EXTI->RTSR \|= ETH_EXTI_LINE_WAKEUP
vladvana	0:23d1f73bf130	2001
vladvana	0:23d1f73bf130	2002	/**
vladvana	0:23d1f73bf130	2003	* @brief Disables the rising edge trigger to the ETH External interrupt line.
vladvana	0:23d1f73bf130	2004	* @retval None
vladvana	0:23d1f73bf130	2005	*/
vladvana	0:23d1f73bf130	2006	#define __HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP)
vladvana	0:23d1f73bf130	2007
vladvana	0:23d1f73bf130	2008	/**
vladvana	0:23d1f73bf130	2009	* @brief Enables falling edge trigger to the ETH External interrupt line.
vladvana	0:23d1f73bf130	2010	* @retval None
vladvana	0:23d1f73bf130	2011	*/
vladvana	0:23d1f73bf130	2012	#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR \|= (ETH_EXTI_LINE_WAKEUP)
vladvana	0:23d1f73bf130	2013
vladvana	0:23d1f73bf130	2014	/**
vladvana	0:23d1f73bf130	2015	* @brief Disables falling edge trigger to the ETH External interrupt line.
vladvana	0:23d1f73bf130	2016	* @retval None
vladvana	0:23d1f73bf130	2017	*/
vladvana	0:23d1f73bf130	2018	#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP)
vladvana	0:23d1f73bf130	2019
vladvana	0:23d1f73bf130	2020
vladvana	0:23d1f73bf130	2021	/**
vladvana	0:23d1f73bf130	2022	* @brief Enables rising/falling edge trigger to the ETH External interrupt line.
vladvana	0:23d1f73bf130	2023	* @retval None
vladvana	0:23d1f73bf130	2024	*/
vladvana	0:23d1f73bf130	2025	#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER() EXTI->RTSR \|= ETH_EXTI_LINE_WAKEUP;\
vladvana	0:23d1f73bf130	2026	EXTI->FTSR \|= ETH_EXTI_LINE_WAKEUP
vladvana	0:23d1f73bf130	2027
vladvana	0:23d1f73bf130	2028	/**
vladvana	0:23d1f73bf130	2029	* @brief Disables rising/falling edge trigger to the ETH External interrupt line.
vladvana	0:23d1f73bf130	2030	* @retval None
vladvana	0:23d1f73bf130	2031	*/
vladvana	0:23d1f73bf130	2032	#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
vladvana	0:23d1f73bf130	2033	EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP)
vladvana	0:23d1f73bf130	2034
vladvana	0:23d1f73bf130	2035	/**
vladvana	0:23d1f73bf130	2036	* @brief Generate a Software interrupt on selected EXTI line.
vladvana	0:23d1f73bf130	2037	* @retval None.
vladvana	0:23d1f73bf130	2038	*/
vladvana	0:23d1f73bf130	2039	#define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT() EXTI->SWIER\|= ETH_EXTI_LINE_WAKEUP
vladvana	0:23d1f73bf130	2040
vladvana	0:23d1f73bf130	2041	/**
vladvana	0:23d1f73bf130	2042	* @}
vladvana	0:23d1f73bf130	2043	*/
vladvana	0:23d1f73bf130	2044
vladvana	0:23d1f73bf130	2045	/* Exported functions --------------------------------------------------------*/
vladvana	0:23d1f73bf130	2046
vladvana	0:23d1f73bf130	2047	/** @addtogroup ETH_Exported_Functions
vladvana	0:23d1f73bf130	2048	* @{
vladvana	0:23d1f73bf130	2049	*/
vladvana	0:23d1f73bf130	2050
vladvana	0:23d1f73bf130	2051	/* Initialization and de-initialization functions ****************************/
vladvana	0:23d1f73bf130	2052
vladvana	0:23d1f73bf130	2053	/** @addtogroup ETH_Exported_Functions_Group1
vladvana	0:23d1f73bf130	2054	* @{
vladvana	0:23d1f73bf130	2055	*/
vladvana	0:23d1f73bf130	2056
vladvana	0:23d1f73bf130	2057	HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth);
vladvana	0:23d1f73bf130	2058	HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth);
vladvana	0:23d1f73bf130	2059	void HAL_ETH_MspInit(ETH_HandleTypeDef *heth);
vladvana	0:23d1f73bf130	2060	void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth);
vladvana	0:23d1f73bf130	2061	HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef heth, ETH_DMADescTypeDef DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount);
vladvana	0:23d1f73bf130	2062	HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef heth, ETH_DMADescTypeDef DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount);
vladvana	0:23d1f73bf130	2063
vladvana	0:23d1f73bf130	2064	/**
vladvana	0:23d1f73bf130	2065	* @}
vladvana	0:23d1f73bf130	2066	*/
vladvana	0:23d1f73bf130	2067
vladvana	0:23d1f73bf130	2068	/* IO operation functions ****************************************************/
vladvana	0:23d1f73bf130	2069
vladvana	0:23d1f73bf130	2070	/** @addtogroup ETH_Exported_Functions_Group2
vladvana	0:23d1f73bf130	2071	* @{
vladvana	0:23d1f73bf130	2072	*/
vladvana	0:23d1f73bf130	2073	HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength);
vladvana	0:23d1f73bf130	2074	HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth);
vladvana	0:23d1f73bf130	2075	/* Communication with PHY functions*/
vladvana	0:23d1f73bf130	2076	HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef heth, uint16_t PHYReg, uint32_t RegValue);
vladvana	0:23d1f73bf130	2077	HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue);
vladvana	0:23d1f73bf130	2078	/* Non-Blocking mode: Interrupt */
vladvana	0:23d1f73bf130	2079	HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth);
vladvana	0:23d1f73bf130	2080	void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth);
vladvana	0:23d1f73bf130	2081	/* Callback in non blocking modes (Interrupt) */
vladvana	0:23d1f73bf130	2082	void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth);
vladvana	0:23d1f73bf130	2083	void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth);
vladvana	0:23d1f73bf130	2084	void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth);
vladvana	0:23d1f73bf130	2085
vladvana	0:23d1f73bf130	2086	/**
vladvana	0:23d1f73bf130	2087	* @}
vladvana	0:23d1f73bf130	2088	*/
vladvana	0:23d1f73bf130	2089
vladvana	0:23d1f73bf130	2090	/* Peripheral Control functions **********************************************/
vladvana	0:23d1f73bf130	2091
vladvana	0:23d1f73bf130	2092	/** @addtogroup ETH_Exported_Functions_Group3
vladvana	0:23d1f73bf130	2093	* @{
vladvana	0:23d1f73bf130	2094	*/
vladvana	0:23d1f73bf130	2095	HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth);
vladvana	0:23d1f73bf130	2096	HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth);
vladvana	0:23d1f73bf130	2097	HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef heth, ETH_MACInitTypeDef macconf);
vladvana	0:23d1f73bf130	2098	HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef heth, ETH_DMAInitTypeDef dmaconf);
vladvana	0:23d1f73bf130	2099	/**
vladvana	0:23d1f73bf130	2100	* @}
vladvana	0:23d1f73bf130	2101	*/
vladvana	0:23d1f73bf130	2102
vladvana	0:23d1f73bf130	2103	/* Peripheral State functions ************************************************/
vladvana	0:23d1f73bf130	2104
vladvana	0:23d1f73bf130	2105	/** @addtogroup ETH_Exported_Functions_Group4
vladvana	0:23d1f73bf130	2106	* @{
vladvana	0:23d1f73bf130	2107	*/
vladvana	0:23d1f73bf130	2108	HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth);
vladvana	0:23d1f73bf130	2109
vladvana	0:23d1f73bf130	2110	/**
vladvana	0:23d1f73bf130	2111	* @}
vladvana	0:23d1f73bf130	2112	*/
vladvana	0:23d1f73bf130	2113
vladvana	0:23d1f73bf130	2114	/**
vladvana	0:23d1f73bf130	2115	* @}
vladvana	0:23d1f73bf130	2116	*/
vladvana	0:23d1f73bf130	2117
vladvana	0:23d1f73bf130	2118	/**
vladvana	0:23d1f73bf130	2119	* @}
vladvana	0:23d1f73bf130	2120	*/
vladvana	0:23d1f73bf130	2121
vladvana	0:23d1f73bf130	2122	#endif /* STM32F107xC */
vladvana	0:23d1f73bf130	2123	/**
vladvana	0:23d1f73bf130	2124	* @}
vladvana	0:23d1f73bf130	2125	*/
vladvana	0:23d1f73bf130	2126
vladvana	0:23d1f73bf130	2127	#ifdef __cplusplus
vladvana	0:23d1f73bf130	2128	}
vladvana	0:23d1f73bf130	2129	#endif
vladvana	0:23d1f73bf130	2130
vladvana	0:23d1f73bf130	2131	#endif /* __STM32F1xx_HAL_ETH_H */
vladvana	0:23d1f73bf130	2132
vladvana	0:23d1f73bf130	2133
vladvana	0:23d1f73bf130	2134
vladvana	0:23d1f73bf130	2135	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Program
Created:	24 Sep 2017
Imports:	1
Forks:	0
Commits:	1
Dependents:	0
Dependencies:	0
Followers:	1

TARGET_NUCLEO_F103RB/stm32f1xx_hal_eth.h@0:23d1f73bf130, 2017-09-24 (annotated)

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