Vladimir Vana
pro vyuku PSS v Jecne
TARGET_NUCLEO_F103RB/stm32f1xx_hal_adc.h@0:23d1f73bf130, 2017-09-24 (annotated)
- Committer:
- vladvana
- Date:
- Sun Sep 24 12:31:52 2017 +0000
- Revision:
- 0:23d1f73bf130
podklady pro cviceni z PSS
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| vladvana | 0:23d1f73bf130 | 1 | /** |
| vladvana | 0:23d1f73bf130 | 2 | ****************************************************************************** |
| vladvana | 0:23d1f73bf130 | 3 | * @file stm32f1xx_hal_adc.h |
| vladvana | 0:23d1f73bf130 | 4 | * @author MCD Application Team |
| vladvana | 0:23d1f73bf130 | 5 | * @version V1.0.0 |
| vladvana | 0:23d1f73bf130 | 6 | * @date 15-December-2014 |
| vladvana | 0:23d1f73bf130 | 7 | * @brief Header file containing functions prototypes of ADC HAL library. |
| vladvana | 0:23d1f73bf130 | 8 | ****************************************************************************** |
| vladvana | 0:23d1f73bf130 | 9 | * @attention |
| vladvana | 0:23d1f73bf130 | 10 | * |
| vladvana | 0:23d1f73bf130 | 11 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
| vladvana | 0:23d1f73bf130 | 12 | * |
| vladvana | 0:23d1f73bf130 | 13 | * Redistribution and use in source and binary forms, with or without modification, |
| vladvana | 0:23d1f73bf130 | 14 | * are permitted provided that the following conditions are met: |
| vladvana | 0:23d1f73bf130 | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
| vladvana | 0:23d1f73bf130 | 16 | * this list of conditions and the following disclaimer. |
| vladvana | 0:23d1f73bf130 | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| vladvana | 0:23d1f73bf130 | 18 | * this list of conditions and the following disclaimer in the documentation |
| vladvana | 0:23d1f73bf130 | 19 | * and/or other materials provided with the distribution. |
| vladvana | 0:23d1f73bf130 | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| vladvana | 0:23d1f73bf130 | 21 | * may be used to endorse or promote products derived from this software |
| vladvana | 0:23d1f73bf130 | 22 | * without specific prior written permission. |
| vladvana | 0:23d1f73bf130 | 23 | * |
| vladvana | 0:23d1f73bf130 | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| vladvana | 0:23d1f73bf130 | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| vladvana | 0:23d1f73bf130 | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| vladvana | 0:23d1f73bf130 | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| vladvana | 0:23d1f73bf130 | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| vladvana | 0:23d1f73bf130 | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| vladvana | 0:23d1f73bf130 | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| vladvana | 0:23d1f73bf130 | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| vladvana | 0:23d1f73bf130 | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| vladvana | 0:23d1f73bf130 | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| vladvana | 0:23d1f73bf130 | 34 | * |
| vladvana | 0:23d1f73bf130 | 35 | ****************************************************************************** |
| vladvana | 0:23d1f73bf130 | 36 | */ |
| vladvana | 0:23d1f73bf130 | 37 | |
| vladvana | 0:23d1f73bf130 | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| vladvana | 0:23d1f73bf130 | 39 | #ifndef __STM32F1xx_HAL_ADC_H |
| vladvana | 0:23d1f73bf130 | 40 | #define __STM32F1xx_HAL_ADC_H |
| vladvana | 0:23d1f73bf130 | 41 | |
| vladvana | 0:23d1f73bf130 | 42 | #ifdef __cplusplus |
| vladvana | 0:23d1f73bf130 | 43 | extern "C" { |
| vladvana | 0:23d1f73bf130 | 44 | #endif |
| vladvana | 0:23d1f73bf130 | 45 | |
| vladvana | 0:23d1f73bf130 | 46 | /* Includes ------------------------------------------------------------------*/ |
| vladvana | 0:23d1f73bf130 | 47 | #include "stm32f1xx_hal_def.h" |
| vladvana | 0:23d1f73bf130 | 48 | /** @addtogroup STM32F1xx_HAL_Driver |
| vladvana | 0:23d1f73bf130 | 49 | * @{ |
| vladvana | 0:23d1f73bf130 | 50 | */ |
| vladvana | 0:23d1f73bf130 | 51 | |
| vladvana | 0:23d1f73bf130 | 52 | /** @addtogroup ADC |
| vladvana | 0:23d1f73bf130 | 53 | * @{ |
| vladvana | 0:23d1f73bf130 | 54 | */ |
| vladvana | 0:23d1f73bf130 | 55 | |
| vladvana | 0:23d1f73bf130 | 56 | /* Exported types ------------------------------------------------------------*/ |
| vladvana | 0:23d1f73bf130 | 57 | /** @defgroup ADC_Exported_Types ADC Exported Types |
| vladvana | 0:23d1f73bf130 | 58 | * @{ |
| vladvana | 0:23d1f73bf130 | 59 | */ |
| vladvana | 0:23d1f73bf130 | 60 | |
| vladvana | 0:23d1f73bf130 | 61 | /** |
| vladvana | 0:23d1f73bf130 | 62 | * @brief Structure definition of ADC and regular group initialization |
| vladvana | 0:23d1f73bf130 | 63 | * @note Parameters of this structure are shared within 2 scopes: |
| vladvana | 0:23d1f73bf130 | 64 | * - Scope entire ADC (affects regular and injected groups): DataAlign, ScanConvMode. |
| vladvana | 0:23d1f73bf130 | 65 | * - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv. |
| vladvana | 0:23d1f73bf130 | 66 | * @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state. |
| vladvana | 0:23d1f73bf130 | 67 | * ADC can be either disabled or enabled without conversion on going on regular group. |
| vladvana | 0:23d1f73bf130 | 68 | */ |
| vladvana | 0:23d1f73bf130 | 69 | typedef struct |
| vladvana | 0:23d1f73bf130 | 70 | { |
| vladvana | 0:23d1f73bf130 | 71 | uint32_t DataAlign; /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting) |
| vladvana | 0:23d1f73bf130 | 72 | or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3). |
| vladvana | 0:23d1f73bf130 | 73 | This parameter can be a value of @ref ADC_Data_align */ |
| vladvana | 0:23d1f73bf130 | 74 | uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups. |
| vladvana | 0:23d1f73bf130 | 75 | This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts. |
| vladvana | 0:23d1f73bf130 | 76 | If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1). |
| vladvana | 0:23d1f73bf130 | 77 | Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1). |
| vladvana | 0:23d1f73bf130 | 78 | If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank). |
| vladvana | 0:23d1f73bf130 | 79 | Scan direction is upward: from rank1 to rank 'n'. |
| vladvana | 0:23d1f73bf130 | 80 | This parameter can be a value of @ref ADC_Scan_mode |
| vladvana | 0:23d1f73bf130 | 81 | Note: For regular group, this parameter should be enabled in conversion either by polling (HAL_ADC_Start with Discontinuous mode and NbrOfDiscConversion=1) |
| vladvana | 0:23d1f73bf130 | 82 | or by DMA (HAL_ADC_Start_DMA), but not by interruption (HAL_ADC_Start_IT): in scan mode, interruption is triggered only on the |
| vladvana | 0:23d1f73bf130 | 83 | the last conversion of the sequence. All previous conversions would be overwritten by the last one. |
| vladvana | 0:23d1f73bf130 | 84 | Injected group used with scan mode has not this constraint: each rank has its own result register, no data is overwritten. */ |
| vladvana | 0:23d1f73bf130 | 85 | uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group, |
| vladvana | 0:23d1f73bf130 | 86 | after the selected trigger occurred (software start or external trigger). |
| vladvana | 0:23d1f73bf130 | 87 | This parameter can be set to ENABLE or DISABLE. */ |
| vladvana | 0:23d1f73bf130 | 88 | uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer. |
| vladvana | 0:23d1f73bf130 | 89 | To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. |
| vladvana | 0:23d1f73bf130 | 90 | This parameter must be a number between Min_Data = 1 and Max_Data = 16. */ |
| vladvana | 0:23d1f73bf130 | 91 | uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). |
| vladvana | 0:23d1f73bf130 | 92 | Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. |
| vladvana | 0:23d1f73bf130 | 93 | Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. |
| vladvana | 0:23d1f73bf130 | 94 | This parameter can be set to ENABLE or DISABLE. */ |
| vladvana | 0:23d1f73bf130 | 95 | uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of regular group (parameter NbrOfConversion) will be subdivided. |
| vladvana | 0:23d1f73bf130 | 96 | If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded. |
| vladvana | 0:23d1f73bf130 | 97 | This parameter must be a number between Min_Data = 1 and Max_Data = 8. */ |
| vladvana | 0:23d1f73bf130 | 98 | uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group. |
| vladvana | 0:23d1f73bf130 | 99 | If set to ADC_SOFTWARE_START, external triggers are disabled. |
| vladvana | 0:23d1f73bf130 | 100 | If set to external trigger source, triggering is on event rising edge. |
| vladvana | 0:23d1f73bf130 | 101 | This parameter can be a value of @ref ADC_External_trigger_source_Regular */ |
| vladvana | 0:23d1f73bf130 | 102 | }ADC_InitTypeDef; |
| vladvana | 0:23d1f73bf130 | 103 | |
| vladvana | 0:23d1f73bf130 | 104 | /** |
| vladvana | 0:23d1f73bf130 | 105 | * @brief Structure definition of ADC channel for regular group |
| vladvana | 0:23d1f73bf130 | 106 | * @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state. |
| vladvana | 0:23d1f73bf130 | 107 | * ADC can be either disabled or enabled without conversion on going on regular group. |
| vladvana | 0:23d1f73bf130 | 108 | */ |
| vladvana | 0:23d1f73bf130 | 109 | typedef struct |
| vladvana | 0:23d1f73bf130 | 110 | { |
| vladvana | 0:23d1f73bf130 | 111 | uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group. |
| vladvana | 0:23d1f73bf130 | 112 | This parameter can be a value of @ref ADC_channels |
| vladvana | 0:23d1f73bf130 | 113 | Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. |
| vladvana | 0:23d1f73bf130 | 114 | Note: On STM32F1 devices with several ADC: Only ADC1 can access internal measurement channels (VrefInt/TempSensor) |
| vladvana | 0:23d1f73bf130 | 115 | Note: On STM32F10xx8 and STM32F10xxB devices: A low-amplitude voltage glitch may be generated (on ADC input 0) on the PA0 pin, when the ADC is converting with injection trigger. |
| vladvana | 0:23d1f73bf130 | 116 | It is advised to distribute the analog channels so that Channel 0 is configured as an injected channel. |
| vladvana | 0:23d1f73bf130 | 117 | Refer to errata sheet of these devices for more details. */ |
| vladvana | 0:23d1f73bf130 | 118 | uint32_t Rank; /*!< Specifies the rank in the regular group sequencer |
| vladvana | 0:23d1f73bf130 | 119 | This parameter can be a value of @ref ADC_regular_rank |
| vladvana | 0:23d1f73bf130 | 120 | Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */ |
| vladvana | 0:23d1f73bf130 | 121 | uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel. |
| vladvana | 0:23d1f73bf130 | 122 | Unit: ADC clock cycles |
| vladvana | 0:23d1f73bf130 | 123 | Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits). |
| vladvana | 0:23d1f73bf130 | 124 | This parameter can be a value of @ref ADC_sampling_times |
| vladvana | 0:23d1f73bf130 | 125 | Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups. |
| vladvana | 0:23d1f73bf130 | 126 | If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting. |
| vladvana | 0:23d1f73bf130 | 127 | Note: In case of usage of internal measurement channels (VrefInt/TempSensor), |
| vladvana | 0:23d1f73bf130 | 128 | sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) |
| vladvana | 0:23d1f73bf130 | 129 | Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 5us to 17.1us min). */ |
| vladvana | 0:23d1f73bf130 | 130 | }ADC_ChannelConfTypeDef; |
| vladvana | 0:23d1f73bf130 | 131 | |
| vladvana | 0:23d1f73bf130 | 132 | /** |
| vladvana | 0:23d1f73bf130 | 133 | * @brief ADC Configuration analog watchdog definition |
| vladvana | 0:23d1f73bf130 | 134 | * @note The setting of these parameters with function is conditioned to ADC state. |
| vladvana | 0:23d1f73bf130 | 135 | * ADC state can be either disabled or enabled without conversion on going on regular and injected groups. |
| vladvana | 0:23d1f73bf130 | 136 | */ |
| vladvana | 0:23d1f73bf130 | 137 | typedef struct |
| vladvana | 0:23d1f73bf130 | 138 | { |
| vladvana | 0:23d1f73bf130 | 139 | uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode: single/all channels, regular/injected group. |
| vladvana | 0:23d1f73bf130 | 140 | This parameter can be a value of @ref ADC_analog_watchdog_mode. */ |
| vladvana | 0:23d1f73bf130 | 141 | uint32_t Channel; /*!< Selects which ADC channel to monitor by analog watchdog. |
| vladvana | 0:23d1f73bf130 | 142 | This parameter has an effect only if watchdog mode is configured on single channel (parameter WatchdogMode) |
| vladvana | 0:23d1f73bf130 | 143 | This parameter can be a value of @ref ADC_channels. */ |
| vladvana | 0:23d1f73bf130 | 144 | uint32_t ITMode; /*!< Specifies whether the analog watchdog is configured in interrupt or polling mode. |
| vladvana | 0:23d1f73bf130 | 145 | This parameter can be set to ENABLE or DISABLE */ |
| vladvana | 0:23d1f73bf130 | 146 | uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value. |
| vladvana | 0:23d1f73bf130 | 147 | This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */ |
| vladvana | 0:23d1f73bf130 | 148 | uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value. |
| vladvana | 0:23d1f73bf130 | 149 | This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */ |
| vladvana | 0:23d1f73bf130 | 150 | uint32_t WatchdogNumber; /*!< Reserved for future use, can be set to 0 */ |
| vladvana | 0:23d1f73bf130 | 151 | }ADC_AnalogWDGConfTypeDef; |
| vladvana | 0:23d1f73bf130 | 152 | |
| vladvana | 0:23d1f73bf130 | 153 | /** |
| vladvana | 0:23d1f73bf130 | 154 | * @brief HAL ADC state machine: ADC States structure definition |
| vladvana | 0:23d1f73bf130 | 155 | */ |
| vladvana | 0:23d1f73bf130 | 156 | typedef enum |
| vladvana | 0:23d1f73bf130 | 157 | { |
| vladvana | 0:23d1f73bf130 | 158 | HAL_ADC_STATE_RESET = 0x00, /*!< ADC not yet initialized or disabled */ |
| vladvana | 0:23d1f73bf130 | 159 | HAL_ADC_STATE_READY = 0x01, /*!< ADC peripheral ready for use */ |
| vladvana | 0:23d1f73bf130 | 160 | HAL_ADC_STATE_BUSY = 0x02, /*!< An internal process is ongoing */ |
| vladvana | 0:23d1f73bf130 | 161 | HAL_ADC_STATE_BUSY_REG = 0x12, /*!< Regular conversion is ongoing */ |
| vladvana | 0:23d1f73bf130 | 162 | HAL_ADC_STATE_BUSY_INJ = 0x22, /*!< Injected conversion is ongoing */ |
| vladvana | 0:23d1f73bf130 | 163 | HAL_ADC_STATE_BUSY_INJ_REG = 0x32, /*!< Injected and regular conversion are ongoing */ |
| vladvana | 0:23d1f73bf130 | 164 | HAL_ADC_STATE_TIMEOUT = 0x03, /*!< Timeout state */ |
| vladvana | 0:23d1f73bf130 | 165 | HAL_ADC_STATE_ERROR = 0x04, /*!< ADC state error */ |
| vladvana | 0:23d1f73bf130 | 166 | HAL_ADC_STATE_EOC = 0x05, /*!< Conversion is completed */ |
| vladvana | 0:23d1f73bf130 | 167 | HAL_ADC_STATE_EOC_REG = 0x15, /*!< Regular conversion is completed */ |
| vladvana | 0:23d1f73bf130 | 168 | HAL_ADC_STATE_EOC_INJ = 0x25, /*!< Injected conversion is completed */ |
| vladvana | 0:23d1f73bf130 | 169 | HAL_ADC_STATE_EOC_INJ_REG = 0x35, /*!< Injected and regular conversion are completed */ |
| vladvana | 0:23d1f73bf130 | 170 | HAL_ADC_STATE_AWD = 0x06, /*!< ADC state analog watchdog */ |
| vladvana | 0:23d1f73bf130 | 171 | HAL_ADC_STATE_AWD2 = 0x07, /*!< Not used on STM32F1xx devices (kept for compatibility with other devices featuring several AWD) */ |
| vladvana | 0:23d1f73bf130 | 172 | HAL_ADC_STATE_AWD3 = 0x08, /*!< Not used on STM32F1xx devices (kept for compatibility with other devices featuring several AWD) */ |
| vladvana | 0:23d1f73bf130 | 173 | }HAL_ADC_StateTypeDef; |
| vladvana | 0:23d1f73bf130 | 174 | |
| vladvana | 0:23d1f73bf130 | 175 | /** |
| vladvana | 0:23d1f73bf130 | 176 | * @brief ADC handle Structure definition |
| vladvana | 0:23d1f73bf130 | 177 | */ |
| vladvana | 0:23d1f73bf130 | 178 | typedef struct |
| vladvana | 0:23d1f73bf130 | 179 | { |
| vladvana | 0:23d1f73bf130 | 180 | ADC_TypeDef *Instance; /*!< Register base address */ |
| vladvana | 0:23d1f73bf130 | 181 | |
| vladvana | 0:23d1f73bf130 | 182 | ADC_InitTypeDef Init; /*!< ADC required parameters */ |
| vladvana | 0:23d1f73bf130 | 183 | |
| vladvana | 0:23d1f73bf130 | 184 | __IO uint32_t NbrOfConversionRank ; /*!< ADC conversion rank counter */ |
| vladvana | 0:23d1f73bf130 | 185 | |
| vladvana | 0:23d1f73bf130 | 186 | DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */ |
| vladvana | 0:23d1f73bf130 | 187 | |
| vladvana | 0:23d1f73bf130 | 188 | HAL_LockTypeDef Lock; /*!< ADC locking object */ |
| vladvana | 0:23d1f73bf130 | 189 | |
| vladvana | 0:23d1f73bf130 | 190 | __IO HAL_ADC_StateTypeDef State; /*!< ADC communication state */ |
| vladvana | 0:23d1f73bf130 | 191 | |
| vladvana | 0:23d1f73bf130 | 192 | __IO uint32_t ErrorCode; /*!< ADC Error code */ |
| vladvana | 0:23d1f73bf130 | 193 | }ADC_HandleTypeDef; |
| vladvana | 0:23d1f73bf130 | 194 | /** |
| vladvana | 0:23d1f73bf130 | 195 | * @} |
| vladvana | 0:23d1f73bf130 | 196 | */ |
| vladvana | 0:23d1f73bf130 | 197 | |
| vladvana | 0:23d1f73bf130 | 198 | |
| vladvana | 0:23d1f73bf130 | 199 | |
| vladvana | 0:23d1f73bf130 | 200 | /* Exported constants --------------------------------------------------------*/ |
| vladvana | 0:23d1f73bf130 | 201 | |
| vladvana | 0:23d1f73bf130 | 202 | /** @defgroup ADC_Exported_Constants ADC Exported Constants |
| vladvana | 0:23d1f73bf130 | 203 | * @{ |
| vladvana | 0:23d1f73bf130 | 204 | */ |
| vladvana | 0:23d1f73bf130 | 205 | |
| vladvana | 0:23d1f73bf130 | 206 | /** @defgroup ADC_Error_Code ADC Error Code |
| vladvana | 0:23d1f73bf130 | 207 | * @{ |
| vladvana | 0:23d1f73bf130 | 208 | */ |
| vladvana | 0:23d1f73bf130 | 209 | #define HAL_ADC_ERROR_NONE ((uint32_t)0x00) /*!< No error */ |
| vladvana | 0:23d1f73bf130 | 210 | #define HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01) /*!< ADC IP internal error: if problem of clocking, |
| vladvana | 0:23d1f73bf130 | 211 | enable/disable, erroneous state */ |
| vladvana | 0:23d1f73bf130 | 212 | #define HAL_ADC_ERROR_OVR ((uint32_t)0x02) /*!< Overrun error */ |
| vladvana | 0:23d1f73bf130 | 213 | #define HAL_ADC_ERROR_DMA ((uint32_t)0x04) /*!< DMA transfer error */ |
| vladvana | 0:23d1f73bf130 | 214 | |
| vladvana | 0:23d1f73bf130 | 215 | /** |
| vladvana | 0:23d1f73bf130 | 216 | * @} |
| vladvana | 0:23d1f73bf130 | 217 | */ |
| vladvana | 0:23d1f73bf130 | 218 | |
| vladvana | 0:23d1f73bf130 | 219 | |
| vladvana | 0:23d1f73bf130 | 220 | /** @defgroup ADC_Data_align ADC data alignment |
| vladvana | 0:23d1f73bf130 | 221 | * @{ |
| vladvana | 0:23d1f73bf130 | 222 | */ |
| vladvana | 0:23d1f73bf130 | 223 | #define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000) |
| vladvana | 0:23d1f73bf130 | 224 | #define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN) |
| vladvana | 0:23d1f73bf130 | 225 | /** |
| vladvana | 0:23d1f73bf130 | 226 | * @} |
| vladvana | 0:23d1f73bf130 | 227 | */ |
| vladvana | 0:23d1f73bf130 | 228 | |
| vladvana | 0:23d1f73bf130 | 229 | /** @defgroup ADC_Scan_mode ADC scan mode |
| vladvana | 0:23d1f73bf130 | 230 | * @{ |
| vladvana | 0:23d1f73bf130 | 231 | */ |
| vladvana | 0:23d1f73bf130 | 232 | /* Note: Scan mode values are not among binary choices ENABLE/DISABLE for */ |
| vladvana | 0:23d1f73bf130 | 233 | /* compatibility with other STM32 devices having a sequencer with */ |
| vladvana | 0:23d1f73bf130 | 234 | /* additional options. */ |
| vladvana | 0:23d1f73bf130 | 235 | #define ADC_SCAN_DISABLE ((uint32_t)0x00000000) |
| vladvana | 0:23d1f73bf130 | 236 | #define ADC_SCAN_ENABLE ((uint32_t)ADC_CR1_SCAN) |
| vladvana | 0:23d1f73bf130 | 237 | /** |
| vladvana | 0:23d1f73bf130 | 238 | * @} |
| vladvana | 0:23d1f73bf130 | 239 | */ |
| vladvana | 0:23d1f73bf130 | 240 | |
| vladvana | 0:23d1f73bf130 | 241 | /** @defgroup ADC_External_trigger_edge_Regular ADC external trigger enable for regular group |
| vladvana | 0:23d1f73bf130 | 242 | * @{ |
| vladvana | 0:23d1f73bf130 | 243 | */ |
| vladvana | 0:23d1f73bf130 | 244 | #define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000) |
| vladvana | 0:23d1f73bf130 | 245 | #define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTTRIG) |
| vladvana | 0:23d1f73bf130 | 246 | /** |
| vladvana | 0:23d1f73bf130 | 247 | * @} |
| vladvana | 0:23d1f73bf130 | 248 | */ |
| vladvana | 0:23d1f73bf130 | 249 | |
| vladvana | 0:23d1f73bf130 | 250 | /** @defgroup ADC_channels ADC channels |
| vladvana | 0:23d1f73bf130 | 251 | * @{ |
| vladvana | 0:23d1f73bf130 | 252 | */ |
| vladvana | 0:23d1f73bf130 | 253 | /* Note: Depending on devices, some channels may not be available on package */ |
| vladvana | 0:23d1f73bf130 | 254 | /* pins. Refer to device datasheet for channels availability. */ |
| vladvana | 0:23d1f73bf130 | 255 | #define ADC_CHANNEL_0 ((uint32_t)0x00000000) |
| vladvana | 0:23d1f73bf130 | 256 | #define ADC_CHANNEL_1 ((uint32_t)( ADC_SQR3_SQ1_0)) |
| vladvana | 0:23d1f73bf130 | 257 | #define ADC_CHANNEL_2 ((uint32_t)( ADC_SQR3_SQ1_1 )) |
| vladvana | 0:23d1f73bf130 | 258 | #define ADC_CHANNEL_3 ((uint32_t)( ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0)) |
| vladvana | 0:23d1f73bf130 | 259 | #define ADC_CHANNEL_4 ((uint32_t)( ADC_SQR3_SQ1_2 )) |
| vladvana | 0:23d1f73bf130 | 260 | #define ADC_CHANNEL_5 ((uint32_t)( ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_0)) |
| vladvana | 0:23d1f73bf130 | 261 | #define ADC_CHANNEL_6 ((uint32_t)( ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 )) |
| vladvana | 0:23d1f73bf130 | 262 | #define ADC_CHANNEL_7 ((uint32_t)( ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0)) |
| vladvana | 0:23d1f73bf130 | 263 | #define ADC_CHANNEL_8 ((uint32_t)( ADC_SQR3_SQ1_3 )) |
| vladvana | 0:23d1f73bf130 | 264 | #define ADC_CHANNEL_9 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_0)) |
| vladvana | 0:23d1f73bf130 | 265 | #define ADC_CHANNEL_10 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_1 )) |
| vladvana | 0:23d1f73bf130 | 266 | #define ADC_CHANNEL_11 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0)) |
| vladvana | 0:23d1f73bf130 | 267 | #define ADC_CHANNEL_12 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 )) |
| vladvana | 0:23d1f73bf130 | 268 | #define ADC_CHANNEL_13 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_0)) |
| vladvana | 0:23d1f73bf130 | 269 | #define ADC_CHANNEL_14 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 )) |
| vladvana | 0:23d1f73bf130 | 270 | #define ADC_CHANNEL_15 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0)) |
| vladvana | 0:23d1f73bf130 | 271 | #define ADC_CHANNEL_16 ((uint32_t)(ADC_SQR3_SQ1_4 )) |
| vladvana | 0:23d1f73bf130 | 272 | #define ADC_CHANNEL_17 ((uint32_t)(ADC_SQR3_SQ1_4 | ADC_SQR3_SQ1_0)) |
| vladvana | 0:23d1f73bf130 | 273 | |
| vladvana | 0:23d1f73bf130 | 274 | #define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_16 /* ADC internal channel (no connection on device pin) */ |
| vladvana | 0:23d1f73bf130 | 275 | #define ADC_CHANNEL_VREFINT ADC_CHANNEL_17 /* ADC internal channel (no connection on device pin) */ |
| vladvana | 0:23d1f73bf130 | 276 | /** |
| vladvana | 0:23d1f73bf130 | 277 | * @} |
| vladvana | 0:23d1f73bf130 | 278 | */ |
| vladvana | 0:23d1f73bf130 | 279 | |
| vladvana | 0:23d1f73bf130 | 280 | /** @defgroup ADC_sampling_times ADC sampling times |
| vladvana | 0:23d1f73bf130 | 281 | * @{ |
| vladvana | 0:23d1f73bf130 | 282 | */ |
| vladvana | 0:23d1f73bf130 | 283 | #define ADC_SAMPLETIME_1CYCLE_5 ((uint32_t)0x00000000) /*!< Sampling time 1.5 ADC clock cycle */ |
| vladvana | 0:23d1f73bf130 | 284 | #define ADC_SAMPLETIME_7CYCLES_5 ((uint32_t)( ADC_SMPR2_SMP0_0)) /*!< Sampling time 7.5 ADC clock cycles */ |
| vladvana | 0:23d1f73bf130 | 285 | #define ADC_SAMPLETIME_13CYCLES_5 ((uint32_t)( ADC_SMPR2_SMP0_1 )) /*!< Sampling time 13.5 ADC clock cycles */ |
| vladvana | 0:23d1f73bf130 | 286 | #define ADC_SAMPLETIME_28CYCLES_5 ((uint32_t)( ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0)) /*!< Sampling time 28.5 ADC clock cycles */ |
| vladvana | 0:23d1f73bf130 | 287 | #define ADC_SAMPLETIME_41CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 )) /*!< Sampling time 41.5 ADC clock cycles */ |
| vladvana | 0:23d1f73bf130 | 288 | #define ADC_SAMPLETIME_55CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_0)) /*!< Sampling time 55.5 ADC clock cycles */ |
| vladvana | 0:23d1f73bf130 | 289 | #define ADC_SAMPLETIME_71CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1 )) /*!< Sampling time 71.5 ADC clock cycles */ |
| vladvana | 0:23d1f73bf130 | 290 | #define ADC_SAMPLETIME_239CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0)) /*!< Sampling time 239.5 ADC clock cycles */ |
| vladvana | 0:23d1f73bf130 | 291 | /** |
| vladvana | 0:23d1f73bf130 | 292 | * @} |
| vladvana | 0:23d1f73bf130 | 293 | */ |
| vladvana | 0:23d1f73bf130 | 294 | |
| vladvana | 0:23d1f73bf130 | 295 | /** @defgroup ADC_regular_rank ADC rank into regular group |
| vladvana | 0:23d1f73bf130 | 296 | * @{ |
| vladvana | 0:23d1f73bf130 | 297 | */ |
| vladvana | 0:23d1f73bf130 | 298 | #define ADC_REGULAR_RANK_1 ((uint32_t)0x00000001) |
| vladvana | 0:23d1f73bf130 | 299 | #define ADC_REGULAR_RANK_2 ((uint32_t)0x00000002) |
| vladvana | 0:23d1f73bf130 | 300 | #define ADC_REGULAR_RANK_3 ((uint32_t)0x00000003) |
| vladvana | 0:23d1f73bf130 | 301 | #define ADC_REGULAR_RANK_4 ((uint32_t)0x00000004) |
| vladvana | 0:23d1f73bf130 | 302 | #define ADC_REGULAR_RANK_5 ((uint32_t)0x00000005) |
| vladvana | 0:23d1f73bf130 | 303 | #define ADC_REGULAR_RANK_6 ((uint32_t)0x00000006) |
| vladvana | 0:23d1f73bf130 | 304 | #define ADC_REGULAR_RANK_7 ((uint32_t)0x00000007) |
| vladvana | 0:23d1f73bf130 | 305 | #define ADC_REGULAR_RANK_8 ((uint32_t)0x00000008) |
| vladvana | 0:23d1f73bf130 | 306 | #define ADC_REGULAR_RANK_9 ((uint32_t)0x00000009) |
| vladvana | 0:23d1f73bf130 | 307 | #define ADC_REGULAR_RANK_10 ((uint32_t)0x0000000A) |
| vladvana | 0:23d1f73bf130 | 308 | #define ADC_REGULAR_RANK_11 ((uint32_t)0x0000000B) |
| vladvana | 0:23d1f73bf130 | 309 | #define ADC_REGULAR_RANK_12 ((uint32_t)0x0000000C) |
| vladvana | 0:23d1f73bf130 | 310 | #define ADC_REGULAR_RANK_13 ((uint32_t)0x0000000D) |
| vladvana | 0:23d1f73bf130 | 311 | #define ADC_REGULAR_RANK_14 ((uint32_t)0x0000000E) |
| vladvana | 0:23d1f73bf130 | 312 | #define ADC_REGULAR_RANK_15 ((uint32_t)0x0000000F) |
| vladvana | 0:23d1f73bf130 | 313 | #define ADC_REGULAR_RANK_16 ((uint32_t)0x00000010) |
| vladvana | 0:23d1f73bf130 | 314 | /** |
| vladvana | 0:23d1f73bf130 | 315 | * @} |
| vladvana | 0:23d1f73bf130 | 316 | */ |
| vladvana | 0:23d1f73bf130 | 317 | |
| vladvana | 0:23d1f73bf130 | 318 | /** @defgroup ADC_analog_watchdog_mode ADC analog watchdog mode |
| vladvana | 0:23d1f73bf130 | 319 | * @{ |
| vladvana | 0:23d1f73bf130 | 320 | */ |
| vladvana | 0:23d1f73bf130 | 321 | #define ADC_ANALOGWATCHDOG_NONE ((uint32_t)0x00000000) |
| vladvana | 0:23d1f73bf130 | 322 | #define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN)) |
| vladvana | 0:23d1f73bf130 | 323 | #define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN)) |
| vladvana | 0:23d1f73bf130 | 324 | #define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN)) |
| vladvana | 0:23d1f73bf130 | 325 | #define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t) ADC_CR1_AWDEN) |
| vladvana | 0:23d1f73bf130 | 326 | #define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t) ADC_CR1_JAWDEN) |
| vladvana | 0:23d1f73bf130 | 327 | #define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN)) |
| vladvana | 0:23d1f73bf130 | 328 | /** |
| vladvana | 0:23d1f73bf130 | 329 | * @} |
| vladvana | 0:23d1f73bf130 | 330 | */ |
| vladvana | 0:23d1f73bf130 | 331 | |
| vladvana | 0:23d1f73bf130 | 332 | /** @defgroup ADC_conversion_group ADC conversion group |
| vladvana | 0:23d1f73bf130 | 333 | * @{ |
| vladvana | 0:23d1f73bf130 | 334 | */ |
| vladvana | 0:23d1f73bf130 | 335 | #define ADC_REGULAR_GROUP ((uint32_t)(ADC_FLAG_EOC)) |
| vladvana | 0:23d1f73bf130 | 336 | #define ADC_INJECTED_GROUP ((uint32_t)(ADC_FLAG_JEOC)) |
| vladvana | 0:23d1f73bf130 | 337 | #define ADC_REGULAR_INJECTED_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_JEOC)) |
| vladvana | 0:23d1f73bf130 | 338 | /** |
| vladvana | 0:23d1f73bf130 | 339 | * @} |
| vladvana | 0:23d1f73bf130 | 340 | */ |
| vladvana | 0:23d1f73bf130 | 341 | |
| vladvana | 0:23d1f73bf130 | 342 | /** @defgroup ADC_Event_type ADC Event type |
| vladvana | 0:23d1f73bf130 | 343 | * @{ |
| vladvana | 0:23d1f73bf130 | 344 | */ |
| vladvana | 0:23d1f73bf130 | 345 | #define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD) /*!< ADC Analog watchdog event */ |
| vladvana | 0:23d1f73bf130 | 346 | |
| vladvana | 0:23d1f73bf130 | 347 | #define ADC_AWD1_EVENT ADC_AWD_EVENT /*!< ADC Analog watchdog 1 event: Alternate naming for compatibility with other STM32 devices having several analog watchdogs */ |
| vladvana | 0:23d1f73bf130 | 348 | /** |
| vladvana | 0:23d1f73bf130 | 349 | * @} |
| vladvana | 0:23d1f73bf130 | 350 | */ |
| vladvana | 0:23d1f73bf130 | 351 | |
| vladvana | 0:23d1f73bf130 | 352 | /** @defgroup ADC_interrupts_definition ADC interrupts definition |
| vladvana | 0:23d1f73bf130 | 353 | * @{ |
| vladvana | 0:23d1f73bf130 | 354 | */ |
| vladvana | 0:23d1f73bf130 | 355 | #define ADC_IT_EOC ADC_CR1_EOCIE /*!< ADC End of Regular Conversion interrupt source */ |
| vladvana | 0:23d1f73bf130 | 356 | #define ADC_IT_JEOC ADC_CR1_JEOCIE /*!< ADC End of Injected Conversion interrupt source */ |
| vladvana | 0:23d1f73bf130 | 357 | #define ADC_IT_AWD ADC_CR1_AWDIE /*!< ADC Analog watchdog interrupt source */ |
| vladvana | 0:23d1f73bf130 | 358 | /** |
| vladvana | 0:23d1f73bf130 | 359 | * @} |
| vladvana | 0:23d1f73bf130 | 360 | */ |
| vladvana | 0:23d1f73bf130 | 361 | |
| vladvana | 0:23d1f73bf130 | 362 | /** @defgroup ADC_flags_definition ADC flags definition |
| vladvana | 0:23d1f73bf130 | 363 | * @{ |
| vladvana | 0:23d1f73bf130 | 364 | */ |
| vladvana | 0:23d1f73bf130 | 365 | #define ADC_FLAG_STRT ADC_SR_STRT /*!< ADC Regular group start flag */ |
| vladvana | 0:23d1f73bf130 | 366 | #define ADC_FLAG_JSTRT ADC_SR_JSTRT /*!< ADC Injected group start flag */ |
| vladvana | 0:23d1f73bf130 | 367 | #define ADC_FLAG_EOC ADC_SR_EOC /*!< ADC End of Regular conversion flag */ |
| vladvana | 0:23d1f73bf130 | 368 | #define ADC_FLAG_JEOC ADC_SR_JEOC /*!< ADC End of Injected conversion flag */ |
| vladvana | 0:23d1f73bf130 | 369 | #define ADC_FLAG_AWD ADC_SR_AWD /*!< ADC Analog watchdog flag */ |
| vladvana | 0:23d1f73bf130 | 370 | /** |
| vladvana | 0:23d1f73bf130 | 371 | * @} |
| vladvana | 0:23d1f73bf130 | 372 | */ |
| vladvana | 0:23d1f73bf130 | 373 | |
| vladvana | 0:23d1f73bf130 | 374 | |
| vladvana | 0:23d1f73bf130 | 375 | /** |
| vladvana | 0:23d1f73bf130 | 376 | * @} |
| vladvana | 0:23d1f73bf130 | 377 | */ |
| vladvana | 0:23d1f73bf130 | 378 | |
| vladvana | 0:23d1f73bf130 | 379 | /* Private constants ---------------------------------------------------------*/ |
| vladvana | 0:23d1f73bf130 | 380 | |
| vladvana | 0:23d1f73bf130 | 381 | /** @addtogroup ADC_Private_Constants ADC Private Constants |
| vladvana | 0:23d1f73bf130 | 382 | * @{ |
| vladvana | 0:23d1f73bf130 | 383 | */ |
| vladvana | 0:23d1f73bf130 | 384 | |
| vladvana | 0:23d1f73bf130 | 385 | /** @defgroup ADC_conversion_cycles ADC conversion cycles |
| vladvana | 0:23d1f73bf130 | 386 | * @{ |
| vladvana | 0:23d1f73bf130 | 387 | */ |
| vladvana | 0:23d1f73bf130 | 388 | /* ADC conversion cycles (unit: ADC clock cycles) */ |
| vladvana | 0:23d1f73bf130 | 389 | /* (selected sampling time + conversion time of 12.5 ADC clock cycles, with */ |
| vladvana | 0:23d1f73bf130 | 390 | /* resolution 12 bits) */ |
| vladvana | 0:23d1f73bf130 | 391 | #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_1CYCLE5 ((uint32_t) 14) |
| vladvana | 0:23d1f73bf130 | 392 | #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5 ((uint32_t) 20) |
| vladvana | 0:23d1f73bf130 | 393 | #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_13CYCLES5 ((uint32_t) 26) |
| vladvana | 0:23d1f73bf130 | 394 | #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5 ((uint32_t) 41) |
| vladvana | 0:23d1f73bf130 | 395 | #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_41CYCLES5 ((uint32_t) 54) |
| vladvana | 0:23d1f73bf130 | 396 | #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_55CYCLES5 ((uint32_t) 68) |
| vladvana | 0:23d1f73bf130 | 397 | #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5 ((uint32_t) 84) |
| vladvana | 0:23d1f73bf130 | 398 | #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5 ((uint32_t)252) |
| vladvana | 0:23d1f73bf130 | 399 | /** |
| vladvana | 0:23d1f73bf130 | 400 | * @} |
| vladvana | 0:23d1f73bf130 | 401 | */ |
| vladvana | 0:23d1f73bf130 | 402 | |
| vladvana | 0:23d1f73bf130 | 403 | /** @defgroup ADC_sampling_times_all_channels ADC sampling times all channels |
| vladvana | 0:23d1f73bf130 | 404 | * @{ |
| vladvana | 0:23d1f73bf130 | 405 | */ |
| vladvana | 0:23d1f73bf130 | 406 | #define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 \ |
| vladvana | 0:23d1f73bf130 | 407 | (ADC_SMPR2_SMP9_2 | ADC_SMPR2_SMP8_2 | ADC_SMPR2_SMP7_2 | ADC_SMPR2_SMP6_2 | \ |
| vladvana | 0:23d1f73bf130 | 408 | ADC_SMPR2_SMP5_2 | ADC_SMPR2_SMP4_2 | ADC_SMPR2_SMP3_2 | ADC_SMPR2_SMP2_2 | \ |
| vladvana | 0:23d1f73bf130 | 409 | ADC_SMPR2_SMP1_2 | ADC_SMPR2_SMP0_2) |
| vladvana | 0:23d1f73bf130 | 410 | #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 \ |
| vladvana | 0:23d1f73bf130 | 411 | (ADC_SMPR1_SMP17_2 | ADC_SMPR1_SMP16_2 | ADC_SMPR1_SMP15_2 | ADC_SMPR1_SMP14_2 | \ |
| vladvana | 0:23d1f73bf130 | 412 | ADC_SMPR1_SMP13_2 | ADC_SMPR1_SMP12_2 | ADC_SMPR1_SMP11_2 | ADC_SMPR1_SMP10_2 ) |
| vladvana | 0:23d1f73bf130 | 413 | |
| vladvana | 0:23d1f73bf130 | 414 | #define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 \ |
| vladvana | 0:23d1f73bf130 | 415 | (ADC_SMPR2_SMP9_1 | ADC_SMPR2_SMP8_1 | ADC_SMPR2_SMP7_1 | ADC_SMPR2_SMP6_1 | \ |
| vladvana | 0:23d1f73bf130 | 416 | ADC_SMPR2_SMP5_1 | ADC_SMPR2_SMP4_1 | ADC_SMPR2_SMP3_1 | ADC_SMPR2_SMP2_1 | \ |
| vladvana | 0:23d1f73bf130 | 417 | ADC_SMPR2_SMP1_1 | ADC_SMPR2_SMP0_1) |
| vladvana | 0:23d1f73bf130 | 418 | #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 \ |
| vladvana | 0:23d1f73bf130 | 419 | (ADC_SMPR1_SMP17_1 | ADC_SMPR1_SMP16_1 | ADC_SMPR1_SMP15_1 | ADC_SMPR1_SMP14_1 | \ |
| vladvana | 0:23d1f73bf130 | 420 | ADC_SMPR1_SMP13_1 | ADC_SMPR1_SMP12_1 | ADC_SMPR1_SMP11_1 | ADC_SMPR1_SMP10_1 ) |
| vladvana | 0:23d1f73bf130 | 421 | |
| vladvana | 0:23d1f73bf130 | 422 | #define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0 \ |
| vladvana | 0:23d1f73bf130 | 423 | (ADC_SMPR2_SMP9_0 | ADC_SMPR2_SMP8_0 | ADC_SMPR2_SMP7_0 | ADC_SMPR2_SMP6_0 | \ |
| vladvana | 0:23d1f73bf130 | 424 | ADC_SMPR2_SMP5_0 | ADC_SMPR2_SMP4_0 | ADC_SMPR2_SMP3_0 | ADC_SMPR2_SMP2_0 | \ |
| vladvana | 0:23d1f73bf130 | 425 | ADC_SMPR2_SMP1_0 | ADC_SMPR2_SMP0_0) |
| vladvana | 0:23d1f73bf130 | 426 | #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0 \ |
| vladvana | 0:23d1f73bf130 | 427 | (ADC_SMPR1_SMP17_0 | ADC_SMPR1_SMP16_0 | ADC_SMPR1_SMP15_0 | ADC_SMPR1_SMP14_0 | \ |
| vladvana | 0:23d1f73bf130 | 428 | ADC_SMPR1_SMP13_0 | ADC_SMPR1_SMP12_0 | ADC_SMPR1_SMP11_0 | ADC_SMPR1_SMP10_0 ) |
| vladvana | 0:23d1f73bf130 | 429 | |
| vladvana | 0:23d1f73bf130 | 430 | #define ADC_SAMPLETIME_1CYCLE5_SMPR2ALLCHANNELS ((uint32_t)0x00000000) |
| vladvana | 0:23d1f73bf130 | 431 | #define ADC_SAMPLETIME_7CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0) |
| vladvana | 0:23d1f73bf130 | 432 | #define ADC_SAMPLETIME_13CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) |
| vladvana | 0:23d1f73bf130 | 433 | #define ADC_SAMPLETIME_28CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0) |
| vladvana | 0:23d1f73bf130 | 434 | #define ADC_SAMPLETIME_41CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2) |
| vladvana | 0:23d1f73bf130 | 435 | #define ADC_SAMPLETIME_55CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0) |
| vladvana | 0:23d1f73bf130 | 436 | #define ADC_SAMPLETIME_71CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) |
| vladvana | 0:23d1f73bf130 | 437 | #define ADC_SAMPLETIME_239CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0) |
| vladvana | 0:23d1f73bf130 | 438 | |
| vladvana | 0:23d1f73bf130 | 439 | #define ADC_SAMPLETIME_1CYCLE5_SMPR1ALLCHANNELS ((uint32_t)0x00000000) |
| vladvana | 0:23d1f73bf130 | 440 | #define ADC_SAMPLETIME_7CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) |
| vladvana | 0:23d1f73bf130 | 441 | #define ADC_SAMPLETIME_13CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) |
| vladvana | 0:23d1f73bf130 | 442 | #define ADC_SAMPLETIME_28CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) |
| vladvana | 0:23d1f73bf130 | 443 | #define ADC_SAMPLETIME_41CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2) |
| vladvana | 0:23d1f73bf130 | 444 | #define ADC_SAMPLETIME_55CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) |
| vladvana | 0:23d1f73bf130 | 445 | #define ADC_SAMPLETIME_71CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) |
| vladvana | 0:23d1f73bf130 | 446 | #define ADC_SAMPLETIME_239CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) |
| vladvana | 0:23d1f73bf130 | 447 | /** |
| vladvana | 0:23d1f73bf130 | 448 | * @} |
| vladvana | 0:23d1f73bf130 | 449 | */ |
| vladvana | 0:23d1f73bf130 | 450 | |
| vladvana | 0:23d1f73bf130 | 451 | /* Combination of all post-conversion flags bits: EOC/EOS, JEOC/JEOS, OVR, AWDx */ |
| vladvana | 0:23d1f73bf130 | 452 | #define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_EOC | ADC_FLAG_JEOC | ADC_FLAG_AWD ) |
| vladvana | 0:23d1f73bf130 | 453 | |
| vladvana | 0:23d1f73bf130 | 454 | /** |
| vladvana | 0:23d1f73bf130 | 455 | * @} |
| vladvana | 0:23d1f73bf130 | 456 | */ |
| vladvana | 0:23d1f73bf130 | 457 | |
| vladvana | 0:23d1f73bf130 | 458 | |
| vladvana | 0:23d1f73bf130 | 459 | /* Exported macro ------------------------------------------------------------*/ |
| vladvana | 0:23d1f73bf130 | 460 | |
| vladvana | 0:23d1f73bf130 | 461 | /** @defgroup ADC_Exported_Macros ADC Exported Macros |
| vladvana | 0:23d1f73bf130 | 462 | * @{ |
| vladvana | 0:23d1f73bf130 | 463 | */ |
| vladvana | 0:23d1f73bf130 | 464 | /* Macro for internal HAL driver usage, and possibly can be used into code of */ |
| vladvana | 0:23d1f73bf130 | 465 | /* final user. */ |
| vladvana | 0:23d1f73bf130 | 466 | |
| vladvana | 0:23d1f73bf130 | 467 | /** |
| vladvana | 0:23d1f73bf130 | 468 | * @brief Enable the ADC peripheral |
| vladvana | 0:23d1f73bf130 | 469 | * @note ADC enable requires a delay for ADC stabilization time |
| vladvana | 0:23d1f73bf130 | 470 | * (refer to device datasheet, parameter tSTAB) |
| vladvana | 0:23d1f73bf130 | 471 | * @note On STM32F1, if ADC is already enabled this macro trigs a conversion |
| vladvana | 0:23d1f73bf130 | 472 | * SW start on regular group. |
| vladvana | 0:23d1f73bf130 | 473 | * @param __HANDLE__: ADC handle |
| vladvana | 0:23d1f73bf130 | 474 | * @retval None |
| vladvana | 0:23d1f73bf130 | 475 | */ |
| vladvana | 0:23d1f73bf130 | 476 | #define __HAL_ADC_ENABLE(__HANDLE__) \ |
| vladvana | 0:23d1f73bf130 | 477 | (SET_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON))) |
| vladvana | 0:23d1f73bf130 | 478 | |
| vladvana | 0:23d1f73bf130 | 479 | /** |
| vladvana | 0:23d1f73bf130 | 480 | * @brief Disable the ADC peripheral |
| vladvana | 0:23d1f73bf130 | 481 | * @param __HANDLE__: ADC handle |
| vladvana | 0:23d1f73bf130 | 482 | * @retval None |
| vladvana | 0:23d1f73bf130 | 483 | */ |
| vladvana | 0:23d1f73bf130 | 484 | #define __HAL_ADC_DISABLE(__HANDLE__) \ |
| vladvana | 0:23d1f73bf130 | 485 | (CLEAR_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON))) |
| vladvana | 0:23d1f73bf130 | 486 | |
| vladvana | 0:23d1f73bf130 | 487 | /** @brief Enable the ADC end of conversion interrupt. |
| vladvana | 0:23d1f73bf130 | 488 | * @param __HANDLE__: ADC handle |
| vladvana | 0:23d1f73bf130 | 489 | * @param __INTERRUPT__: ADC Interrupt |
| vladvana | 0:23d1f73bf130 | 490 | * This parameter can be any combination of the following values: |
| vladvana | 0:23d1f73bf130 | 491 | * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source |
| vladvana | 0:23d1f73bf130 | 492 | * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source |
| vladvana | 0:23d1f73bf130 | 493 | * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source |
| vladvana | 0:23d1f73bf130 | 494 | * @retval None |
| vladvana | 0:23d1f73bf130 | 495 | */ |
| vladvana | 0:23d1f73bf130 | 496 | #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ |
| vladvana | 0:23d1f73bf130 | 497 | (SET_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__))) |
| vladvana | 0:23d1f73bf130 | 498 | |
| vladvana | 0:23d1f73bf130 | 499 | /** @brief Disable the ADC end of conversion interrupt. |
| vladvana | 0:23d1f73bf130 | 500 | * @param __HANDLE__: ADC handle |
| vladvana | 0:23d1f73bf130 | 501 | * @param __INTERRUPT__: ADC Interrupt |
| vladvana | 0:23d1f73bf130 | 502 | * This parameter can be any combination of the following values: |
| vladvana | 0:23d1f73bf130 | 503 | * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source |
| vladvana | 0:23d1f73bf130 | 504 | * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source |
| vladvana | 0:23d1f73bf130 | 505 | * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source |
| vladvana | 0:23d1f73bf130 | 506 | * @retval None |
| vladvana | 0:23d1f73bf130 | 507 | */ |
| vladvana | 0:23d1f73bf130 | 508 | #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ |
| vladvana | 0:23d1f73bf130 | 509 | (CLEAR_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__))) |
| vladvana | 0:23d1f73bf130 | 510 | |
| vladvana | 0:23d1f73bf130 | 511 | /** @brief Checks if the specified ADC interrupt source is enabled or disabled. |
| vladvana | 0:23d1f73bf130 | 512 | * @param __HANDLE__: ADC handle |
| vladvana | 0:23d1f73bf130 | 513 | * @param __INTERRUPT__: ADC interrupt source to check |
| vladvana | 0:23d1f73bf130 | 514 | * This parameter can be any combination of the following values: |
| vladvana | 0:23d1f73bf130 | 515 | * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source |
| vladvana | 0:23d1f73bf130 | 516 | * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source |
| vladvana | 0:23d1f73bf130 | 517 | * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source |
| vladvana | 0:23d1f73bf130 | 518 | * @retval None |
| vladvana | 0:23d1f73bf130 | 519 | */ |
| vladvana | 0:23d1f73bf130 | 520 | #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ |
| vladvana | 0:23d1f73bf130 | 521 | (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) |
| vladvana | 0:23d1f73bf130 | 522 | |
| vladvana | 0:23d1f73bf130 | 523 | /** @brief Get the selected ADC's flag status. |
| vladvana | 0:23d1f73bf130 | 524 | * @param __HANDLE__: ADC handle |
| vladvana | 0:23d1f73bf130 | 525 | * @param __FLAG__: ADC flag |
| vladvana | 0:23d1f73bf130 | 526 | * This parameter can be any combination of the following values: |
| vladvana | 0:23d1f73bf130 | 527 | * @arg ADC_FLAG_STRT: ADC Regular group start flag |
| vladvana | 0:23d1f73bf130 | 528 | * @arg ADC_FLAG_JSTRT: ADC Injected group start flag |
| vladvana | 0:23d1f73bf130 | 529 | * @arg ADC_FLAG_EOC: ADC End of Regular conversion flag |
| vladvana | 0:23d1f73bf130 | 530 | * @arg ADC_FLAG_JEOC: ADC End of Injected conversion flag |
| vladvana | 0:23d1f73bf130 | 531 | * @arg ADC_FLAG_AWD: ADC Analog watchdog flag |
| vladvana | 0:23d1f73bf130 | 532 | * @retval None |
| vladvana | 0:23d1f73bf130 | 533 | */ |
| vladvana | 0:23d1f73bf130 | 534 | #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \ |
| vladvana | 0:23d1f73bf130 | 535 | ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) |
| vladvana | 0:23d1f73bf130 | 536 | |
| vladvana | 0:23d1f73bf130 | 537 | /** @brief Clear the ADC's pending flags |
| vladvana | 0:23d1f73bf130 | 538 | * @param __HANDLE__: ADC handle |
| vladvana | 0:23d1f73bf130 | 539 | * @param __FLAG__: ADC flag |
| vladvana | 0:23d1f73bf130 | 540 | * This parameter can be any combination of the following values: |
| vladvana | 0:23d1f73bf130 | 541 | * @arg ADC_FLAG_STRT: ADC Regular group start flag |
| vladvana | 0:23d1f73bf130 | 542 | * @arg ADC_FLAG_JSTRT: ADC Injected group start flag |
| vladvana | 0:23d1f73bf130 | 543 | * @arg ADC_FLAG_EOC: ADC End of Regular conversion flag |
| vladvana | 0:23d1f73bf130 | 544 | * @arg ADC_FLAG_JEOC: ADC End of Injected conversion flag |
| vladvana | 0:23d1f73bf130 | 545 | * @arg ADC_FLAG_AWD: ADC Analog watchdog flag |
| vladvana | 0:23d1f73bf130 | 546 | * @retval None |
| vladvana | 0:23d1f73bf130 | 547 | */ |
| vladvana | 0:23d1f73bf130 | 548 | #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \ |
| vladvana | 0:23d1f73bf130 | 549 | (CLEAR_BIT((__HANDLE__)->Instance->SR, (__FLAG__))) |
| vladvana | 0:23d1f73bf130 | 550 | |
| vladvana | 0:23d1f73bf130 | 551 | /** @brief Reset ADC handle state |
| vladvana | 0:23d1f73bf130 | 552 | * @param __HANDLE__: ADC handle |
| vladvana | 0:23d1f73bf130 | 553 | * @retval None |
| vladvana | 0:23d1f73bf130 | 554 | */ |
| vladvana | 0:23d1f73bf130 | 555 | #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ |
| vladvana | 0:23d1f73bf130 | 556 | ((__HANDLE__)->State = HAL_ADC_STATE_RESET) |
| vladvana | 0:23d1f73bf130 | 557 | |
| vladvana | 0:23d1f73bf130 | 558 | /** |
| vladvana | 0:23d1f73bf130 | 559 | * @} |
| vladvana | 0:23d1f73bf130 | 560 | */ |
| vladvana | 0:23d1f73bf130 | 561 | |
| vladvana | 0:23d1f73bf130 | 562 | /* Private macro ------------------------------------------------------------*/ |
| vladvana | 0:23d1f73bf130 | 563 | |
| vladvana | 0:23d1f73bf130 | 564 | /** @defgroup ADC_Private_Macros ADC Private Macros |
| vladvana | 0:23d1f73bf130 | 565 | * @{ |
| vladvana | 0:23d1f73bf130 | 566 | */ |
| vladvana | 0:23d1f73bf130 | 567 | /* Macro reserved for internal HAL driver usage, not intended to be used in */ |
| vladvana | 0:23d1f73bf130 | 568 | /* code of final user. */ |
| vladvana | 0:23d1f73bf130 | 569 | |
| vladvana | 0:23d1f73bf130 | 570 | /** |
| vladvana | 0:23d1f73bf130 | 571 | * @brief Verification of ADC state: enabled or disabled |
| vladvana | 0:23d1f73bf130 | 572 | * @param __HANDLE__: ADC handle |
| vladvana | 0:23d1f73bf130 | 573 | * @retval SET (ADC enabled) or RESET (ADC disabled) |
| vladvana | 0:23d1f73bf130 | 574 | */ |
| vladvana | 0:23d1f73bf130 | 575 | #define ADC_IS_ENABLE(__HANDLE__) \ |
| vladvana | 0:23d1f73bf130 | 576 | ((( ((__HANDLE__)->Instance->CR2 & ADC_CR2_ADON) == ADC_CR2_ADON ) \ |
| vladvana | 0:23d1f73bf130 | 577 | ) ? SET : RESET) |
| vladvana | 0:23d1f73bf130 | 578 | |
| vladvana | 0:23d1f73bf130 | 579 | /** |
| vladvana | 0:23d1f73bf130 | 580 | * @brief Test if conversion trigger of regular group is software start |
| vladvana | 0:23d1f73bf130 | 581 | * or external trigger. |
| vladvana | 0:23d1f73bf130 | 582 | * @param __HANDLE__: ADC handle |
| vladvana | 0:23d1f73bf130 | 583 | * @retval SET (software start) or RESET (external trigger) |
| vladvana | 0:23d1f73bf130 | 584 | */ |
| vladvana | 0:23d1f73bf130 | 585 | #define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \ |
| vladvana | 0:23d1f73bf130 | 586 | (READ_BIT((__HANDLE__)->Instance->CR2, ADC_CR2_EXTSEL) == ADC_SOFTWARE_START) |
| vladvana | 0:23d1f73bf130 | 587 | |
| vladvana | 0:23d1f73bf130 | 588 | /** |
| vladvana | 0:23d1f73bf130 | 589 | * @brief Test if conversion trigger of injected group is software start |
| vladvana | 0:23d1f73bf130 | 590 | * or external trigger. |
| vladvana | 0:23d1f73bf130 | 591 | * @param __HANDLE__: ADC handle |
| vladvana | 0:23d1f73bf130 | 592 | * @retval SET (software start) or RESET (external trigger) |
| vladvana | 0:23d1f73bf130 | 593 | */ |
| vladvana | 0:23d1f73bf130 | 594 | #define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \ |
| vladvana | 0:23d1f73bf130 | 595 | (READ_BIT((__HANDLE__)->Instance->CR2, ADC_CR2_JEXTSEL) == ADC_INJECTED_SOFTWARE_START) |
| vladvana | 0:23d1f73bf130 | 596 | |
| vladvana | 0:23d1f73bf130 | 597 | /** |
| vladvana | 0:23d1f73bf130 | 598 | * @brief Clear ADC error code (set it to error code: "no error") |
| vladvana | 0:23d1f73bf130 | 599 | * @param __HANDLE__: ADC handle |
| vladvana | 0:23d1f73bf130 | 600 | * @retval None |
| vladvana | 0:23d1f73bf130 | 601 | */ |
| vladvana | 0:23d1f73bf130 | 602 | #define ADC_CLEAR_ERRORCODE(__HANDLE__) \ |
| vladvana | 0:23d1f73bf130 | 603 | ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) |
| vladvana | 0:23d1f73bf130 | 604 | |
| vladvana | 0:23d1f73bf130 | 605 | /** |
| vladvana | 0:23d1f73bf130 | 606 | * @brief Set ADC number of conversions into regular channel sequence length. |
| vladvana | 0:23d1f73bf130 | 607 | * @param _NbrOfConversion_: Regular channel sequence length |
| vladvana | 0:23d1f73bf130 | 608 | * @retval None |
| vladvana | 0:23d1f73bf130 | 609 | */ |
| vladvana | 0:23d1f73bf130 | 610 | #define ADC_SQR1_L_SHIFT(_NbrOfConversion_) \ |
| vladvana | 0:23d1f73bf130 | 611 | (((_NbrOfConversion_) - (uint8_t)1) << POSITION_VAL(ADC_SQR1_L)) |
| vladvana | 0:23d1f73bf130 | 612 | |
| vladvana | 0:23d1f73bf130 | 613 | /** |
| vladvana | 0:23d1f73bf130 | 614 | * @brief Set the ADC's sample time for channel numbers between 10 and 18. |
| vladvana | 0:23d1f73bf130 | 615 | * @param _SAMPLETIME_: Sample time parameter. |
| vladvana | 0:23d1f73bf130 | 616 | * @param _CHANNELNB_: Channel number. |
| vladvana | 0:23d1f73bf130 | 617 | * @retval None |
| vladvana | 0:23d1f73bf130 | 618 | */ |
| vladvana | 0:23d1f73bf130 | 619 | #define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) \ |
| vladvana | 0:23d1f73bf130 | 620 | ((_SAMPLETIME_) << (POSITION_VAL(ADC_SMPR1_SMP11) * ((_CHANNELNB_) - 10))) |
| vladvana | 0:23d1f73bf130 | 621 | |
| vladvana | 0:23d1f73bf130 | 622 | /** |
| vladvana | 0:23d1f73bf130 | 623 | * @brief Set the ADC's sample time for channel numbers between 0 and 9. |
| vladvana | 0:23d1f73bf130 | 624 | * @param _SAMPLETIME_: Sample time parameter. |
| vladvana | 0:23d1f73bf130 | 625 | * @param _CHANNELNB_: Channel number. |
| vladvana | 0:23d1f73bf130 | 626 | * @retval None |
| vladvana | 0:23d1f73bf130 | 627 | */ |
| vladvana | 0:23d1f73bf130 | 628 | #define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) \ |
| vladvana | 0:23d1f73bf130 | 629 | ((_SAMPLETIME_) << (POSITION_VAL(ADC_SMPR2_SMP1) * (_CHANNELNB_))) |
| vladvana | 0:23d1f73bf130 | 630 | |
| vladvana | 0:23d1f73bf130 | 631 | /** |
| vladvana | 0:23d1f73bf130 | 632 | * @brief Set the selected regular channel rank for rank between 1 and 6. |
| vladvana | 0:23d1f73bf130 | 633 | * @param _CHANNELNB_: Channel number. |
| vladvana | 0:23d1f73bf130 | 634 | * @param _RANKNB_: Rank number. |
| vladvana | 0:23d1f73bf130 | 635 | * @retval None |
| vladvana | 0:23d1f73bf130 | 636 | */ |
| vladvana | 0:23d1f73bf130 | 637 | #define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) \ |
| vladvana | 0:23d1f73bf130 | 638 | ((_CHANNELNB_) << (POSITION_VAL(ADC_SQR3_SQ2) * ((_RANKNB_) - 1))) |
| vladvana | 0:23d1f73bf130 | 639 | |
| vladvana | 0:23d1f73bf130 | 640 | /** |
| vladvana | 0:23d1f73bf130 | 641 | * @brief Set the selected regular channel rank for rank between 7 and 12. |
| vladvana | 0:23d1f73bf130 | 642 | * @param _CHANNELNB_: Channel number. |
| vladvana | 0:23d1f73bf130 | 643 | * @param _RANKNB_: Rank number. |
| vladvana | 0:23d1f73bf130 | 644 | * @retval None |
| vladvana | 0:23d1f73bf130 | 645 | */ |
| vladvana | 0:23d1f73bf130 | 646 | #define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) \ |
| vladvana | 0:23d1f73bf130 | 647 | ((_CHANNELNB_) << (POSITION_VAL(ADC_SQR2_SQ8) * ((_RANKNB_) - 7))) |
| vladvana | 0:23d1f73bf130 | 648 | |
| vladvana | 0:23d1f73bf130 | 649 | /** |
| vladvana | 0:23d1f73bf130 | 650 | * @brief Set the selected regular channel rank for rank between 13 and 16. |
| vladvana | 0:23d1f73bf130 | 651 | * @param _CHANNELNB_: Channel number. |
| vladvana | 0:23d1f73bf130 | 652 | * @param _RANKNB_: Rank number. |
| vladvana | 0:23d1f73bf130 | 653 | * @retval None |
| vladvana | 0:23d1f73bf130 | 654 | */ |
| vladvana | 0:23d1f73bf130 | 655 | #define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) \ |
| vladvana | 0:23d1f73bf130 | 656 | ((_CHANNELNB_) << (POSITION_VAL(ADC_SQR1_SQ14) * ((_RANKNB_) - 13))) |
| vladvana | 0:23d1f73bf130 | 657 | |
| vladvana | 0:23d1f73bf130 | 658 | /** |
| vladvana | 0:23d1f73bf130 | 659 | * @brief Set the injected sequence length. |
| vladvana | 0:23d1f73bf130 | 660 | * @param _JSQR_JL_: Sequence length. |
| vladvana | 0:23d1f73bf130 | 661 | * @retval None |
| vladvana | 0:23d1f73bf130 | 662 | */ |
| vladvana | 0:23d1f73bf130 | 663 | #define ADC_JSQR_JL_SHIFT(_JSQR_JL_) \ |
| vladvana | 0:23d1f73bf130 | 664 | (((_JSQR_JL_) -1) << POSITION_VAL(ADC_JSQR_JL)) |
| vladvana | 0:23d1f73bf130 | 665 | |
| vladvana | 0:23d1f73bf130 | 666 | /** |
| vladvana | 0:23d1f73bf130 | 667 | * @brief Set the selected injected channel rank |
| vladvana | 0:23d1f73bf130 | 668 | * Note: on STM32F1 devices, channel rank position in JSQR register |
| vladvana | 0:23d1f73bf130 | 669 | * is depending on total number of ranks selected into |
| vladvana | 0:23d1f73bf130 | 670 | * injected sequencer (ranks sequence starting from 4-JL) |
| vladvana | 0:23d1f73bf130 | 671 | * @param _CHANNELNB_: Channel number. |
| vladvana | 0:23d1f73bf130 | 672 | * @param _RANKNB_: Rank number. |
| vladvana | 0:23d1f73bf130 | 673 | * @param _JSQR_JL_: Sequence length. |
| vladvana | 0:23d1f73bf130 | 674 | * @retval None |
| vladvana | 0:23d1f73bf130 | 675 | */ |
| vladvana | 0:23d1f73bf130 | 676 | #define ADC_JSQR_RK_JL(_CHANNELNB_, _RANKNB_, _JSQR_JL_) \ |
| vladvana | 0:23d1f73bf130 | 677 | ((_CHANNELNB_) << (POSITION_VAL(ADC_JSQR_JSQ2) * ((4 - ((_JSQR_JL_) - (_RANKNB_))) - 1))) |
| vladvana | 0:23d1f73bf130 | 678 | |
| vladvana | 0:23d1f73bf130 | 679 | /** |
| vladvana | 0:23d1f73bf130 | 680 | * @brief Enable ADC continuous conversion mode. |
| vladvana | 0:23d1f73bf130 | 681 | * @param _CONTINUOUS_MODE_: Continuous mode. |
| vladvana | 0:23d1f73bf130 | 682 | * @retval None |
| vladvana | 0:23d1f73bf130 | 683 | */ |
| vladvana | 0:23d1f73bf130 | 684 | #define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) \ |
| vladvana | 0:23d1f73bf130 | 685 | ((_CONTINUOUS_MODE_) << POSITION_VAL(ADC_CR2_CONT)) |
| vladvana | 0:23d1f73bf130 | 686 | |
| vladvana | 0:23d1f73bf130 | 687 | /** |
| vladvana | 0:23d1f73bf130 | 688 | * @brief Configures the number of discontinuous conversions for the regular group channels. |
| vladvana | 0:23d1f73bf130 | 689 | * @param _NBR_DISCONTINUOUS_CONV_: Number of discontinuous conversions. |
| vladvana | 0:23d1f73bf130 | 690 | * @retval None |
| vladvana | 0:23d1f73bf130 | 691 | */ |
| vladvana | 0:23d1f73bf130 | 692 | #define ADC_CR1_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) \ |
| vladvana | 0:23d1f73bf130 | 693 | (((_NBR_DISCONTINUOUS_CONV_) - 1) << POSITION_VAL(ADC_CR1_DISCNUM)) |
| vladvana | 0:23d1f73bf130 | 694 | |
| vladvana | 0:23d1f73bf130 | 695 | /** |
| vladvana | 0:23d1f73bf130 | 696 | * @brief Enable ADC scan mode to convert multiple ranks with sequencer. |
| vladvana | 0:23d1f73bf130 | 697 | * @param _SCAN_MODE_: Scan conversion mode. |
| vladvana | 0:23d1f73bf130 | 698 | * @retval None |
| vladvana | 0:23d1f73bf130 | 699 | */ |
| vladvana | 0:23d1f73bf130 | 700 | /* Note: Scan mode is compared to ENABLE for legacy purpose, this parameter */ |
| vladvana | 0:23d1f73bf130 | 701 | /* is equivalent to ADC_SCAN_ENABLE. */ |
| vladvana | 0:23d1f73bf130 | 702 | #define ADC_CR1_SCAN_SET(_SCAN_MODE_) \ |
| vladvana | 0:23d1f73bf130 | 703 | (( ((_SCAN_MODE_) == ADC_SCAN_ENABLE) || ((_SCAN_MODE_) == ENABLE) \ |
| vladvana | 0:23d1f73bf130 | 704 | )? (ADC_SCAN_ENABLE) : (ADC_SCAN_DISABLE) \ |
| vladvana | 0:23d1f73bf130 | 705 | ) |
| vladvana | 0:23d1f73bf130 | 706 | |
| vladvana | 0:23d1f73bf130 | 707 | /** |
| vladvana | 0:23d1f73bf130 | 708 | * @brief Get the maximum ADC conversion cycles on all channels. |
| vladvana | 0:23d1f73bf130 | 709 | * Returns the selected sampling time + conversion time (12.5 ADC clock cycles) |
| vladvana | 0:23d1f73bf130 | 710 | * Approximation of sampling time within 4 ranges, returns the highest value: |
| vladvana | 0:23d1f73bf130 | 711 | * below 7.5 cycles {1.5 cycle; 7.5 cycles}, |
| vladvana | 0:23d1f73bf130 | 712 | * between 13.5 cycles and 28.5 cycles {13.5 cycles; 28.5 cycles} |
| vladvana | 0:23d1f73bf130 | 713 | * between 41.5 cycles and 71.5 cycles {41.5 cycles; 55.5 cycles; 71.5cycles} |
| vladvana | 0:23d1f73bf130 | 714 | * equal to 239.5 cycles |
| vladvana | 0:23d1f73bf130 | 715 | * Unit: ADC clock cycles |
| vladvana | 0:23d1f73bf130 | 716 | * @param __HANDLE__: ADC handle |
| vladvana | 0:23d1f73bf130 | 717 | * @retval ADC conversion cycles on all channels |
| vladvana | 0:23d1f73bf130 | 718 | */ |
| vladvana | 0:23d1f73bf130 | 719 | #define ADC_CONVCYCLES_MAX_RANGE(__HANDLE__) \ |
| vladvana | 0:23d1f73bf130 | 720 | (( (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2) == RESET) && \ |
| vladvana | 0:23d1f73bf130 | 721 | (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2) == RESET) ) ? \ |
| vladvana | 0:23d1f73bf130 | 722 | \ |
| vladvana | 0:23d1f73bf130 | 723 | (( (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) == RESET) && \ |
| vladvana | 0:23d1f73bf130 | 724 | (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) == RESET) ) ? \ |
| vladvana | 0:23d1f73bf130 | 725 | ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5 : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5) \ |
| vladvana | 0:23d1f73bf130 | 726 | : \ |
| vladvana | 0:23d1f73bf130 | 727 | ((((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) == RESET) && \ |
| vladvana | 0:23d1f73bf130 | 728 | (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) == RESET)) || \ |
| vladvana | 0:23d1f73bf130 | 729 | ((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) == RESET) && \ |
| vladvana | 0:23d1f73bf130 | 730 | (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) == RESET))) ? \ |
| vladvana | 0:23d1f73bf130 | 731 | ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5 : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5) \ |
| vladvana | 0:23d1f73bf130 | 732 | ) |
| vladvana | 0:23d1f73bf130 | 733 | |
| vladvana | 0:23d1f73bf130 | 734 | #define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \ |
| vladvana | 0:23d1f73bf130 | 735 | ((ALIGN) == ADC_DATAALIGN_LEFT) ) |
| vladvana | 0:23d1f73bf130 | 736 | |
| vladvana | 0:23d1f73bf130 | 737 | #define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DISABLE) || \ |
| vladvana | 0:23d1f73bf130 | 738 | ((SCAN_MODE) == ADC_SCAN_ENABLE) ) |
| vladvana | 0:23d1f73bf130 | 739 | |
| vladvana | 0:23d1f73bf130 | 740 | #define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \ |
| vladvana | 0:23d1f73bf130 | 741 | ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) ) |
| vladvana | 0:23d1f73bf130 | 742 | |
| vladvana | 0:23d1f73bf130 | 743 | #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \ |
| vladvana | 0:23d1f73bf130 | 744 | ((CHANNEL) == ADC_CHANNEL_1) || \ |
| vladvana | 0:23d1f73bf130 | 745 | ((CHANNEL) == ADC_CHANNEL_2) || \ |
| vladvana | 0:23d1f73bf130 | 746 | ((CHANNEL) == ADC_CHANNEL_3) || \ |
| vladvana | 0:23d1f73bf130 | 747 | ((CHANNEL) == ADC_CHANNEL_4) || \ |
| vladvana | 0:23d1f73bf130 | 748 | ((CHANNEL) == ADC_CHANNEL_5) || \ |
| vladvana | 0:23d1f73bf130 | 749 | ((CHANNEL) == ADC_CHANNEL_6) || \ |
| vladvana | 0:23d1f73bf130 | 750 | ((CHANNEL) == ADC_CHANNEL_7) || \ |
| vladvana | 0:23d1f73bf130 | 751 | ((CHANNEL) == ADC_CHANNEL_8) || \ |
| vladvana | 0:23d1f73bf130 | 752 | ((CHANNEL) == ADC_CHANNEL_9) || \ |
| vladvana | 0:23d1f73bf130 | 753 | ((CHANNEL) == ADC_CHANNEL_10) || \ |
| vladvana | 0:23d1f73bf130 | 754 | ((CHANNEL) == ADC_CHANNEL_11) || \ |
| vladvana | 0:23d1f73bf130 | 755 | ((CHANNEL) == ADC_CHANNEL_12) || \ |
| vladvana | 0:23d1f73bf130 | 756 | ((CHANNEL) == ADC_CHANNEL_13) || \ |
| vladvana | 0:23d1f73bf130 | 757 | ((CHANNEL) == ADC_CHANNEL_14) || \ |
| vladvana | 0:23d1f73bf130 | 758 | ((CHANNEL) == ADC_CHANNEL_15) || \ |
| vladvana | 0:23d1f73bf130 | 759 | ((CHANNEL) == ADC_CHANNEL_16) || \ |
| vladvana | 0:23d1f73bf130 | 760 | ((CHANNEL) == ADC_CHANNEL_17) ) |
| vladvana | 0:23d1f73bf130 | 761 | |
| vladvana | 0:23d1f73bf130 | 762 | #define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5) || \ |
| vladvana | 0:23d1f73bf130 | 763 | ((TIME) == ADC_SAMPLETIME_7CYCLES_5) || \ |
| vladvana | 0:23d1f73bf130 | 764 | ((TIME) == ADC_SAMPLETIME_13CYCLES_5) || \ |
| vladvana | 0:23d1f73bf130 | 765 | ((TIME) == ADC_SAMPLETIME_28CYCLES_5) || \ |
| vladvana | 0:23d1f73bf130 | 766 | ((TIME) == ADC_SAMPLETIME_41CYCLES_5) || \ |
| vladvana | 0:23d1f73bf130 | 767 | ((TIME) == ADC_SAMPLETIME_55CYCLES_5) || \ |
| vladvana | 0:23d1f73bf130 | 768 | ((TIME) == ADC_SAMPLETIME_71CYCLES_5) || \ |
| vladvana | 0:23d1f73bf130 | 769 | ((TIME) == ADC_SAMPLETIME_239CYCLES_5) ) |
| vladvana | 0:23d1f73bf130 | 770 | |
| vladvana | 0:23d1f73bf130 | 771 | #define IS_ADC_REGULAR_RANK(CHANNEL) (((CHANNEL) == ADC_REGULAR_RANK_1 ) || \ |
| vladvana | 0:23d1f73bf130 | 772 | ((CHANNEL) == ADC_REGULAR_RANK_2 ) || \ |
| vladvana | 0:23d1f73bf130 | 773 | ((CHANNEL) == ADC_REGULAR_RANK_3 ) || \ |
| vladvana | 0:23d1f73bf130 | 774 | ((CHANNEL) == ADC_REGULAR_RANK_4 ) || \ |
| vladvana | 0:23d1f73bf130 | 775 | ((CHANNEL) == ADC_REGULAR_RANK_5 ) || \ |
| vladvana | 0:23d1f73bf130 | 776 | ((CHANNEL) == ADC_REGULAR_RANK_6 ) || \ |
| vladvana | 0:23d1f73bf130 | 777 | ((CHANNEL) == ADC_REGULAR_RANK_7 ) || \ |
| vladvana | 0:23d1f73bf130 | 778 | ((CHANNEL) == ADC_REGULAR_RANK_8 ) || \ |
| vladvana | 0:23d1f73bf130 | 779 | ((CHANNEL) == ADC_REGULAR_RANK_9 ) || \ |
| vladvana | 0:23d1f73bf130 | 780 | ((CHANNEL) == ADC_REGULAR_RANK_10) || \ |
| vladvana | 0:23d1f73bf130 | 781 | ((CHANNEL) == ADC_REGULAR_RANK_11) || \ |
| vladvana | 0:23d1f73bf130 | 782 | ((CHANNEL) == ADC_REGULAR_RANK_12) || \ |
| vladvana | 0:23d1f73bf130 | 783 | ((CHANNEL) == ADC_REGULAR_RANK_13) || \ |
| vladvana | 0:23d1f73bf130 | 784 | ((CHANNEL) == ADC_REGULAR_RANK_14) || \ |
| vladvana | 0:23d1f73bf130 | 785 | ((CHANNEL) == ADC_REGULAR_RANK_15) || \ |
| vladvana | 0:23d1f73bf130 | 786 | ((CHANNEL) == ADC_REGULAR_RANK_16) ) |
| vladvana | 0:23d1f73bf130 | 787 | |
| vladvana | 0:23d1f73bf130 | 788 | #define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE) || \ |
| vladvana | 0:23d1f73bf130 | 789 | ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \ |
| vladvana | 0:23d1f73bf130 | 790 | ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \ |
| vladvana | 0:23d1f73bf130 | 791 | ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \ |
| vladvana | 0:23d1f73bf130 | 792 | ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) || \ |
| vladvana | 0:23d1f73bf130 | 793 | ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \ |
| vladvana | 0:23d1f73bf130 | 794 | ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) ) |
| vladvana | 0:23d1f73bf130 | 795 | |
| vladvana | 0:23d1f73bf130 | 796 | #define IS_ADC_CONVERSION_GROUP(CONVERSION) (((CONVERSION) == ADC_REGULAR_GROUP) || \ |
| vladvana | 0:23d1f73bf130 | 797 | ((CONVERSION) == ADC_INJECTED_GROUP) || \ |
| vladvana | 0:23d1f73bf130 | 798 | ((CONVERSION) == ADC_REGULAR_INJECTED_GROUP) ) |
| vladvana | 0:23d1f73bf130 | 799 | |
| vladvana | 0:23d1f73bf130 | 800 | #define IS_ADC_EVENT_TYPE(EVENT) ((EVENT) == ADC_AWD_EVENT) |
| vladvana | 0:23d1f73bf130 | 801 | |
| vladvana | 0:23d1f73bf130 | 802 | |
| vladvana | 0:23d1f73bf130 | 803 | /** @defgroup ADC_range_verification ADC range verification |
| vladvana | 0:23d1f73bf130 | 804 | * For a unique ADC resolution: 12 bits |
| vladvana | 0:23d1f73bf130 | 805 | * @{ |
| vladvana | 0:23d1f73bf130 | 806 | */ |
| vladvana | 0:23d1f73bf130 | 807 | #define IS_ADC_RANGE(ADC_VALUE) ((ADC_VALUE) <= ((uint32_t)0x0FFF)) |
| vladvana | 0:23d1f73bf130 | 808 | /** |
| vladvana | 0:23d1f73bf130 | 809 | * @} |
| vladvana | 0:23d1f73bf130 | 810 | */ |
| vladvana | 0:23d1f73bf130 | 811 | |
| vladvana | 0:23d1f73bf130 | 812 | /** @defgroup ADC_regular_nb_conv_verification ADC regular nb conv verification |
| vladvana | 0:23d1f73bf130 | 813 | * @{ |
| vladvana | 0:23d1f73bf130 | 814 | */ |
| vladvana | 0:23d1f73bf130 | 815 | #define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)16))) |
| vladvana | 0:23d1f73bf130 | 816 | /** |
| vladvana | 0:23d1f73bf130 | 817 | * @} |
| vladvana | 0:23d1f73bf130 | 818 | */ |
| vladvana | 0:23d1f73bf130 | 819 | |
| vladvana | 0:23d1f73bf130 | 820 | /** @defgroup ADC_regular_discontinuous_mode_number_verification ADC regular discontinuous mode number verification |
| vladvana | 0:23d1f73bf130 | 821 | * @{ |
| vladvana | 0:23d1f73bf130 | 822 | */ |
| vladvana | 0:23d1f73bf130 | 823 | #define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= ((uint32_t)1)) && ((NUMBER) <= ((uint32_t)8))) |
| vladvana | 0:23d1f73bf130 | 824 | /** |
| vladvana | 0:23d1f73bf130 | 825 | * @} |
| vladvana | 0:23d1f73bf130 | 826 | */ |
| vladvana | 0:23d1f73bf130 | 827 | |
| vladvana | 0:23d1f73bf130 | 828 | /** |
| vladvana | 0:23d1f73bf130 | 829 | * @} |
| vladvana | 0:23d1f73bf130 | 830 | */ |
| vladvana | 0:23d1f73bf130 | 831 | |
| vladvana | 0:23d1f73bf130 | 832 | /* Include ADC HAL Extension module */ |
| vladvana | 0:23d1f73bf130 | 833 | #include "stm32f1xx_hal_adc_ex.h" |
| vladvana | 0:23d1f73bf130 | 834 | |
| vladvana | 0:23d1f73bf130 | 835 | /* Exported functions --------------------------------------------------------*/ |
| vladvana | 0:23d1f73bf130 | 836 | /** @addtogroup ADC_Exported_Functions |
| vladvana | 0:23d1f73bf130 | 837 | * @{ |
| vladvana | 0:23d1f73bf130 | 838 | */ |
| vladvana | 0:23d1f73bf130 | 839 | |
| vladvana | 0:23d1f73bf130 | 840 | /** @addtogroup ADC_Exported_Functions_Group1 |
| vladvana | 0:23d1f73bf130 | 841 | * @{ |
| vladvana | 0:23d1f73bf130 | 842 | */ |
| vladvana | 0:23d1f73bf130 | 843 | |
| vladvana | 0:23d1f73bf130 | 844 | |
| vladvana | 0:23d1f73bf130 | 845 | /* Initialization and de-initialization functions **********************************/ |
| vladvana | 0:23d1f73bf130 | 846 | HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc); |
| vladvana | 0:23d1f73bf130 | 847 | HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc); |
| vladvana | 0:23d1f73bf130 | 848 | void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc); |
| vladvana | 0:23d1f73bf130 | 849 | void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc); |
| vladvana | 0:23d1f73bf130 | 850 | /** |
| vladvana | 0:23d1f73bf130 | 851 | * @} |
| vladvana | 0:23d1f73bf130 | 852 | */ |
| vladvana | 0:23d1f73bf130 | 853 | |
| vladvana | 0:23d1f73bf130 | 854 | /* IO operation functions *****************************************************/ |
| vladvana | 0:23d1f73bf130 | 855 | |
| vladvana | 0:23d1f73bf130 | 856 | /** @addtogroup ADC_Exported_Functions_Group2 |
| vladvana | 0:23d1f73bf130 | 857 | * @{ |
| vladvana | 0:23d1f73bf130 | 858 | */ |
| vladvana | 0:23d1f73bf130 | 859 | |
| vladvana | 0:23d1f73bf130 | 860 | |
| vladvana | 0:23d1f73bf130 | 861 | /* Blocking mode: Polling */ |
| vladvana | 0:23d1f73bf130 | 862 | HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc); |
| vladvana | 0:23d1f73bf130 | 863 | HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc); |
| vladvana | 0:23d1f73bf130 | 864 | HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout); |
| vladvana | 0:23d1f73bf130 | 865 | HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout); |
| vladvana | 0:23d1f73bf130 | 866 | |
| vladvana | 0:23d1f73bf130 | 867 | /* Non-blocking mode: Interruption */ |
| vladvana | 0:23d1f73bf130 | 868 | HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc); |
| vladvana | 0:23d1f73bf130 | 869 | HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc); |
| vladvana | 0:23d1f73bf130 | 870 | |
| vladvana | 0:23d1f73bf130 | 871 | /* Non-blocking mode: DMA */ |
| vladvana | 0:23d1f73bf130 | 872 | HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length); |
| vladvana | 0:23d1f73bf130 | 873 | HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc); |
| vladvana | 0:23d1f73bf130 | 874 | |
| vladvana | 0:23d1f73bf130 | 875 | /* ADC retrieve conversion value intended to be used with polling or interruption */ |
| vladvana | 0:23d1f73bf130 | 876 | uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc); |
| vladvana | 0:23d1f73bf130 | 877 | |
| vladvana | 0:23d1f73bf130 | 878 | /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */ |
| vladvana | 0:23d1f73bf130 | 879 | void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc); |
| vladvana | 0:23d1f73bf130 | 880 | void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc); |
| vladvana | 0:23d1f73bf130 | 881 | void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc); |
| vladvana | 0:23d1f73bf130 | 882 | void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc); |
| vladvana | 0:23d1f73bf130 | 883 | void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); |
| vladvana | 0:23d1f73bf130 | 884 | /** |
| vladvana | 0:23d1f73bf130 | 885 | * @} |
| vladvana | 0:23d1f73bf130 | 886 | */ |
| vladvana | 0:23d1f73bf130 | 887 | |
| vladvana | 0:23d1f73bf130 | 888 | |
| vladvana | 0:23d1f73bf130 | 889 | /* Peripheral Control functions ***********************************************/ |
| vladvana | 0:23d1f73bf130 | 890 | /** @addtogroup ADC_Exported_Functions_Group3 |
| vladvana | 0:23d1f73bf130 | 891 | * @{ |
| vladvana | 0:23d1f73bf130 | 892 | */ |
| vladvana | 0:23d1f73bf130 | 893 | HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig); |
| vladvana | 0:23d1f73bf130 | 894 | HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig); |
| vladvana | 0:23d1f73bf130 | 895 | /** |
| vladvana | 0:23d1f73bf130 | 896 | * @} |
| vladvana | 0:23d1f73bf130 | 897 | */ |
| vladvana | 0:23d1f73bf130 | 898 | |
| vladvana | 0:23d1f73bf130 | 899 | |
| vladvana | 0:23d1f73bf130 | 900 | /* Peripheral State functions *************************************************/ |
| vladvana | 0:23d1f73bf130 | 901 | /** @addtogroup ADC_Exported_Functions_Group4 |
| vladvana | 0:23d1f73bf130 | 902 | * @{ |
| vladvana | 0:23d1f73bf130 | 903 | */ |
| vladvana | 0:23d1f73bf130 | 904 | HAL_ADC_StateTypeDef HAL_ADC_GetState(ADC_HandleTypeDef* hadc); |
| vladvana | 0:23d1f73bf130 | 905 | uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); |
| vladvana | 0:23d1f73bf130 | 906 | /** |
| vladvana | 0:23d1f73bf130 | 907 | * @} |
| vladvana | 0:23d1f73bf130 | 908 | */ |
| vladvana | 0:23d1f73bf130 | 909 | |
| vladvana | 0:23d1f73bf130 | 910 | |
| vladvana | 0:23d1f73bf130 | 911 | /** |
| vladvana | 0:23d1f73bf130 | 912 | * @} |
| vladvana | 0:23d1f73bf130 | 913 | */ |
| vladvana | 0:23d1f73bf130 | 914 | |
| vladvana | 0:23d1f73bf130 | 915 | |
| vladvana | 0:23d1f73bf130 | 916 | /* Internal HAL driver functions **********************************************/ |
| vladvana | 0:23d1f73bf130 | 917 | /** @addtogroup ADC_Private_Functions |
| vladvana | 0:23d1f73bf130 | 918 | * @{ |
| vladvana | 0:23d1f73bf130 | 919 | */ |
| vladvana | 0:23d1f73bf130 | 920 | HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc); |
| vladvana | 0:23d1f73bf130 | 921 | HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc); |
| vladvana | 0:23d1f73bf130 | 922 | void ADC_StabilizationTime(uint32_t DelayUs); |
| vladvana | 0:23d1f73bf130 | 923 | void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma); |
| vladvana | 0:23d1f73bf130 | 924 | void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma); |
| vladvana | 0:23d1f73bf130 | 925 | void ADC_DMAError(DMA_HandleTypeDef *hdma); |
| vladvana | 0:23d1f73bf130 | 926 | /** |
| vladvana | 0:23d1f73bf130 | 927 | * @} |
| vladvana | 0:23d1f73bf130 | 928 | */ |
| vladvana | 0:23d1f73bf130 | 929 | |
| vladvana | 0:23d1f73bf130 | 930 | |
| vladvana | 0:23d1f73bf130 | 931 | /** |
| vladvana | 0:23d1f73bf130 | 932 | * @} |
| vladvana | 0:23d1f73bf130 | 933 | */ |
| vladvana | 0:23d1f73bf130 | 934 | |
| vladvana | 0:23d1f73bf130 | 935 | /** |
| vladvana | 0:23d1f73bf130 | 936 | * @} |
| vladvana | 0:23d1f73bf130 | 937 | */ |
| vladvana | 0:23d1f73bf130 | 938 | |
| vladvana | 0:23d1f73bf130 | 939 | #ifdef __cplusplus |
| vladvana | 0:23d1f73bf130 | 940 | } |
| vladvana | 0:23d1f73bf130 | 941 | #endif |
| vladvana | 0:23d1f73bf130 | 942 | |
| vladvana | 0:23d1f73bf130 | 943 | |
| vladvana | 0:23d1f73bf130 | 944 | #endif /* __STM32F1xx_HAL_ADC_H */ |
| vladvana | 0:23d1f73bf130 | 945 | |
| vladvana | 0:23d1f73bf130 | 946 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |