Vladimir Vana / mbed

pro vyuku PSS v Jecne

TARGET_NUCLEO_F103RB/stm32f1xx_hal.h@0:23d1f73bf130, 2017-09-24 (annotated)

Committer:
vladvana
Date:
Sun Sep 24 12:31:52 2017 +0000
Revision:
0:23d1f73bf130
podklady pro cviceni z PSS

Who changed what in which revision?

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vladvana 0:23d1f73bf130 1 /**
vladvana 0:23d1f73bf130 2 ******************************************************************************
vladvana 0:23d1f73bf130 3 * @file stm32f1xx_hal.h
vladvana 0:23d1f73bf130 4 * @author MCD Application Team
vladvana 0:23d1f73bf130 5 * @version V1.0.0
vladvana 0:23d1f73bf130 6 * @date 15-December-2014
vladvana 0:23d1f73bf130 7 * @brief This file contains all the functions prototypes for the HAL
vladvana 0:23d1f73bf130 8 * module driver.
vladvana 0:23d1f73bf130 9 ******************************************************************************
vladvana 0:23d1f73bf130 10 * @attention
vladvana 0:23d1f73bf130 11 *
vladvana 0:23d1f73bf130 12 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
vladvana 0:23d1f73bf130 13 *
vladvana 0:23d1f73bf130 14 * Redistribution and use in source and binary forms, with or without modification,
vladvana 0:23d1f73bf130 15 * are permitted provided that the following conditions are met:
vladvana 0:23d1f73bf130 16 * 1. Redistributions of source code must retain the above copyright notice,
vladvana 0:23d1f73bf130 17 * this list of conditions and the following disclaimer.
vladvana 0:23d1f73bf130 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
vladvana 0:23d1f73bf130 19 * this list of conditions and the following disclaimer in the documentation
vladvana 0:23d1f73bf130 20 * and/or other materials provided with the distribution.
vladvana 0:23d1f73bf130 21 * 3. Neither the name of STMicroelectronics nor the names of its contributors
vladvana 0:23d1f73bf130 22 * may be used to endorse or promote products derived from this software
vladvana 0:23d1f73bf130 23 * without specific prior written permission.
vladvana 0:23d1f73bf130 24 *
vladvana 0:23d1f73bf130 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
vladvana 0:23d1f73bf130 26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
vladvana 0:23d1f73bf130 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
vladvana 0:23d1f73bf130 28 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
vladvana 0:23d1f73bf130 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
vladvana 0:23d1f73bf130 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
vladvana 0:23d1f73bf130 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
vladvana 0:23d1f73bf130 32 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
vladvana 0:23d1f73bf130 33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
vladvana 0:23d1f73bf130 34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
vladvana 0:23d1f73bf130 35 *
vladvana 0:23d1f73bf130 36 ******************************************************************************
vladvana 0:23d1f73bf130 37 */
vladvana 0:23d1f73bf130 38
vladvana 0:23d1f73bf130 39 /* Define to prevent recursive inclusion -------------------------------------*/
vladvana 0:23d1f73bf130 40 #ifndef __STM32F1xx_HAL_H
vladvana 0:23d1f73bf130 41 #define __STM32F1xx_HAL_H
vladvana 0:23d1f73bf130 42
vladvana 0:23d1f73bf130 43 #ifdef __cplusplus
vladvana 0:23d1f73bf130 44 extern "C" {
vladvana 0:23d1f73bf130 45 #endif
vladvana 0:23d1f73bf130 46
vladvana 0:23d1f73bf130 47 /* Includes ------------------------------------------------------------------*/
vladvana 0:23d1f73bf130 48 #include "stm32f1xx_hal_conf.h"
vladvana 0:23d1f73bf130 49
vladvana 0:23d1f73bf130 50 /** @addtogroup STM32F1xx_HAL_Driver
vladvana 0:23d1f73bf130 51 * @{
vladvana 0:23d1f73bf130 52 */
vladvana 0:23d1f73bf130 53
vladvana 0:23d1f73bf130 54 /** @addtogroup HAL
vladvana 0:23d1f73bf130 55 * @{
vladvana 0:23d1f73bf130 56 */
vladvana 0:23d1f73bf130 57
vladvana 0:23d1f73bf130 58 /* Exported types ------------------------------------------------------------*/
vladvana 0:23d1f73bf130 59 /* Exported constants --------------------------------------------------------*/
vladvana 0:23d1f73bf130 60
vladvana 0:23d1f73bf130 61 /* Exported macro ------------------------------------------------------------*/
vladvana 0:23d1f73bf130 62
vladvana 0:23d1f73bf130 63 /** @defgroup HAL_Exported_Macros HAL Exported Macros
vladvana 0:23d1f73bf130 64 * @{
vladvana 0:23d1f73bf130 65 */
vladvana 0:23d1f73bf130 66
vladvana 0:23d1f73bf130 67 /** @defgroup DBGMCU_Freeze_Unfreeze Freeze Unfreeze Peripherals in Debug mode
vladvana 0:23d1f73bf130 68 * @brief Freeze/Unfreeze Peripherals in Debug mode
vladvana 0:23d1f73bf130 69 * Note: On devices STM32F10xx8 and STM32F10xxB,
vladvana 0:23d1f73bf130 70 * STM32F101xC/D/E and STM32F103xC/D/E,
vladvana 0:23d1f73bf130 71 * STM32F101xF/G and STM32F103xF/G
vladvana 0:23d1f73bf130 72 * STM32F10xx4 and STM32F10xx6
vladvana 0:23d1f73bf130 73 * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in
vladvana 0:23d1f73bf130 74 * debug mode (not accessible by the user software in normal mode).
vladvana 0:23d1f73bf130 75 * Refer to errata sheet of these devices for more details.
vladvana 0:23d1f73bf130 76 * @{
vladvana 0:23d1f73bf130 77 */
vladvana 0:23d1f73bf130 78
vladvana 0:23d1f73bf130 79 /* Peripherals on APB1 */
vladvana 0:23d1f73bf130 80 /**
vladvana 0:23d1f73bf130 81 * @brief TIM2 Peripherals Debug mode
vladvana 0:23d1f73bf130 82 */
vladvana 0:23d1f73bf130 83 #define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP)
vladvana 0:23d1f73bf130 84 #define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP)
vladvana 0:23d1f73bf130 85
vladvana 0:23d1f73bf130 86 /**
vladvana 0:23d1f73bf130 87 * @brief TIM3 Peripherals Debug mode
vladvana 0:23d1f73bf130 88 */
vladvana 0:23d1f73bf130 89 #define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP)
vladvana 0:23d1f73bf130 90 #define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP)
vladvana 0:23d1f73bf130 91
vladvana 0:23d1f73bf130 92 #if defined (DBGMCU_CR_DBG_TIM4_STOP)
vladvana 0:23d1f73bf130 93 /**
vladvana 0:23d1f73bf130 94 * @brief TIM4 Peripherals Debug mode
vladvana 0:23d1f73bf130 95 */
vladvana 0:23d1f73bf130 96 #define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP)
vladvana 0:23d1f73bf130 97 #define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP)
vladvana 0:23d1f73bf130 98 #endif
vladvana 0:23d1f73bf130 99
vladvana 0:23d1f73bf130 100 #if defined (DBGMCU_CR_DBG_TIM5_STOP)
vladvana 0:23d1f73bf130 101 /**
vladvana 0:23d1f73bf130 102 * @brief TIM5 Peripherals Debug mode
vladvana 0:23d1f73bf130 103 */
vladvana 0:23d1f73bf130 104 #define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM5_STOP)
vladvana 0:23d1f73bf130 105 #define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM5_STOP)
vladvana 0:23d1f73bf130 106 #endif
vladvana 0:23d1f73bf130 107
vladvana 0:23d1f73bf130 108 #if defined (DBGMCU_CR_DBG_TIM6_STOP)
vladvana 0:23d1f73bf130 109 /**
vladvana 0:23d1f73bf130 110 * @brief TIM6 Peripherals Debug mode
vladvana 0:23d1f73bf130 111 */
vladvana 0:23d1f73bf130 112 #define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM6_STOP)
vladvana 0:23d1f73bf130 113 #define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM6_STOP)
vladvana 0:23d1f73bf130 114 #endif
vladvana 0:23d1f73bf130 115
vladvana 0:23d1f73bf130 116 #if defined (DBGMCU_CR_DBG_TIM7_STOP)
vladvana 0:23d1f73bf130 117 /**
vladvana 0:23d1f73bf130 118 * @brief TIM7 Peripherals Debug mode
vladvana 0:23d1f73bf130 119 */
vladvana 0:23d1f73bf130 120 #define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM7_STOP)
vladvana 0:23d1f73bf130 121 #define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM7_STOP)
vladvana 0:23d1f73bf130 122 #endif
vladvana 0:23d1f73bf130 123
vladvana 0:23d1f73bf130 124 #if defined (DBGMCU_CR_DBG_TIM12_STOP)
vladvana 0:23d1f73bf130 125 /**
vladvana 0:23d1f73bf130 126 * @brief TIM12 Peripherals Debug mode
vladvana 0:23d1f73bf130 127 */
vladvana 0:23d1f73bf130 128 #define __HAL_DBGMCU_FREEZE_TIM12() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM12_STOP)
vladvana 0:23d1f73bf130 129 #define __HAL_DBGMCU_UNFREEZE_TIM12() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM12_STOP)
vladvana 0:23d1f73bf130 130 #endif
vladvana 0:23d1f73bf130 131
vladvana 0:23d1f73bf130 132 #if defined (DBGMCU_CR_DBG_TIM13_STOP)
vladvana 0:23d1f73bf130 133 /**
vladvana 0:23d1f73bf130 134 * @brief TIM13 Peripherals Debug mode
vladvana 0:23d1f73bf130 135 */
vladvana 0:23d1f73bf130 136 #define __HAL_DBGMCU_FREEZE_TIM13() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM13_STOP)
vladvana 0:23d1f73bf130 137 #define __HAL_DBGMCU_UNFREEZE_TIM13() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM13_STOP)
vladvana 0:23d1f73bf130 138 #endif
vladvana 0:23d1f73bf130 139
vladvana 0:23d1f73bf130 140 #if defined (DBGMCU_CR_DBG_TIM14_STOP)
vladvana 0:23d1f73bf130 141 /**
vladvana 0:23d1f73bf130 142 * @brief TIM14 Peripherals Debug mode
vladvana 0:23d1f73bf130 143 */
vladvana 0:23d1f73bf130 144 #define __HAL_DBGMCU_FREEZE_TIM14() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM14_STOP)
vladvana 0:23d1f73bf130 145 #define __HAL_DBGMCU_UNFREEZE_TIM14() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM14_STOP)
vladvana 0:23d1f73bf130 146 #endif
vladvana 0:23d1f73bf130 147
vladvana 0:23d1f73bf130 148 /**
vladvana 0:23d1f73bf130 149 * @brief WWDG Peripherals Debug mode
vladvana 0:23d1f73bf130 150 */
vladvana 0:23d1f73bf130 151 #define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP)
vladvana 0:23d1f73bf130 152 #define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP)
vladvana 0:23d1f73bf130 153
vladvana 0:23d1f73bf130 154 /**
vladvana 0:23d1f73bf130 155 * @brief IWDG Peripherals Debug mode
vladvana 0:23d1f73bf130 156 */
vladvana 0:23d1f73bf130 157 #define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP)
vladvana 0:23d1f73bf130 158 #define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP)
vladvana 0:23d1f73bf130 159
vladvana 0:23d1f73bf130 160 /**
vladvana 0:23d1f73bf130 161 * @brief I2C1 Peripherals Debug mode
vladvana 0:23d1f73bf130 162 */
vladvana 0:23d1f73bf130 163 #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT)
vladvana 0:23d1f73bf130 164 #define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT)
vladvana 0:23d1f73bf130 165
vladvana 0:23d1f73bf130 166 #if defined (DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)
vladvana 0:23d1f73bf130 167 /**
vladvana 0:23d1f73bf130 168 * @brief I2C2 Peripherals Debug mode
vladvana 0:23d1f73bf130 169 */
vladvana 0:23d1f73bf130 170 #define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)
vladvana 0:23d1f73bf130 171 #define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)
vladvana 0:23d1f73bf130 172 #endif
vladvana 0:23d1f73bf130 173
vladvana 0:23d1f73bf130 174 #if defined (DBGMCU_CR_DBG_CAN1_STOP)
vladvana 0:23d1f73bf130 175 /**
vladvana 0:23d1f73bf130 176 * @brief CAN1 Peripherals Debug mode
vladvana 0:23d1f73bf130 177 */
vladvana 0:23d1f73bf130 178 #define __HAL_DBGMCU_FREEZE_CAN1() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP)
vladvana 0:23d1f73bf130 179 #define __HAL_DBGMCU_UNFREEZE_CAN1() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP)
vladvana 0:23d1f73bf130 180 #endif
vladvana 0:23d1f73bf130 181
vladvana 0:23d1f73bf130 182 #if defined (DBGMCU_CR_DBG_CAN2_STOP)
vladvana 0:23d1f73bf130 183 /**
vladvana 0:23d1f73bf130 184 * @brief CAN2 Peripherals Debug mode
vladvana 0:23d1f73bf130 185 */
vladvana 0:23d1f73bf130 186 #define __HAL_DBGMCU_FREEZE_CAN2() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN2_STOP)
vladvana 0:23d1f73bf130 187 #define __HAL_DBGMCU_UNFREEZE_CAN2() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN2_STOP)
vladvana 0:23d1f73bf130 188 #endif
vladvana 0:23d1f73bf130 189
vladvana 0:23d1f73bf130 190 /* Peripherals on APB2 */
vladvana 0:23d1f73bf130 191 #if defined (DBGMCU_CR_DBG_TIM1_STOP)
vladvana 0:23d1f73bf130 192 /**
vladvana 0:23d1f73bf130 193 * @brief TIM1 Peripherals Debug mode
vladvana 0:23d1f73bf130 194 */
vladvana 0:23d1f73bf130 195 #define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP)
vladvana 0:23d1f73bf130 196 #define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP)
vladvana 0:23d1f73bf130 197 #endif
vladvana 0:23d1f73bf130 198
vladvana 0:23d1f73bf130 199 #if defined (DBGMCU_CR_DBG_TIM8_STOP)
vladvana 0:23d1f73bf130 200 /**
vladvana 0:23d1f73bf130 201 * @brief TIM8 Peripherals Debug mode
vladvana 0:23d1f73bf130 202 */
vladvana 0:23d1f73bf130 203 #define __HAL_DBGMCU_FREEZE_TIM8() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM8_STOP)
vladvana 0:23d1f73bf130 204 #define __HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM8_STOP)
vladvana 0:23d1f73bf130 205 #endif
vladvana 0:23d1f73bf130 206
vladvana 0:23d1f73bf130 207 #if defined (DBGMCU_CR_DBG_TIM9_STOP)
vladvana 0:23d1f73bf130 208 /**
vladvana 0:23d1f73bf130 209 * @brief TIM9 Peripherals Debug mode
vladvana 0:23d1f73bf130 210 */
vladvana 0:23d1f73bf130 211 #define __HAL_DBGMCU_FREEZE_TIM9() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM9_STOP)
vladvana 0:23d1f73bf130 212 #define __HAL_DBGMCU_UNFREEZE_TIM9() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM9_STOP)
vladvana 0:23d1f73bf130 213 #endif
vladvana 0:23d1f73bf130 214
vladvana 0:23d1f73bf130 215 #if defined (DBGMCU_CR_DBG_TIM10_STOP)
vladvana 0:23d1f73bf130 216 /**
vladvana 0:23d1f73bf130 217 * @brief TIM10 Peripherals Debug mode
vladvana 0:23d1f73bf130 218 */
vladvana 0:23d1f73bf130 219 #define __HAL_DBGMCU_FREEZE_TIM10() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM10_STOP)
vladvana 0:23d1f73bf130 220 #define __HAL_DBGMCU_UNFREEZE_TIM10() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM10_STOP)
vladvana 0:23d1f73bf130 221 #endif
vladvana 0:23d1f73bf130 222
vladvana 0:23d1f73bf130 223 #if defined (DBGMCU_CR_DBG_TIM11_STOP)
vladvana 0:23d1f73bf130 224 /**
vladvana 0:23d1f73bf130 225 * @brief TIM11 Peripherals Debug mode
vladvana 0:23d1f73bf130 226 */
vladvana 0:23d1f73bf130 227 #define __HAL_DBGMCU_FREEZE_TIM11() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM11_STOP)
vladvana 0:23d1f73bf130 228 #define __HAL_DBGMCU_UNFREEZE_TIM11() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM11_STOP)
vladvana 0:23d1f73bf130 229 #endif
vladvana 0:23d1f73bf130 230
vladvana 0:23d1f73bf130 231
vladvana 0:23d1f73bf130 232 #if defined (DBGMCU_CR_DBG_TIM15_STOP)
vladvana 0:23d1f73bf130 233 /**
vladvana 0:23d1f73bf130 234 * @brief TIM15 Peripherals Debug mode
vladvana 0:23d1f73bf130 235 */
vladvana 0:23d1f73bf130 236 #define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM15_STOP)
vladvana 0:23d1f73bf130 237 #define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM15_STOP)
vladvana 0:23d1f73bf130 238 #endif
vladvana 0:23d1f73bf130 239
vladvana 0:23d1f73bf130 240 #if defined (DBGMCU_CR_DBG_TIM16_STOP)
vladvana 0:23d1f73bf130 241 /**
vladvana 0:23d1f73bf130 242 * @brief TIM16 Peripherals Debug mode
vladvana 0:23d1f73bf130 243 */
vladvana 0:23d1f73bf130 244 #define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM16_STOP)
vladvana 0:23d1f73bf130 245 #define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM16_STOP)
vladvana 0:23d1f73bf130 246 #endif
vladvana 0:23d1f73bf130 247
vladvana 0:23d1f73bf130 248 #if defined (DBGMCU_CR_DBG_TIM17_STOP)
vladvana 0:23d1f73bf130 249 /**
vladvana 0:23d1f73bf130 250 * @brief TIM17 Peripherals Debug mode
vladvana 0:23d1f73bf130 251 */
vladvana 0:23d1f73bf130 252 #define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM17_STOP)
vladvana 0:23d1f73bf130 253 #define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM17_STOP)
vladvana 0:23d1f73bf130 254 #endif
vladvana 0:23d1f73bf130 255
vladvana 0:23d1f73bf130 256 /**
vladvana 0:23d1f73bf130 257 * @}
vladvana 0:23d1f73bf130 258 */
vladvana 0:23d1f73bf130 259
vladvana 0:23d1f73bf130 260 /**
vladvana 0:23d1f73bf130 261 * @}
vladvana 0:23d1f73bf130 262 */
vladvana 0:23d1f73bf130 263
vladvana 0:23d1f73bf130 264 /* Exported functions --------------------------------------------------------*/
vladvana 0:23d1f73bf130 265
vladvana 0:23d1f73bf130 266 /** @addtogroup HAL_Exported_Functions
vladvana 0:23d1f73bf130 267 * @{
vladvana 0:23d1f73bf130 268 */
vladvana 0:23d1f73bf130 269
vladvana 0:23d1f73bf130 270 /** @addtogroup HAL_Exported_Functions_Group1
vladvana 0:23d1f73bf130 271 * @{
vladvana 0:23d1f73bf130 272 */
vladvana 0:23d1f73bf130 273
vladvana 0:23d1f73bf130 274 /* Initialization and de-initialization functions ******************************/
vladvana 0:23d1f73bf130 275 HAL_StatusTypeDef HAL_Init(void);
vladvana 0:23d1f73bf130 276 HAL_StatusTypeDef HAL_DeInit(void);
vladvana 0:23d1f73bf130 277 void HAL_MspInit(void);
vladvana 0:23d1f73bf130 278 void HAL_MspDeInit(void);
vladvana 0:23d1f73bf130 279 HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
vladvana 0:23d1f73bf130 280
vladvana 0:23d1f73bf130 281 /**
vladvana 0:23d1f73bf130 282 * @}
vladvana 0:23d1f73bf130 283 */
vladvana 0:23d1f73bf130 284
vladvana 0:23d1f73bf130 285 /** @addtogroup HAL_Exported_Functions_Group2
vladvana 0:23d1f73bf130 286 * @{
vladvana 0:23d1f73bf130 287 */
vladvana 0:23d1f73bf130 288
vladvana 0:23d1f73bf130 289 /* Peripheral Control functions ************************************************/
vladvana 0:23d1f73bf130 290 void HAL_IncTick(void);
vladvana 0:23d1f73bf130 291 void HAL_Delay(__IO uint32_t Delay);
vladvana 0:23d1f73bf130 292 uint32_t HAL_GetTick(void);
vladvana 0:23d1f73bf130 293 void HAL_SuspendTick(void);
vladvana 0:23d1f73bf130 294 void HAL_ResumeTick(void);
vladvana 0:23d1f73bf130 295 uint32_t HAL_GetHalVersion(void);
vladvana 0:23d1f73bf130 296 uint32_t HAL_GetREVID(void);
vladvana 0:23d1f73bf130 297 uint32_t HAL_GetDEVID(void);
vladvana 0:23d1f73bf130 298 void HAL_DBGMCU_EnableDBGSleepMode(void);
vladvana 0:23d1f73bf130 299 void HAL_DBGMCU_DisableDBGSleepMode(void);
vladvana 0:23d1f73bf130 300 void HAL_DBGMCU_EnableDBGStopMode(void);
vladvana 0:23d1f73bf130 301 void HAL_DBGMCU_DisableDBGStopMode(void);
vladvana 0:23d1f73bf130 302 void HAL_DBGMCU_EnableDBGStandbyMode(void);
vladvana 0:23d1f73bf130 303 void HAL_DBGMCU_DisableDBGStandbyMode(void);
vladvana 0:23d1f73bf130 304
vladvana 0:23d1f73bf130 305 /**
vladvana 0:23d1f73bf130 306 * @}
vladvana 0:23d1f73bf130 307 */
vladvana 0:23d1f73bf130 308
vladvana 0:23d1f73bf130 309 /**
vladvana 0:23d1f73bf130 310 * @}
vladvana 0:23d1f73bf130 311 */
vladvana 0:23d1f73bf130 312
vladvana 0:23d1f73bf130 313
vladvana 0:23d1f73bf130 314 /**
vladvana 0:23d1f73bf130 315 * @}
vladvana 0:23d1f73bf130 316 */
vladvana 0:23d1f73bf130 317
vladvana 0:23d1f73bf130 318 /**
vladvana 0:23d1f73bf130 319 * @}
vladvana 0:23d1f73bf130 320 */
vladvana 0:23d1f73bf130 321
vladvana 0:23d1f73bf130 322 #ifdef __cplusplus
vladvana 0:23d1f73bf130 323 }
vladvana 0:23d1f73bf130 324 #endif
vladvana 0:23d1f73bf130 325
vladvana 0:23d1f73bf130 326 #endif /* __STM32F1xx_HAL_H */
vladvana 0:23d1f73bf130 327
vladvana 0:23d1f73bf130 328 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/