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TARGET_NUCLEO_F103RB/stm32_hal_legacy.h@0:23d1f73bf130, 2017-09-24 (annotated)

Committer:: vladvana
Date:: Sun Sep 24 12:31:52 2017 +0000
Revision:: 0:23d1f73bf130

podklady pro cviceni z PSS

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User	Revision	Line number	New contents of line
vladvana	0:23d1f73bf130	1	/**
vladvana	0:23d1f73bf130	2	******************************************************************************
vladvana	0:23d1f73bf130	3	* @file stm32_hal_legacy.h
vladvana	0:23d1f73bf130	4	* @author MCD Application Team
vladvana	0:23d1f73bf130	5	* @version V1.0.0
vladvana	0:23d1f73bf130	6	* @date 15-December-2014
vladvana	0:23d1f73bf130	7	* @brief This file contains aliases definition for the STM32Cube HAL constants
vladvana	0:23d1f73bf130	8	* macros and functions maintained for legacy purpose.
vladvana	0:23d1f73bf130	9	******************************************************************************
vladvana	0:23d1f73bf130	10	* @attention
vladvana	0:23d1f73bf130	11	*
vladvana	0:23d1f73bf130	12	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
vladvana	0:23d1f73bf130	13	*
vladvana	0:23d1f73bf130	14	* Redistribution and use in source and binary forms, with or without modification,
vladvana	0:23d1f73bf130	15	* are permitted provided that the following conditions are met:
vladvana	0:23d1f73bf130	16	* 1. Redistributions of source code must retain the above copyright notice,
vladvana	0:23d1f73bf130	17	* this list of conditions and the following disclaimer.
vladvana	0:23d1f73bf130	18	* 2. Redistributions in binary form must reproduce the above copyright notice,
vladvana	0:23d1f73bf130	19	* this list of conditions and the following disclaimer in the documentation
vladvana	0:23d1f73bf130	20	* and/or other materials provided with the distribution.
vladvana	0:23d1f73bf130	21	* 3. Neither the name of STMicroelectronics nor the names of its contributors
vladvana	0:23d1f73bf130	22	* may be used to endorse or promote products derived from this software
vladvana	0:23d1f73bf130	23	* without specific prior written permission.
vladvana	0:23d1f73bf130	24	*
vladvana	0:23d1f73bf130	25	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
vladvana	0:23d1f73bf130	26	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
vladvana	0:23d1f73bf130	27	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
vladvana	0:23d1f73bf130	28	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
vladvana	0:23d1f73bf130	29	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
vladvana	0:23d1f73bf130	30	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
vladvana	0:23d1f73bf130	31	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
vladvana	0:23d1f73bf130	32	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
vladvana	0:23d1f73bf130	33	UART * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
vladvana	0:23d1f73bf130	34	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
vladvana	0:23d1f73bf130	35	*
vladvana	0:23d1f73bf130	36	******************************************************************************
vladvana	0:23d1f73bf130	37	*/
vladvana	0:23d1f73bf130	38
vladvana	0:23d1f73bf130	39	/* Define to prevent recursive inclusion -------------------------------------*/
vladvana	0:23d1f73bf130	40	#ifndef __STM32_HAL_LEGACY
vladvana	0:23d1f73bf130	41	#define __STM32_HAL_LEGACY
vladvana	0:23d1f73bf130	42
vladvana	0:23d1f73bf130	43	#ifdef __cplusplus
vladvana	0:23d1f73bf130	44	extern "C" {
vladvana	0:23d1f73bf130	45	#endif
vladvana	0:23d1f73bf130	46
vladvana	0:23d1f73bf130	47	/* Includes ------------------------------------------------------------------*/
vladvana	0:23d1f73bf130	48	/* Exported types ------------------------------------------------------------*/
vladvana	0:23d1f73bf130	49	/* Exported constants --------------------------------------------------------*/
vladvana	0:23d1f73bf130	50
vladvana	0:23d1f73bf130	51	/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose
vladvana	0:23d1f73bf130	52	* @{
vladvana	0:23d1f73bf130	53	*/
vladvana	0:23d1f73bf130	54	#define AES_FLAG_RDERR CRYP_FLAG_RDERR
vladvana	0:23d1f73bf130	55	#define AES_FLAG_WRERR CRYP_FLAG_WRERR
vladvana	0:23d1f73bf130	56	#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
vladvana	0:23d1f73bf130	57	#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
vladvana	0:23d1f73bf130	58	#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
vladvana	0:23d1f73bf130	59
vladvana	0:23d1f73bf130	60	/**
vladvana	0:23d1f73bf130	61	* @}
vladvana	0:23d1f73bf130	62	*/
vladvana	0:23d1f73bf130	63
vladvana	0:23d1f73bf130	64	/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose
vladvana	0:23d1f73bf130	65	* @{
vladvana	0:23d1f73bf130	66	*/
vladvana	0:23d1f73bf130	67	#define ADC_RESOLUTION12b ADC_RESOLUTION_12B
vladvana	0:23d1f73bf130	68	#define ADC_RESOLUTION10b ADC_RESOLUTION_10B
vladvana	0:23d1f73bf130	69	#define ADC_RESOLUTION8b ADC_RESOLUTION_8B
vladvana	0:23d1f73bf130	70	#define ADC_RESOLUTION6b ADC_RESOLUTION_6B
vladvana	0:23d1f73bf130	71	#define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN
vladvana	0:23d1f73bf130	72	#define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED
vladvana	0:23d1f73bf130	73	#define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV
vladvana	0:23d1f73bf130	74	#define EOC_SEQ_CONV ADC_EOC_SEQ_CONV
vladvana	0:23d1f73bf130	75	#define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV
vladvana	0:23d1f73bf130	76	#define REGULAR_GROUP ADC_REGULAR_GROUP
vladvana	0:23d1f73bf130	77	#define INJECTED_GROUP ADC_INJECTED_GROUP
vladvana	0:23d1f73bf130	78	#define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP
vladvana	0:23d1f73bf130	79	#define AWD_EVENT ADC_AWD_EVENT
vladvana	0:23d1f73bf130	80	#define AWD1_EVENT ADC_AWD1_EVENT
vladvana	0:23d1f73bf130	81	#define AWD2_EVENT ADC_AWD2_EVENT
vladvana	0:23d1f73bf130	82	#define AWD3_EVENT ADC_AWD3_EVENT
vladvana	0:23d1f73bf130	83	#define OVR_EVENT ADC_OVR_EVENT
vladvana	0:23d1f73bf130	84	#define JQOVF_EVENT ADC_JQOVF_EVENT
vladvana	0:23d1f73bf130	85	#define ALL_CHANNELS ADC_ALL_CHANNELS
vladvana	0:23d1f73bf130	86	#define REGULAR_CHANNELS ADC_REGULAR_CHANNELS
vladvana	0:23d1f73bf130	87	#define INJECTED_CHANNELS ADC_INJECTED_CHANNELS
vladvana	0:23d1f73bf130	88	#define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR
vladvana	0:23d1f73bf130	89	#define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT
vladvana	0:23d1f73bf130	90	#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1
vladvana	0:23d1f73bf130	91	#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2
vladvana	0:23d1f73bf130	92	#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4
vladvana	0:23d1f73bf130	93	#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO
vladvana	0:23d1f73bf130	94	#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2
vladvana	0:23d1f73bf130	95	#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO
vladvana	0:23d1f73bf130	96	#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4
vladvana	0:23d1f73bf130	97	#define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO
vladvana	0:23d1f73bf130	98	#define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11
vladvana	0:23d1f73bf130	99	#define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1
vladvana	0:23d1f73bf130	100
vladvana	0:23d1f73bf130	101
vladvana	0:23d1f73bf130	102	/**
vladvana	0:23d1f73bf130	103	* @}
vladvana	0:23d1f73bf130	104	*/
vladvana	0:23d1f73bf130	105
vladvana	0:23d1f73bf130	106	/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose
vladvana	0:23d1f73bf130	107	* @{
vladvana	0:23d1f73bf130	108	*/
vladvana	0:23d1f73bf130	109
vladvana	0:23d1f73bf130	110	#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG
vladvana	0:23d1f73bf130	111
vladvana	0:23d1f73bf130	112	/**
vladvana	0:23d1f73bf130	113	* @}
vladvana	0:23d1f73bf130	114	*/
vladvana	0:23d1f73bf130	115
vladvana	0:23d1f73bf130	116	/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose
vladvana	0:23d1f73bf130	117	* @{
vladvana	0:23d1f73bf130	118	*/
vladvana	0:23d1f73bf130	119
vladvana	0:23d1f73bf130	120	#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE
vladvana	0:23d1f73bf130	121	#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE
vladvana	0:23d1f73bf130	122	#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1
vladvana	0:23d1f73bf130	123	#define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2
vladvana	0:23d1f73bf130	124
vladvana	0:23d1f73bf130	125	/**
vladvana	0:23d1f73bf130	126	* @}
vladvana	0:23d1f73bf130	127	*/
vladvana	0:23d1f73bf130	128
vladvana	0:23d1f73bf130	129	/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose
vladvana	0:23d1f73bf130	130	* @{
vladvana	0:23d1f73bf130	131	*/
vladvana	0:23d1f73bf130	132
vladvana	0:23d1f73bf130	133	#define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE
vladvana	0:23d1f73bf130	134	#define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE
vladvana	0:23d1f73bf130	135
vladvana	0:23d1f73bf130	136	/**
vladvana	0:23d1f73bf130	137	* @}
vladvana	0:23d1f73bf130	138	*/
vladvana	0:23d1f73bf130	139
vladvana	0:23d1f73bf130	140	/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose
vladvana	0:23d1f73bf130	141	* @{
vladvana	0:23d1f73bf130	142	*/
vladvana	0:23d1f73bf130	143
vladvana	0:23d1f73bf130	144	#define DAC1_CHANNEL_1 DAC_CHANNEL_1
vladvana	0:23d1f73bf130	145	#define DAC1_CHANNEL_2 DAC_CHANNEL_2
vladvana	0:23d1f73bf130	146	#define DAC2_CHANNEL_1 DAC_CHANNEL_1
vladvana	0:23d1f73bf130	147
vladvana	0:23d1f73bf130	148	/**
vladvana	0:23d1f73bf130	149	* @}
vladvana	0:23d1f73bf130	150	*/
vladvana	0:23d1f73bf130	151
vladvana	0:23d1f73bf130	152
vladvana	0:23d1f73bf130	153	/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose
vladvana	0:23d1f73bf130	154	* @{
vladvana	0:23d1f73bf130	155	*/
vladvana	0:23d1f73bf130	156
vladvana	0:23d1f73bf130	157	#define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE
vladvana	0:23d1f73bf130	158	#define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD
vladvana	0:23d1f73bf130	159	#define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD
vladvana	0:23d1f73bf130	160	#define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD
vladvana	0:23d1f73bf130	161	#define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS
vladvana	0:23d1f73bf130	162	#define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES
vladvana	0:23d1f73bf130	163	#define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES
vladvana	0:23d1f73bf130	164	#define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE
vladvana	0:23d1f73bf130	165	#define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE
vladvana	0:23d1f73bf130	166	#define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE
vladvana	0:23d1f73bf130	167	#define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE
vladvana	0:23d1f73bf130	168	#define OBEX_PCROP OPTIONBYTE_PCROP
vladvana	0:23d1f73bf130	169	#define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG
vladvana	0:23d1f73bf130	170	#define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE
vladvana	0:23d1f73bf130	171	#define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE
vladvana	0:23d1f73bf130	172	#define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE
vladvana	0:23d1f73bf130	173	#define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD
vladvana	0:23d1f73bf130	174	#define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD
vladvana	0:23d1f73bf130	175	#define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE
vladvana	0:23d1f73bf130	176	#define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD
vladvana	0:23d1f73bf130	177	#define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD
vladvana	0:23d1f73bf130	178	#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE
vladvana	0:23d1f73bf130	179	#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD
vladvana	0:23d1f73bf130	180	#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD
vladvana	0:23d1f73bf130	181	#define PAGESIZE FLASH_PAGE_SIZE
vladvana	0:23d1f73bf130	182	#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE
vladvana	0:23d1f73bf130	183	#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD
vladvana	0:23d1f73bf130	184	#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD
vladvana	0:23d1f73bf130	185	#define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1
vladvana	0:23d1f73bf130	186	#define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2
vladvana	0:23d1f73bf130	187	#define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3
vladvana	0:23d1f73bf130	188	#define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4
vladvana	0:23d1f73bf130	189	#define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST
vladvana	0:23d1f73bf130	190	#define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST
vladvana	0:23d1f73bf130	191	#define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA
vladvana	0:23d1f73bf130	192	#define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB
vladvana	0:23d1f73bf130	193	#define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA
vladvana	0:23d1f73bf130	194	#define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB
vladvana	0:23d1f73bf130	195	#define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE
vladvana	0:23d1f73bf130	196	#define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN
vladvana	0:23d1f73bf130	197	#define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE
vladvana	0:23d1f73bf130	198	#define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN
vladvana	0:23d1f73bf130	199	#define IS_NBSECTORS IS_FLASH_NBSECTORS
vladvana	0:23d1f73bf130	200	#define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE
vladvana	0:23d1f73bf130	201	#define FLASH_ERROR_RD HAL_FLASH_ERROR_RD
vladvana	0:23d1f73bf130	202	#define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG
vladvana	0:23d1f73bf130	203	#define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS
vladvana	0:23d1f73bf130	204	#define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP
vladvana	0:23d1f73bf130	205	#define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV
vladvana	0:23d1f73bf130	206	#define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR
vladvana	0:23d1f73bf130	207	#define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG
vladvana	0:23d1f73bf130	208	#define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION
vladvana	0:23d1f73bf130	209	#define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA
vladvana	0:23d1f73bf130	210	#define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE
vladvana	0:23d1f73bf130	211	#define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE
vladvana	0:23d1f73bf130	212	#define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS
vladvana	0:23d1f73bf130	213	#define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS
vladvana	0:23d1f73bf130	214	#define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST
vladvana	0:23d1f73bf130	215	#define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR
vladvana	0:23d1f73bf130	216	#define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO
vladvana	0:23d1f73bf130	217	#define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION
vladvana	0:23d1f73bf130	218	#define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS
vladvana	0:23d1f73bf130	219
vladvana	0:23d1f73bf130	220	/**
vladvana	0:23d1f73bf130	221	* @}
vladvana	0:23d1f73bf130	222	*/
vladvana	0:23d1f73bf130	223
vladvana	0:23d1f73bf130	224	/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose
vladvana	0:23d1f73bf130	225	* @{
vladvana	0:23d1f73bf130	226	*/
vladvana	0:23d1f73bf130	227
vladvana	0:23d1f73bf130	228	#define SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6
vladvana	0:23d1f73bf130	229	#define SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7
vladvana	0:23d1f73bf130	230	#define SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8
vladvana	0:23d1f73bf130	231	#define SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9
vladvana	0:23d1f73bf130	232	#define SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1
vladvana	0:23d1f73bf130	233	#define SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2
vladvana	0:23d1f73bf130	234	#define SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3
vladvana	0:23d1f73bf130	235
vladvana	0:23d1f73bf130	236	/**
vladvana	0:23d1f73bf130	237	* @}
vladvana	0:23d1f73bf130	238	*/
vladvana	0:23d1f73bf130	239
vladvana	0:23d1f73bf130	240
vladvana	0:23d1f73bf130	241	/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose
vladvana	0:23d1f73bf130	242	* @{
vladvana	0:23d1f73bf130	243	*/
vladvana	0:23d1f73bf130	244
vladvana	0:23d1f73bf130	245	#define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef
vladvana	0:23d1f73bf130	246	#define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef
vladvana	0:23d1f73bf130	247	/**
vladvana	0:23d1f73bf130	248	* @}
vladvana	0:23d1f73bf130	249	*/
vladvana	0:23d1f73bf130	250
vladvana	0:23d1f73bf130	251	/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose
vladvana	0:23d1f73bf130	252	* @{
vladvana	0:23d1f73bf130	253	*/
vladvana	0:23d1f73bf130	254	#define GET_GPIO_SOURCE GPIO_GET_INDEX
vladvana	0:23d1f73bf130	255	#define GET_GPIO_INDEX GPIO_GET_INDEX
vladvana	0:23d1f73bf130	256	/**
vladvana	0:23d1f73bf130	257	* @}
vladvana	0:23d1f73bf130	258	*/
vladvana	0:23d1f73bf130	259
vladvana	0:23d1f73bf130	260
vladvana	0:23d1f73bf130	261	/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose
vladvana	0:23d1f73bf130	262	* @{
vladvana	0:23d1f73bf130	263	*/
vladvana	0:23d1f73bf130	264	#define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE
vladvana	0:23d1f73bf130	265	#define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE
vladvana	0:23d1f73bf130	266	#define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE
vladvana	0:23d1f73bf130	267	#define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE
vladvana	0:23d1f73bf130	268	#define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE
vladvana	0:23d1f73bf130	269	#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE
vladvana	0:23d1f73bf130	270	#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE
vladvana	0:23d1f73bf130	271	#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE
vladvana	0:23d1f73bf130	272	/**
vladvana	0:23d1f73bf130	273	* @}
vladvana	0:23d1f73bf130	274	*/
vladvana	0:23d1f73bf130	275
vladvana	0:23d1f73bf130	276	/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose
vladvana	0:23d1f73bf130	277	* @{
vladvana	0:23d1f73bf130	278	*/
vladvana	0:23d1f73bf130	279	#define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE
vladvana	0:23d1f73bf130	280	#define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE
vladvana	0:23d1f73bf130	281
vladvana	0:23d1f73bf130	282	/**
vladvana	0:23d1f73bf130	283	* @}
vladvana	0:23d1f73bf130	284	*/
vladvana	0:23d1f73bf130	285
vladvana	0:23d1f73bf130	286	/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose
vladvana	0:23d1f73bf130	287	* @{
vladvana	0:23d1f73bf130	288	*/
vladvana	0:23d1f73bf130	289	#define KR_KEY_RELOAD IWDG_KEY_RELOAD
vladvana	0:23d1f73bf130	290	#define KR_KEY_ENABLE IWDG_KEY_ENABLE
vladvana	0:23d1f73bf130	291	#define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE
vladvana	0:23d1f73bf130	292	#define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE
vladvana	0:23d1f73bf130	293	/**
vladvana	0:23d1f73bf130	294	* @}
vladvana	0:23d1f73bf130	295	*/
vladvana	0:23d1f73bf130	296
vladvana	0:23d1f73bf130	297	/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose
vladvana	0:23d1f73bf130	298	* @{
vladvana	0:23d1f73bf130	299	*/
vladvana	0:23d1f73bf130	300	#define NAND_AddressTypedef NAND_AddressTypeDef
vladvana	0:23d1f73bf130	301
vladvana	0:23d1f73bf130	302	/**
vladvana	0:23d1f73bf130	303	* @}
vladvana	0:23d1f73bf130	304	*/
vladvana	0:23d1f73bf130	305
vladvana	0:23d1f73bf130	306	/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose
vladvana	0:23d1f73bf130	307	* @{
vladvana	0:23d1f73bf130	308	*/
vladvana	0:23d1f73bf130	309	#define NOR_StatusTypedef HAL_NOR_StatusTypeDef
vladvana	0:23d1f73bf130	310	#define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS
vladvana	0:23d1f73bf130	311	#define NOR_ONGOING HAL_NOR_STATUS_ONGOING
vladvana	0:23d1f73bf130	312	#define NOR_ERROR HAL_NOR_STATUS_ERROR
vladvana	0:23d1f73bf130	313	#define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT
vladvana	0:23d1f73bf130	314
vladvana	0:23d1f73bf130	315	/**
vladvana	0:23d1f73bf130	316	* @}
vladvana	0:23d1f73bf130	317	*/
vladvana	0:23d1f73bf130	318
vladvana	0:23d1f73bf130	319	/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose
vladvana	0:23d1f73bf130	320	* @{
vladvana	0:23d1f73bf130	321	*/
vladvana	0:23d1f73bf130	322
vladvana	0:23d1f73bf130	323	#define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0
vladvana	0:23d1f73bf130	324	#define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1
vladvana	0:23d1f73bf130	325	#define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2
vladvana	0:23d1f73bf130	326	#define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3
vladvana	0:23d1f73bf130	327
vladvana	0:23d1f73bf130	328	#define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0
vladvana	0:23d1f73bf130	329	#define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1
vladvana	0:23d1f73bf130	330	#define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2
vladvana	0:23d1f73bf130	331	#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3
vladvana	0:23d1f73bf130	332
vladvana	0:23d1f73bf130	333	#define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
vladvana	0:23d1f73bf130	334	#define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
vladvana	0:23d1f73bf130	335
vladvana	0:23d1f73bf130	336	#define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
vladvana	0:23d1f73bf130	337	#define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
vladvana	0:23d1f73bf130	338
vladvana	0:23d1f73bf130	339	#define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0
vladvana	0:23d1f73bf130	340	#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1
vladvana	0:23d1f73bf130	341
vladvana	0:23d1f73bf130	342	#define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1
vladvana	0:23d1f73bf130	343
vladvana	0:23d1f73bf130	344	#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO
vladvana	0:23d1f73bf130	345	#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
vladvana	0:23d1f73bf130	346	#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
vladvana	0:23d1f73bf130	347
vladvana	0:23d1f73bf130	348	/**
vladvana	0:23d1f73bf130	349	* @}
vladvana	0:23d1f73bf130	350	*/
vladvana	0:23d1f73bf130	351
vladvana	0:23d1f73bf130	352	/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose
vladvana	0:23d1f73bf130	353	* @{
vladvana	0:23d1f73bf130	354	*/
vladvana	0:23d1f73bf130	355	#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS
vladvana	0:23d1f73bf130	356	/**
vladvana	0:23d1f73bf130	357	* @}
vladvana	0:23d1f73bf130	358	*/
vladvana	0:23d1f73bf130	359
vladvana	0:23d1f73bf130	360	/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose
vladvana	0:23d1f73bf130	361	* @{
vladvana	0:23d1f73bf130	362	*/
vladvana	0:23d1f73bf130	363
vladvana	0:23d1f73bf130	364	/* Compact Flash-ATA registers description */
vladvana	0:23d1f73bf130	365	#define CF_DATA ATA_DATA
vladvana	0:23d1f73bf130	366	#define CF_SECTOR_COUNT ATA_SECTOR_COUNT
vladvana	0:23d1f73bf130	367	#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER
vladvana	0:23d1f73bf130	368	#define CF_CYLINDER_LOW ATA_CYLINDER_LOW
vladvana	0:23d1f73bf130	369	#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH
vladvana	0:23d1f73bf130	370	#define CF_CARD_HEAD ATA_CARD_HEAD
vladvana	0:23d1f73bf130	371	#define CF_STATUS_CMD ATA_STATUS_CMD
vladvana	0:23d1f73bf130	372	#define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE
vladvana	0:23d1f73bf130	373	#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA
vladvana	0:23d1f73bf130	374
vladvana	0:23d1f73bf130	375	/* Compact Flash-ATA commands */
vladvana	0:23d1f73bf130	376	#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD
vladvana	0:23d1f73bf130	377	#define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD
vladvana	0:23d1f73bf130	378	#define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD
vladvana	0:23d1f73bf130	379	#define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD
vladvana	0:23d1f73bf130	380
vladvana	0:23d1f73bf130	381	#define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef
vladvana	0:23d1f73bf130	382	#define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS
vladvana	0:23d1f73bf130	383	#define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING
vladvana	0:23d1f73bf130	384	#define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR
vladvana	0:23d1f73bf130	385	#define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT
vladvana	0:23d1f73bf130	386	/**
vladvana	0:23d1f73bf130	387	* @}
vladvana	0:23d1f73bf130	388	*/
vladvana	0:23d1f73bf130	389
vladvana	0:23d1f73bf130	390	/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
vladvana	0:23d1f73bf130	391	* @{
vladvana	0:23d1f73bf130	392	*/
vladvana	0:23d1f73bf130	393
vladvana	0:23d1f73bf130	394	#define FORMAT_BIN RTC_FORMAT_BIN
vladvana	0:23d1f73bf130	395	#define FORMAT_BCD RTC_FORMAT_BCD
vladvana	0:23d1f73bf130	396
vladvana	0:23d1f73bf130	397	#define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE
vladvana	0:23d1f73bf130	398	#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
vladvana	0:23d1f73bf130	399	#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
vladvana	0:23d1f73bf130	400	#define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
vladvana	0:23d1f73bf130	401	#define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
vladvana	0:23d1f73bf130	402
vladvana	0:23d1f73bf130	403	#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
vladvana	0:23d1f73bf130	404	#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
vladvana	0:23d1f73bf130	405	#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
vladvana	0:23d1f73bf130	406	#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
vladvana	0:23d1f73bf130	407	#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
vladvana	0:23d1f73bf130	408	#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
vladvana	0:23d1f73bf130	409	#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
vladvana	0:23d1f73bf130	410	#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
vladvana	0:23d1f73bf130	411
vladvana	0:23d1f73bf130	412	/**
vladvana	0:23d1f73bf130	413	* @}
vladvana	0:23d1f73bf130	414	*/
vladvana	0:23d1f73bf130	415
vladvana	0:23d1f73bf130	416
vladvana	0:23d1f73bf130	417	/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose
vladvana	0:23d1f73bf130	418	* @{
vladvana	0:23d1f73bf130	419	*/
vladvana	0:23d1f73bf130	420	#define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE
vladvana	0:23d1f73bf130	421	#define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE
vladvana	0:23d1f73bf130	422
vladvana	0:23d1f73bf130	423	#define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE
vladvana	0:23d1f73bf130	424	#define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE
vladvana	0:23d1f73bf130	425	#define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE
vladvana	0:23d1f73bf130	426	#define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE
vladvana	0:23d1f73bf130	427
vladvana	0:23d1f73bf130	428	#define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE
vladvana	0:23d1f73bf130	429	#define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE
vladvana	0:23d1f73bf130	430
vladvana	0:23d1f73bf130	431	#define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE
vladvana	0:23d1f73bf130	432	#define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE
vladvana	0:23d1f73bf130	433	/**
vladvana	0:23d1f73bf130	434	* @}
vladvana	0:23d1f73bf130	435	*/
vladvana	0:23d1f73bf130	436
vladvana	0:23d1f73bf130	437
vladvana	0:23d1f73bf130	438	/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
vladvana	0:23d1f73bf130	439	* @{
vladvana	0:23d1f73bf130	440	*/
vladvana	0:23d1f73bf130	441	#define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE
vladvana	0:23d1f73bf130	442	#define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE
vladvana	0:23d1f73bf130	443	#define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE
vladvana	0:23d1f73bf130	444	#define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE
vladvana	0:23d1f73bf130	445	#define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE
vladvana	0:23d1f73bf130	446	#define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE
vladvana	0:23d1f73bf130	447	#define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE
vladvana	0:23d1f73bf130	448	#define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE
vladvana	0:23d1f73bf130	449	#define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN
vladvana	0:23d1f73bf130	450	/**
vladvana	0:23d1f73bf130	451	* @}
vladvana	0:23d1f73bf130	452	*/
vladvana	0:23d1f73bf130	453
vladvana	0:23d1f73bf130	454	/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose
vladvana	0:23d1f73bf130	455	* @{
vladvana	0:23d1f73bf130	456	*/
vladvana	0:23d1f73bf130	457	#define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE
vladvana	0:23d1f73bf130	458	#define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE
vladvana	0:23d1f73bf130	459
vladvana	0:23d1f73bf130	460	#define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE
vladvana	0:23d1f73bf130	461	#define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE
vladvana	0:23d1f73bf130	462
vladvana	0:23d1f73bf130	463	#define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE
vladvana	0:23d1f73bf130	464	#define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE
vladvana	0:23d1f73bf130	465
vladvana	0:23d1f73bf130	466	/**
vladvana	0:23d1f73bf130	467	* @}
vladvana	0:23d1f73bf130	468	*/
vladvana	0:23d1f73bf130	469
vladvana	0:23d1f73bf130	470	/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose
vladvana	0:23d1f73bf130	471	* @{
vladvana	0:23d1f73bf130	472	*/
vladvana	0:23d1f73bf130	473	#define CCER_CCxE_MASK TIM_CCER_CCxE_MASK
vladvana	0:23d1f73bf130	474	#define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK
vladvana	0:23d1f73bf130	475
vladvana	0:23d1f73bf130	476	#define TIM_DMABase_CR1 TIM_DMABASE_CR1
vladvana	0:23d1f73bf130	477	#define TIM_DMABase_CR2 TIM_DMABASE_CR2
vladvana	0:23d1f73bf130	478	#define TIM_DMABase_SMCR TIM_DMABASE_SMCR
vladvana	0:23d1f73bf130	479	#define TIM_DMABase_DIER TIM_DMABASE_DIER
vladvana	0:23d1f73bf130	480	#define TIM_DMABase_SR TIM_DMABASE_SR
vladvana	0:23d1f73bf130	481	#define TIM_DMABase_EGR TIM_DMABASE_EGR
vladvana	0:23d1f73bf130	482	#define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1
vladvana	0:23d1f73bf130	483	#define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2
vladvana	0:23d1f73bf130	484	#define TIM_DMABase_CCER TIM_DMABASE_CCER
vladvana	0:23d1f73bf130	485	#define TIM_DMABase_CNT TIM_DMABASE_CNT
vladvana	0:23d1f73bf130	486	#define TIM_DMABase_PSC TIM_DMABASE_PSC
vladvana	0:23d1f73bf130	487	#define TIM_DMABase_ARR TIM_DMABASE_ARR
vladvana	0:23d1f73bf130	488	#define TIM_DMABase_RCR TIM_DMABASE_RCR
vladvana	0:23d1f73bf130	489	#define TIM_DMABase_CCR1 TIM_DMABASE_CCR1
vladvana	0:23d1f73bf130	490	#define TIM_DMABase_CCR2 TIM_DMABASE_CCR2
vladvana	0:23d1f73bf130	491	#define TIM_DMABase_CCR3 TIM_DMABASE_CCR3
vladvana	0:23d1f73bf130	492	#define TIM_DMABase_CCR4 TIM_DMABASE_CCR4
vladvana	0:23d1f73bf130	493	#define TIM_DMABase_BDTR TIM_DMABASE_BDTR
vladvana	0:23d1f73bf130	494	#define TIM_DMABase_DCR TIM_DMABASE_DCR
vladvana	0:23d1f73bf130	495	#define TIM_DMABase_DMAR TIM_DMABASE_DMAR
vladvana	0:23d1f73bf130	496	#define TIM_DMABase_OR1 TIM_DMABASE_OR1
vladvana	0:23d1f73bf130	497	#define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3
vladvana	0:23d1f73bf130	498	#define TIM_DMABase_CCR5 TIM_DMABASE_CCR5
vladvana	0:23d1f73bf130	499	#define TIM_DMABase_CCR6 TIM_DMABASE_CCR6
vladvana	0:23d1f73bf130	500	#define TIM_DMABase_OR2 TIM_DMABASE_OR2
vladvana	0:23d1f73bf130	501	#define TIM_DMABase_OR3 TIM_DMABASE_OR3
vladvana	0:23d1f73bf130	502
vladvana	0:23d1f73bf130	503	#define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE
vladvana	0:23d1f73bf130	504	#define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1
vladvana	0:23d1f73bf130	505	#define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2
vladvana	0:23d1f73bf130	506	#define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3
vladvana	0:23d1f73bf130	507	#define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4
vladvana	0:23d1f73bf130	508	#define TIM_EventSource_COM TIM_EVENTSOURCE_COM
vladvana	0:23d1f73bf130	509	#define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER
vladvana	0:23d1f73bf130	510	#define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK
vladvana	0:23d1f73bf130	511	#define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2
vladvana	0:23d1f73bf130	512
vladvana	0:23d1f73bf130	513	#define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER
vladvana	0:23d1f73bf130	514	#define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS
vladvana	0:23d1f73bf130	515	#define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS
vladvana	0:23d1f73bf130	516	#define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS
vladvana	0:23d1f73bf130	517	#define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS
vladvana	0:23d1f73bf130	518	#define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS
vladvana	0:23d1f73bf130	519	#define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS
vladvana	0:23d1f73bf130	520	#define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS
vladvana	0:23d1f73bf130	521	#define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS
vladvana	0:23d1f73bf130	522	#define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS
vladvana	0:23d1f73bf130	523	#define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS
vladvana	0:23d1f73bf130	524	#define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS
vladvana	0:23d1f73bf130	525	#define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS
vladvana	0:23d1f73bf130	526	#define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS
vladvana	0:23d1f73bf130	527	#define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS
vladvana	0:23d1f73bf130	528	#define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS
vladvana	0:23d1f73bf130	529	#define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS
vladvana	0:23d1f73bf130	530	#define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS
vladvana	0:23d1f73bf130	531
vladvana	0:23d1f73bf130	532	/**
vladvana	0:23d1f73bf130	533	* @}
vladvana	0:23d1f73bf130	534	*/
vladvana	0:23d1f73bf130	535
vladvana	0:23d1f73bf130	536	/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose
vladvana	0:23d1f73bf130	537	* @{
vladvana	0:23d1f73bf130	538	*/
vladvana	0:23d1f73bf130	539	#define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
vladvana	0:23d1f73bf130	540	#define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
vladvana	0:23d1f73bf130	541	#define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
vladvana	0:23d1f73bf130	542	#define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
vladvana	0:23d1f73bf130	543
vladvana	0:23d1f73bf130	544	#define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE
vladvana	0:23d1f73bf130	545	#define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE
vladvana	0:23d1f73bf130	546
vladvana	0:23d1f73bf130	547	#define __DIV_SAMPLING16 UART_DIV_SAMPLING16
vladvana	0:23d1f73bf130	548	#define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16
vladvana	0:23d1f73bf130	549	#define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16
vladvana	0:23d1f73bf130	550	#define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16
vladvana	0:23d1f73bf130	551
vladvana	0:23d1f73bf130	552	#define __DIV_SAMPLING8 UART_DIV_SAMPLING8
vladvana	0:23d1f73bf130	553	#define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8
vladvana	0:23d1f73bf130	554	#define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8
vladvana	0:23d1f73bf130	555	#define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8
vladvana	0:23d1f73bf130	556
vladvana	0:23d1f73bf130	557	#define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE
vladvana	0:23d1f73bf130	558	#define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK
vladvana	0:23d1f73bf130	559
vladvana	0:23d1f73bf130	560	/**
vladvana	0:23d1f73bf130	561	* @}
vladvana	0:23d1f73bf130	562	*/
vladvana	0:23d1f73bf130	563
vladvana	0:23d1f73bf130	564
vladvana	0:23d1f73bf130	565	/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose
vladvana	0:23d1f73bf130	566	* @{
vladvana	0:23d1f73bf130	567	*/
vladvana	0:23d1f73bf130	568
vladvana	0:23d1f73bf130	569	#define USART_CLOCK_DISABLED USART_CLOCK_DISABLE
vladvana	0:23d1f73bf130	570	#define USART_CLOCK_ENABLED USART_CLOCK_ENABLE
vladvana	0:23d1f73bf130	571
vladvana	0:23d1f73bf130	572	#define USARTNACK_ENABLED USART_NACK_ENABLE
vladvana	0:23d1f73bf130	573	#define USARTNACK_DISABLED USART_NACK_DISABLE
vladvana	0:23d1f73bf130	574	/**
vladvana	0:23d1f73bf130	575	* @}
vladvana	0:23d1f73bf130	576	*/
vladvana	0:23d1f73bf130	577
vladvana	0:23d1f73bf130	578	/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose
vladvana	0:23d1f73bf130	579	* @{
vladvana	0:23d1f73bf130	580	*/
vladvana	0:23d1f73bf130	581	#define CFR_BASE WWDG_CFR_BASE
vladvana	0:23d1f73bf130	582
vladvana	0:23d1f73bf130	583	/**
vladvana	0:23d1f73bf130	584	* @}
vladvana	0:23d1f73bf130	585	*/
vladvana	0:23d1f73bf130	586
vladvana	0:23d1f73bf130	587	/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose
vladvana	0:23d1f73bf130	588	* @{
vladvana	0:23d1f73bf130	589	*/
vladvana	0:23d1f73bf130	590	#define CAN_FilterFIFO0 CAN_FILTER_FIFO0
vladvana	0:23d1f73bf130	591	#define CAN_FilterFIFO1 CAN_FILTER_FIFO1
vladvana	0:23d1f73bf130	592	#define CAN_IT_RQCP0 CAN_IT_TME
vladvana	0:23d1f73bf130	593	#define CAN_IT_RQCP1 CAN_IT_TME
vladvana	0:23d1f73bf130	594	#define CAN_IT_RQCP2 CAN_IT_TME
vladvana	0:23d1f73bf130	595	#define INAK_TIMEOUT CAN_TIMEOUT_VALUE
vladvana	0:23d1f73bf130	596	#define SLAK_TIMEOUT CAN_TIMEOUT_VALUE
vladvana	0:23d1f73bf130	597	#define CAN_TXSTATUS_FAILED ((uint8_t)0x00)
vladvana	0:23d1f73bf130	598	#define CAN_TXSTATUS_OK ((uint8_t)0x01)
vladvana	0:23d1f73bf130	599	#define CAN_TXSTATUS_PENDING ((uint8_t)0x02)
vladvana	0:23d1f73bf130	600
vladvana	0:23d1f73bf130	601	/**
vladvana	0:23d1f73bf130	602	* @}
vladvana	0:23d1f73bf130	603	*/
vladvana	0:23d1f73bf130	604
vladvana	0:23d1f73bf130	605	/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose
vladvana	0:23d1f73bf130	606	* @{
vladvana	0:23d1f73bf130	607	*/
vladvana	0:23d1f73bf130	608
vladvana	0:23d1f73bf130	609	#define VLAN_TAG ETH_VLAN_TAG
vladvana	0:23d1f73bf130	610	#define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD
vladvana	0:23d1f73bf130	611	#define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD
vladvana	0:23d1f73bf130	612	#define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD
vladvana	0:23d1f73bf130	613	#define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK
vladvana	0:23d1f73bf130	614	#define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK
vladvana	0:23d1f73bf130	615	#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK
vladvana	0:23d1f73bf130	616	#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK
vladvana	0:23d1f73bf130	617
vladvana	0:23d1f73bf130	618	#define ETH_MMCCR ((uint32_t)0x00000100)
vladvana	0:23d1f73bf130	619	#define ETH_MMCRIR ((uint32_t)0x00000104)
vladvana	0:23d1f73bf130	620	#define ETH_MMCTIR ((uint32_t)0x00000108)
vladvana	0:23d1f73bf130	621	#define ETH_MMCRIMR ((uint32_t)0x0000010C)
vladvana	0:23d1f73bf130	622	#define ETH_MMCTIMR ((uint32_t)0x00000110)
vladvana	0:23d1f73bf130	623	#define ETH_MMCTGFSCCR ((uint32_t)0x0000014C)
vladvana	0:23d1f73bf130	624	#define ETH_MMCTGFMSCCR ((uint32_t)0x00000150)
vladvana	0:23d1f73bf130	625	#define ETH_MMCTGFCR ((uint32_t)0x00000168)
vladvana	0:23d1f73bf130	626	#define ETH_MMCRFCECR ((uint32_t)0x00000194)
vladvana	0:23d1f73bf130	627	#define ETH_MMCRFAECR ((uint32_t)0x00000198)
vladvana	0:23d1f73bf130	628	#define ETH_MMCRGUFCR ((uint32_t)0x000001C4)
vladvana	0:23d1f73bf130	629
vladvana	0:23d1f73bf130	630	/**
vladvana	0:23d1f73bf130	631	* @}
vladvana	0:23d1f73bf130	632	*/
vladvana	0:23d1f73bf130	633
vladvana	0:23d1f73bf130	634	/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
vladvana	0:23d1f73bf130	635	* @{
vladvana	0:23d1f73bf130	636	*/
vladvana	0:23d1f73bf130	637
vladvana	0:23d1f73bf130	638	/**
vladvana	0:23d1f73bf130	639	* @}
vladvana	0:23d1f73bf130	640	*/
vladvana	0:23d1f73bf130	641
vladvana	0:23d1f73bf130	642	/* Exported functions --------------------------------------------------------*/
vladvana	0:23d1f73bf130	643
vladvana	0:23d1f73bf130	644	/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose
vladvana	0:23d1f73bf130	645	* @{
vladvana	0:23d1f73bf130	646	*/
vladvana	0:23d1f73bf130	647	#define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback
vladvana	0:23d1f73bf130	648	/**
vladvana	0:23d1f73bf130	649	* @}
vladvana	0:23d1f73bf130	650	*/
vladvana	0:23d1f73bf130	651
vladvana	0:23d1f73bf130	652	/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose
vladvana	0:23d1f73bf130	653	* @{
vladvana	0:23d1f73bf130	654	*/
vladvana	0:23d1f73bf130	655
vladvana	0:23d1f73bf130	656	#define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish
vladvana	0:23d1f73bf130	657	#define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish
vladvana	0:23d1f73bf130	658	#define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish
vladvana	0:23d1f73bf130	659	#define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish
vladvana	0:23d1f73bf130	660
vladvana	0:23d1f73bf130	661	/HASH Algorithm Selection/
vladvana	0:23d1f73bf130	662
vladvana	0:23d1f73bf130	663	#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1
vladvana	0:23d1f73bf130	664	#define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224
vladvana	0:23d1f73bf130	665	#define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256
vladvana	0:23d1f73bf130	666	#define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5
vladvana	0:23d1f73bf130	667
vladvana	0:23d1f73bf130	668	#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH
vladvana	0:23d1f73bf130	669	#define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC
vladvana	0:23d1f73bf130	670
vladvana	0:23d1f73bf130	671	#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY
vladvana	0:23d1f73bf130	672	#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY
vladvana	0:23d1f73bf130	673	/**
vladvana	0:23d1f73bf130	674	* @}
vladvana	0:23d1f73bf130	675	*/
vladvana	0:23d1f73bf130	676
vladvana	0:23d1f73bf130	677	/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose
vladvana	0:23d1f73bf130	678	* @{
vladvana	0:23d1f73bf130	679	*/
vladvana	0:23d1f73bf130	680	#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode
vladvana	0:23d1f73bf130	681	#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode
vladvana	0:23d1f73bf130	682	#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode
vladvana	0:23d1f73bf130	683	#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
vladvana	0:23d1f73bf130	684	#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
vladvana	0:23d1f73bf130	685	#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
vladvana	0:23d1f73bf130	686	#define HAL_DBG_LowPowerConfig(Periph, cmd) ((cmd==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
vladvana	0:23d1f73bf130	687	#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
vladvana	0:23d1f73bf130	688	#define HAL_Lock_Cmd(cmd) ((cmd==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
vladvana	0:23d1f73bf130	689	#define HAL_VREFINT_Cmd(cmd) ((cmd==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
vladvana	0:23d1f73bf130	690	#define HAL_ADC_EnableBuffer_Cmd(cmd) ((cmd==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
vladvana	0:23d1f73bf130	691	#define HAL_ADC_EnableBufferSensor_Cmd(cmd) ((cmd==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
vladvana	0:23d1f73bf130	692	/**
vladvana	0:23d1f73bf130	693	* @}
vladvana	0:23d1f73bf130	694	*/
vladvana	0:23d1f73bf130	695
vladvana	0:23d1f73bf130	696	/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose
vladvana	0:23d1f73bf130	697	* @{
vladvana	0:23d1f73bf130	698	*/
vladvana	0:23d1f73bf130	699	#define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram
vladvana	0:23d1f73bf130	700	#define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown
vladvana	0:23d1f73bf130	701	#define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown
vladvana	0:23d1f73bf130	702	#define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock
vladvana	0:23d1f73bf130	703	#define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock
vladvana	0:23d1f73bf130	704	#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase
vladvana	0:23d1f73bf130	705	#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program
vladvana	0:23d1f73bf130	706
vladvana	0:23d1f73bf130	707	/**
vladvana	0:23d1f73bf130	708	* @}
vladvana	0:23d1f73bf130	709	*/
vladvana	0:23d1f73bf130	710
vladvana	0:23d1f73bf130	711	/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose
vladvana	0:23d1f73bf130	712	* @{
vladvana	0:23d1f73bf130	713	*/
vladvana	0:23d1f73bf130	714	#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter
vladvana	0:23d1f73bf130	715	#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter
vladvana	0:23d1f73bf130	716
vladvana	0:23d1f73bf130	717	#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) ((cmd==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
vladvana	0:23d1f73bf130	718	/**
vladvana	0:23d1f73bf130	719	* @}
vladvana	0:23d1f73bf130	720	*/
vladvana	0:23d1f73bf130	721
vladvana	0:23d1f73bf130	722	/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
vladvana	0:23d1f73bf130	723	* @{
vladvana	0:23d1f73bf130	724	*/
vladvana	0:23d1f73bf130	725	#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD
vladvana	0:23d1f73bf130	726	#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg
vladvana	0:23d1f73bf130	727	#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown
vladvana	0:23d1f73bf130	728	#define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor
vladvana	0:23d1f73bf130	729	#define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg
vladvana	0:23d1f73bf130	730	#define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown
vladvana	0:23d1f73bf130	731	#define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor
vladvana	0:23d1f73bf130	732	#define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler
vladvana	0:23d1f73bf130	733	#define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD
vladvana	0:23d1f73bf130	734	#define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler
vladvana	0:23d1f73bf130	735	#define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback
vladvana	0:23d1f73bf130	736	#define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive
vladvana	0:23d1f73bf130	737	#define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive
vladvana	0:23d1f73bf130	738	#define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC
vladvana	0:23d1f73bf130	739	#define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC
vladvana	0:23d1f73bf130	740	#define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM
vladvana	0:23d1f73bf130	741
vladvana	0:23d1f73bf130	742	#define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL
vladvana	0:23d1f73bf130	743	#define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING
vladvana	0:23d1f73bf130	744	#define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING
vladvana	0:23d1f73bf130	745	#define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING
vladvana	0:23d1f73bf130	746	#define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING
vladvana	0:23d1f73bf130	747	#define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING
vladvana	0:23d1f73bf130	748	#define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING
vladvana	0:23d1f73bf130	749
vladvana	0:23d1f73bf130	750	#define CR_OFFSET_BB PWR_CR_OFFSET_BB
vladvana	0:23d1f73bf130	751	#define CSR_OFFSET_BB PWR_CSR_OFFSET_BB
vladvana	0:23d1f73bf130	752
vladvana	0:23d1f73bf130	753	#define DBP_BitNumber DBP_BIT_NUMBER
vladvana	0:23d1f73bf130	754	#define PVDE_BitNumber PVDE_BIT_NUMBER
vladvana	0:23d1f73bf130	755	#define PMODE_BitNumber PMODE_BIT_NUMBER
vladvana	0:23d1f73bf130	756	#define EWUP_BitNumber EWUP_BIT_NUMBER
vladvana	0:23d1f73bf130	757	#define FPDS_BitNumber FPDS_BIT_NUMBER
vladvana	0:23d1f73bf130	758	#define ODEN_BitNumber ODEN_BIT_NUMBER
vladvana	0:23d1f73bf130	759	#define ODSWEN_BitNumber ODSWEN_BIT_NUMBER
vladvana	0:23d1f73bf130	760	#define MRLVDS_BitNumber MRLVDS_BIT_NUMBER
vladvana	0:23d1f73bf130	761	#define LPLVDS_BitNumber LPLVDS_BIT_NUMBER
vladvana	0:23d1f73bf130	762	#define BRE_BitNumber BRE_BIT_NUMBER
vladvana	0:23d1f73bf130	763
vladvana	0:23d1f73bf130	764	#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL
vladvana	0:23d1f73bf130	765
vladvana	0:23d1f73bf130	766	/**
vladvana	0:23d1f73bf130	767	* @}
vladvana	0:23d1f73bf130	768	*/
vladvana	0:23d1f73bf130	769
vladvana	0:23d1f73bf130	770	/** @defgroup HAL_RCC_Aliased_Functions HAL RCC Aliased Functions maintained for legacy purpose
vladvana	0:23d1f73bf130	771	* @{
vladvana	0:23d1f73bf130	772	*/
vladvana	0:23d1f73bf130	773	#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
vladvana	0:23d1f73bf130	774	#define HAL_RC48_EnableBuffer_Cmd(cmd) ((cmd==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
vladvana	0:23d1f73bf130	775
vladvana	0:23d1f73bf130	776	/**
vladvana	0:23d1f73bf130	777	* @}
vladvana	0:23d1f73bf130	778	*/
vladvana	0:23d1f73bf130	779
vladvana	0:23d1f73bf130	780	/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
vladvana	0:23d1f73bf130	781	* @{
vladvana	0:23d1f73bf130	782	*/
vladvana	0:23d1f73bf130	783	#define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT
vladvana	0:23d1f73bf130	784	#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback
vladvana	0:23d1f73bf130	785	#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback
vladvana	0:23d1f73bf130	786	/**
vladvana	0:23d1f73bf130	787	* @}
vladvana	0:23d1f73bf130	788	*/
vladvana	0:23d1f73bf130	789
vladvana	0:23d1f73bf130	790	/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose
vladvana	0:23d1f73bf130	791	* @{
vladvana	0:23d1f73bf130	792	*/
vladvana	0:23d1f73bf130	793	#define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo
vladvana	0:23d1f73bf130	794	/**
vladvana	0:23d1f73bf130	795	* @}
vladvana	0:23d1f73bf130	796	*/
vladvana	0:23d1f73bf130	797
vladvana	0:23d1f73bf130	798	/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose
vladvana	0:23d1f73bf130	799	* @{
vladvana	0:23d1f73bf130	800	*/
vladvana	0:23d1f73bf130	801	#define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt
vladvana	0:23d1f73bf130	802	#define HAL_TIM_DMAError TIM_DMAError
vladvana	0:23d1f73bf130	803	#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
vladvana	0:23d1f73bf130	804	#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
vladvana	0:23d1f73bf130	805	/**
vladvana	0:23d1f73bf130	806	* @}
vladvana	0:23d1f73bf130	807	*/
vladvana	0:23d1f73bf130	808
vladvana	0:23d1f73bf130	809	/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose
vladvana	0:23d1f73bf130	810	* @{
vladvana	0:23d1f73bf130	811	*/
vladvana	0:23d1f73bf130	812	#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback
vladvana	0:23d1f73bf130	813	/**
vladvana	0:23d1f73bf130	814	* @}
vladvana	0:23d1f73bf130	815	*/
vladvana	0:23d1f73bf130	816
vladvana	0:23d1f73bf130	817
vladvana	0:23d1f73bf130	818	/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
vladvana	0:23d1f73bf130	819	* @{
vladvana	0:23d1f73bf130	820	*/
vladvana	0:23d1f73bf130	821
vladvana	0:23d1f73bf130	822	/**
vladvana	0:23d1f73bf130	823	* @}
vladvana	0:23d1f73bf130	824	*/
vladvana	0:23d1f73bf130	825
vladvana	0:23d1f73bf130	826	/* Exported macros ------------------------------------------------------------*/
vladvana	0:23d1f73bf130	827
vladvana	0:23d1f73bf130	828	/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose
vladvana	0:23d1f73bf130	829	* @{
vladvana	0:23d1f73bf130	830	*/
vladvana	0:23d1f73bf130	831	#define AES_IT_CC CRYP_IT_CC
vladvana	0:23d1f73bf130	832	#define AES_IT_ERR CRYP_IT_ERR
vladvana	0:23d1f73bf130	833	#define AES_FLAG_CCF CRYP_FLAG_CCF
vladvana	0:23d1f73bf130	834	/**
vladvana	0:23d1f73bf130	835	* @}
vladvana	0:23d1f73bf130	836	*/
vladvana	0:23d1f73bf130	837
vladvana	0:23d1f73bf130	838	/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
vladvana	0:23d1f73bf130	839	* @{
vladvana	0:23d1f73bf130	840	*/
vladvana	0:23d1f73bf130	841	#define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE
vladvana	0:23d1f73bf130	842	#define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH
vladvana	0:23d1f73bf130	843	#define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH
vladvana	0:23d1f73bf130	844	#define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM
vladvana	0:23d1f73bf130	845	#define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC
vladvana	0:23d1f73bf130	846	#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM
vladvana	0:23d1f73bf130	847	#define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK
vladvana	0:23d1f73bf130	848	#define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG
vladvana	0:23d1f73bf130	849	#define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG
vladvana	0:23d1f73bf130	850	#define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY
vladvana	0:23d1f73bf130	851	#define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48
vladvana	0:23d1f73bf130	852	#define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS
vladvana	0:23d1f73bf130	853	#define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER
vladvana	0:23d1f73bf130	854	#define CMP_PD_BitNumber CMP_PD_BIT_NUMBER
vladvana	0:23d1f73bf130	855
vladvana	0:23d1f73bf130	856	/**
vladvana	0:23d1f73bf130	857	* @}
vladvana	0:23d1f73bf130	858	*/
vladvana	0:23d1f73bf130	859
vladvana	0:23d1f73bf130	860
vladvana	0:23d1f73bf130	861	/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose
vladvana	0:23d1f73bf130	862	* @{
vladvana	0:23d1f73bf130	863	*/
vladvana	0:23d1f73bf130	864	#define __ADC_ENABLE __HAL_ADC_ENABLE
vladvana	0:23d1f73bf130	865	#define __ADC_DISABLE __HAL_ADC_DISABLE
vladvana	0:23d1f73bf130	866	#define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS
vladvana	0:23d1f73bf130	867	#define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS
vladvana	0:23d1f73bf130	868	#define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE
vladvana	0:23d1f73bf130	869	#define __ADC_IS_ENABLED ADC_IS_ENABLE
vladvana	0:23d1f73bf130	870	#define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR
vladvana	0:23d1f73bf130	871	#define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED
vladvana	0:23d1f73bf130	872	#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED
vladvana	0:23d1f73bf130	873	#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR
vladvana	0:23d1f73bf130	874	#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED
vladvana	0:23d1f73bf130	875	#define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING
vladvana	0:23d1f73bf130	876	#define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE
vladvana	0:23d1f73bf130	877
vladvana	0:23d1f73bf130	878	#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
vladvana	0:23d1f73bf130	879	#define __HAL_ADC_JSQR_RK ADC_JSQR_RK
vladvana	0:23d1f73bf130	880	#define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT
vladvana	0:23d1f73bf130	881	#define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR
vladvana	0:23d1f73bf130	882	#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION
vladvana	0:23d1f73bf130	883	#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE
vladvana	0:23d1f73bf130	884	#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS
vladvana	0:23d1f73bf130	885	#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS
vladvana	0:23d1f73bf130	886	#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM
vladvana	0:23d1f73bf130	887	#define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT
vladvana	0:23d1f73bf130	888	#define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS
vladvana	0:23d1f73bf130	889	#define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN
vladvana	0:23d1f73bf130	890	#define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ
vladvana	0:23d1f73bf130	891	#define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET
vladvana	0:23d1f73bf130	892	#define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET
vladvana	0:23d1f73bf130	893	#define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL
vladvana	0:23d1f73bf130	894	#define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL
vladvana	0:23d1f73bf130	895	#define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET
vladvana	0:23d1f73bf130	896	#define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET
vladvana	0:23d1f73bf130	897	#define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD
vladvana	0:23d1f73bf130	898
vladvana	0:23d1f73bf130	899	#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION
vladvana	0:23d1f73bf130	900	#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION
vladvana	0:23d1f73bf130	901	#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION
vladvana	0:23d1f73bf130	902	#define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER
vladvana	0:23d1f73bf130	903	#define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI
vladvana	0:23d1f73bf130	904	#define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
vladvana	0:23d1f73bf130	905	#define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
vladvana	0:23d1f73bf130	906	#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER
vladvana	0:23d1f73bf130	907	#define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER
vladvana	0:23d1f73bf130	908	#define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE
vladvana	0:23d1f73bf130	909
vladvana	0:23d1f73bf130	910	#define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT
vladvana	0:23d1f73bf130	911	#define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT
vladvana	0:23d1f73bf130	912	#define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL
vladvana	0:23d1f73bf130	913	#define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM
vladvana	0:23d1f73bf130	914	#define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET
vladvana	0:23d1f73bf130	915	#define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE
vladvana	0:23d1f73bf130	916	#define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE
vladvana	0:23d1f73bf130	917	#define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER
vladvana	0:23d1f73bf130	918
vladvana	0:23d1f73bf130	919	#define __HAL_ADC_SQR1 ADC_SQR1
vladvana	0:23d1f73bf130	920	#define __HAL_ADC_SMPR1 ADC_SMPR1
vladvana	0:23d1f73bf130	921	#define __HAL_ADC_SMPR2 ADC_SMPR2
vladvana	0:23d1f73bf130	922	#define __HAL_ADC_SQR3_RK ADC_SQR3_RK
vladvana	0:23d1f73bf130	923	#define __HAL_ADC_SQR2_RK ADC_SQR2_RK
vladvana	0:23d1f73bf130	924	#define __HAL_ADC_SQR1_RK ADC_SQR1_RK
vladvana	0:23d1f73bf130	925	#define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS
vladvana	0:23d1f73bf130	926	#define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS
vladvana	0:23d1f73bf130	927	#define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV
vladvana	0:23d1f73bf130	928	#define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection
vladvana	0:23d1f73bf130	929	#define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq
vladvana	0:23d1f73bf130	930	#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
vladvana	0:23d1f73bf130	931	#define __HAL_ADC_JSQR ADC_JSQR
vladvana	0:23d1f73bf130	932
vladvana	0:23d1f73bf130	933	#define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL
vladvana	0:23d1f73bf130	934	#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS
vladvana	0:23d1f73bf130	935	#define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF
vladvana	0:23d1f73bf130	936	#define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT
vladvana	0:23d1f73bf130	937	#define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS
vladvana	0:23d1f73bf130	938	#define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN
vladvana	0:23d1f73bf130	939	#define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR
vladvana	0:23d1f73bf130	940	#define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ
vladvana	0:23d1f73bf130	941
vladvana	0:23d1f73bf130	942	/**
vladvana	0:23d1f73bf130	943	* @}
vladvana	0:23d1f73bf130	944	*/
vladvana	0:23d1f73bf130	945
vladvana	0:23d1f73bf130	946	/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
vladvana	0:23d1f73bf130	947	* @{
vladvana	0:23d1f73bf130	948	*/
vladvana	0:23d1f73bf130	949	#define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT
vladvana	0:23d1f73bf130	950	#define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT
vladvana	0:23d1f73bf130	951	#define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT
vladvana	0:23d1f73bf130	952
vladvana	0:23d1f73bf130	953	/**
vladvana	0:23d1f73bf130	954	* @}
vladvana	0:23d1f73bf130	955	*/
vladvana	0:23d1f73bf130	956
vladvana	0:23d1f73bf130	957	/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose
vladvana	0:23d1f73bf130	958	* @{
vladvana	0:23d1f73bf130	959	*/
vladvana	0:23d1f73bf130	960	#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1
vladvana	0:23d1f73bf130	961	#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1
vladvana	0:23d1f73bf130	962	#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2
vladvana	0:23d1f73bf130	963	#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2
vladvana	0:23d1f73bf130	964	#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3
vladvana	0:23d1f73bf130	965	#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3
vladvana	0:23d1f73bf130	966	#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4
vladvana	0:23d1f73bf130	967	#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4
vladvana	0:23d1f73bf130	968	#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5
vladvana	0:23d1f73bf130	969	#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5
vladvana	0:23d1f73bf130	970	#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6
vladvana	0:23d1f73bf130	971	#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6
vladvana	0:23d1f73bf130	972	#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7
vladvana	0:23d1f73bf130	973	#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7
vladvana	0:23d1f73bf130	974	#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8
vladvana	0:23d1f73bf130	975	#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8
vladvana	0:23d1f73bf130	976
vladvana	0:23d1f73bf130	977	#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9
vladvana	0:23d1f73bf130	978	#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9
vladvana	0:23d1f73bf130	979	#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10
vladvana	0:23d1f73bf130	980	#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10
vladvana	0:23d1f73bf130	981	#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11
vladvana	0:23d1f73bf130	982	#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11
vladvana	0:23d1f73bf130	983	#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12
vladvana	0:23d1f73bf130	984	#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12
vladvana	0:23d1f73bf130	985	#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13
vladvana	0:23d1f73bf130	986	#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13
vladvana	0:23d1f73bf130	987	#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14
vladvana	0:23d1f73bf130	988	#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14
vladvana	0:23d1f73bf130	989	#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2
vladvana	0:23d1f73bf130	990	#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2
vladvana	0:23d1f73bf130	991
vladvana	0:23d1f73bf130	992
vladvana	0:23d1f73bf130	993	#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15
vladvana	0:23d1f73bf130	994	#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15
vladvana	0:23d1f73bf130	995	#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16
vladvana	0:23d1f73bf130	996	#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16
vladvana	0:23d1f73bf130	997	#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17
vladvana	0:23d1f73bf130	998	#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17
vladvana	0:23d1f73bf130	999	#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
vladvana	0:23d1f73bf130	1000	#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
vladvana	0:23d1f73bf130	1001	#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
vladvana	0:23d1f73bf130	1002	#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
vladvana	0:23d1f73bf130	1003	#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
vladvana	0:23d1f73bf130	1004	#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
vladvana	0:23d1f73bf130	1005	#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
vladvana	0:23d1f73bf130	1006	#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
vladvana	0:23d1f73bf130	1007	#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT
vladvana	0:23d1f73bf130	1008	#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT
vladvana	0:23d1f73bf130	1009	#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT
vladvana	0:23d1f73bf130	1010	#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT
vladvana	0:23d1f73bf130	1011	#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1
vladvana	0:23d1f73bf130	1012	#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1
vladvana	0:23d1f73bf130	1013	#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1
vladvana	0:23d1f73bf130	1014	#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1
vladvana	0:23d1f73bf130	1015	#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2
vladvana	0:23d1f73bf130	1016	#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2
vladvana	0:23d1f73bf130	1017
vladvana	0:23d1f73bf130	1018	/**
vladvana	0:23d1f73bf130	1019	* @}
vladvana	0:23d1f73bf130	1020	*/
vladvana	0:23d1f73bf130	1021
vladvana	0:23d1f73bf130	1022	/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose
vladvana	0:23d1f73bf130	1023	* @{
vladvana	0:23d1f73bf130	1024	*/
vladvana	0:23d1f73bf130	1025
vladvana	0:23d1f73bf130	1026	#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
vladvana	0:23d1f73bf130	1027	__HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
vladvana	0:23d1f73bf130	1028	#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
vladvana	0:23d1f73bf130	1029	__HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
vladvana	0:23d1f73bf130	1030	#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
vladvana	0:23d1f73bf130	1031	__HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
vladvana	0:23d1f73bf130	1032	#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
vladvana	0:23d1f73bf130	1033	__HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
vladvana	0:23d1f73bf130	1034	#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
vladvana	0:23d1f73bf130	1035	__HAL_COMP_COMP2_EXTI_ENABLE_IT())
vladvana	0:23d1f73bf130	1036	#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
vladvana	0:23d1f73bf130	1037	__HAL_COMP_COMP2_EXTI_DISABLE_IT())
vladvana	0:23d1f73bf130	1038	#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
vladvana	0:23d1f73bf130	1039	__HAL_COMP_COMP2_EXTI_GET_FLAG())
vladvana	0:23d1f73bf130	1040	#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
vladvana	0:23d1f73bf130	1041	__HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
vladvana	0:23d1f73bf130	1042	#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE
vladvana	0:23d1f73bf130	1043
vladvana	0:23d1f73bf130	1044	/**
vladvana	0:23d1f73bf130	1045	* @}
vladvana	0:23d1f73bf130	1046	*/
vladvana	0:23d1f73bf130	1047
vladvana	0:23d1f73bf130	1048	/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose
vladvana	0:23d1f73bf130	1049	* @{
vladvana	0:23d1f73bf130	1050	*/
vladvana	0:23d1f73bf130	1051
vladvana	0:23d1f73bf130	1052	#define IS_WRPAREA IS_OB_WRPAREA
vladvana	0:23d1f73bf130	1053	#define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM
vladvana	0:23d1f73bf130	1054	#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM
vladvana	0:23d1f73bf130	1055	#define IS_TYPEERASE IS_FLASH_TYPEERASE
vladvana	0:23d1f73bf130	1056
vladvana	0:23d1f73bf130	1057	/**
vladvana	0:23d1f73bf130	1058	* @}
vladvana	0:23d1f73bf130	1059	*/
vladvana	0:23d1f73bf130	1060
vladvana	0:23d1f73bf130	1061	/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose
vladvana	0:23d1f73bf130	1062	* @{
vladvana	0:23d1f73bf130	1063	*/
vladvana	0:23d1f73bf130	1064
vladvana	0:23d1f73bf130	1065	#define __HAL_I2C_RESET_CR2 I2C_RESET_CR2
vladvana	0:23d1f73bf130	1066	#define __HAL_I2C_GENERATE_START I2C_GENERATE_START
vladvana	0:23d1f73bf130	1067	#define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE
vladvana	0:23d1f73bf130	1068	#define __HAL_I2C_RISE_TIME I2C_RISE_TIME
vladvana	0:23d1f73bf130	1069	#define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD
vladvana	0:23d1f73bf130	1070	#define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST
vladvana	0:23d1f73bf130	1071	#define __HAL_I2C_SPEED I2C_SPEED
vladvana	0:23d1f73bf130	1072	#define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE
vladvana	0:23d1f73bf130	1073	#define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ
vladvana	0:23d1f73bf130	1074	#define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS
vladvana	0:23d1f73bf130	1075	#define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE
vladvana	0:23d1f73bf130	1076	#define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ
vladvana	0:23d1f73bf130	1077	#define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB
vladvana	0:23d1f73bf130	1078	#define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB
vladvana	0:23d1f73bf130	1079	#define __HAL_I2C_FREQRANGE I2C_FREQRANGE
vladvana	0:23d1f73bf130	1080	/**
vladvana	0:23d1f73bf130	1081	* @}
vladvana	0:23d1f73bf130	1082	*/
vladvana	0:23d1f73bf130	1083
vladvana	0:23d1f73bf130	1084	/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose
vladvana	0:23d1f73bf130	1085	* @{
vladvana	0:23d1f73bf130	1086	*/
vladvana	0:23d1f73bf130	1087
vladvana	0:23d1f73bf130	1088	#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE
vladvana	0:23d1f73bf130	1089	#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT
vladvana	0:23d1f73bf130	1090
vladvana	0:23d1f73bf130	1091	/**
vladvana	0:23d1f73bf130	1092	* @}
vladvana	0:23d1f73bf130	1093	*/
vladvana	0:23d1f73bf130	1094
vladvana	0:23d1f73bf130	1095	/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose
vladvana	0:23d1f73bf130	1096	* @{
vladvana	0:23d1f73bf130	1097	*/
vladvana	0:23d1f73bf130	1098
vladvana	0:23d1f73bf130	1099	#define __IRDA_DISABLE __HAL_IRDA_DISABLE
vladvana	0:23d1f73bf130	1100	#define __IRDA_ENABLE __HAL_IRDA_ENABLE
vladvana	0:23d1f73bf130	1101
vladvana	0:23d1f73bf130	1102	#define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
vladvana	0:23d1f73bf130	1103	#define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
vladvana	0:23d1f73bf130	1104	#define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
vladvana	0:23d1f73bf130	1105	#define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
vladvana	0:23d1f73bf130	1106
vladvana	0:23d1f73bf130	1107	#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE
vladvana	0:23d1f73bf130	1108
vladvana	0:23d1f73bf130	1109
vladvana	0:23d1f73bf130	1110	/**
vladvana	0:23d1f73bf130	1111	* @}
vladvana	0:23d1f73bf130	1112	*/
vladvana	0:23d1f73bf130	1113
vladvana	0:23d1f73bf130	1114
vladvana	0:23d1f73bf130	1115	/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose
vladvana	0:23d1f73bf130	1116	* @{
vladvana	0:23d1f73bf130	1117	*/
vladvana	0:23d1f73bf130	1118	#define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS
vladvana	0:23d1f73bf130	1119	#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS
vladvana	0:23d1f73bf130	1120	/**
vladvana	0:23d1f73bf130	1121	* @}
vladvana	0:23d1f73bf130	1122	*/
vladvana	0:23d1f73bf130	1123
vladvana	0:23d1f73bf130	1124
vladvana	0:23d1f73bf130	1125	/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose
vladvana	0:23d1f73bf130	1126	* @{
vladvana	0:23d1f73bf130	1127	*/
vladvana	0:23d1f73bf130	1128
vladvana	0:23d1f73bf130	1129	#define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT
vladvana	0:23d1f73bf130	1130	#define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT
vladvana	0:23d1f73bf130	1131	#define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE
vladvana	0:23d1f73bf130	1132
vladvana	0:23d1f73bf130	1133	/**
vladvana	0:23d1f73bf130	1134	* @}
vladvana	0:23d1f73bf130	1135	*/
vladvana	0:23d1f73bf130	1136
vladvana	0:23d1f73bf130	1137	/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose
vladvana	0:23d1f73bf130	1138	* @{
vladvana	0:23d1f73bf130	1139	*/
vladvana	0:23d1f73bf130	1140	#define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
vladvana	0:23d1f73bf130	1141	#define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
vladvana	0:23d1f73bf130	1142	#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
vladvana	0:23d1f73bf130	1143	#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
vladvana	0:23d1f73bf130	1144	#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
vladvana	0:23d1f73bf130	1145	#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
vladvana	0:23d1f73bf130	1146	#define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE
vladvana	0:23d1f73bf130	1147	#define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE
vladvana	0:23d1f73bf130	1148	#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE
vladvana	0:23d1f73bf130	1149	#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE
vladvana	0:23d1f73bf130	1150	#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE
vladvana	0:23d1f73bf130	1151	#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE
vladvana	0:23d1f73bf130	1152	#define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine
vladvana	0:23d1f73bf130	1153	#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine
vladvana	0:23d1f73bf130	1154	#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig
vladvana	0:23d1f73bf130	1155	#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig
vladvana	0:23d1f73bf130	1156	#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE()
vladvana	0:23d1f73bf130	1157	#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
vladvana	0:23d1f73bf130	1158	#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
vladvana	0:23d1f73bf130	1159	#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
vladvana	0:23d1f73bf130	1160	#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
vladvana	0:23d1f73bf130	1161	#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
vladvana	0:23d1f73bf130	1162	#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
vladvana	0:23d1f73bf130	1163	#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
vladvana	0:23d1f73bf130	1164	#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
vladvana	0:23d1f73bf130	1165	#define __HAL_PWR_PVM_DISABLE() HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4()
vladvana	0:23d1f73bf130	1166	#define __HAL_PWR_PVM_ENABLE() HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4()
vladvana	0:23d1f73bf130	1167	#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention
vladvana	0:23d1f73bf130	1168	#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention
vladvana	0:23d1f73bf130	1169	#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2
vladvana	0:23d1f73bf130	1170	#define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2
vladvana	0:23d1f73bf130	1171	#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE
vladvana	0:23d1f73bf130	1172	#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE
vladvana	0:23d1f73bf130	1173	#define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB
vladvana	0:23d1f73bf130	1174	#define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB
vladvana	0:23d1f73bf130	1175
vladvana	0:23d1f73bf130	1176	#if defined (STM32F4)
vladvana	0:23d1f73bf130	1177	#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT()
vladvana	0:23d1f73bf130	1178	#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT()
vladvana	0:23d1f73bf130	1179	#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG()
vladvana	0:23d1f73bf130	1180	#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG()
vladvana	0:23d1f73bf130	1181	#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT()
vladvana	0:23d1f73bf130	1182	#else
vladvana	0:23d1f73bf130	1183	#define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG
vladvana	0:23d1f73bf130	1184	#define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT
vladvana	0:23d1f73bf130	1185	#define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT
vladvana	0:23d1f73bf130	1186	#define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT
vladvana	0:23d1f73bf130	1187	#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG
vladvana	0:23d1f73bf130	1188	#endif /* STM32F4 */
vladvana	0:23d1f73bf130	1189	/**
vladvana	0:23d1f73bf130	1190	* @}
vladvana	0:23d1f73bf130	1191	*/
vladvana	0:23d1f73bf130	1192
vladvana	0:23d1f73bf130	1193
vladvana	0:23d1f73bf130	1194	/** @defgroup HAL_RCC_Aliased_Macros HAL RCC Aliased Macros maintained for legacy purpose
vladvana	0:23d1f73bf130	1195	* @{
vladvana	0:23d1f73bf130	1196	*/
vladvana	0:23d1f73bf130	1197	#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
vladvana	0:23d1f73bf130	1198	#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
vladvana	0:23d1f73bf130	1199	#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1200	#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1201	#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET
vladvana	0:23d1f73bf130	1202	#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET
vladvana	0:23d1f73bf130	1203	#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE
vladvana	0:23d1f73bf130	1204	#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE
vladvana	0:23d1f73bf130	1205	#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET
vladvana	0:23d1f73bf130	1206	#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET
vladvana	0:23d1f73bf130	1207	#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE
vladvana	0:23d1f73bf130	1208	#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE
vladvana	0:23d1f73bf130	1209	#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET
vladvana	0:23d1f73bf130	1210	#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET
vladvana	0:23d1f73bf130	1211	#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE
vladvana	0:23d1f73bf130	1212	#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE
vladvana	0:23d1f73bf130	1213	#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET
vladvana	0:23d1f73bf130	1214	#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET
vladvana	0:23d1f73bf130	1215	#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
vladvana	0:23d1f73bf130	1216	#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
vladvana	0:23d1f73bf130	1217	#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1218	#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1219	#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
vladvana	0:23d1f73bf130	1220	#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
vladvana	0:23d1f73bf130	1221	#define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1222	#define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1223	#define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE
vladvana	0:23d1f73bf130	1224	#define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE
vladvana	0:23d1f73bf130	1225	#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
vladvana	0:23d1f73bf130	1226	#define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET
vladvana	0:23d1f73bf130	1227	#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
vladvana	0:23d1f73bf130	1228	#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
vladvana	0:23d1f73bf130	1229	#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
vladvana	0:23d1f73bf130	1230	#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
vladvana	0:23d1f73bf130	1231	#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET
vladvana	0:23d1f73bf130	1232	#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET
vladvana	0:23d1f73bf130	1233	#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET
vladvana	0:23d1f73bf130	1234	#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET
vladvana	0:23d1f73bf130	1235	#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET
vladvana	0:23d1f73bf130	1236	#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET
vladvana	0:23d1f73bf130	1237	#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET
vladvana	0:23d1f73bf130	1238	#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET
vladvana	0:23d1f73bf130	1239	#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET
vladvana	0:23d1f73bf130	1240	#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
vladvana	0:23d1f73bf130	1241	#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
vladvana	0:23d1f73bf130	1242	#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
vladvana	0:23d1f73bf130	1243	#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
vladvana	0:23d1f73bf130	1244	#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
vladvana	0:23d1f73bf130	1245	#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
vladvana	0:23d1f73bf130	1246	#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET
vladvana	0:23d1f73bf130	1247	#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
vladvana	0:23d1f73bf130	1248	#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
vladvana	0:23d1f73bf130	1249	#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1250	#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1251	#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
vladvana	0:23d1f73bf130	1252	#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
vladvana	0:23d1f73bf130	1253	#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE
vladvana	0:23d1f73bf130	1254	#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE
vladvana	0:23d1f73bf130	1255	#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET
vladvana	0:23d1f73bf130	1256	#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET
vladvana	0:23d1f73bf130	1257	#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE
vladvana	0:23d1f73bf130	1258	#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE
vladvana	0:23d1f73bf130	1259	#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET
vladvana	0:23d1f73bf130	1260	#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET
vladvana	0:23d1f73bf130	1261	#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE
vladvana	0:23d1f73bf130	1262	#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE
vladvana	0:23d1f73bf130	1263	#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1264	#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1265	#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET
vladvana	0:23d1f73bf130	1266	#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET
vladvana	0:23d1f73bf130	1267	#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE
vladvana	0:23d1f73bf130	1268	#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE
vladvana	0:23d1f73bf130	1269	#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET
vladvana	0:23d1f73bf130	1270	#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET
vladvana	0:23d1f73bf130	1271	#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE
vladvana	0:23d1f73bf130	1272	#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE
vladvana	0:23d1f73bf130	1273	#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1274	#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1275	#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET
vladvana	0:23d1f73bf130	1276	#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET
vladvana	0:23d1f73bf130	1277	#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE
vladvana	0:23d1f73bf130	1278	#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE
vladvana	0:23d1f73bf130	1279	#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1280	#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1281	#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET
vladvana	0:23d1f73bf130	1282	#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET
vladvana	0:23d1f73bf130	1283	#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE
vladvana	0:23d1f73bf130	1284	#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE
vladvana	0:23d1f73bf130	1285	#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1286	#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1287	#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET
vladvana	0:23d1f73bf130	1288	#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET
vladvana	0:23d1f73bf130	1289	#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
vladvana	0:23d1f73bf130	1290	#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
vladvana	0:23d1f73bf130	1291	#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1292	#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1293	#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET
vladvana	0:23d1f73bf130	1294	#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET
vladvana	0:23d1f73bf130	1295	#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE
vladvana	0:23d1f73bf130	1296	#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE
vladvana	0:23d1f73bf130	1297	#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET
vladvana	0:23d1f73bf130	1298	#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET
vladvana	0:23d1f73bf130	1299	#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE
vladvana	0:23d1f73bf130	1300	#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE
vladvana	0:23d1f73bf130	1301	#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE
vladvana	0:23d1f73bf130	1302	#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE
vladvana	0:23d1f73bf130	1303	#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE
vladvana	0:23d1f73bf130	1304	#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE
vladvana	0:23d1f73bf130	1305	#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE
vladvana	0:23d1f73bf130	1306	#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE
vladvana	0:23d1f73bf130	1307	#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1308	#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1309	#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET
vladvana	0:23d1f73bf130	1310	#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET
vladvana	0:23d1f73bf130	1311	#define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE
vladvana	0:23d1f73bf130	1312	#define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE
vladvana	0:23d1f73bf130	1313	#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE
vladvana	0:23d1f73bf130	1314	#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE
vladvana	0:23d1f73bf130	1315	#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1316	#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1317	#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET
vladvana	0:23d1f73bf130	1318	#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET
vladvana	0:23d1f73bf130	1319	#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE
vladvana	0:23d1f73bf130	1320	#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE
vladvana	0:23d1f73bf130	1321	#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE
vladvana	0:23d1f73bf130	1322	#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE
vladvana	0:23d1f73bf130	1323	#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1324	#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1325	#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET
vladvana	0:23d1f73bf130	1326	#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET
vladvana	0:23d1f73bf130	1327	#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE
vladvana	0:23d1f73bf130	1328	#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE
vladvana	0:23d1f73bf130	1329	#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1330	#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1331	#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET
vladvana	0:23d1f73bf130	1332	#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET
vladvana	0:23d1f73bf130	1333	#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE
vladvana	0:23d1f73bf130	1334	#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE
vladvana	0:23d1f73bf130	1335	#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1336	#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1337	#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET
vladvana	0:23d1f73bf130	1338	#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET
vladvana	0:23d1f73bf130	1339	#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE
vladvana	0:23d1f73bf130	1340	#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE
vladvana	0:23d1f73bf130	1341	#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1342	#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1343	#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET
vladvana	0:23d1f73bf130	1344	#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET
vladvana	0:23d1f73bf130	1345	#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE
vladvana	0:23d1f73bf130	1346	#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE
vladvana	0:23d1f73bf130	1347	#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1348	#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1349	#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET
vladvana	0:23d1f73bf130	1350	#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET
vladvana	0:23d1f73bf130	1351	#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE
vladvana	0:23d1f73bf130	1352	#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE
vladvana	0:23d1f73bf130	1353	#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1354	#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1355	#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET
vladvana	0:23d1f73bf130	1356	#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET
vladvana	0:23d1f73bf130	1357	#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE
vladvana	0:23d1f73bf130	1358	#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE
vladvana	0:23d1f73bf130	1359	#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1360	#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1361	#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET
vladvana	0:23d1f73bf130	1362	#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET
vladvana	0:23d1f73bf130	1363	#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE
vladvana	0:23d1f73bf130	1364	#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE
vladvana	0:23d1f73bf130	1365	#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1366	#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1367	#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET
vladvana	0:23d1f73bf130	1368	#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET
vladvana	0:23d1f73bf130	1369	#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE
vladvana	0:23d1f73bf130	1370	#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE
vladvana	0:23d1f73bf130	1371	#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1372	#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1373	#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET
vladvana	0:23d1f73bf130	1374	#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET
vladvana	0:23d1f73bf130	1375	#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE
vladvana	0:23d1f73bf130	1376	#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE
vladvana	0:23d1f73bf130	1377	#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1378	#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1379	#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET
vladvana	0:23d1f73bf130	1380	#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET
vladvana	0:23d1f73bf130	1381	#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE
vladvana	0:23d1f73bf130	1382	#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE
vladvana	0:23d1f73bf130	1383	#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1384	#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1385	#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET
vladvana	0:23d1f73bf130	1386	#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET
vladvana	0:23d1f73bf130	1387	#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE
vladvana	0:23d1f73bf130	1388	#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE
vladvana	0:23d1f73bf130	1389	#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1390	#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1391	#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET
vladvana	0:23d1f73bf130	1392	#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET
vladvana	0:23d1f73bf130	1393	#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE
vladvana	0:23d1f73bf130	1394	#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE
vladvana	0:23d1f73bf130	1395	#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1396	#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1397	#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET
vladvana	0:23d1f73bf130	1398	#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET
vladvana	0:23d1f73bf130	1399	#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE
vladvana	0:23d1f73bf130	1400	#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE
vladvana	0:23d1f73bf130	1401	#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1402	#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1403	#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET
vladvana	0:23d1f73bf130	1404	#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET
vladvana	0:23d1f73bf130	1405	#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE
vladvana	0:23d1f73bf130	1406	#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE
vladvana	0:23d1f73bf130	1407	#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1408	#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1409	#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET
vladvana	0:23d1f73bf130	1410	#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET
vladvana	0:23d1f73bf130	1411	#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE
vladvana	0:23d1f73bf130	1412	#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE
vladvana	0:23d1f73bf130	1413	#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1414	#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1415	#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET
vladvana	0:23d1f73bf130	1416	#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET
vladvana	0:23d1f73bf130	1417	#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE
vladvana	0:23d1f73bf130	1418	#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE
vladvana	0:23d1f73bf130	1419	#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1420	#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1421	#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET
vladvana	0:23d1f73bf130	1422	#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET
vladvana	0:23d1f73bf130	1423	#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE
vladvana	0:23d1f73bf130	1424	#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE
vladvana	0:23d1f73bf130	1425	#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1426	#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1427	#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET
vladvana	0:23d1f73bf130	1428	#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET
vladvana	0:23d1f73bf130	1429	#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE
vladvana	0:23d1f73bf130	1430	#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE
vladvana	0:23d1f73bf130	1431	#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1432	#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1433	#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
vladvana	0:23d1f73bf130	1434	#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
vladvana	0:23d1f73bf130	1435	#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
vladvana	0:23d1f73bf130	1436	#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
vladvana	0:23d1f73bf130	1437	#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1438	#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1439	#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET
vladvana	0:23d1f73bf130	1440	#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET
vladvana	0:23d1f73bf130	1441	#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE
vladvana	0:23d1f73bf130	1442	#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE
vladvana	0:23d1f73bf130	1443	#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1444	#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1445	#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET
vladvana	0:23d1f73bf130	1446	#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET
vladvana	0:23d1f73bf130	1447	#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE
vladvana	0:23d1f73bf130	1448	#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE
vladvana	0:23d1f73bf130	1449	#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1450	#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1451	#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET
vladvana	0:23d1f73bf130	1452	#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET
vladvana	0:23d1f73bf130	1453	#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
vladvana	0:23d1f73bf130	1454	#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
vladvana	0:23d1f73bf130	1455	#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE
vladvana	0:23d1f73bf130	1456	#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE
vladvana	0:23d1f73bf130	1457	#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1458	#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1459	#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET
vladvana	0:23d1f73bf130	1460	#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET
vladvana	0:23d1f73bf130	1461	#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE
vladvana	0:23d1f73bf130	1462	#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE
vladvana	0:23d1f73bf130	1463	#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1464	#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1465	#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET
vladvana	0:23d1f73bf130	1466	#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET
vladvana	0:23d1f73bf130	1467	#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE
vladvana	0:23d1f73bf130	1468	#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE
vladvana	0:23d1f73bf130	1469	#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1470	#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1471	#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET
vladvana	0:23d1f73bf130	1472	#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET
vladvana	0:23d1f73bf130	1473	#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE
vladvana	0:23d1f73bf130	1474	#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE
vladvana	0:23d1f73bf130	1475	#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1476	#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1477	#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET
vladvana	0:23d1f73bf130	1478	#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET
vladvana	0:23d1f73bf130	1479	#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE
vladvana	0:23d1f73bf130	1480	#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE
vladvana	0:23d1f73bf130	1481	#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1482	#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1483	#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1484	#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1485	#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE
vladvana	0:23d1f73bf130	1486	#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE
vladvana	0:23d1f73bf130	1487	#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1488	#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1489	#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET
vladvana	0:23d1f73bf130	1490	#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET
vladvana	0:23d1f73bf130	1491	#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE
vladvana	0:23d1f73bf130	1492	#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE
vladvana	0:23d1f73bf130	1493	#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1494	#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1495	#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET
vladvana	0:23d1f73bf130	1496	#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET
vladvana	0:23d1f73bf130	1497	#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE
vladvana	0:23d1f73bf130	1498	#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE
vladvana	0:23d1f73bf130	1499	#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1500	#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1501	#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET
vladvana	0:23d1f73bf130	1502	#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET
vladvana	0:23d1f73bf130	1503	#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE
vladvana	0:23d1f73bf130	1504	#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE
vladvana	0:23d1f73bf130	1505	#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET
vladvana	0:23d1f73bf130	1506	#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET
vladvana	0:23d1f73bf130	1507	#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE
vladvana	0:23d1f73bf130	1508	#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE
vladvana	0:23d1f73bf130	1509	#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET
vladvana	0:23d1f73bf130	1510	#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET
vladvana	0:23d1f73bf130	1511	#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE
vladvana	0:23d1f73bf130	1512	#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE
vladvana	0:23d1f73bf130	1513	#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET
vladvana	0:23d1f73bf130	1514	#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET
vladvana	0:23d1f73bf130	1515	#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE
vladvana	0:23d1f73bf130	1516	#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE
vladvana	0:23d1f73bf130	1517	#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET
vladvana	0:23d1f73bf130	1518	#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET
vladvana	0:23d1f73bf130	1519	#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE
vladvana	0:23d1f73bf130	1520	#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE
vladvana	0:23d1f73bf130	1521	#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET
vladvana	0:23d1f73bf130	1522	#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET
vladvana	0:23d1f73bf130	1523	#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE
vladvana	0:23d1f73bf130	1524	#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE
vladvana	0:23d1f73bf130	1525	#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1526	#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1527	#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET
vladvana	0:23d1f73bf130	1528	#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET
vladvana	0:23d1f73bf130	1529	#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE
vladvana	0:23d1f73bf130	1530	#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE
vladvana	0:23d1f73bf130	1531	#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1532	#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1533	#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET
vladvana	0:23d1f73bf130	1534	#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET
vladvana	0:23d1f73bf130	1535	#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE
vladvana	0:23d1f73bf130	1536	#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE
vladvana	0:23d1f73bf130	1537	#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1538	#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1539	#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET
vladvana	0:23d1f73bf130	1540	#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET
vladvana	0:23d1f73bf130	1541	#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE
vladvana	0:23d1f73bf130	1542	#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE
vladvana	0:23d1f73bf130	1543	#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1544	#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1545	#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET
vladvana	0:23d1f73bf130	1546	#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET
vladvana	0:23d1f73bf130	1547	#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE
vladvana	0:23d1f73bf130	1548	#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE
vladvana	0:23d1f73bf130	1549	#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1550	#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1551	#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET
vladvana	0:23d1f73bf130	1552	#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET
vladvana	0:23d1f73bf130	1553	#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE
vladvana	0:23d1f73bf130	1554	#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE
vladvana	0:23d1f73bf130	1555	#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1556	#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1557	#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET
vladvana	0:23d1f73bf130	1558	#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET
vladvana	0:23d1f73bf130	1559	#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE
vladvana	0:23d1f73bf130	1560	#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE
vladvana	0:23d1f73bf130	1561	#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1562	#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1563	#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET
vladvana	0:23d1f73bf130	1564	#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET
vladvana	0:23d1f73bf130	1565	#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE
vladvana	0:23d1f73bf130	1566	#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE
vladvana	0:23d1f73bf130	1567	#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1568	#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1569	#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET
vladvana	0:23d1f73bf130	1570	#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET
vladvana	0:23d1f73bf130	1571	#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE
vladvana	0:23d1f73bf130	1572	#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE
vladvana	0:23d1f73bf130	1573	#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1574	#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1575	#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET
vladvana	0:23d1f73bf130	1576	#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET
vladvana	0:23d1f73bf130	1577	#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE
vladvana	0:23d1f73bf130	1578	#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE
vladvana	0:23d1f73bf130	1579	#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1580	#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1581	#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET
vladvana	0:23d1f73bf130	1582	#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET
vladvana	0:23d1f73bf130	1583	#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE
vladvana	0:23d1f73bf130	1584	#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE
vladvana	0:23d1f73bf130	1585	#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET
vladvana	0:23d1f73bf130	1586	#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET
vladvana	0:23d1f73bf130	1587	#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE
vladvana	0:23d1f73bf130	1588	#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE
vladvana	0:23d1f73bf130	1589	#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1590	#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1591	#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET
vladvana	0:23d1f73bf130	1592	#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET
vladvana	0:23d1f73bf130	1593	#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
vladvana	0:23d1f73bf130	1594	#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
vladvana	0:23d1f73bf130	1595	#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1596	#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1597	#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
vladvana	0:23d1f73bf130	1598	#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
vladvana	0:23d1f73bf130	1599	#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
vladvana	0:23d1f73bf130	1600	#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
vladvana	0:23d1f73bf130	1601	#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1602	#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1603	#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
vladvana	0:23d1f73bf130	1604	#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
vladvana	0:23d1f73bf130	1605	#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE
vladvana	0:23d1f73bf130	1606	#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE
vladvana	0:23d1f73bf130	1607	#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1608	#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1609	#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET
vladvana	0:23d1f73bf130	1610	#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET
vladvana	0:23d1f73bf130	1611	#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE
vladvana	0:23d1f73bf130	1612	#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE
vladvana	0:23d1f73bf130	1613	#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1614	#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1615	#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET
vladvana	0:23d1f73bf130	1616	#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET
vladvana	0:23d1f73bf130	1617	#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE
vladvana	0:23d1f73bf130	1618	#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE
vladvana	0:23d1f73bf130	1619	#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1620	#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1621	#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
vladvana	0:23d1f73bf130	1622	#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
vladvana	0:23d1f73bf130	1623	#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE
vladvana	0:23d1f73bf130	1624	#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE
vladvana	0:23d1f73bf130	1625	#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET
vladvana	0:23d1f73bf130	1626	#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE
vladvana	0:23d1f73bf130	1627	#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE
vladvana	0:23d1f73bf130	1628	#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET
vladvana	0:23d1f73bf130	1629	#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
vladvana	0:23d1f73bf130	1630	#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE
vladvana	0:23d1f73bf130	1631	#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1632	#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1633	#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET
vladvana	0:23d1f73bf130	1634	#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET
vladvana	0:23d1f73bf130	1635	#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE
vladvana	0:23d1f73bf130	1636	#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE
vladvana	0:23d1f73bf130	1637	#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET
vladvana	0:23d1f73bf130	1638	#define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET
vladvana	0:23d1f73bf130	1639	#define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1640	#define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1641	#define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE
vladvana	0:23d1f73bf130	1642	#define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE
vladvana	0:23d1f73bf130	1643	#define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET
vladvana	0:23d1f73bf130	1644	#define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET
vladvana	0:23d1f73bf130	1645	#define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1646	#define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1647	#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE
vladvana	0:23d1f73bf130	1648	#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE
vladvana	0:23d1f73bf130	1649	#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1650	#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1651	#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET
vladvana	0:23d1f73bf130	1652	#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET
vladvana	0:23d1f73bf130	1653	#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE
vladvana	0:23d1f73bf130	1654	#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE
vladvana	0:23d1f73bf130	1655
vladvana	0:23d1f73bf130	1656	#define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
vladvana	0:23d1f73bf130	1657	#define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
vladvana	0:23d1f73bf130	1658	#define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1659	#define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1660	#define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE
vladvana	0:23d1f73bf130	1661	#define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE
vladvana	0:23d1f73bf130	1662	#define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE
vladvana	0:23d1f73bf130	1663	#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE
vladvana	0:23d1f73bf130	1664	#define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1665	#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1666	#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1667	#define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1668	#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1669	#define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1670	#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1671	#define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1672	#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1673	#define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1674	#define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1675	#define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE
vladvana	0:23d1f73bf130	1676	#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE
vladvana	0:23d1f73bf130	1677	#define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE
vladvana	0:23d1f73bf130	1678	#define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET
vladvana	0:23d1f73bf130	1679	#define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET
vladvana	0:23d1f73bf130	1680	#define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1681	#define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1682	#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE
vladvana	0:23d1f73bf130	1683	#define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE
vladvana	0:23d1f73bf130	1684	#define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE
vladvana	0:23d1f73bf130	1685	#define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET
vladvana	0:23d1f73bf130	1686	#define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET
vladvana	0:23d1f73bf130	1687	#define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1688	#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1689	#define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE
vladvana	0:23d1f73bf130	1690	#define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE
vladvana	0:23d1f73bf130	1691	#define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET
vladvana	0:23d1f73bf130	1692	#define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET
vladvana	0:23d1f73bf130	1693	#define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1694	#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1695	#define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE
vladvana	0:23d1f73bf130	1696	#define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE
vladvana	0:23d1f73bf130	1697	#define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET
vladvana	0:23d1f73bf130	1698	#define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET
vladvana	0:23d1f73bf130	1699	#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1700	#define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1701	#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1702	#define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1703	#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1704	#define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1705	#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1706	#define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1707	#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1708	#define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1709	#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1710	#define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1711	#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1712	#define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE
vladvana	0:23d1f73bf130	1713	#define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE
vladvana	0:23d1f73bf130	1714	#define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1715	#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1716	#define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE
vladvana	0:23d1f73bf130	1717	#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE
vladvana	0:23d1f73bf130	1718	#define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE
vladvana	0:23d1f73bf130	1719	#define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE
vladvana	0:23d1f73bf130	1720	#define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET
vladvana	0:23d1f73bf130	1721	#define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET
vladvana	0:23d1f73bf130	1722	#define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1723	#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1724	#define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE
vladvana	0:23d1f73bf130	1725	#define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE
vladvana	0:23d1f73bf130	1726	#define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET
vladvana	0:23d1f73bf130	1727	#define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET
vladvana	0:23d1f73bf130	1728	#define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1729	#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1730	#define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE
vladvana	0:23d1f73bf130	1731	#define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE
vladvana	0:23d1f73bf130	1732	#define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET
vladvana	0:23d1f73bf130	1733	#define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET
vladvana	0:23d1f73bf130	1734	#define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1735	#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1736	#define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE
vladvana	0:23d1f73bf130	1737	#define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE
vladvana	0:23d1f73bf130	1738	#define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET
vladvana	0:23d1f73bf130	1739	#define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET
vladvana	0:23d1f73bf130	1740	#define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1741	#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1742	#define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE
vladvana	0:23d1f73bf130	1743	#define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE
vladvana	0:23d1f73bf130	1744	#define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET
vladvana	0:23d1f73bf130	1745	#define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1746	#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1747	#define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE
vladvana	0:23d1f73bf130	1748	#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE
vladvana	0:23d1f73bf130	1749	#define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE
vladvana	0:23d1f73bf130	1750	#define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE
vladvana	0:23d1f73bf130	1751	#define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET
vladvana	0:23d1f73bf130	1752	#define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET
vladvana	0:23d1f73bf130	1753	#define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1754	#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1755	#define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
vladvana	0:23d1f73bf130	1756	#define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
vladvana	0:23d1f73bf130	1757	#define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
vladvana	0:23d1f73bf130	1758	#define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
vladvana	0:23d1f73bf130	1759	#define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1760	#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1761	#define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
vladvana	0:23d1f73bf130	1762	#define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
vladvana	0:23d1f73bf130	1763	#define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
vladvana	0:23d1f73bf130	1764	#define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
vladvana	0:23d1f73bf130	1765	#define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1766	#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1767	#define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1768	#define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1769	#define __OTGHS_FORCE_RESET __HAL_RCC_OTGHS_FORCE_RESET
vladvana	0:23d1f73bf130	1770	#define __OTGHS_RELEASE_RESET __HAL_RCC_OTGHS_RELEASE_RESET
vladvana	0:23d1f73bf130	1771	#define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1772	#define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1773	#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
vladvana	0:23d1f73bf130	1774	#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1775	#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1776	#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1777	#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1778	#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1779	#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1780	#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1781	#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1782	#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1783	#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET
vladvana	0:23d1f73bf130	1784	#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET
vladvana	0:23d1f73bf130	1785	#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1786	#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1787	#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
vladvana	0:23d1f73bf130	1788	#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
vladvana	0:23d1f73bf130	1789	#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1790	#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1791	#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE
vladvana	0:23d1f73bf130	1792	#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE
vladvana	0:23d1f73bf130	1793	#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET
vladvana	0:23d1f73bf130	1794	#define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET
vladvana	0:23d1f73bf130	1795	#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE
vladvana	0:23d1f73bf130	1796	#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE
vladvana	0:23d1f73bf130	1797
vladvana	0:23d1f73bf130	1798	/* alias define maintained for legacy */
vladvana	0:23d1f73bf130	1799	#define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
vladvana	0:23d1f73bf130	1800	#define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
vladvana	0:23d1f73bf130	1801
vladvana	0:23d1f73bf130	1802	#define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG
vladvana	0:23d1f73bf130	1803	#define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG
vladvana	0:23d1f73bf130	1804
vladvana	0:23d1f73bf130	1805	#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE
vladvana	0:23d1f73bf130	1806
vladvana	0:23d1f73bf130	1807	#define HSION_BitNumber RCC_HSION_BIT_NUMBER
vladvana	0:23d1f73bf130	1808	#define CSSON_BitNumber RCC_CSSON_BIT_NUMBER
vladvana	0:23d1f73bf130	1809	#define PLLON_BitNumber RCC_PLLON_BIT_NUMBER
vladvana	0:23d1f73bf130	1810	#define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER
vladvana	0:23d1f73bf130	1811	#define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER
vladvana	0:23d1f73bf130	1812	#define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER
vladvana	0:23d1f73bf130	1813	#define BDRST_BitNumber RCC_BDRST_BIT_NUMBER
vladvana	0:23d1f73bf130	1814	#define LSION_BitNumber RCC_LSION_BIT_NUMBER
vladvana	0:23d1f73bf130	1815	#define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER
vladvana	0:23d1f73bf130	1816	#define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER
vladvana	0:23d1f73bf130	1817
vladvana	0:23d1f73bf130	1818	#define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS
vladvana	0:23d1f73bf130	1819	#define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS
vladvana	0:23d1f73bf130	1820	#define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS
vladvana	0:23d1f73bf130	1821	#define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS
vladvana	0:23d1f73bf130	1822	#define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE
vladvana	0:23d1f73bf130	1823	#define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE
vladvana	0:23d1f73bf130	1824
vladvana	0:23d1f73bf130	1825	#define CR_HSION_BB RCC_CR_HSION_BB
vladvana	0:23d1f73bf130	1826	#define CR_CSSON_BB RCC_CR_CSSON_BB
vladvana	0:23d1f73bf130	1827	#define CR_PLLON_BB RCC_CR_PLLON_BB
vladvana	0:23d1f73bf130	1828	#define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB
vladvana	0:23d1f73bf130	1829	#define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB
vladvana	0:23d1f73bf130	1830	#define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB
vladvana	0:23d1f73bf130	1831	#define BDCR_BDRST_BB RCC_BDCR_BDRST_BB
vladvana	0:23d1f73bf130	1832	#define CSR_LSION_BB RCC_CSR_LSION_BB
vladvana	0:23d1f73bf130	1833	#define CR_PLLSAION_BB RCC_CR_PLLSAION_BB
vladvana	0:23d1f73bf130	1834	#define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB
vladvana	0:23d1f73bf130	1835
vladvana	0:23d1f73bf130	1836	/**
vladvana	0:23d1f73bf130	1837	* @}
vladvana	0:23d1f73bf130	1838	*/
vladvana	0:23d1f73bf130	1839
vladvana	0:23d1f73bf130	1840	/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose
vladvana	0:23d1f73bf130	1841	* @{
vladvana	0:23d1f73bf130	1842	*/
vladvana	0:23d1f73bf130	1843	#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback(__HANDLE__, uint32_t random32bit)
vladvana	0:23d1f73bf130	1844
vladvana	0:23d1f73bf130	1845	/**
vladvana	0:23d1f73bf130	1846	* @}
vladvana	0:23d1f73bf130	1847	*/
vladvana	0:23d1f73bf130	1848
vladvana	0:23d1f73bf130	1849	/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
vladvana	0:23d1f73bf130	1850	* @{
vladvana	0:23d1f73bf130	1851	*/
vladvana	0:23d1f73bf130	1852
vladvana	0:23d1f73bf130	1853	#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
vladvana	0:23d1f73bf130	1854	#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT
vladvana	0:23d1f73bf130	1855	#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT
vladvana	0:23d1f73bf130	1856	#if defined (RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
vladvana	0:23d1f73bf130	1857	#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) ((__EXTI_LINE__ == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \
vladvana	0:23d1f73bf130	1858	((__EXTI_LINE__ == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \
vladvana	0:23d1f73bf130	1859	__HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
vladvana	0:23d1f73bf130	1860	#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) ((__EXTI_LINE__ == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \
vladvana	0:23d1f73bf130	1861	((__EXTI_LINE__ == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
vladvana	0:23d1f73bf130	1862	__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
vladvana	0:23d1f73bf130	1863	#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) ((__EXTI_LINE__ == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \
vladvana	0:23d1f73bf130	1864	((__EXTI_LINE__ == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
vladvana	0:23d1f73bf130	1865	__HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
vladvana	0:23d1f73bf130	1866	#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) ((__EXTI_LINE__ == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \
vladvana	0:23d1f73bf130	1867	((__EXTI_LINE__ == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
vladvana	0:23d1f73bf130	1868	__HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
vladvana	0:23d1f73bf130	1869	#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) ((__EXTI_LINE__ == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \
vladvana	0:23d1f73bf130	1870	((__EXTI_LINE__ == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \
vladvana	0:23d1f73bf130	1871	__HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
vladvana	0:23d1f73bf130	1872
vladvana	0:23d1f73bf130	1873	#else
vladvana	0:23d1f73bf130	1874	#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()
vladvana	0:23d1f73bf130	1875
vladvana	0:23d1f73bf130	1876	#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT()
vladvana	0:23d1f73bf130	1877
vladvana	0:23d1f73bf130	1878	#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT()
vladvana	0:23d1f73bf130	1879
vladvana	0:23d1f73bf130	1880	#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG()
vladvana	0:23d1f73bf130	1881
vladvana	0:23d1f73bf130	1882	#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()
vladvana	0:23d1f73bf130	1883
vladvana	0:23d1f73bf130	1884	#endif
vladvana	0:23d1f73bf130	1885
vladvana	0:23d1f73bf130	1886	#define IS_ALARM IS_RTC_ALARM
vladvana	0:23d1f73bf130	1887	#define IS_ALARM_MASK IS_RTC_ALARM_MASK
vladvana	0:23d1f73bf130	1888	#define IS_TAMPER IS_RTC_TAMPER
vladvana	0:23d1f73bf130	1889	#define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE
vladvana	0:23d1f73bf130	1890	#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER
vladvana	0:23d1f73bf130	1891	#define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT
vladvana	0:23d1f73bf130	1892	#define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE
vladvana	0:23d1f73bf130	1893	#define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION
vladvana	0:23d1f73bf130	1894	#define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE
vladvana	0:23d1f73bf130	1895	#define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ
vladvana	0:23d1f73bf130	1896	#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION
vladvana	0:23d1f73bf130	1897	#define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER
vladvana	0:23d1f73bf130	1898	#define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK
vladvana	0:23d1f73bf130	1899	#define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER
vladvana	0:23d1f73bf130	1900
vladvana	0:23d1f73bf130	1901	#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE
vladvana	0:23d1f73bf130	1902	#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE
vladvana	0:23d1f73bf130	1903
vladvana	0:23d1f73bf130	1904	/**
vladvana	0:23d1f73bf130	1905	* @}
vladvana	0:23d1f73bf130	1906	*/
vladvana	0:23d1f73bf130	1907
vladvana	0:23d1f73bf130	1908	/** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose
vladvana	0:23d1f73bf130	1909	* @{
vladvana	0:23d1f73bf130	1910	*/
vladvana	0:23d1f73bf130	1911
vladvana	0:23d1f73bf130	1912	#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
vladvana	0:23d1f73bf130	1913	#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS
vladvana	0:23d1f73bf130	1914
vladvana	0:23d1f73bf130	1915	/**
vladvana	0:23d1f73bf130	1916	* @}
vladvana	0:23d1f73bf130	1917	*/
vladvana	0:23d1f73bf130	1918
vladvana	0:23d1f73bf130	1919	/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose
vladvana	0:23d1f73bf130	1920	* @{
vladvana	0:23d1f73bf130	1921	*/
vladvana	0:23d1f73bf130	1922
vladvana	0:23d1f73bf130	1923	#define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT
vladvana	0:23d1f73bf130	1924	#define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT
vladvana	0:23d1f73bf130	1925	#define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE
vladvana	0:23d1f73bf130	1926	#define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE
vladvana	0:23d1f73bf130	1927	#define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE
vladvana	0:23d1f73bf130	1928	#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE
vladvana	0:23d1f73bf130	1929
vladvana	0:23d1f73bf130	1930	#define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
vladvana	0:23d1f73bf130	1931	#define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
vladvana	0:23d1f73bf130	1932
vladvana	0:23d1f73bf130	1933	#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE
vladvana	0:23d1f73bf130	1934
vladvana	0:23d1f73bf130	1935	/**
vladvana	0:23d1f73bf130	1936	* @}
vladvana	0:23d1f73bf130	1937	*/
vladvana	0:23d1f73bf130	1938
vladvana	0:23d1f73bf130	1939	/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose
vladvana	0:23d1f73bf130	1940	* @{
vladvana	0:23d1f73bf130	1941	*/
vladvana	0:23d1f73bf130	1942	#define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1
vladvana	0:23d1f73bf130	1943	#define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2
vladvana	0:23d1f73bf130	1944	#define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START
vladvana	0:23d1f73bf130	1945	#define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH
vladvana	0:23d1f73bf130	1946	#define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR
vladvana	0:23d1f73bf130	1947	#define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE
vladvana	0:23d1f73bf130	1948	#define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE
vladvana	0:23d1f73bf130	1949	#define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED
vladvana	0:23d1f73bf130	1950	/**
vladvana	0:23d1f73bf130	1951	* @}
vladvana	0:23d1f73bf130	1952	*/
vladvana	0:23d1f73bf130	1953
vladvana	0:23d1f73bf130	1954	/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose
vladvana	0:23d1f73bf130	1955	* @{
vladvana	0:23d1f73bf130	1956	*/
vladvana	0:23d1f73bf130	1957
vladvana	0:23d1f73bf130	1958	#define __HAL_SPI_1LINE_TX SPI_1LINE_TX
vladvana	0:23d1f73bf130	1959	#define __HAL_SPI_1LINE_RX SPI_1LINE_RX
vladvana	0:23d1f73bf130	1960	#define __HAL_SPI_RESET_CRC SPI_RESET_CRC
vladvana	0:23d1f73bf130	1961
vladvana	0:23d1f73bf130	1962	/**
vladvana	0:23d1f73bf130	1963	* @}
vladvana	0:23d1f73bf130	1964	*/
vladvana	0:23d1f73bf130	1965
vladvana	0:23d1f73bf130	1966	/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose
vladvana	0:23d1f73bf130	1967	* @{
vladvana	0:23d1f73bf130	1968	*/
vladvana	0:23d1f73bf130	1969
vladvana	0:23d1f73bf130	1970	#define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
vladvana	0:23d1f73bf130	1971	#define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION
vladvana	0:23d1f73bf130	1972	#define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
vladvana	0:23d1f73bf130	1973	#define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION
vladvana	0:23d1f73bf130	1974
vladvana	0:23d1f73bf130	1975	#define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD
vladvana	0:23d1f73bf130	1976
vladvana	0:23d1f73bf130	1977	#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE
vladvana	0:23d1f73bf130	1978	#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE
vladvana	0:23d1f73bf130	1979
vladvana	0:23d1f73bf130	1980	/**
vladvana	0:23d1f73bf130	1981	* @}
vladvana	0:23d1f73bf130	1982	*/
vladvana	0:23d1f73bf130	1983
vladvana	0:23d1f73bf130	1984
vladvana	0:23d1f73bf130	1985	/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose
vladvana	0:23d1f73bf130	1986	* @{
vladvana	0:23d1f73bf130	1987	*/
vladvana	0:23d1f73bf130	1988
vladvana	0:23d1f73bf130	1989	#define __USART_ENABLE_IT __HAL_USART_ENABLE_IT
vladvana	0:23d1f73bf130	1990	#define __USART_DISABLE_IT __HAL_USART_DISABLE_IT
vladvana	0:23d1f73bf130	1991	#define __USART_ENABLE __HAL_USART_ENABLE
vladvana	0:23d1f73bf130	1992	#define __USART_DISABLE __HAL_USART_DISABLE
vladvana	0:23d1f73bf130	1993
vladvana	0:23d1f73bf130	1994	#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
vladvana	0:23d1f73bf130	1995	#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
vladvana	0:23d1f73bf130	1996
vladvana	0:23d1f73bf130	1997	/**
vladvana	0:23d1f73bf130	1998	* @}
vladvana	0:23d1f73bf130	1999	*/
vladvana	0:23d1f73bf130	2000
vladvana	0:23d1f73bf130	2001	/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose
vladvana	0:23d1f73bf130	2002	* @{
vladvana	0:23d1f73bf130	2003	*/
vladvana	0:23d1f73bf130	2004	#define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE
vladvana	0:23d1f73bf130	2005
vladvana	0:23d1f73bf130	2006	#define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE
vladvana	0:23d1f73bf130	2007	#define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE
vladvana	0:23d1f73bf130	2008	#define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE
vladvana	0:23d1f73bf130	2009	#define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE
vladvana	0:23d1f73bf130	2010
vladvana	0:23d1f73bf130	2011	#define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE
vladvana	0:23d1f73bf130	2012	#define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE
vladvana	0:23d1f73bf130	2013	#define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE
vladvana	0:23d1f73bf130	2014	#define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE
vladvana	0:23d1f73bf130	2015
vladvana	0:23d1f73bf130	2016	#define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT
vladvana	0:23d1f73bf130	2017	#define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT
vladvana	0:23d1f73bf130	2018	#define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG
vladvana	0:23d1f73bf130	2019	#define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG
vladvana	0:23d1f73bf130	2020	#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE
vladvana	0:23d1f73bf130	2021	#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE
vladvana	0:23d1f73bf130	2022	#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
vladvana	0:23d1f73bf130	2023
vladvana	0:23d1f73bf130	2024	#define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT
vladvana	0:23d1f73bf130	2025	#define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT
vladvana	0:23d1f73bf130	2026	#define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG
vladvana	0:23d1f73bf130	2027	#define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG
vladvana	0:23d1f73bf130	2028	#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE
vladvana	0:23d1f73bf130	2029	#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
vladvana	0:23d1f73bf130	2030	#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
vladvana	0:23d1f73bf130	2031	#define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT
vladvana	0:23d1f73bf130	2032
vladvana	0:23d1f73bf130	2033	#define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT
vladvana	0:23d1f73bf130	2034	#define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT
vladvana	0:23d1f73bf130	2035	#define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG
vladvana	0:23d1f73bf130	2036	#define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG
vladvana	0:23d1f73bf130	2037	#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE
vladvana	0:23d1f73bf130	2038	#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
vladvana	0:23d1f73bf130	2039	#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
vladvana	0:23d1f73bf130	2040	#define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT
vladvana	0:23d1f73bf130	2041
vladvana	0:23d1f73bf130	2042	#define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup
vladvana	0:23d1f73bf130	2043	#define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup
vladvana	0:23d1f73bf130	2044
vladvana	0:23d1f73bf130	2045	#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo
vladvana	0:23d1f73bf130	2046	#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo
vladvana	0:23d1f73bf130	2047	/**
vladvana	0:23d1f73bf130	2048	* @}
vladvana	0:23d1f73bf130	2049	*/
vladvana	0:23d1f73bf130	2050
vladvana	0:23d1f73bf130	2051	/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose
vladvana	0:23d1f73bf130	2052	* @{
vladvana	0:23d1f73bf130	2053	*/
vladvana	0:23d1f73bf130	2054	#define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE
vladvana	0:23d1f73bf130	2055	#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE
vladvana	0:23d1f73bf130	2056
vladvana	0:23d1f73bf130	2057	#define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
vladvana	0:23d1f73bf130	2058	#define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT
vladvana	0:23d1f73bf130	2059
vladvana	0:23d1f73bf130	2060	#define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN
vladvana	0:23d1f73bf130	2061	#define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER
vladvana	0:23d1f73bf130	2062	#define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER
vladvana	0:23d1f73bf130	2063	#define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER
vladvana	0:23d1f73bf130	2064	#define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD
vladvana	0:23d1f73bf130	2065	#define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD
vladvana	0:23d1f73bf130	2066	#define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION
vladvana	0:23d1f73bf130	2067	#define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION
vladvana	0:23d1f73bf130	2068	#define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER
vladvana	0:23d1f73bf130	2069	#define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER
vladvana	0:23d1f73bf130	2070	#define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE
vladvana	0:23d1f73bf130	2071	#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE
vladvana	0:23d1f73bf130	2072
vladvana	0:23d1f73bf130	2073	#define TIM_TS_ITR0 ((uint32_t)0x0000)
vladvana	0:23d1f73bf130	2074	#define TIM_TS_ITR1 ((uint32_t)0x0010)
vladvana	0:23d1f73bf130	2075	#define TIM_TS_ITR2 ((uint32_t)0x0020)
vladvana	0:23d1f73bf130	2076	#define TIM_TS_ITR3 ((uint32_t)0x0030)
vladvana	0:23d1f73bf130	2077	#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) \|\| \
vladvana	0:23d1f73bf130	2078	((SELECTION) == TIM_TS_ITR1) \|\| \
vladvana	0:23d1f73bf130	2079	((SELECTION) == TIM_TS_ITR2) \|\| \
vladvana	0:23d1f73bf130	2080	((SELECTION) == TIM_TS_ITR3))
vladvana	0:23d1f73bf130	2081
vladvana	0:23d1f73bf130	2082	#define TIM_CHANNEL_1 ((uint32_t)0x0000)
vladvana	0:23d1f73bf130	2083	#define TIM_CHANNEL_2 ((uint32_t)0x0004)
vladvana	0:23d1f73bf130	2084	#define IS_TIM_PWMI_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
vladvana	0:23d1f73bf130	2085	((CHANNEL) == TIM_CHANNEL_2))
vladvana	0:23d1f73bf130	2086
vladvana	0:23d1f73bf130	2087	#define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000)
vladvana	0:23d1f73bf130	2088	#define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE)
vladvana	0:23d1f73bf130	2089
vladvana	0:23d1f73bf130	2090	#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OUTPUTNSTATE_DISABLE) \|\| \
vladvana	0:23d1f73bf130	2091	((STATE) == TIM_OUTPUTNSTATE_ENABLE))
vladvana	0:23d1f73bf130	2092
vladvana	0:23d1f73bf130	2093	#define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000)
vladvana	0:23d1f73bf130	2094	#define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E)
vladvana	0:23d1f73bf130	2095
vladvana	0:23d1f73bf130	2096	#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OUTPUTSTATE_DISABLE) \|\| \
vladvana	0:23d1f73bf130	2097	((STATE) == TIM_OUTPUTSTATE_ENABLE))
vladvana	0:23d1f73bf130	2098	/**
vladvana	0:23d1f73bf130	2099	* @}
vladvana	0:23d1f73bf130	2100	*/
vladvana	0:23d1f73bf130	2101
vladvana	0:23d1f73bf130	2102	/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose
vladvana	0:23d1f73bf130	2103	* @{
vladvana	0:23d1f73bf130	2104	*/
vladvana	0:23d1f73bf130	2105
vladvana	0:23d1f73bf130	2106	#define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT
vladvana	0:23d1f73bf130	2107	#define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT
vladvana	0:23d1f73bf130	2108	#define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG
vladvana	0:23d1f73bf130	2109	#define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG
vladvana	0:23d1f73bf130	2110	#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER
vladvana	0:23d1f73bf130	2111	#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER
vladvana	0:23d1f73bf130	2112	#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER
vladvana	0:23d1f73bf130	2113
vladvana	0:23d1f73bf130	2114	#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE
vladvana	0:23d1f73bf130	2115	#define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE
vladvana	0:23d1f73bf130	2116	#define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE
vladvana	0:23d1f73bf130	2117	/**
vladvana	0:23d1f73bf130	2118	* @}
vladvana	0:23d1f73bf130	2119	*/
vladvana	0:23d1f73bf130	2120
vladvana	0:23d1f73bf130	2121	/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose
vladvana	0:23d1f73bf130	2122	* @{
vladvana	0:23d1f73bf130	2123	*/
vladvana	0:23d1f73bf130	2124	#define __HAL_LTDC_LAYER LTDC_LAYER
vladvana	0:23d1f73bf130	2125	/**
vladvana	0:23d1f73bf130	2126	* @}
vladvana	0:23d1f73bf130	2127	*/
vladvana	0:23d1f73bf130	2128
vladvana	0:23d1f73bf130	2129	/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose
vladvana	0:23d1f73bf130	2130	* @{
vladvana	0:23d1f73bf130	2131	*/
vladvana	0:23d1f73bf130	2132	#define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE
vladvana	0:23d1f73bf130	2133	#define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE
vladvana	0:23d1f73bf130	2134	#define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE
vladvana	0:23d1f73bf130	2135	#define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE
vladvana	0:23d1f73bf130	2136	#define SAI_STREOMODE SAI_STEREOMODE
vladvana	0:23d1f73bf130	2137	#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY
vladvana	0:23d1f73bf130	2138	#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL
vladvana	0:23d1f73bf130	2139	#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL
vladvana	0:23d1f73bf130	2140	#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL
vladvana	0:23d1f73bf130	2141	#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL
vladvana	0:23d1f73bf130	2142	#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL
vladvana	0:23d1f73bf130	2143	#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE
vladvana	0:23d1f73bf130	2144
vladvana	0:23d1f73bf130	2145	/**
vladvana	0:23d1f73bf130	2146	* @}
vladvana	0:23d1f73bf130	2147	*/
vladvana	0:23d1f73bf130	2148
vladvana	0:23d1f73bf130	2149
vladvana	0:23d1f73bf130	2150	/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
vladvana	0:23d1f73bf130	2151	* @{
vladvana	0:23d1f73bf130	2152	*/
vladvana	0:23d1f73bf130	2153
vladvana	0:23d1f73bf130	2154	/**
vladvana	0:23d1f73bf130	2155	* @}
vladvana	0:23d1f73bf130	2156	*/
vladvana	0:23d1f73bf130	2157
vladvana	0:23d1f73bf130	2158	#ifdef __cplusplus
vladvana	0:23d1f73bf130	2159	}
vladvana	0:23d1f73bf130	2160	#endif
vladvana	0:23d1f73bf130	2161
vladvana	0:23d1f73bf130	2162	#endif /* ___STM32_HAL_LEGACY */
vladvana	0:23d1f73bf130	2163
vladvana	0:23d1f73bf130	2164	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
vladvana	0:23d1f73bf130	2165

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Type:	Program
Created:	24 Sep 2017
Imports:	1
Forks:	0
Commits:	1
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TARGET_NUCLEO_F103RB/stm32_hal_legacy.h@0:23d1f73bf130, 2017-09-24 (annotated)

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