Vladimir Vana / mbed

pro vyuku PSS v Jecne

TARGET_NUCLEO_F103RB/core_cm7.h@0:23d1f73bf130, 2017-09-24 (annotated)

Committer:
vladvana
Date:
Sun Sep 24 12:31:52 2017 +0000
Revision:
0:23d1f73bf130
podklady pro cviceni z PSS

Who changed what in which revision?

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vladvana 0:23d1f73bf130 1 /**************************************************************************//**
vladvana 0:23d1f73bf130 2 * @file core_cm7.h
vladvana 0:23d1f73bf130 3 * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File
vladvana 0:23d1f73bf130 4 * @version V4.10
vladvana 0:23d1f73bf130 5 * @date 18. March 2015
vladvana 0:23d1f73bf130 6 *
vladvana 0:23d1f73bf130 7 * @note
vladvana 0:23d1f73bf130 8 *
vladvana 0:23d1f73bf130 9 ******************************************************************************/
vladvana 0:23d1f73bf130 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
vladvana 0:23d1f73bf130 11
vladvana 0:23d1f73bf130 12 All rights reserved.
vladvana 0:23d1f73bf130 13 Redistribution and use in source and binary forms, with or without
vladvana 0:23d1f73bf130 14 modification, are permitted provided that the following conditions are met:
vladvana 0:23d1f73bf130 15 - Redistributions of source code must retain the above copyright
vladvana 0:23d1f73bf130 16 notice, this list of conditions and the following disclaimer.
vladvana 0:23d1f73bf130 17 - Redistributions in binary form must reproduce the above copyright
vladvana 0:23d1f73bf130 18 notice, this list of conditions and the following disclaimer in the
vladvana 0:23d1f73bf130 19 documentation and/or other materials provided with the distribution.
vladvana 0:23d1f73bf130 20 - Neither the name of ARM nor the names of its contributors may be used
vladvana 0:23d1f73bf130 21 to endorse or promote products derived from this software without
vladvana 0:23d1f73bf130 22 specific prior written permission.
vladvana 0:23d1f73bf130 23 *
vladvana 0:23d1f73bf130 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
vladvana 0:23d1f73bf130 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
vladvana 0:23d1f73bf130 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
vladvana 0:23d1f73bf130 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
vladvana 0:23d1f73bf130 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
vladvana 0:23d1f73bf130 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
vladvana 0:23d1f73bf130 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
vladvana 0:23d1f73bf130 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
vladvana 0:23d1f73bf130 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
vladvana 0:23d1f73bf130 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
vladvana 0:23d1f73bf130 34 POSSIBILITY OF SUCH DAMAGE.
vladvana 0:23d1f73bf130 35 ---------------------------------------------------------------------------*/
vladvana 0:23d1f73bf130 36
vladvana 0:23d1f73bf130 37
vladvana 0:23d1f73bf130 38 #if defined ( __ICCARM__ )
vladvana 0:23d1f73bf130 39 #pragma system_include /* treat file as system include file for MISRA check */
vladvana 0:23d1f73bf130 40 #endif
vladvana 0:23d1f73bf130 41
vladvana 0:23d1f73bf130 42 #ifndef __CORE_CM7_H_GENERIC
vladvana 0:23d1f73bf130 43 #define __CORE_CM7_H_GENERIC
vladvana 0:23d1f73bf130 44
vladvana 0:23d1f73bf130 45 #ifdef __cplusplus
vladvana 0:23d1f73bf130 46 extern "C" {
vladvana 0:23d1f73bf130 47 #endif
vladvana 0:23d1f73bf130 48
vladvana 0:23d1f73bf130 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
vladvana 0:23d1f73bf130 50 CMSIS violates the following MISRA-C:2004 rules:
vladvana 0:23d1f73bf130 51
vladvana 0:23d1f73bf130 52 \li Required Rule 8.5, object/function definition in header file.<br>
vladvana 0:23d1f73bf130 53 Function definitions in header files are used to allow 'inlining'.
vladvana 0:23d1f73bf130 54
vladvana 0:23d1f73bf130 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
vladvana 0:23d1f73bf130 56 Unions are used for effective representation of core registers.
vladvana 0:23d1f73bf130 57
vladvana 0:23d1f73bf130 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
vladvana 0:23d1f73bf130 59 Function-like macros are used to allow more efficient code.
vladvana 0:23d1f73bf130 60 */
vladvana 0:23d1f73bf130 61
vladvana 0:23d1f73bf130 62
vladvana 0:23d1f73bf130 63 /*******************************************************************************
vladvana 0:23d1f73bf130 64 * CMSIS definitions
vladvana 0:23d1f73bf130 65 ******************************************************************************/
vladvana 0:23d1f73bf130 66 /** \ingroup Cortex_M7
vladvana 0:23d1f73bf130 67 @{
vladvana 0:23d1f73bf130 68 */
vladvana 0:23d1f73bf130 69
vladvana 0:23d1f73bf130 70 /* CMSIS CM7 definitions */
vladvana 0:23d1f73bf130 71 #define __CM7_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
vladvana 0:23d1f73bf130 72 #define __CM7_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
vladvana 0:23d1f73bf130 73 #define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16) | \
vladvana 0:23d1f73bf130 74 __CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
vladvana 0:23d1f73bf130 75
vladvana 0:23d1f73bf130 76 #define __CORTEX_M (0x07) /*!< Cortex-M Core */
vladvana 0:23d1f73bf130 77
vladvana 0:23d1f73bf130 78
vladvana 0:23d1f73bf130 79 #if defined ( __CC_ARM )
vladvana 0:23d1f73bf130 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
vladvana 0:23d1f73bf130 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
vladvana 0:23d1f73bf130 82 #define __STATIC_INLINE static __inline
vladvana 0:23d1f73bf130 83
vladvana 0:23d1f73bf130 84 #elif defined ( __GNUC__ )
vladvana 0:23d1f73bf130 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
vladvana 0:23d1f73bf130 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
vladvana 0:23d1f73bf130 87 #define __STATIC_INLINE static inline
vladvana 0:23d1f73bf130 88
vladvana 0:23d1f73bf130 89 #elif defined ( __ICCARM__ )
vladvana 0:23d1f73bf130 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
vladvana 0:23d1f73bf130 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
vladvana 0:23d1f73bf130 92 #define __STATIC_INLINE static inline
vladvana 0:23d1f73bf130 93
vladvana 0:23d1f73bf130 94 #elif defined ( __TMS470__ )
vladvana 0:23d1f73bf130 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
vladvana 0:23d1f73bf130 96 #define __STATIC_INLINE static inline
vladvana 0:23d1f73bf130 97
vladvana 0:23d1f73bf130 98 #elif defined ( __TASKING__ )
vladvana 0:23d1f73bf130 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
vladvana 0:23d1f73bf130 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
vladvana 0:23d1f73bf130 101 #define __STATIC_INLINE static inline
vladvana 0:23d1f73bf130 102
vladvana 0:23d1f73bf130 103 #elif defined ( __CSMC__ )
vladvana 0:23d1f73bf130 104 #define __packed
vladvana 0:23d1f73bf130 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
vladvana 0:23d1f73bf130 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
vladvana 0:23d1f73bf130 107 #define __STATIC_INLINE static inline
vladvana 0:23d1f73bf130 108
vladvana 0:23d1f73bf130 109 #endif
vladvana 0:23d1f73bf130 110
vladvana 0:23d1f73bf130 111 /** __FPU_USED indicates whether an FPU is used or not.
vladvana 0:23d1f73bf130 112 For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
vladvana 0:23d1f73bf130 113 */
vladvana 0:23d1f73bf130 114 #if defined ( __CC_ARM )
vladvana 0:23d1f73bf130 115 #if defined __TARGET_FPU_VFP
vladvana 0:23d1f73bf130 116 #if (__FPU_PRESENT == 1)
vladvana 0:23d1f73bf130 117 #define __FPU_USED 1
vladvana 0:23d1f73bf130 118 #else
vladvana 0:23d1f73bf130 119 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
vladvana 0:23d1f73bf130 120 #define __FPU_USED 0
vladvana 0:23d1f73bf130 121 #endif
vladvana 0:23d1f73bf130 122 #else
vladvana 0:23d1f73bf130 123 #define __FPU_USED 0
vladvana 0:23d1f73bf130 124 #endif
vladvana 0:23d1f73bf130 125
vladvana 0:23d1f73bf130 126 #elif defined ( __GNUC__ )
vladvana 0:23d1f73bf130 127 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
vladvana 0:23d1f73bf130 128 #if (__FPU_PRESENT == 1)
vladvana 0:23d1f73bf130 129 #define __FPU_USED 1
vladvana 0:23d1f73bf130 130 #else
vladvana 0:23d1f73bf130 131 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
vladvana 0:23d1f73bf130 132 #define __FPU_USED 0
vladvana 0:23d1f73bf130 133 #endif
vladvana 0:23d1f73bf130 134 #else
vladvana 0:23d1f73bf130 135 #define __FPU_USED 0
vladvana 0:23d1f73bf130 136 #endif
vladvana 0:23d1f73bf130 137
vladvana 0:23d1f73bf130 138 #elif defined ( __ICCARM__ )
vladvana 0:23d1f73bf130 139 #if defined __ARMVFP__
vladvana 0:23d1f73bf130 140 #if (__FPU_PRESENT == 1)
vladvana 0:23d1f73bf130 141 #define __FPU_USED 1
vladvana 0:23d1f73bf130 142 #else
vladvana 0:23d1f73bf130 143 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
vladvana 0:23d1f73bf130 144 #define __FPU_USED 0
vladvana 0:23d1f73bf130 145 #endif
vladvana 0:23d1f73bf130 146 #else
vladvana 0:23d1f73bf130 147 #define __FPU_USED 0
vladvana 0:23d1f73bf130 148 #endif
vladvana 0:23d1f73bf130 149
vladvana 0:23d1f73bf130 150 #elif defined ( __TMS470__ )
vladvana 0:23d1f73bf130 151 #if defined __TI_VFP_SUPPORT__
vladvana 0:23d1f73bf130 152 #if (__FPU_PRESENT == 1)
vladvana 0:23d1f73bf130 153 #define __FPU_USED 1
vladvana 0:23d1f73bf130 154 #else
vladvana 0:23d1f73bf130 155 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
vladvana 0:23d1f73bf130 156 #define __FPU_USED 0
vladvana 0:23d1f73bf130 157 #endif
vladvana 0:23d1f73bf130 158 #else
vladvana 0:23d1f73bf130 159 #define __FPU_USED 0
vladvana 0:23d1f73bf130 160 #endif
vladvana 0:23d1f73bf130 161
vladvana 0:23d1f73bf130 162 #elif defined ( __TASKING__ )
vladvana 0:23d1f73bf130 163 #if defined __FPU_VFP__
vladvana 0:23d1f73bf130 164 #if (__FPU_PRESENT == 1)
vladvana 0:23d1f73bf130 165 #define __FPU_USED 1
vladvana 0:23d1f73bf130 166 #else
vladvana 0:23d1f73bf130 167 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
vladvana 0:23d1f73bf130 168 #define __FPU_USED 0
vladvana 0:23d1f73bf130 169 #endif
vladvana 0:23d1f73bf130 170 #else
vladvana 0:23d1f73bf130 171 #define __FPU_USED 0
vladvana 0:23d1f73bf130 172 #endif
vladvana 0:23d1f73bf130 173
vladvana 0:23d1f73bf130 174 #elif defined ( __CSMC__ ) /* Cosmic */
vladvana 0:23d1f73bf130 175 #if ( __CSMC__ & 0x400) // FPU present for parser
vladvana 0:23d1f73bf130 176 #if (__FPU_PRESENT == 1)
vladvana 0:23d1f73bf130 177 #define __FPU_USED 1
vladvana 0:23d1f73bf130 178 #else
vladvana 0:23d1f73bf130 179 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
vladvana 0:23d1f73bf130 180 #define __FPU_USED 0
vladvana 0:23d1f73bf130 181 #endif
vladvana 0:23d1f73bf130 182 #else
vladvana 0:23d1f73bf130 183 #define __FPU_USED 0
vladvana 0:23d1f73bf130 184 #endif
vladvana 0:23d1f73bf130 185 #endif
vladvana 0:23d1f73bf130 186
vladvana 0:23d1f73bf130 187 #include <stdint.h> /* standard types definitions */
vladvana 0:23d1f73bf130 188 #include <core_cmInstr.h> /* Core Instruction Access */
vladvana 0:23d1f73bf130 189 #include <core_cmFunc.h> /* Core Function Access */
vladvana 0:23d1f73bf130 190 #include <core_cmSimd.h> /* Compiler specific SIMD Intrinsics */
vladvana 0:23d1f73bf130 191
vladvana 0:23d1f73bf130 192 #ifdef __cplusplus
vladvana 0:23d1f73bf130 193 }
vladvana 0:23d1f73bf130 194 #endif
vladvana 0:23d1f73bf130 195
vladvana 0:23d1f73bf130 196 #endif /* __CORE_CM7_H_GENERIC */
vladvana 0:23d1f73bf130 197
vladvana 0:23d1f73bf130 198 #ifndef __CMSIS_GENERIC
vladvana 0:23d1f73bf130 199
vladvana 0:23d1f73bf130 200 #ifndef __CORE_CM7_H_DEPENDANT
vladvana 0:23d1f73bf130 201 #define __CORE_CM7_H_DEPENDANT
vladvana 0:23d1f73bf130 202
vladvana 0:23d1f73bf130 203 #ifdef __cplusplus
vladvana 0:23d1f73bf130 204 extern "C" {
vladvana 0:23d1f73bf130 205 #endif
vladvana 0:23d1f73bf130 206
vladvana 0:23d1f73bf130 207 /* check device defines and use defaults */
vladvana 0:23d1f73bf130 208 #if defined __CHECK_DEVICE_DEFINES
vladvana 0:23d1f73bf130 209 #ifndef __CM7_REV
vladvana 0:23d1f73bf130 210 #define __CM7_REV 0x0000
vladvana 0:23d1f73bf130 211 #warning "__CM7_REV not defined in device header file; using default!"
vladvana 0:23d1f73bf130 212 #endif
vladvana 0:23d1f73bf130 213
vladvana 0:23d1f73bf130 214 #ifndef __FPU_PRESENT
vladvana 0:23d1f73bf130 215 #define __FPU_PRESENT 0
vladvana 0:23d1f73bf130 216 #warning "__FPU_PRESENT not defined in device header file; using default!"
vladvana 0:23d1f73bf130 217 #endif
vladvana 0:23d1f73bf130 218
vladvana 0:23d1f73bf130 219 #ifndef __MPU_PRESENT
vladvana 0:23d1f73bf130 220 #define __MPU_PRESENT 0
vladvana 0:23d1f73bf130 221 #warning "__MPU_PRESENT not defined in device header file; using default!"
vladvana 0:23d1f73bf130 222 #endif
vladvana 0:23d1f73bf130 223
vladvana 0:23d1f73bf130 224 #ifndef __ICACHE_PRESENT
vladvana 0:23d1f73bf130 225 #define __ICACHE_PRESENT 0
vladvana 0:23d1f73bf130 226 #warning "__ICACHE_PRESENT not defined in device header file; using default!"
vladvana 0:23d1f73bf130 227 #endif
vladvana 0:23d1f73bf130 228
vladvana 0:23d1f73bf130 229 #ifndef __DCACHE_PRESENT
vladvana 0:23d1f73bf130 230 #define __DCACHE_PRESENT 0
vladvana 0:23d1f73bf130 231 #warning "__DCACHE_PRESENT not defined in device header file; using default!"
vladvana 0:23d1f73bf130 232 #endif
vladvana 0:23d1f73bf130 233
vladvana 0:23d1f73bf130 234 #ifndef __DTCM_PRESENT
vladvana 0:23d1f73bf130 235 #define __DTCM_PRESENT 0
vladvana 0:23d1f73bf130 236 #warning "__DTCM_PRESENT not defined in device header file; using default!"
vladvana 0:23d1f73bf130 237 #endif
vladvana 0:23d1f73bf130 238
vladvana 0:23d1f73bf130 239 #ifndef __NVIC_PRIO_BITS
vladvana 0:23d1f73bf130 240 #define __NVIC_PRIO_BITS 3
vladvana 0:23d1f73bf130 241 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
vladvana 0:23d1f73bf130 242 #endif
vladvana 0:23d1f73bf130 243
vladvana 0:23d1f73bf130 244 #ifndef __Vendor_SysTickConfig
vladvana 0:23d1f73bf130 245 #define __Vendor_SysTickConfig 0
vladvana 0:23d1f73bf130 246 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
vladvana 0:23d1f73bf130 247 #endif
vladvana 0:23d1f73bf130 248 #endif
vladvana 0:23d1f73bf130 249
vladvana 0:23d1f73bf130 250 /* IO definitions (access restrictions to peripheral registers) */
vladvana 0:23d1f73bf130 251 /**
vladvana 0:23d1f73bf130 252 \defgroup CMSIS_glob_defs CMSIS Global Defines
vladvana 0:23d1f73bf130 253
vladvana 0:23d1f73bf130 254 <strong>IO Type Qualifiers</strong> are used
vladvana 0:23d1f73bf130 255 \li to specify the access to peripheral variables.
vladvana 0:23d1f73bf130 256 \li for automatic generation of peripheral register debug information.
vladvana 0:23d1f73bf130 257 */
vladvana 0:23d1f73bf130 258 #ifdef __cplusplus
vladvana 0:23d1f73bf130 259 #define __I volatile /*!< Defines 'read only' permissions */
vladvana 0:23d1f73bf130 260 #else
vladvana 0:23d1f73bf130 261 #define __I volatile const /*!< Defines 'read only' permissions */
vladvana 0:23d1f73bf130 262 #endif
vladvana 0:23d1f73bf130 263 #define __O volatile /*!< Defines 'write only' permissions */
vladvana 0:23d1f73bf130 264 #define __IO volatile /*!< Defines 'read / write' permissions */
vladvana 0:23d1f73bf130 265
vladvana 0:23d1f73bf130 266 /*@} end of group Cortex_M7 */
vladvana 0:23d1f73bf130 267
vladvana 0:23d1f73bf130 268
vladvana 0:23d1f73bf130 269
vladvana 0:23d1f73bf130 270 /*******************************************************************************
vladvana 0:23d1f73bf130 271 * Register Abstraction
vladvana 0:23d1f73bf130 272 Core Register contain:
vladvana 0:23d1f73bf130 273 - Core Register
vladvana 0:23d1f73bf130 274 - Core NVIC Register
vladvana 0:23d1f73bf130 275 - Core SCB Register
vladvana 0:23d1f73bf130 276 - Core SysTick Register
vladvana 0:23d1f73bf130 277 - Core Debug Register
vladvana 0:23d1f73bf130 278 - Core MPU Register
vladvana 0:23d1f73bf130 279 - Core FPU Register
vladvana 0:23d1f73bf130 280 ******************************************************************************/
vladvana 0:23d1f73bf130 281 /** \defgroup CMSIS_core_register Defines and Type Definitions
vladvana 0:23d1f73bf130 282 \brief Type definitions and defines for Cortex-M processor based devices.
vladvana 0:23d1f73bf130 283 */
vladvana 0:23d1f73bf130 284
vladvana 0:23d1f73bf130 285 /** \ingroup CMSIS_core_register
vladvana 0:23d1f73bf130 286 \defgroup CMSIS_CORE Status and Control Registers
vladvana 0:23d1f73bf130 287 \brief Core Register type definitions.
vladvana 0:23d1f73bf130 288 @{
vladvana 0:23d1f73bf130 289 */
vladvana 0:23d1f73bf130 290
vladvana 0:23d1f73bf130 291 /** \brief Union type to access the Application Program Status Register (APSR).
vladvana 0:23d1f73bf130 292 */
vladvana 0:23d1f73bf130 293 typedef union
vladvana 0:23d1f73bf130 294 {
vladvana 0:23d1f73bf130 295 struct
vladvana 0:23d1f73bf130 296 {
vladvana 0:23d1f73bf130 297 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
vladvana 0:23d1f73bf130 298 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
vladvana 0:23d1f73bf130 299 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
vladvana 0:23d1f73bf130 300 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
vladvana 0:23d1f73bf130 301 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
vladvana 0:23d1f73bf130 302 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
vladvana 0:23d1f73bf130 303 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
vladvana 0:23d1f73bf130 304 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
vladvana 0:23d1f73bf130 305 } b; /*!< Structure used for bit access */
vladvana 0:23d1f73bf130 306 uint32_t w; /*!< Type used for word access */
vladvana 0:23d1f73bf130 307 } APSR_Type;
vladvana 0:23d1f73bf130 308
vladvana 0:23d1f73bf130 309 /* APSR Register Definitions */
vladvana 0:23d1f73bf130 310 #define APSR_N_Pos 31 /*!< APSR: N Position */
vladvana 0:23d1f73bf130 311 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
vladvana 0:23d1f73bf130 312
vladvana 0:23d1f73bf130 313 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
vladvana 0:23d1f73bf130 314 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
vladvana 0:23d1f73bf130 315
vladvana 0:23d1f73bf130 316 #define APSR_C_Pos 29 /*!< APSR: C Position */
vladvana 0:23d1f73bf130 317 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
vladvana 0:23d1f73bf130 318
vladvana 0:23d1f73bf130 319 #define APSR_V_Pos 28 /*!< APSR: V Position */
vladvana 0:23d1f73bf130 320 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
vladvana 0:23d1f73bf130 321
vladvana 0:23d1f73bf130 322 #define APSR_Q_Pos 27 /*!< APSR: Q Position */
vladvana 0:23d1f73bf130 323 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
vladvana 0:23d1f73bf130 324
vladvana 0:23d1f73bf130 325 #define APSR_GE_Pos 16 /*!< APSR: GE Position */
vladvana 0:23d1f73bf130 326 #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
vladvana 0:23d1f73bf130 327
vladvana 0:23d1f73bf130 328
vladvana 0:23d1f73bf130 329 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
vladvana 0:23d1f73bf130 330 */
vladvana 0:23d1f73bf130 331 typedef union
vladvana 0:23d1f73bf130 332 {
vladvana 0:23d1f73bf130 333 struct
vladvana 0:23d1f73bf130 334 {
vladvana 0:23d1f73bf130 335 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
vladvana 0:23d1f73bf130 336 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
vladvana 0:23d1f73bf130 337 } b; /*!< Structure used for bit access */
vladvana 0:23d1f73bf130 338 uint32_t w; /*!< Type used for word access */
vladvana 0:23d1f73bf130 339 } IPSR_Type;
vladvana 0:23d1f73bf130 340
vladvana 0:23d1f73bf130 341 /* IPSR Register Definitions */
vladvana 0:23d1f73bf130 342 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
vladvana 0:23d1f73bf130 343 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
vladvana 0:23d1f73bf130 344
vladvana 0:23d1f73bf130 345
vladvana 0:23d1f73bf130 346 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
vladvana 0:23d1f73bf130 347 */
vladvana 0:23d1f73bf130 348 typedef union
vladvana 0:23d1f73bf130 349 {
vladvana 0:23d1f73bf130 350 struct
vladvana 0:23d1f73bf130 351 {
vladvana 0:23d1f73bf130 352 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
vladvana 0:23d1f73bf130 353 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
vladvana 0:23d1f73bf130 354 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
vladvana 0:23d1f73bf130 355 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
vladvana 0:23d1f73bf130 356 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
vladvana 0:23d1f73bf130 357 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
vladvana 0:23d1f73bf130 358 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
vladvana 0:23d1f73bf130 359 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
vladvana 0:23d1f73bf130 360 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
vladvana 0:23d1f73bf130 361 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
vladvana 0:23d1f73bf130 362 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
vladvana 0:23d1f73bf130 363 } b; /*!< Structure used for bit access */
vladvana 0:23d1f73bf130 364 uint32_t w; /*!< Type used for word access */
vladvana 0:23d1f73bf130 365 } xPSR_Type;
vladvana 0:23d1f73bf130 366
vladvana 0:23d1f73bf130 367 /* xPSR Register Definitions */
vladvana 0:23d1f73bf130 368 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
vladvana 0:23d1f73bf130 369 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
vladvana 0:23d1f73bf130 370
vladvana 0:23d1f73bf130 371 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
vladvana 0:23d1f73bf130 372 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
vladvana 0:23d1f73bf130 373
vladvana 0:23d1f73bf130 374 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
vladvana 0:23d1f73bf130 375 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
vladvana 0:23d1f73bf130 376
vladvana 0:23d1f73bf130 377 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
vladvana 0:23d1f73bf130 378 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
vladvana 0:23d1f73bf130 379
vladvana 0:23d1f73bf130 380 #define xPSR_Q_Pos 27 /*!< xPSR: Q Position */
vladvana 0:23d1f73bf130 381 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
vladvana 0:23d1f73bf130 382
vladvana 0:23d1f73bf130 383 #define xPSR_IT_Pos 25 /*!< xPSR: IT Position */
vladvana 0:23d1f73bf130 384 #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
vladvana 0:23d1f73bf130 385
vladvana 0:23d1f73bf130 386 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
vladvana 0:23d1f73bf130 387 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
vladvana 0:23d1f73bf130 388
vladvana 0:23d1f73bf130 389 #define xPSR_GE_Pos 16 /*!< xPSR: GE Position */
vladvana 0:23d1f73bf130 390 #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
vladvana 0:23d1f73bf130 391
vladvana 0:23d1f73bf130 392 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
vladvana 0:23d1f73bf130 393 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
vladvana 0:23d1f73bf130 394
vladvana 0:23d1f73bf130 395
vladvana 0:23d1f73bf130 396 /** \brief Union type to access the Control Registers (CONTROL).
vladvana 0:23d1f73bf130 397 */
vladvana 0:23d1f73bf130 398 typedef union
vladvana 0:23d1f73bf130 399 {
vladvana 0:23d1f73bf130 400 struct
vladvana 0:23d1f73bf130 401 {
vladvana 0:23d1f73bf130 402 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
vladvana 0:23d1f73bf130 403 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
vladvana 0:23d1f73bf130 404 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
vladvana 0:23d1f73bf130 405 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
vladvana 0:23d1f73bf130 406 } b; /*!< Structure used for bit access */
vladvana 0:23d1f73bf130 407 uint32_t w; /*!< Type used for word access */
vladvana 0:23d1f73bf130 408 } CONTROL_Type;
vladvana 0:23d1f73bf130 409
vladvana 0:23d1f73bf130 410 /* CONTROL Register Definitions */
vladvana 0:23d1f73bf130 411 #define CONTROL_FPCA_Pos 2 /*!< CONTROL: FPCA Position */
vladvana 0:23d1f73bf130 412 #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
vladvana 0:23d1f73bf130 413
vladvana 0:23d1f73bf130 414 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
vladvana 0:23d1f73bf130 415 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
vladvana 0:23d1f73bf130 416
vladvana 0:23d1f73bf130 417 #define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
vladvana 0:23d1f73bf130 418 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
vladvana 0:23d1f73bf130 419
vladvana 0:23d1f73bf130 420 /*@} end of group CMSIS_CORE */
vladvana 0:23d1f73bf130 421
vladvana 0:23d1f73bf130 422
vladvana 0:23d1f73bf130 423 /** \ingroup CMSIS_core_register
vladvana 0:23d1f73bf130 424 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
vladvana 0:23d1f73bf130 425 \brief Type definitions for the NVIC Registers
vladvana 0:23d1f73bf130 426 @{
vladvana 0:23d1f73bf130 427 */
vladvana 0:23d1f73bf130 428
vladvana 0:23d1f73bf130 429 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
vladvana 0:23d1f73bf130 430 */
vladvana 0:23d1f73bf130 431 typedef struct
vladvana 0:23d1f73bf130 432 {
vladvana 0:23d1f73bf130 433 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
vladvana 0:23d1f73bf130 434 uint32_t RESERVED0[24];
vladvana 0:23d1f73bf130 435 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
vladvana 0:23d1f73bf130 436 uint32_t RSERVED1[24];
vladvana 0:23d1f73bf130 437 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
vladvana 0:23d1f73bf130 438 uint32_t RESERVED2[24];
vladvana 0:23d1f73bf130 439 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
vladvana 0:23d1f73bf130 440 uint32_t RESERVED3[24];
vladvana 0:23d1f73bf130 441 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
vladvana 0:23d1f73bf130 442 uint32_t RESERVED4[56];
vladvana 0:23d1f73bf130 443 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
vladvana 0:23d1f73bf130 444 uint32_t RESERVED5[644];
vladvana 0:23d1f73bf130 445 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
vladvana 0:23d1f73bf130 446 } NVIC_Type;
vladvana 0:23d1f73bf130 447
vladvana 0:23d1f73bf130 448 /* Software Triggered Interrupt Register Definitions */
vladvana 0:23d1f73bf130 449 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
vladvana 0:23d1f73bf130 450 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
vladvana 0:23d1f73bf130 451
vladvana 0:23d1f73bf130 452 /*@} end of group CMSIS_NVIC */
vladvana 0:23d1f73bf130 453
vladvana 0:23d1f73bf130 454
vladvana 0:23d1f73bf130 455 /** \ingroup CMSIS_core_register
vladvana 0:23d1f73bf130 456 \defgroup CMSIS_SCB System Control Block (SCB)
vladvana 0:23d1f73bf130 457 \brief Type definitions for the System Control Block Registers
vladvana 0:23d1f73bf130 458 @{
vladvana 0:23d1f73bf130 459 */
vladvana 0:23d1f73bf130 460
vladvana 0:23d1f73bf130 461 /** \brief Structure type to access the System Control Block (SCB).
vladvana 0:23d1f73bf130 462 */
vladvana 0:23d1f73bf130 463 typedef struct
vladvana 0:23d1f73bf130 464 {
vladvana 0:23d1f73bf130 465 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
vladvana 0:23d1f73bf130 466 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
vladvana 0:23d1f73bf130 467 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
vladvana 0:23d1f73bf130 468 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
vladvana 0:23d1f73bf130 469 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
vladvana 0:23d1f73bf130 470 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
vladvana 0:23d1f73bf130 471 __IO uint8_t SHPR[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
vladvana 0:23d1f73bf130 472 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
vladvana 0:23d1f73bf130 473 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
vladvana 0:23d1f73bf130 474 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
vladvana 0:23d1f73bf130 475 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
vladvana 0:23d1f73bf130 476 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
vladvana 0:23d1f73bf130 477 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
vladvana 0:23d1f73bf130 478 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
vladvana 0:23d1f73bf130 479 __I uint32_t ID_PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
vladvana 0:23d1f73bf130 480 __I uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
vladvana 0:23d1f73bf130 481 __I uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
vladvana 0:23d1f73bf130 482 __I uint32_t ID_MFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
vladvana 0:23d1f73bf130 483 __I uint32_t ID_ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
vladvana 0:23d1f73bf130 484 uint32_t RESERVED0[1];
vladvana 0:23d1f73bf130 485 __I uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
vladvana 0:23d1f73bf130 486 __I uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
vladvana 0:23d1f73bf130 487 __I uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
vladvana 0:23d1f73bf130 488 __IO uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
vladvana 0:23d1f73bf130 489 __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
vladvana 0:23d1f73bf130 490 uint32_t RESERVED3[93];
vladvana 0:23d1f73bf130 491 __O uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
vladvana 0:23d1f73bf130 492 uint32_t RESERVED4[15];
vladvana 0:23d1f73bf130 493 __I uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
vladvana 0:23d1f73bf130 494 __I uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
vladvana 0:23d1f73bf130 495 __I uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */
vladvana 0:23d1f73bf130 496 uint32_t RESERVED5[1];
vladvana 0:23d1f73bf130 497 __O uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
vladvana 0:23d1f73bf130 498 uint32_t RESERVED6[1];
vladvana 0:23d1f73bf130 499 __O uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
vladvana 0:23d1f73bf130 500 __O uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
vladvana 0:23d1f73bf130 501 __O uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
vladvana 0:23d1f73bf130 502 __O uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
vladvana 0:23d1f73bf130 503 __O uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
vladvana 0:23d1f73bf130 504 __O uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
vladvana 0:23d1f73bf130 505 __O uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
vladvana 0:23d1f73bf130 506 __O uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
vladvana 0:23d1f73bf130 507 uint32_t RESERVED7[6];
vladvana 0:23d1f73bf130 508 __IO uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */
vladvana 0:23d1f73bf130 509 __IO uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */
vladvana 0:23d1f73bf130 510 __IO uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */
vladvana 0:23d1f73bf130 511 __IO uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */
vladvana 0:23d1f73bf130 512 __IO uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */
vladvana 0:23d1f73bf130 513 uint32_t RESERVED8[1];
vladvana 0:23d1f73bf130 514 __IO uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */
vladvana 0:23d1f73bf130 515 } SCB_Type;
vladvana 0:23d1f73bf130 516
vladvana 0:23d1f73bf130 517 /* SCB CPUID Register Definitions */
vladvana 0:23d1f73bf130 518 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
vladvana 0:23d1f73bf130 519 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
vladvana 0:23d1f73bf130 520
vladvana 0:23d1f73bf130 521 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
vladvana 0:23d1f73bf130 522 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
vladvana 0:23d1f73bf130 523
vladvana 0:23d1f73bf130 524 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
vladvana 0:23d1f73bf130 525 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
vladvana 0:23d1f73bf130 526
vladvana 0:23d1f73bf130 527 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
vladvana 0:23d1f73bf130 528 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
vladvana 0:23d1f73bf130 529
vladvana 0:23d1f73bf130 530 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
vladvana 0:23d1f73bf130 531 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
vladvana 0:23d1f73bf130 532
vladvana 0:23d1f73bf130 533 /* SCB Interrupt Control State Register Definitions */
vladvana 0:23d1f73bf130 534 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
vladvana 0:23d1f73bf130 535 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
vladvana 0:23d1f73bf130 536
vladvana 0:23d1f73bf130 537 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
vladvana 0:23d1f73bf130 538 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
vladvana 0:23d1f73bf130 539
vladvana 0:23d1f73bf130 540 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
vladvana 0:23d1f73bf130 541 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
vladvana 0:23d1f73bf130 542
vladvana 0:23d1f73bf130 543 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
vladvana 0:23d1f73bf130 544 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
vladvana 0:23d1f73bf130 545
vladvana 0:23d1f73bf130 546 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
vladvana 0:23d1f73bf130 547 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
vladvana 0:23d1f73bf130 548
vladvana 0:23d1f73bf130 549 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
vladvana 0:23d1f73bf130 550 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
vladvana 0:23d1f73bf130 551
vladvana 0:23d1f73bf130 552 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
vladvana 0:23d1f73bf130 553 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
vladvana 0:23d1f73bf130 554
vladvana 0:23d1f73bf130 555 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
vladvana 0:23d1f73bf130 556 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
vladvana 0:23d1f73bf130 557
vladvana 0:23d1f73bf130 558 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
vladvana 0:23d1f73bf130 559 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
vladvana 0:23d1f73bf130 560
vladvana 0:23d1f73bf130 561 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
vladvana 0:23d1f73bf130 562 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
vladvana 0:23d1f73bf130 563
vladvana 0:23d1f73bf130 564 /* SCB Vector Table Offset Register Definitions */
vladvana 0:23d1f73bf130 565 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
vladvana 0:23d1f73bf130 566 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
vladvana 0:23d1f73bf130 567
vladvana 0:23d1f73bf130 568 /* SCB Application Interrupt and Reset Control Register Definitions */
vladvana 0:23d1f73bf130 569 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
vladvana 0:23d1f73bf130 570 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
vladvana 0:23d1f73bf130 571
vladvana 0:23d1f73bf130 572 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
vladvana 0:23d1f73bf130 573 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
vladvana 0:23d1f73bf130 574
vladvana 0:23d1f73bf130 575 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
vladvana 0:23d1f73bf130 576 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
vladvana 0:23d1f73bf130 577
vladvana 0:23d1f73bf130 578 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
vladvana 0:23d1f73bf130 579 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
vladvana 0:23d1f73bf130 580
vladvana 0:23d1f73bf130 581 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
vladvana 0:23d1f73bf130 582 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
vladvana 0:23d1f73bf130 583
vladvana 0:23d1f73bf130 584 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
vladvana 0:23d1f73bf130 585 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
vladvana 0:23d1f73bf130 586
vladvana 0:23d1f73bf130 587 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
vladvana 0:23d1f73bf130 588 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
vladvana 0:23d1f73bf130 589
vladvana 0:23d1f73bf130 590 /* SCB System Control Register Definitions */
vladvana 0:23d1f73bf130 591 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
vladvana 0:23d1f73bf130 592 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
vladvana 0:23d1f73bf130 593
vladvana 0:23d1f73bf130 594 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
vladvana 0:23d1f73bf130 595 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
vladvana 0:23d1f73bf130 596
vladvana 0:23d1f73bf130 597 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
vladvana 0:23d1f73bf130 598 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
vladvana 0:23d1f73bf130 599
vladvana 0:23d1f73bf130 600 /* SCB Configuration Control Register Definitions */
vladvana 0:23d1f73bf130 601 #define SCB_CCR_BP_Pos 18 /*!< SCB CCR: Branch prediction enable bit Position */
vladvana 0:23d1f73bf130 602 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */
vladvana 0:23d1f73bf130 603
vladvana 0:23d1f73bf130 604 #define SCB_CCR_IC_Pos 17 /*!< SCB CCR: Instruction cache enable bit Position */
vladvana 0:23d1f73bf130 605 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */
vladvana 0:23d1f73bf130 606
vladvana 0:23d1f73bf130 607 #define SCB_CCR_DC_Pos 16 /*!< SCB CCR: Cache enable bit Position */
vladvana 0:23d1f73bf130 608 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */
vladvana 0:23d1f73bf130 609
vladvana 0:23d1f73bf130 610 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
vladvana 0:23d1f73bf130 611 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
vladvana 0:23d1f73bf130 612
vladvana 0:23d1f73bf130 613 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
vladvana 0:23d1f73bf130 614 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
vladvana 0:23d1f73bf130 615
vladvana 0:23d1f73bf130 616 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
vladvana 0:23d1f73bf130 617 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
vladvana 0:23d1f73bf130 618
vladvana 0:23d1f73bf130 619 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
vladvana 0:23d1f73bf130 620 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
vladvana 0:23d1f73bf130 621
vladvana 0:23d1f73bf130 622 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
vladvana 0:23d1f73bf130 623 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
vladvana 0:23d1f73bf130 624
vladvana 0:23d1f73bf130 625 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
vladvana 0:23d1f73bf130 626 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
vladvana 0:23d1f73bf130 627
vladvana 0:23d1f73bf130 628 /* SCB System Handler Control and State Register Definitions */
vladvana 0:23d1f73bf130 629 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
vladvana 0:23d1f73bf130 630 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
vladvana 0:23d1f73bf130 631
vladvana 0:23d1f73bf130 632 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
vladvana 0:23d1f73bf130 633 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
vladvana 0:23d1f73bf130 634
vladvana 0:23d1f73bf130 635 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
vladvana 0:23d1f73bf130 636 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
vladvana 0:23d1f73bf130 637
vladvana 0:23d1f73bf130 638 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
vladvana 0:23d1f73bf130 639 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
vladvana 0:23d1f73bf130 640
vladvana 0:23d1f73bf130 641 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
vladvana 0:23d1f73bf130 642 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
vladvana 0:23d1f73bf130 643
vladvana 0:23d1f73bf130 644 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
vladvana 0:23d1f73bf130 645 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
vladvana 0:23d1f73bf130 646
vladvana 0:23d1f73bf130 647 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
vladvana 0:23d1f73bf130 648 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
vladvana 0:23d1f73bf130 649
vladvana 0:23d1f73bf130 650 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
vladvana 0:23d1f73bf130 651 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
vladvana 0:23d1f73bf130 652
vladvana 0:23d1f73bf130 653 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
vladvana 0:23d1f73bf130 654 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
vladvana 0:23d1f73bf130 655
vladvana 0:23d1f73bf130 656 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
vladvana 0:23d1f73bf130 657 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
vladvana 0:23d1f73bf130 658
vladvana 0:23d1f73bf130 659 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
vladvana 0:23d1f73bf130 660 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
vladvana 0:23d1f73bf130 661
vladvana 0:23d1f73bf130 662 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
vladvana 0:23d1f73bf130 663 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
vladvana 0:23d1f73bf130 664
vladvana 0:23d1f73bf130 665 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
vladvana 0:23d1f73bf130 666 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
vladvana 0:23d1f73bf130 667
vladvana 0:23d1f73bf130 668 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
vladvana 0:23d1f73bf130 669 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
vladvana 0:23d1f73bf130 670
vladvana 0:23d1f73bf130 671 /* SCB Configurable Fault Status Registers Definitions */
vladvana 0:23d1f73bf130 672 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
vladvana 0:23d1f73bf130 673 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
vladvana 0:23d1f73bf130 674
vladvana 0:23d1f73bf130 675 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
vladvana 0:23d1f73bf130 676 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
vladvana 0:23d1f73bf130 677
vladvana 0:23d1f73bf130 678 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
vladvana 0:23d1f73bf130 679 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
vladvana 0:23d1f73bf130 680
vladvana 0:23d1f73bf130 681 /* SCB Hard Fault Status Registers Definitions */
vladvana 0:23d1f73bf130 682 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
vladvana 0:23d1f73bf130 683 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
vladvana 0:23d1f73bf130 684
vladvana 0:23d1f73bf130 685 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
vladvana 0:23d1f73bf130 686 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
vladvana 0:23d1f73bf130 687
vladvana 0:23d1f73bf130 688 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
vladvana 0:23d1f73bf130 689 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
vladvana 0:23d1f73bf130 690
vladvana 0:23d1f73bf130 691 /* SCB Debug Fault Status Register Definitions */
vladvana 0:23d1f73bf130 692 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
vladvana 0:23d1f73bf130 693 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
vladvana 0:23d1f73bf130 694
vladvana 0:23d1f73bf130 695 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
vladvana 0:23d1f73bf130 696 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
vladvana 0:23d1f73bf130 697
vladvana 0:23d1f73bf130 698 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
vladvana 0:23d1f73bf130 699 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
vladvana 0:23d1f73bf130 700
vladvana 0:23d1f73bf130 701 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
vladvana 0:23d1f73bf130 702 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
vladvana 0:23d1f73bf130 703
vladvana 0:23d1f73bf130 704 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
vladvana 0:23d1f73bf130 705 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
vladvana 0:23d1f73bf130 706
vladvana 0:23d1f73bf130 707 /* Cache Level ID register */
vladvana 0:23d1f73bf130 708 #define SCB_CLIDR_LOUU_Pos 27 /*!< SCB CLIDR: LoUU Position */
vladvana 0:23d1f73bf130 709 #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
vladvana 0:23d1f73bf130 710
vladvana 0:23d1f73bf130 711 #define SCB_CLIDR_LOC_Pos 24 /*!< SCB CLIDR: LoC Position */
vladvana 0:23d1f73bf130 712 #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_FORMAT_Pos) /*!< SCB CLIDR: LoC Mask */
vladvana 0:23d1f73bf130 713
vladvana 0:23d1f73bf130 714 /* Cache Type register */
vladvana 0:23d1f73bf130 715 #define SCB_CTR_FORMAT_Pos 29 /*!< SCB CTR: Format Position */
vladvana 0:23d1f73bf130 716 #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
vladvana 0:23d1f73bf130 717
vladvana 0:23d1f73bf130 718 #define SCB_CTR_CWG_Pos 24 /*!< SCB CTR: CWG Position */
vladvana 0:23d1f73bf130 719 #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
vladvana 0:23d1f73bf130 720
vladvana 0:23d1f73bf130 721 #define SCB_CTR_ERG_Pos 20 /*!< SCB CTR: ERG Position */
vladvana 0:23d1f73bf130 722 #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
vladvana 0:23d1f73bf130 723
vladvana 0:23d1f73bf130 724 #define SCB_CTR_DMINLINE_Pos 16 /*!< SCB CTR: DminLine Position */
vladvana 0:23d1f73bf130 725 #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
vladvana 0:23d1f73bf130 726
vladvana 0:23d1f73bf130 727 #define SCB_CTR_IMINLINE_Pos 0 /*!< SCB CTR: ImInLine Position */
vladvana 0:23d1f73bf130 728 #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
vladvana 0:23d1f73bf130 729
vladvana 0:23d1f73bf130 730 /* Cache Size ID Register */
vladvana 0:23d1f73bf130 731 #define SCB_CCSIDR_WT_Pos 31 /*!< SCB CCSIDR: WT Position */
vladvana 0:23d1f73bf130 732 #define SCB_CCSIDR_WT_Msk (7UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
vladvana 0:23d1f73bf130 733
vladvana 0:23d1f73bf130 734 #define SCB_CCSIDR_WB_Pos 30 /*!< SCB CCSIDR: WB Position */
vladvana 0:23d1f73bf130 735 #define SCB_CCSIDR_WB_Msk (7UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
vladvana 0:23d1f73bf130 736
vladvana 0:23d1f73bf130 737 #define SCB_CCSIDR_RA_Pos 29 /*!< SCB CCSIDR: RA Position */
vladvana 0:23d1f73bf130 738 #define SCB_CCSIDR_RA_Msk (7UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
vladvana 0:23d1f73bf130 739
vladvana 0:23d1f73bf130 740 #define SCB_CCSIDR_WA_Pos 28 /*!< SCB CCSIDR: WA Position */
vladvana 0:23d1f73bf130 741 #define SCB_CCSIDR_WA_Msk (7UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
vladvana 0:23d1f73bf130 742
vladvana 0:23d1f73bf130 743 #define SCB_CCSIDR_NUMSETS_Pos 13 /*!< SCB CCSIDR: NumSets Position */
vladvana 0:23d1f73bf130 744 #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
vladvana 0:23d1f73bf130 745
vladvana 0:23d1f73bf130 746 #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3 /*!< SCB CCSIDR: Associativity Position */
vladvana 0:23d1f73bf130 747 #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
vladvana 0:23d1f73bf130 748
vladvana 0:23d1f73bf130 749 #define SCB_CCSIDR_LINESIZE_Pos 0 /*!< SCB CCSIDR: LineSize Position */
vladvana 0:23d1f73bf130 750 #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
vladvana 0:23d1f73bf130 751
vladvana 0:23d1f73bf130 752 /* Cache Size Selection Register */
vladvana 0:23d1f73bf130 753 #define SCB_CSSELR_LEVEL_Pos 1 /*!< SCB CSSELR: Level Position */
vladvana 0:23d1f73bf130 754 #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
vladvana 0:23d1f73bf130 755
vladvana 0:23d1f73bf130 756 #define SCB_CSSELR_IND_Pos 0 /*!< SCB CSSELR: InD Position */
vladvana 0:23d1f73bf130 757 #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
vladvana 0:23d1f73bf130 758
vladvana 0:23d1f73bf130 759 /* SCB Software Triggered Interrupt Register */
vladvana 0:23d1f73bf130 760 #define SCB_STIR_INTID_Pos 0 /*!< SCB STIR: INTID Position */
vladvana 0:23d1f73bf130 761 #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
vladvana 0:23d1f73bf130 762
vladvana 0:23d1f73bf130 763 /* Instruction Tightly-Coupled Memory Control Register*/
vladvana 0:23d1f73bf130 764 #define SCB_ITCMCR_SZ_Pos 3 /*!< SCB ITCMCR: SZ Position */
vladvana 0:23d1f73bf130 765 #define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */
vladvana 0:23d1f73bf130 766
vladvana 0:23d1f73bf130 767 #define SCB_ITCMCR_RETEN_Pos 2 /*!< SCB ITCMCR: RETEN Position */
vladvana 0:23d1f73bf130 768 #define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */
vladvana 0:23d1f73bf130 769
vladvana 0:23d1f73bf130 770 #define SCB_ITCMCR_RMW_Pos 1 /*!< SCB ITCMCR: RMW Position */
vladvana 0:23d1f73bf130 771 #define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */
vladvana 0:23d1f73bf130 772
vladvana 0:23d1f73bf130 773 #define SCB_ITCMCR_EN_Pos 0 /*!< SCB ITCMCR: EN Position */
vladvana 0:23d1f73bf130 774 #define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */
vladvana 0:23d1f73bf130 775
vladvana 0:23d1f73bf130 776 /* Data Tightly-Coupled Memory Control Registers */
vladvana 0:23d1f73bf130 777 #define SCB_DTCMCR_SZ_Pos 3 /*!< SCB DTCMCR: SZ Position */
vladvana 0:23d1f73bf130 778 #define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */
vladvana 0:23d1f73bf130 779
vladvana 0:23d1f73bf130 780 #define SCB_DTCMCR_RETEN_Pos 2 /*!< SCB DTCMCR: RETEN Position */
vladvana 0:23d1f73bf130 781 #define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */
vladvana 0:23d1f73bf130 782
vladvana 0:23d1f73bf130 783 #define SCB_DTCMCR_RMW_Pos 1 /*!< SCB DTCMCR: RMW Position */
vladvana 0:23d1f73bf130 784 #define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */
vladvana 0:23d1f73bf130 785
vladvana 0:23d1f73bf130 786 #define SCB_DTCMCR_EN_Pos 0 /*!< SCB DTCMCR: EN Position */
vladvana 0:23d1f73bf130 787 #define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */
vladvana 0:23d1f73bf130 788
vladvana 0:23d1f73bf130 789 /* AHBP Control Register */
vladvana 0:23d1f73bf130 790 #define SCB_AHBPCR_SZ_Pos 1 /*!< SCB AHBPCR: SZ Position */
vladvana 0:23d1f73bf130 791 #define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */
vladvana 0:23d1f73bf130 792
vladvana 0:23d1f73bf130 793 #define SCB_AHBPCR_EN_Pos 0 /*!< SCB AHBPCR: EN Position */
vladvana 0:23d1f73bf130 794 #define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */
vladvana 0:23d1f73bf130 795
vladvana 0:23d1f73bf130 796 /* L1 Cache Control Register */
vladvana 0:23d1f73bf130 797 #define SCB_CACR_FORCEWT_Pos 2 /*!< SCB CACR: FORCEWT Position */
vladvana 0:23d1f73bf130 798 #define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */
vladvana 0:23d1f73bf130 799
vladvana 0:23d1f73bf130 800 #define SCB_CACR_ECCEN_Pos 1 /*!< SCB CACR: ECCEN Position */
vladvana 0:23d1f73bf130 801 #define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */
vladvana 0:23d1f73bf130 802
vladvana 0:23d1f73bf130 803 #define SCB_CACR_SIWT_Pos 0 /*!< SCB CACR: SIWT Position */
vladvana 0:23d1f73bf130 804 #define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */
vladvana 0:23d1f73bf130 805
vladvana 0:23d1f73bf130 806 /* AHBS control register */
vladvana 0:23d1f73bf130 807 #define SCB_AHBSCR_INITCOUNT_Pos 11 /*!< SCB AHBSCR: INITCOUNT Position */
vladvana 0:23d1f73bf130 808 #define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */
vladvana 0:23d1f73bf130 809
vladvana 0:23d1f73bf130 810 #define SCB_AHBSCR_TPRI_Pos 2 /*!< SCB AHBSCR: TPRI Position */
vladvana 0:23d1f73bf130 811 #define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */
vladvana 0:23d1f73bf130 812
vladvana 0:23d1f73bf130 813 #define SCB_AHBSCR_CTL_Pos 0 /*!< SCB AHBSCR: CTL Position*/
vladvana 0:23d1f73bf130 814 #define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */
vladvana 0:23d1f73bf130 815
vladvana 0:23d1f73bf130 816 /* Auxiliary Bus Fault Status Register */
vladvana 0:23d1f73bf130 817 #define SCB_ABFSR_AXIMTYPE_Pos 8 /*!< SCB ABFSR: AXIMTYPE Position*/
vladvana 0:23d1f73bf130 818 #define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */
vladvana 0:23d1f73bf130 819
vladvana 0:23d1f73bf130 820 #define SCB_ABFSR_EPPB_Pos 4 /*!< SCB ABFSR: EPPB Position*/
vladvana 0:23d1f73bf130 821 #define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */
vladvana 0:23d1f73bf130 822
vladvana 0:23d1f73bf130 823 #define SCB_ABFSR_AXIM_Pos 3 /*!< SCB ABFSR: AXIM Position*/
vladvana 0:23d1f73bf130 824 #define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */
vladvana 0:23d1f73bf130 825
vladvana 0:23d1f73bf130 826 #define SCB_ABFSR_AHBP_Pos 2 /*!< SCB ABFSR: AHBP Position*/
vladvana 0:23d1f73bf130 827 #define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */
vladvana 0:23d1f73bf130 828
vladvana 0:23d1f73bf130 829 #define SCB_ABFSR_DTCM_Pos 1 /*!< SCB ABFSR: DTCM Position*/
vladvana 0:23d1f73bf130 830 #define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */
vladvana 0:23d1f73bf130 831
vladvana 0:23d1f73bf130 832 #define SCB_ABFSR_ITCM_Pos 0 /*!< SCB ABFSR: ITCM Position*/
vladvana 0:23d1f73bf130 833 #define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */
vladvana 0:23d1f73bf130 834
vladvana 0:23d1f73bf130 835 /*@} end of group CMSIS_SCB */
vladvana 0:23d1f73bf130 836
vladvana 0:23d1f73bf130 837
vladvana 0:23d1f73bf130 838 /** \ingroup CMSIS_core_register
vladvana 0:23d1f73bf130 839 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
vladvana 0:23d1f73bf130 840 \brief Type definitions for the System Control and ID Register not in the SCB
vladvana 0:23d1f73bf130 841 @{
vladvana 0:23d1f73bf130 842 */
vladvana 0:23d1f73bf130 843
vladvana 0:23d1f73bf130 844 /** \brief Structure type to access the System Control and ID Register not in the SCB.
vladvana 0:23d1f73bf130 845 */
vladvana 0:23d1f73bf130 846 typedef struct
vladvana 0:23d1f73bf130 847 {
vladvana 0:23d1f73bf130 848 uint32_t RESERVED0[1];
vladvana 0:23d1f73bf130 849 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
vladvana 0:23d1f73bf130 850 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
vladvana 0:23d1f73bf130 851 } SCnSCB_Type;
vladvana 0:23d1f73bf130 852
vladvana 0:23d1f73bf130 853 /* Interrupt Controller Type Register Definitions */
vladvana 0:23d1f73bf130 854 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
vladvana 0:23d1f73bf130 855 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
vladvana 0:23d1f73bf130 856
vladvana 0:23d1f73bf130 857 /* Auxiliary Control Register Definitions */
vladvana 0:23d1f73bf130 858 #define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12 /*!< ACTLR: DISITMATBFLUSH Position */
vladvana 0:23d1f73bf130 859 #define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */
vladvana 0:23d1f73bf130 860
vladvana 0:23d1f73bf130 861 #define SCnSCB_ACTLR_DISRAMODE_Pos 11 /*!< ACTLR: DISRAMODE Position */
vladvana 0:23d1f73bf130 862 #define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */
vladvana 0:23d1f73bf130 863
vladvana 0:23d1f73bf130 864 #define SCnSCB_ACTLR_FPEXCODIS_Pos 10 /*!< ACTLR: FPEXCODIS Position */
vladvana 0:23d1f73bf130 865 #define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */
vladvana 0:23d1f73bf130 866
vladvana 0:23d1f73bf130 867 #define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
vladvana 0:23d1f73bf130 868 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
vladvana 0:23d1f73bf130 869
vladvana 0:23d1f73bf130 870 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
vladvana 0:23d1f73bf130 871 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
vladvana 0:23d1f73bf130 872
vladvana 0:23d1f73bf130 873 /*@} end of group CMSIS_SCnotSCB */
vladvana 0:23d1f73bf130 874
vladvana 0:23d1f73bf130 875
vladvana 0:23d1f73bf130 876 /** \ingroup CMSIS_core_register
vladvana 0:23d1f73bf130 877 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
vladvana 0:23d1f73bf130 878 \brief Type definitions for the System Timer Registers.
vladvana 0:23d1f73bf130 879 @{
vladvana 0:23d1f73bf130 880 */
vladvana 0:23d1f73bf130 881
vladvana 0:23d1f73bf130 882 /** \brief Structure type to access the System Timer (SysTick).
vladvana 0:23d1f73bf130 883 */
vladvana 0:23d1f73bf130 884 typedef struct
vladvana 0:23d1f73bf130 885 {
vladvana 0:23d1f73bf130 886 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
vladvana 0:23d1f73bf130 887 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
vladvana 0:23d1f73bf130 888 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
vladvana 0:23d1f73bf130 889 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
vladvana 0:23d1f73bf130 890 } SysTick_Type;
vladvana 0:23d1f73bf130 891
vladvana 0:23d1f73bf130 892 /* SysTick Control / Status Register Definitions */
vladvana 0:23d1f73bf130 893 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
vladvana 0:23d1f73bf130 894 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
vladvana 0:23d1f73bf130 895
vladvana 0:23d1f73bf130 896 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
vladvana 0:23d1f73bf130 897 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
vladvana 0:23d1f73bf130 898
vladvana 0:23d1f73bf130 899 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
vladvana 0:23d1f73bf130 900 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
vladvana 0:23d1f73bf130 901
vladvana 0:23d1f73bf130 902 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
vladvana 0:23d1f73bf130 903 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
vladvana 0:23d1f73bf130 904
vladvana 0:23d1f73bf130 905 /* SysTick Reload Register Definitions */
vladvana 0:23d1f73bf130 906 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
vladvana 0:23d1f73bf130 907 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
vladvana 0:23d1f73bf130 908
vladvana 0:23d1f73bf130 909 /* SysTick Current Register Definitions */
vladvana 0:23d1f73bf130 910 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
vladvana 0:23d1f73bf130 911 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
vladvana 0:23d1f73bf130 912
vladvana 0:23d1f73bf130 913 /* SysTick Calibration Register Definitions */
vladvana 0:23d1f73bf130 914 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
vladvana 0:23d1f73bf130 915 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
vladvana 0:23d1f73bf130 916
vladvana 0:23d1f73bf130 917 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
vladvana 0:23d1f73bf130 918 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
vladvana 0:23d1f73bf130 919
vladvana 0:23d1f73bf130 920 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
vladvana 0:23d1f73bf130 921 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
vladvana 0:23d1f73bf130 922
vladvana 0:23d1f73bf130 923 /*@} end of group CMSIS_SysTick */
vladvana 0:23d1f73bf130 924
vladvana 0:23d1f73bf130 925
vladvana 0:23d1f73bf130 926 /** \ingroup CMSIS_core_register
vladvana 0:23d1f73bf130 927 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
vladvana 0:23d1f73bf130 928 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
vladvana 0:23d1f73bf130 929 @{
vladvana 0:23d1f73bf130 930 */
vladvana 0:23d1f73bf130 931
vladvana 0:23d1f73bf130 932 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
vladvana 0:23d1f73bf130 933 */
vladvana 0:23d1f73bf130 934 typedef struct
vladvana 0:23d1f73bf130 935 {
vladvana 0:23d1f73bf130 936 __O union
vladvana 0:23d1f73bf130 937 {
vladvana 0:23d1f73bf130 938 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
vladvana 0:23d1f73bf130 939 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
vladvana 0:23d1f73bf130 940 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
vladvana 0:23d1f73bf130 941 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
vladvana 0:23d1f73bf130 942 uint32_t RESERVED0[864];
vladvana 0:23d1f73bf130 943 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
vladvana 0:23d1f73bf130 944 uint32_t RESERVED1[15];
vladvana 0:23d1f73bf130 945 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
vladvana 0:23d1f73bf130 946 uint32_t RESERVED2[15];
vladvana 0:23d1f73bf130 947 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
vladvana 0:23d1f73bf130 948 uint32_t RESERVED3[29];
vladvana 0:23d1f73bf130 949 __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
vladvana 0:23d1f73bf130 950 __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
vladvana 0:23d1f73bf130 951 __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
vladvana 0:23d1f73bf130 952 uint32_t RESERVED4[43];
vladvana 0:23d1f73bf130 953 __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
vladvana 0:23d1f73bf130 954 __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
vladvana 0:23d1f73bf130 955 uint32_t RESERVED5[6];
vladvana 0:23d1f73bf130 956 __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
vladvana 0:23d1f73bf130 957 __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
vladvana 0:23d1f73bf130 958 __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
vladvana 0:23d1f73bf130 959 __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
vladvana 0:23d1f73bf130 960 __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
vladvana 0:23d1f73bf130 961 __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
vladvana 0:23d1f73bf130 962 __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
vladvana 0:23d1f73bf130 963 __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
vladvana 0:23d1f73bf130 964 __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
vladvana 0:23d1f73bf130 965 __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
vladvana 0:23d1f73bf130 966 __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
vladvana 0:23d1f73bf130 967 __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
vladvana 0:23d1f73bf130 968 } ITM_Type;
vladvana 0:23d1f73bf130 969
vladvana 0:23d1f73bf130 970 /* ITM Trace Privilege Register Definitions */
vladvana 0:23d1f73bf130 971 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
vladvana 0:23d1f73bf130 972 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
vladvana 0:23d1f73bf130 973
vladvana 0:23d1f73bf130 974 /* ITM Trace Control Register Definitions */
vladvana 0:23d1f73bf130 975 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
vladvana 0:23d1f73bf130 976 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
vladvana 0:23d1f73bf130 977
vladvana 0:23d1f73bf130 978 #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
vladvana 0:23d1f73bf130 979 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
vladvana 0:23d1f73bf130 980
vladvana 0:23d1f73bf130 981 #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
vladvana 0:23d1f73bf130 982 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
vladvana 0:23d1f73bf130 983
vladvana 0:23d1f73bf130 984 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
vladvana 0:23d1f73bf130 985 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
vladvana 0:23d1f73bf130 986
vladvana 0:23d1f73bf130 987 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
vladvana 0:23d1f73bf130 988 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
vladvana 0:23d1f73bf130 989
vladvana 0:23d1f73bf130 990 #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
vladvana 0:23d1f73bf130 991 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
vladvana 0:23d1f73bf130 992
vladvana 0:23d1f73bf130 993 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
vladvana 0:23d1f73bf130 994 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
vladvana 0:23d1f73bf130 995
vladvana 0:23d1f73bf130 996 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
vladvana 0:23d1f73bf130 997 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
vladvana 0:23d1f73bf130 998
vladvana 0:23d1f73bf130 999 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
vladvana 0:23d1f73bf130 1000 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
vladvana 0:23d1f73bf130 1001
vladvana 0:23d1f73bf130 1002 /* ITM Integration Write Register Definitions */
vladvana 0:23d1f73bf130 1003 #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
vladvana 0:23d1f73bf130 1004 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
vladvana 0:23d1f73bf130 1005
vladvana 0:23d1f73bf130 1006 /* ITM Integration Read Register Definitions */
vladvana 0:23d1f73bf130 1007 #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
vladvana 0:23d1f73bf130 1008 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
vladvana 0:23d1f73bf130 1009
vladvana 0:23d1f73bf130 1010 /* ITM Integration Mode Control Register Definitions */
vladvana 0:23d1f73bf130 1011 #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
vladvana 0:23d1f73bf130 1012 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
vladvana 0:23d1f73bf130 1013
vladvana 0:23d1f73bf130 1014 /* ITM Lock Status Register Definitions */
vladvana 0:23d1f73bf130 1015 #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
vladvana 0:23d1f73bf130 1016 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
vladvana 0:23d1f73bf130 1017
vladvana 0:23d1f73bf130 1018 #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
vladvana 0:23d1f73bf130 1019 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
vladvana 0:23d1f73bf130 1020
vladvana 0:23d1f73bf130 1021 #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
vladvana 0:23d1f73bf130 1022 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
vladvana 0:23d1f73bf130 1023
vladvana 0:23d1f73bf130 1024 /*@}*/ /* end of group CMSIS_ITM */
vladvana 0:23d1f73bf130 1025
vladvana 0:23d1f73bf130 1026
vladvana 0:23d1f73bf130 1027 /** \ingroup CMSIS_core_register
vladvana 0:23d1f73bf130 1028 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
vladvana 0:23d1f73bf130 1029 \brief Type definitions for the Data Watchpoint and Trace (DWT)
vladvana 0:23d1f73bf130 1030 @{
vladvana 0:23d1f73bf130 1031 */
vladvana 0:23d1f73bf130 1032
vladvana 0:23d1f73bf130 1033 /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
vladvana 0:23d1f73bf130 1034 */
vladvana 0:23d1f73bf130 1035 typedef struct
vladvana 0:23d1f73bf130 1036 {
vladvana 0:23d1f73bf130 1037 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
vladvana 0:23d1f73bf130 1038 __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
vladvana 0:23d1f73bf130 1039 __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
vladvana 0:23d1f73bf130 1040 __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
vladvana 0:23d1f73bf130 1041 __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
vladvana 0:23d1f73bf130 1042 __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
vladvana 0:23d1f73bf130 1043 __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
vladvana 0:23d1f73bf130 1044 __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
vladvana 0:23d1f73bf130 1045 __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
vladvana 0:23d1f73bf130 1046 __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
vladvana 0:23d1f73bf130 1047 __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
vladvana 0:23d1f73bf130 1048 uint32_t RESERVED0[1];
vladvana 0:23d1f73bf130 1049 __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
vladvana 0:23d1f73bf130 1050 __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
vladvana 0:23d1f73bf130 1051 __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
vladvana 0:23d1f73bf130 1052 uint32_t RESERVED1[1];
vladvana 0:23d1f73bf130 1053 __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
vladvana 0:23d1f73bf130 1054 __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
vladvana 0:23d1f73bf130 1055 __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
vladvana 0:23d1f73bf130 1056 uint32_t RESERVED2[1];
vladvana 0:23d1f73bf130 1057 __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
vladvana 0:23d1f73bf130 1058 __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
vladvana 0:23d1f73bf130 1059 __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
vladvana 0:23d1f73bf130 1060 uint32_t RESERVED3[981];
vladvana 0:23d1f73bf130 1061 __O uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */
vladvana 0:23d1f73bf130 1062 __I uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
vladvana 0:23d1f73bf130 1063 } DWT_Type;
vladvana 0:23d1f73bf130 1064
vladvana 0:23d1f73bf130 1065 /* DWT Control Register Definitions */
vladvana 0:23d1f73bf130 1066 #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
vladvana 0:23d1f73bf130 1067 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
vladvana 0:23d1f73bf130 1068
vladvana 0:23d1f73bf130 1069 #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
vladvana 0:23d1f73bf130 1070 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
vladvana 0:23d1f73bf130 1071
vladvana 0:23d1f73bf130 1072 #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
vladvana 0:23d1f73bf130 1073 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
vladvana 0:23d1f73bf130 1074
vladvana 0:23d1f73bf130 1075 #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
vladvana 0:23d1f73bf130 1076 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
vladvana 0:23d1f73bf130 1077
vladvana 0:23d1f73bf130 1078 #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
vladvana 0:23d1f73bf130 1079 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
vladvana 0:23d1f73bf130 1080
vladvana 0:23d1f73bf130 1081 #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
vladvana 0:23d1f73bf130 1082 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
vladvana 0:23d1f73bf130 1083
vladvana 0:23d1f73bf130 1084 #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
vladvana 0:23d1f73bf130 1085 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
vladvana 0:23d1f73bf130 1086
vladvana 0:23d1f73bf130 1087 #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
vladvana 0:23d1f73bf130 1088 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
vladvana 0:23d1f73bf130 1089
vladvana 0:23d1f73bf130 1090 #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
vladvana 0:23d1f73bf130 1091 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
vladvana 0:23d1f73bf130 1092
vladvana 0:23d1f73bf130 1093 #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
vladvana 0:23d1f73bf130 1094 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
vladvana 0:23d1f73bf130 1095
vladvana 0:23d1f73bf130 1096 #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
vladvana 0:23d1f73bf130 1097 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
vladvana 0:23d1f73bf130 1098
vladvana 0:23d1f73bf130 1099 #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
vladvana 0:23d1f73bf130 1100 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
vladvana 0:23d1f73bf130 1101
vladvana 0:23d1f73bf130 1102 #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
vladvana 0:23d1f73bf130 1103 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
vladvana 0:23d1f73bf130 1104
vladvana 0:23d1f73bf130 1105 #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
vladvana 0:23d1f73bf130 1106 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
vladvana 0:23d1f73bf130 1107
vladvana 0:23d1f73bf130 1108 #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
vladvana 0:23d1f73bf130 1109 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
vladvana 0:23d1f73bf130 1110
vladvana 0:23d1f73bf130 1111 #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
vladvana 0:23d1f73bf130 1112 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
vladvana 0:23d1f73bf130 1113
vladvana 0:23d1f73bf130 1114 #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
vladvana 0:23d1f73bf130 1115 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
vladvana 0:23d1f73bf130 1116
vladvana 0:23d1f73bf130 1117 #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
vladvana 0:23d1f73bf130 1118 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
vladvana 0:23d1f73bf130 1119
vladvana 0:23d1f73bf130 1120 /* DWT CPI Count Register Definitions */
vladvana 0:23d1f73bf130 1121 #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
vladvana 0:23d1f73bf130 1122 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
vladvana 0:23d1f73bf130 1123
vladvana 0:23d1f73bf130 1124 /* DWT Exception Overhead Count Register Definitions */
vladvana 0:23d1f73bf130 1125 #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
vladvana 0:23d1f73bf130 1126 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
vladvana 0:23d1f73bf130 1127
vladvana 0:23d1f73bf130 1128 /* DWT Sleep Count Register Definitions */
vladvana 0:23d1f73bf130 1129 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
vladvana 0:23d1f73bf130 1130 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
vladvana 0:23d1f73bf130 1131
vladvana 0:23d1f73bf130 1132 /* DWT LSU Count Register Definitions */
vladvana 0:23d1f73bf130 1133 #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
vladvana 0:23d1f73bf130 1134 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
vladvana 0:23d1f73bf130 1135
vladvana 0:23d1f73bf130 1136 /* DWT Folded-instruction Count Register Definitions */
vladvana 0:23d1f73bf130 1137 #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
vladvana 0:23d1f73bf130 1138 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
vladvana 0:23d1f73bf130 1139
vladvana 0:23d1f73bf130 1140 /* DWT Comparator Mask Register Definitions */
vladvana 0:23d1f73bf130 1141 #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
vladvana 0:23d1f73bf130 1142 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
vladvana 0:23d1f73bf130 1143
vladvana 0:23d1f73bf130 1144 /* DWT Comparator Function Register Definitions */
vladvana 0:23d1f73bf130 1145 #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
vladvana 0:23d1f73bf130 1146 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
vladvana 0:23d1f73bf130 1147
vladvana 0:23d1f73bf130 1148 #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
vladvana 0:23d1f73bf130 1149 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
vladvana 0:23d1f73bf130 1150
vladvana 0:23d1f73bf130 1151 #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
vladvana 0:23d1f73bf130 1152 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
vladvana 0:23d1f73bf130 1153
vladvana 0:23d1f73bf130 1154 #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
vladvana 0:23d1f73bf130 1155 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
vladvana 0:23d1f73bf130 1156
vladvana 0:23d1f73bf130 1157 #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
vladvana 0:23d1f73bf130 1158 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
vladvana 0:23d1f73bf130 1159
vladvana 0:23d1f73bf130 1160 #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
vladvana 0:23d1f73bf130 1161 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
vladvana 0:23d1f73bf130 1162
vladvana 0:23d1f73bf130 1163 #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
vladvana 0:23d1f73bf130 1164 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
vladvana 0:23d1f73bf130 1165
vladvana 0:23d1f73bf130 1166 #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
vladvana 0:23d1f73bf130 1167 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
vladvana 0:23d1f73bf130 1168
vladvana 0:23d1f73bf130 1169 #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
vladvana 0:23d1f73bf130 1170 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
vladvana 0:23d1f73bf130 1171
vladvana 0:23d1f73bf130 1172 /*@}*/ /* end of group CMSIS_DWT */
vladvana 0:23d1f73bf130 1173
vladvana 0:23d1f73bf130 1174
vladvana 0:23d1f73bf130 1175 /** \ingroup CMSIS_core_register
vladvana 0:23d1f73bf130 1176 \defgroup CMSIS_TPI Trace Port Interface (TPI)
vladvana 0:23d1f73bf130 1177 \brief Type definitions for the Trace Port Interface (TPI)
vladvana 0:23d1f73bf130 1178 @{
vladvana 0:23d1f73bf130 1179 */
vladvana 0:23d1f73bf130 1180
vladvana 0:23d1f73bf130 1181 /** \brief Structure type to access the Trace Port Interface Register (TPI).
vladvana 0:23d1f73bf130 1182 */
vladvana 0:23d1f73bf130 1183 typedef struct
vladvana 0:23d1f73bf130 1184 {
vladvana 0:23d1f73bf130 1185 __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
vladvana 0:23d1f73bf130 1186 __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
vladvana 0:23d1f73bf130 1187 uint32_t RESERVED0[2];
vladvana 0:23d1f73bf130 1188 __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
vladvana 0:23d1f73bf130 1189 uint32_t RESERVED1[55];
vladvana 0:23d1f73bf130 1190 __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
vladvana 0:23d1f73bf130 1191 uint32_t RESERVED2[131];
vladvana 0:23d1f73bf130 1192 __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
vladvana 0:23d1f73bf130 1193 __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
vladvana 0:23d1f73bf130 1194 __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
vladvana 0:23d1f73bf130 1195 uint32_t RESERVED3[759];
vladvana 0:23d1f73bf130 1196 __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
vladvana 0:23d1f73bf130 1197 __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
vladvana 0:23d1f73bf130 1198 __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
vladvana 0:23d1f73bf130 1199 uint32_t RESERVED4[1];
vladvana 0:23d1f73bf130 1200 __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
vladvana 0:23d1f73bf130 1201 __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
vladvana 0:23d1f73bf130 1202 __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
vladvana 0:23d1f73bf130 1203 uint32_t RESERVED5[39];
vladvana 0:23d1f73bf130 1204 __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
vladvana 0:23d1f73bf130 1205 __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
vladvana 0:23d1f73bf130 1206 uint32_t RESERVED7[8];
vladvana 0:23d1f73bf130 1207 __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
vladvana 0:23d1f73bf130 1208 __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
vladvana 0:23d1f73bf130 1209 } TPI_Type;
vladvana 0:23d1f73bf130 1210
vladvana 0:23d1f73bf130 1211 /* TPI Asynchronous Clock Prescaler Register Definitions */
vladvana 0:23d1f73bf130 1212 #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
vladvana 0:23d1f73bf130 1213 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
vladvana 0:23d1f73bf130 1214
vladvana 0:23d1f73bf130 1215 /* TPI Selected Pin Protocol Register Definitions */
vladvana 0:23d1f73bf130 1216 #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
vladvana 0:23d1f73bf130 1217 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
vladvana 0:23d1f73bf130 1218
vladvana 0:23d1f73bf130 1219 /* TPI Formatter and Flush Status Register Definitions */
vladvana 0:23d1f73bf130 1220 #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
vladvana 0:23d1f73bf130 1221 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
vladvana 0:23d1f73bf130 1222
vladvana 0:23d1f73bf130 1223 #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
vladvana 0:23d1f73bf130 1224 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
vladvana 0:23d1f73bf130 1225
vladvana 0:23d1f73bf130 1226 #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
vladvana 0:23d1f73bf130 1227 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
vladvana 0:23d1f73bf130 1228
vladvana 0:23d1f73bf130 1229 #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
vladvana 0:23d1f73bf130 1230 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
vladvana 0:23d1f73bf130 1231
vladvana 0:23d1f73bf130 1232 /* TPI Formatter and Flush Control Register Definitions */
vladvana 0:23d1f73bf130 1233 #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
vladvana 0:23d1f73bf130 1234 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
vladvana 0:23d1f73bf130 1235
vladvana 0:23d1f73bf130 1236 #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
vladvana 0:23d1f73bf130 1237 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
vladvana 0:23d1f73bf130 1238
vladvana 0:23d1f73bf130 1239 /* TPI TRIGGER Register Definitions */
vladvana 0:23d1f73bf130 1240 #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
vladvana 0:23d1f73bf130 1241 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
vladvana 0:23d1f73bf130 1242
vladvana 0:23d1f73bf130 1243 /* TPI Integration ETM Data Register Definitions (FIFO0) */
vladvana 0:23d1f73bf130 1244 #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
vladvana 0:23d1f73bf130 1245 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
vladvana 0:23d1f73bf130 1246
vladvana 0:23d1f73bf130 1247 #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
vladvana 0:23d1f73bf130 1248 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
vladvana 0:23d1f73bf130 1249
vladvana 0:23d1f73bf130 1250 #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
vladvana 0:23d1f73bf130 1251 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
vladvana 0:23d1f73bf130 1252
vladvana 0:23d1f73bf130 1253 #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
vladvana 0:23d1f73bf130 1254 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
vladvana 0:23d1f73bf130 1255
vladvana 0:23d1f73bf130 1256 #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
vladvana 0:23d1f73bf130 1257 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
vladvana 0:23d1f73bf130 1258
vladvana 0:23d1f73bf130 1259 #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
vladvana 0:23d1f73bf130 1260 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
vladvana 0:23d1f73bf130 1261
vladvana 0:23d1f73bf130 1262 #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
vladvana 0:23d1f73bf130 1263 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
vladvana 0:23d1f73bf130 1264
vladvana 0:23d1f73bf130 1265 /* TPI ITATBCTR2 Register Definitions */
vladvana 0:23d1f73bf130 1266 #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
vladvana 0:23d1f73bf130 1267 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
vladvana 0:23d1f73bf130 1268
vladvana 0:23d1f73bf130 1269 /* TPI Integration ITM Data Register Definitions (FIFO1) */
vladvana 0:23d1f73bf130 1270 #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
vladvana 0:23d1f73bf130 1271 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
vladvana 0:23d1f73bf130 1272
vladvana 0:23d1f73bf130 1273 #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
vladvana 0:23d1f73bf130 1274 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
vladvana 0:23d1f73bf130 1275
vladvana 0:23d1f73bf130 1276 #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
vladvana 0:23d1f73bf130 1277 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
vladvana 0:23d1f73bf130 1278
vladvana 0:23d1f73bf130 1279 #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
vladvana 0:23d1f73bf130 1280 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
vladvana 0:23d1f73bf130 1281
vladvana 0:23d1f73bf130 1282 #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
vladvana 0:23d1f73bf130 1283 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
vladvana 0:23d1f73bf130 1284
vladvana 0:23d1f73bf130 1285 #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
vladvana 0:23d1f73bf130 1286 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
vladvana 0:23d1f73bf130 1287
vladvana 0:23d1f73bf130 1288 #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
vladvana 0:23d1f73bf130 1289 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
vladvana 0:23d1f73bf130 1290
vladvana 0:23d1f73bf130 1291 /* TPI ITATBCTR0 Register Definitions */
vladvana 0:23d1f73bf130 1292 #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
vladvana 0:23d1f73bf130 1293 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
vladvana 0:23d1f73bf130 1294
vladvana 0:23d1f73bf130 1295 /* TPI Integration Mode Control Register Definitions */
vladvana 0:23d1f73bf130 1296 #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
vladvana 0:23d1f73bf130 1297 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
vladvana 0:23d1f73bf130 1298
vladvana 0:23d1f73bf130 1299 /* TPI DEVID Register Definitions */
vladvana 0:23d1f73bf130 1300 #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
vladvana 0:23d1f73bf130 1301 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
vladvana 0:23d1f73bf130 1302
vladvana 0:23d1f73bf130 1303 #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
vladvana 0:23d1f73bf130 1304 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
vladvana 0:23d1f73bf130 1305
vladvana 0:23d1f73bf130 1306 #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
vladvana 0:23d1f73bf130 1307 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
vladvana 0:23d1f73bf130 1308
vladvana 0:23d1f73bf130 1309 #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
vladvana 0:23d1f73bf130 1310 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
vladvana 0:23d1f73bf130 1311
vladvana 0:23d1f73bf130 1312 #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
vladvana 0:23d1f73bf130 1313 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
vladvana 0:23d1f73bf130 1314
vladvana 0:23d1f73bf130 1315 #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
vladvana 0:23d1f73bf130 1316 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
vladvana 0:23d1f73bf130 1317
vladvana 0:23d1f73bf130 1318 /* TPI DEVTYPE Register Definitions */
vladvana 0:23d1f73bf130 1319 #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
vladvana 0:23d1f73bf130 1320 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
vladvana 0:23d1f73bf130 1321
vladvana 0:23d1f73bf130 1322 #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
vladvana 0:23d1f73bf130 1323 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
vladvana 0:23d1f73bf130 1324
vladvana 0:23d1f73bf130 1325 /*@}*/ /* end of group CMSIS_TPI */
vladvana 0:23d1f73bf130 1326
vladvana 0:23d1f73bf130 1327
vladvana 0:23d1f73bf130 1328 #if (__MPU_PRESENT == 1)
vladvana 0:23d1f73bf130 1329 /** \ingroup CMSIS_core_register
vladvana 0:23d1f73bf130 1330 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
vladvana 0:23d1f73bf130 1331 \brief Type definitions for the Memory Protection Unit (MPU)
vladvana 0:23d1f73bf130 1332 @{
vladvana 0:23d1f73bf130 1333 */
vladvana 0:23d1f73bf130 1334
vladvana 0:23d1f73bf130 1335 /** \brief Structure type to access the Memory Protection Unit (MPU).
vladvana 0:23d1f73bf130 1336 */
vladvana 0:23d1f73bf130 1337 typedef struct
vladvana 0:23d1f73bf130 1338 {
vladvana 0:23d1f73bf130 1339 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
vladvana 0:23d1f73bf130 1340 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
vladvana 0:23d1f73bf130 1341 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
vladvana 0:23d1f73bf130 1342 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
vladvana 0:23d1f73bf130 1343 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
vladvana 0:23d1f73bf130 1344 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
vladvana 0:23d1f73bf130 1345 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
vladvana 0:23d1f73bf130 1346 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
vladvana 0:23d1f73bf130 1347 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
vladvana 0:23d1f73bf130 1348 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
vladvana 0:23d1f73bf130 1349 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
vladvana 0:23d1f73bf130 1350 } MPU_Type;
vladvana 0:23d1f73bf130 1351
vladvana 0:23d1f73bf130 1352 /* MPU Type Register */
vladvana 0:23d1f73bf130 1353 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
vladvana 0:23d1f73bf130 1354 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
vladvana 0:23d1f73bf130 1355
vladvana 0:23d1f73bf130 1356 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
vladvana 0:23d1f73bf130 1357 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
vladvana 0:23d1f73bf130 1358
vladvana 0:23d1f73bf130 1359 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
vladvana 0:23d1f73bf130 1360 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
vladvana 0:23d1f73bf130 1361
vladvana 0:23d1f73bf130 1362 /* MPU Control Register */
vladvana 0:23d1f73bf130 1363 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
vladvana 0:23d1f73bf130 1364 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
vladvana 0:23d1f73bf130 1365
vladvana 0:23d1f73bf130 1366 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
vladvana 0:23d1f73bf130 1367 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
vladvana 0:23d1f73bf130 1368
vladvana 0:23d1f73bf130 1369 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
vladvana 0:23d1f73bf130 1370 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
vladvana 0:23d1f73bf130 1371
vladvana 0:23d1f73bf130 1372 /* MPU Region Number Register */
vladvana 0:23d1f73bf130 1373 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
vladvana 0:23d1f73bf130 1374 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
vladvana 0:23d1f73bf130 1375
vladvana 0:23d1f73bf130 1376 /* MPU Region Base Address Register */
vladvana 0:23d1f73bf130 1377 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
vladvana 0:23d1f73bf130 1378 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
vladvana 0:23d1f73bf130 1379
vladvana 0:23d1f73bf130 1380 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
vladvana 0:23d1f73bf130 1381 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
vladvana 0:23d1f73bf130 1382
vladvana 0:23d1f73bf130 1383 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
vladvana 0:23d1f73bf130 1384 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
vladvana 0:23d1f73bf130 1385
vladvana 0:23d1f73bf130 1386 /* MPU Region Attribute and Size Register */
vladvana 0:23d1f73bf130 1387 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
vladvana 0:23d1f73bf130 1388 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
vladvana 0:23d1f73bf130 1389
vladvana 0:23d1f73bf130 1390 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
vladvana 0:23d1f73bf130 1391 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
vladvana 0:23d1f73bf130 1392
vladvana 0:23d1f73bf130 1393 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
vladvana 0:23d1f73bf130 1394 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
vladvana 0:23d1f73bf130 1395
vladvana 0:23d1f73bf130 1396 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
vladvana 0:23d1f73bf130 1397 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
vladvana 0:23d1f73bf130 1398
vladvana 0:23d1f73bf130 1399 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
vladvana 0:23d1f73bf130 1400 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
vladvana 0:23d1f73bf130 1401
vladvana 0:23d1f73bf130 1402 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
vladvana 0:23d1f73bf130 1403 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
vladvana 0:23d1f73bf130 1404
vladvana 0:23d1f73bf130 1405 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
vladvana 0:23d1f73bf130 1406 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
vladvana 0:23d1f73bf130 1407
vladvana 0:23d1f73bf130 1408 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
vladvana 0:23d1f73bf130 1409 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
vladvana 0:23d1f73bf130 1410
vladvana 0:23d1f73bf130 1411 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
vladvana 0:23d1f73bf130 1412 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
vladvana 0:23d1f73bf130 1413
vladvana 0:23d1f73bf130 1414 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
vladvana 0:23d1f73bf130 1415 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
vladvana 0:23d1f73bf130 1416
vladvana 0:23d1f73bf130 1417 /*@} end of group CMSIS_MPU */
vladvana 0:23d1f73bf130 1418 #endif
vladvana 0:23d1f73bf130 1419
vladvana 0:23d1f73bf130 1420
vladvana 0:23d1f73bf130 1421 #if (__FPU_PRESENT == 1)
vladvana 0:23d1f73bf130 1422 /** \ingroup CMSIS_core_register
vladvana 0:23d1f73bf130 1423 \defgroup CMSIS_FPU Floating Point Unit (FPU)
vladvana 0:23d1f73bf130 1424 \brief Type definitions for the Floating Point Unit (FPU)
vladvana 0:23d1f73bf130 1425 @{
vladvana 0:23d1f73bf130 1426 */
vladvana 0:23d1f73bf130 1427
vladvana 0:23d1f73bf130 1428 /** \brief Structure type to access the Floating Point Unit (FPU).
vladvana 0:23d1f73bf130 1429 */
vladvana 0:23d1f73bf130 1430 typedef struct
vladvana 0:23d1f73bf130 1431 {
vladvana 0:23d1f73bf130 1432 uint32_t RESERVED0[1];
vladvana 0:23d1f73bf130 1433 __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
vladvana 0:23d1f73bf130 1434 __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
vladvana 0:23d1f73bf130 1435 __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
vladvana 0:23d1f73bf130 1436 __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
vladvana 0:23d1f73bf130 1437 __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
vladvana 0:23d1f73bf130 1438 __I uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */
vladvana 0:23d1f73bf130 1439 } FPU_Type;
vladvana 0:23d1f73bf130 1440
vladvana 0:23d1f73bf130 1441 /* Floating-Point Context Control Register */
vladvana 0:23d1f73bf130 1442 #define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */
vladvana 0:23d1f73bf130 1443 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
vladvana 0:23d1f73bf130 1444
vladvana 0:23d1f73bf130 1445 #define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */
vladvana 0:23d1f73bf130 1446 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
vladvana 0:23d1f73bf130 1447
vladvana 0:23d1f73bf130 1448 #define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */
vladvana 0:23d1f73bf130 1449 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
vladvana 0:23d1f73bf130 1450
vladvana 0:23d1f73bf130 1451 #define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */
vladvana 0:23d1f73bf130 1452 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
vladvana 0:23d1f73bf130 1453
vladvana 0:23d1f73bf130 1454 #define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */
vladvana 0:23d1f73bf130 1455 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
vladvana 0:23d1f73bf130 1456
vladvana 0:23d1f73bf130 1457 #define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */
vladvana 0:23d1f73bf130 1458 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
vladvana 0:23d1f73bf130 1459
vladvana 0:23d1f73bf130 1460 #define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */
vladvana 0:23d1f73bf130 1461 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
vladvana 0:23d1f73bf130 1462
vladvana 0:23d1f73bf130 1463 #define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */
vladvana 0:23d1f73bf130 1464 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
vladvana 0:23d1f73bf130 1465
vladvana 0:23d1f73bf130 1466 #define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */
vladvana 0:23d1f73bf130 1467 #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
vladvana 0:23d1f73bf130 1468
vladvana 0:23d1f73bf130 1469 /* Floating-Point Context Address Register */
vladvana 0:23d1f73bf130 1470 #define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */
vladvana 0:23d1f73bf130 1471 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
vladvana 0:23d1f73bf130 1472
vladvana 0:23d1f73bf130 1473 /* Floating-Point Default Status Control Register */
vladvana 0:23d1f73bf130 1474 #define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */
vladvana 0:23d1f73bf130 1475 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
vladvana 0:23d1f73bf130 1476
vladvana 0:23d1f73bf130 1477 #define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */
vladvana 0:23d1f73bf130 1478 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
vladvana 0:23d1f73bf130 1479
vladvana 0:23d1f73bf130 1480 #define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */
vladvana 0:23d1f73bf130 1481 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
vladvana 0:23d1f73bf130 1482
vladvana 0:23d1f73bf130 1483 #define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */
vladvana 0:23d1f73bf130 1484 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
vladvana 0:23d1f73bf130 1485
vladvana 0:23d1f73bf130 1486 /* Media and FP Feature Register 0 */
vladvana 0:23d1f73bf130 1487 #define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */
vladvana 0:23d1f73bf130 1488 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
vladvana 0:23d1f73bf130 1489
vladvana 0:23d1f73bf130 1490 #define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */
vladvana 0:23d1f73bf130 1491 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
vladvana 0:23d1f73bf130 1492
vladvana 0:23d1f73bf130 1493 #define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */
vladvana 0:23d1f73bf130 1494 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
vladvana 0:23d1f73bf130 1495
vladvana 0:23d1f73bf130 1496 #define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */
vladvana 0:23d1f73bf130 1497 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
vladvana 0:23d1f73bf130 1498
vladvana 0:23d1f73bf130 1499 #define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */
vladvana 0:23d1f73bf130 1500 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
vladvana 0:23d1f73bf130 1501
vladvana 0:23d1f73bf130 1502 #define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */
vladvana 0:23d1f73bf130 1503 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
vladvana 0:23d1f73bf130 1504
vladvana 0:23d1f73bf130 1505 #define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */
vladvana 0:23d1f73bf130 1506 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
vladvana 0:23d1f73bf130 1507
vladvana 0:23d1f73bf130 1508 #define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */
vladvana 0:23d1f73bf130 1509 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
vladvana 0:23d1f73bf130 1510
vladvana 0:23d1f73bf130 1511 /* Media and FP Feature Register 1 */
vladvana 0:23d1f73bf130 1512 #define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */
vladvana 0:23d1f73bf130 1513 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
vladvana 0:23d1f73bf130 1514
vladvana 0:23d1f73bf130 1515 #define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */
vladvana 0:23d1f73bf130 1516 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
vladvana 0:23d1f73bf130 1517
vladvana 0:23d1f73bf130 1518 #define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */
vladvana 0:23d1f73bf130 1519 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
vladvana 0:23d1f73bf130 1520
vladvana 0:23d1f73bf130 1521 #define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */
vladvana 0:23d1f73bf130 1522 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
vladvana 0:23d1f73bf130 1523
vladvana 0:23d1f73bf130 1524 /* Media and FP Feature Register 2 */
vladvana 0:23d1f73bf130 1525
vladvana 0:23d1f73bf130 1526 /*@} end of group CMSIS_FPU */
vladvana 0:23d1f73bf130 1527 #endif
vladvana 0:23d1f73bf130 1528
vladvana 0:23d1f73bf130 1529
vladvana 0:23d1f73bf130 1530 /** \ingroup CMSIS_core_register
vladvana 0:23d1f73bf130 1531 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
vladvana 0:23d1f73bf130 1532 \brief Type definitions for the Core Debug Registers
vladvana 0:23d1f73bf130 1533 @{
vladvana 0:23d1f73bf130 1534 */
vladvana 0:23d1f73bf130 1535
vladvana 0:23d1f73bf130 1536 /** \brief Structure type to access the Core Debug Register (CoreDebug).
vladvana 0:23d1f73bf130 1537 */
vladvana 0:23d1f73bf130 1538 typedef struct
vladvana 0:23d1f73bf130 1539 {
vladvana 0:23d1f73bf130 1540 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
vladvana 0:23d1f73bf130 1541 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
vladvana 0:23d1f73bf130 1542 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
vladvana 0:23d1f73bf130 1543 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
vladvana 0:23d1f73bf130 1544 } CoreDebug_Type;
vladvana 0:23d1f73bf130 1545
vladvana 0:23d1f73bf130 1546 /* Debug Halting Control and Status Register */
vladvana 0:23d1f73bf130 1547 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
vladvana 0:23d1f73bf130 1548 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
vladvana 0:23d1f73bf130 1549
vladvana 0:23d1f73bf130 1550 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
vladvana 0:23d1f73bf130 1551 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
vladvana 0:23d1f73bf130 1552
vladvana 0:23d1f73bf130 1553 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
vladvana 0:23d1f73bf130 1554 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
vladvana 0:23d1f73bf130 1555
vladvana 0:23d1f73bf130 1556 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
vladvana 0:23d1f73bf130 1557 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
vladvana 0:23d1f73bf130 1558
vladvana 0:23d1f73bf130 1559 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
vladvana 0:23d1f73bf130 1560 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
vladvana 0:23d1f73bf130 1561
vladvana 0:23d1f73bf130 1562 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
vladvana 0:23d1f73bf130 1563 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
vladvana 0:23d1f73bf130 1564
vladvana 0:23d1f73bf130 1565 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
vladvana 0:23d1f73bf130 1566 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
vladvana 0:23d1f73bf130 1567
vladvana 0:23d1f73bf130 1568 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
vladvana 0:23d1f73bf130 1569 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
vladvana 0:23d1f73bf130 1570
vladvana 0:23d1f73bf130 1571 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
vladvana 0:23d1f73bf130 1572 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
vladvana 0:23d1f73bf130 1573
vladvana 0:23d1f73bf130 1574 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
vladvana 0:23d1f73bf130 1575 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
vladvana 0:23d1f73bf130 1576
vladvana 0:23d1f73bf130 1577 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
vladvana 0:23d1f73bf130 1578 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
vladvana 0:23d1f73bf130 1579
vladvana 0:23d1f73bf130 1580 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
vladvana 0:23d1f73bf130 1581 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
vladvana 0:23d1f73bf130 1582
vladvana 0:23d1f73bf130 1583 /* Debug Core Register Selector Register */
vladvana 0:23d1f73bf130 1584 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
vladvana 0:23d1f73bf130 1585 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
vladvana 0:23d1f73bf130 1586
vladvana 0:23d1f73bf130 1587 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
vladvana 0:23d1f73bf130 1588 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
vladvana 0:23d1f73bf130 1589
vladvana 0:23d1f73bf130 1590 /* Debug Exception and Monitor Control Register */
vladvana 0:23d1f73bf130 1591 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
vladvana 0:23d1f73bf130 1592 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
vladvana 0:23d1f73bf130 1593
vladvana 0:23d1f73bf130 1594 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
vladvana 0:23d1f73bf130 1595 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
vladvana 0:23d1f73bf130 1596
vladvana 0:23d1f73bf130 1597 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
vladvana 0:23d1f73bf130 1598 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
vladvana 0:23d1f73bf130 1599
vladvana 0:23d1f73bf130 1600 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
vladvana 0:23d1f73bf130 1601 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
vladvana 0:23d1f73bf130 1602
vladvana 0:23d1f73bf130 1603 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
vladvana 0:23d1f73bf130 1604 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
vladvana 0:23d1f73bf130 1605
vladvana 0:23d1f73bf130 1606 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
vladvana 0:23d1f73bf130 1607 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
vladvana 0:23d1f73bf130 1608
vladvana 0:23d1f73bf130 1609 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
vladvana 0:23d1f73bf130 1610 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
vladvana 0:23d1f73bf130 1611
vladvana 0:23d1f73bf130 1612 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
vladvana 0:23d1f73bf130 1613 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
vladvana 0:23d1f73bf130 1614
vladvana 0:23d1f73bf130 1615 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
vladvana 0:23d1f73bf130 1616 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
vladvana 0:23d1f73bf130 1617
vladvana 0:23d1f73bf130 1618 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
vladvana 0:23d1f73bf130 1619 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
vladvana 0:23d1f73bf130 1620
vladvana 0:23d1f73bf130 1621 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
vladvana 0:23d1f73bf130 1622 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
vladvana 0:23d1f73bf130 1623
vladvana 0:23d1f73bf130 1624 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
vladvana 0:23d1f73bf130 1625 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
vladvana 0:23d1f73bf130 1626
vladvana 0:23d1f73bf130 1627 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
vladvana 0:23d1f73bf130 1628 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
vladvana 0:23d1f73bf130 1629
vladvana 0:23d1f73bf130 1630 /*@} end of group CMSIS_CoreDebug */
vladvana 0:23d1f73bf130 1631
vladvana 0:23d1f73bf130 1632
vladvana 0:23d1f73bf130 1633 /** \ingroup CMSIS_core_register
vladvana 0:23d1f73bf130 1634 \defgroup CMSIS_core_base Core Definitions
vladvana 0:23d1f73bf130 1635 \brief Definitions for base addresses, unions, and structures.
vladvana 0:23d1f73bf130 1636 @{
vladvana 0:23d1f73bf130 1637 */
vladvana 0:23d1f73bf130 1638
vladvana 0:23d1f73bf130 1639 /* Memory mapping of Cortex-M4 Hardware */
vladvana 0:23d1f73bf130 1640 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
vladvana 0:23d1f73bf130 1641 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
vladvana 0:23d1f73bf130 1642 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
vladvana 0:23d1f73bf130 1643 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
vladvana 0:23d1f73bf130 1644 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
vladvana 0:23d1f73bf130 1645 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
vladvana 0:23d1f73bf130 1646 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
vladvana 0:23d1f73bf130 1647 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
vladvana 0:23d1f73bf130 1648
vladvana 0:23d1f73bf130 1649 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
vladvana 0:23d1f73bf130 1650 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
vladvana 0:23d1f73bf130 1651 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
vladvana 0:23d1f73bf130 1652 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
vladvana 0:23d1f73bf130 1653 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
vladvana 0:23d1f73bf130 1654 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
vladvana 0:23d1f73bf130 1655 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
vladvana 0:23d1f73bf130 1656 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
vladvana 0:23d1f73bf130 1657
vladvana 0:23d1f73bf130 1658 #if (__MPU_PRESENT == 1)
vladvana 0:23d1f73bf130 1659 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
vladvana 0:23d1f73bf130 1660 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
vladvana 0:23d1f73bf130 1661 #endif
vladvana 0:23d1f73bf130 1662
vladvana 0:23d1f73bf130 1663 #if (__FPU_PRESENT == 1)
vladvana 0:23d1f73bf130 1664 #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
vladvana 0:23d1f73bf130 1665 #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
vladvana 0:23d1f73bf130 1666 #endif
vladvana 0:23d1f73bf130 1667
vladvana 0:23d1f73bf130 1668 /*@} */
vladvana 0:23d1f73bf130 1669
vladvana 0:23d1f73bf130 1670
vladvana 0:23d1f73bf130 1671
vladvana 0:23d1f73bf130 1672 /*******************************************************************************
vladvana 0:23d1f73bf130 1673 * Hardware Abstraction Layer
vladvana 0:23d1f73bf130 1674 Core Function Interface contains:
vladvana 0:23d1f73bf130 1675 - Core NVIC Functions
vladvana 0:23d1f73bf130 1676 - Core SysTick Functions
vladvana 0:23d1f73bf130 1677 - Core Debug Functions
vladvana 0:23d1f73bf130 1678 - Core Register Access Functions
vladvana 0:23d1f73bf130 1679 ******************************************************************************/
vladvana 0:23d1f73bf130 1680 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
vladvana 0:23d1f73bf130 1681 */
vladvana 0:23d1f73bf130 1682
vladvana 0:23d1f73bf130 1683
vladvana 0:23d1f73bf130 1684
vladvana 0:23d1f73bf130 1685 /* ########################## NVIC functions #################################### */
vladvana 0:23d1f73bf130 1686 /** \ingroup CMSIS_Core_FunctionInterface
vladvana 0:23d1f73bf130 1687 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
vladvana 0:23d1f73bf130 1688 \brief Functions that manage interrupts and exceptions via the NVIC.
vladvana 0:23d1f73bf130 1689 @{
vladvana 0:23d1f73bf130 1690 */
vladvana 0:23d1f73bf130 1691
vladvana 0:23d1f73bf130 1692 /** \brief Set Priority Grouping
vladvana 0:23d1f73bf130 1693
vladvana 0:23d1f73bf130 1694 The function sets the priority grouping field using the required unlock sequence.
vladvana 0:23d1f73bf130 1695 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
vladvana 0:23d1f73bf130 1696 Only values from 0..7 are used.
vladvana 0:23d1f73bf130 1697 In case of a conflict between priority grouping and available
vladvana 0:23d1f73bf130 1698 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
vladvana 0:23d1f73bf130 1699
vladvana 0:23d1f73bf130 1700 \param [in] PriorityGroup Priority grouping field.
vladvana 0:23d1f73bf130 1701 */
vladvana 0:23d1f73bf130 1702 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
vladvana 0:23d1f73bf130 1703 {
vladvana 0:23d1f73bf130 1704 uint32_t reg_value;
vladvana 0:23d1f73bf130 1705 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
vladvana 0:23d1f73bf130 1706
vladvana 0:23d1f73bf130 1707 reg_value = SCB->AIRCR; /* read old register configuration */
vladvana 0:23d1f73bf130 1708 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
vladvana 0:23d1f73bf130 1709 reg_value = (reg_value |
vladvana 0:23d1f73bf130 1710 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
vladvana 0:23d1f73bf130 1711 (PriorityGroupTmp << 8) ); /* Insert write key and priorty group */
vladvana 0:23d1f73bf130 1712 SCB->AIRCR = reg_value;
vladvana 0:23d1f73bf130 1713 }
vladvana 0:23d1f73bf130 1714
vladvana 0:23d1f73bf130 1715
vladvana 0:23d1f73bf130 1716 /** \brief Get Priority Grouping
vladvana 0:23d1f73bf130 1717
vladvana 0:23d1f73bf130 1718 The function reads the priority grouping field from the NVIC Interrupt Controller.
vladvana 0:23d1f73bf130 1719
vladvana 0:23d1f73bf130 1720 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
vladvana 0:23d1f73bf130 1721 */
vladvana 0:23d1f73bf130 1722 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
vladvana 0:23d1f73bf130 1723 {
vladvana 0:23d1f73bf130 1724 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
vladvana 0:23d1f73bf130 1725 }
vladvana 0:23d1f73bf130 1726
vladvana 0:23d1f73bf130 1727
vladvana 0:23d1f73bf130 1728 /** \brief Enable External Interrupt
vladvana 0:23d1f73bf130 1729
vladvana 0:23d1f73bf130 1730 The function enables a device-specific interrupt in the NVIC interrupt controller.
vladvana 0:23d1f73bf130 1731
vladvana 0:23d1f73bf130 1732 \param [in] IRQn External interrupt number. Value cannot be negative.
vladvana 0:23d1f73bf130 1733 */
vladvana 0:23d1f73bf130 1734 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
vladvana 0:23d1f73bf130 1735 {
vladvana 0:23d1f73bf130 1736 NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
vladvana 0:23d1f73bf130 1737 }
vladvana 0:23d1f73bf130 1738
vladvana 0:23d1f73bf130 1739
vladvana 0:23d1f73bf130 1740 /** \brief Disable External Interrupt
vladvana 0:23d1f73bf130 1741
vladvana 0:23d1f73bf130 1742 The function disables a device-specific interrupt in the NVIC interrupt controller.
vladvana 0:23d1f73bf130 1743
vladvana 0:23d1f73bf130 1744 \param [in] IRQn External interrupt number. Value cannot be negative.
vladvana 0:23d1f73bf130 1745 */
vladvana 0:23d1f73bf130 1746 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
vladvana 0:23d1f73bf130 1747 {
vladvana 0:23d1f73bf130 1748 NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
vladvana 0:23d1f73bf130 1749 }
vladvana 0:23d1f73bf130 1750
vladvana 0:23d1f73bf130 1751
vladvana 0:23d1f73bf130 1752 /** \brief Get Pending Interrupt
vladvana 0:23d1f73bf130 1753
vladvana 0:23d1f73bf130 1754 The function reads the pending register in the NVIC and returns the pending bit
vladvana 0:23d1f73bf130 1755 for the specified interrupt.
vladvana 0:23d1f73bf130 1756
vladvana 0:23d1f73bf130 1757 \param [in] IRQn Interrupt number.
vladvana 0:23d1f73bf130 1758
vladvana 0:23d1f73bf130 1759 \return 0 Interrupt status is not pending.
vladvana 0:23d1f73bf130 1760 \return 1 Interrupt status is pending.
vladvana 0:23d1f73bf130 1761 */
vladvana 0:23d1f73bf130 1762 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
vladvana 0:23d1f73bf130 1763 {
vladvana 0:23d1f73bf130 1764 return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
vladvana 0:23d1f73bf130 1765 }
vladvana 0:23d1f73bf130 1766
vladvana 0:23d1f73bf130 1767
vladvana 0:23d1f73bf130 1768 /** \brief Set Pending Interrupt
vladvana 0:23d1f73bf130 1769
vladvana 0:23d1f73bf130 1770 The function sets the pending bit of an external interrupt.
vladvana 0:23d1f73bf130 1771
vladvana 0:23d1f73bf130 1772 \param [in] IRQn Interrupt number. Value cannot be negative.
vladvana 0:23d1f73bf130 1773 */
vladvana 0:23d1f73bf130 1774 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
vladvana 0:23d1f73bf130 1775 {
vladvana 0:23d1f73bf130 1776 NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
vladvana 0:23d1f73bf130 1777 }
vladvana 0:23d1f73bf130 1778
vladvana 0:23d1f73bf130 1779
vladvana 0:23d1f73bf130 1780 /** \brief Clear Pending Interrupt
vladvana 0:23d1f73bf130 1781
vladvana 0:23d1f73bf130 1782 The function clears the pending bit of an external interrupt.
vladvana 0:23d1f73bf130 1783
vladvana 0:23d1f73bf130 1784 \param [in] IRQn External interrupt number. Value cannot be negative.
vladvana 0:23d1f73bf130 1785 */
vladvana 0:23d1f73bf130 1786 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
vladvana 0:23d1f73bf130 1787 {
vladvana 0:23d1f73bf130 1788 NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
vladvana 0:23d1f73bf130 1789 }
vladvana 0:23d1f73bf130 1790
vladvana 0:23d1f73bf130 1791
vladvana 0:23d1f73bf130 1792 /** \brief Get Active Interrupt
vladvana 0:23d1f73bf130 1793
vladvana 0:23d1f73bf130 1794 The function reads the active register in NVIC and returns the active bit.
vladvana 0:23d1f73bf130 1795
vladvana 0:23d1f73bf130 1796 \param [in] IRQn Interrupt number.
vladvana 0:23d1f73bf130 1797
vladvana 0:23d1f73bf130 1798 \return 0 Interrupt status is not active.
vladvana 0:23d1f73bf130 1799 \return 1 Interrupt status is active.
vladvana 0:23d1f73bf130 1800 */
vladvana 0:23d1f73bf130 1801 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
vladvana 0:23d1f73bf130 1802 {
vladvana 0:23d1f73bf130 1803 return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
vladvana 0:23d1f73bf130 1804 }
vladvana 0:23d1f73bf130 1805
vladvana 0:23d1f73bf130 1806
vladvana 0:23d1f73bf130 1807 /** \brief Set Interrupt Priority
vladvana 0:23d1f73bf130 1808
vladvana 0:23d1f73bf130 1809 The function sets the priority of an interrupt.
vladvana 0:23d1f73bf130 1810
vladvana 0:23d1f73bf130 1811 \note The priority cannot be set for every core interrupt.
vladvana 0:23d1f73bf130 1812
vladvana 0:23d1f73bf130 1813 \param [in] IRQn Interrupt number.
vladvana 0:23d1f73bf130 1814 \param [in] priority Priority to set.
vladvana 0:23d1f73bf130 1815 */
vladvana 0:23d1f73bf130 1816 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
vladvana 0:23d1f73bf130 1817 {
vladvana 0:23d1f73bf130 1818 if((int32_t)IRQn < 0) {
vladvana 0:23d1f73bf130 1819 SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
vladvana 0:23d1f73bf130 1820 }
vladvana 0:23d1f73bf130 1821 else {
vladvana 0:23d1f73bf130 1822 NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
vladvana 0:23d1f73bf130 1823 }
vladvana 0:23d1f73bf130 1824 }
vladvana 0:23d1f73bf130 1825
vladvana 0:23d1f73bf130 1826
vladvana 0:23d1f73bf130 1827 /** \brief Get Interrupt Priority
vladvana 0:23d1f73bf130 1828
vladvana 0:23d1f73bf130 1829 The function reads the priority of an interrupt. The interrupt
vladvana 0:23d1f73bf130 1830 number can be positive to specify an external (device specific)
vladvana 0:23d1f73bf130 1831 interrupt, or negative to specify an internal (core) interrupt.
vladvana 0:23d1f73bf130 1832
vladvana 0:23d1f73bf130 1833
vladvana 0:23d1f73bf130 1834 \param [in] IRQn Interrupt number.
vladvana 0:23d1f73bf130 1835 \return Interrupt Priority. Value is aligned automatically to the implemented
vladvana 0:23d1f73bf130 1836 priority bits of the microcontroller.
vladvana 0:23d1f73bf130 1837 */
vladvana 0:23d1f73bf130 1838 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
vladvana 0:23d1f73bf130 1839 {
vladvana 0:23d1f73bf130 1840
vladvana 0:23d1f73bf130 1841 if((int32_t)IRQn < 0) {
vladvana 0:23d1f73bf130 1842 return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
vladvana 0:23d1f73bf130 1843 }
vladvana 0:23d1f73bf130 1844 else {
vladvana 0:23d1f73bf130 1845 return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));
vladvana 0:23d1f73bf130 1846 }
vladvana 0:23d1f73bf130 1847 }
vladvana 0:23d1f73bf130 1848
vladvana 0:23d1f73bf130 1849
vladvana 0:23d1f73bf130 1850 /** \brief Encode Priority
vladvana 0:23d1f73bf130 1851
vladvana 0:23d1f73bf130 1852 The function encodes the priority for an interrupt with the given priority group,
vladvana 0:23d1f73bf130 1853 preemptive priority value, and subpriority value.
vladvana 0:23d1f73bf130 1854 In case of a conflict between priority grouping and available
vladvana 0:23d1f73bf130 1855 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
vladvana 0:23d1f73bf130 1856
vladvana 0:23d1f73bf130 1857 \param [in] PriorityGroup Used priority group.
vladvana 0:23d1f73bf130 1858 \param [in] PreemptPriority Preemptive priority value (starting from 0).
vladvana 0:23d1f73bf130 1859 \param [in] SubPriority Subpriority value (starting from 0).
vladvana 0:23d1f73bf130 1860 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
vladvana 0:23d1f73bf130 1861 */
vladvana 0:23d1f73bf130 1862 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
vladvana 0:23d1f73bf130 1863 {
vladvana 0:23d1f73bf130 1864 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
vladvana 0:23d1f73bf130 1865 uint32_t PreemptPriorityBits;
vladvana 0:23d1f73bf130 1866 uint32_t SubPriorityBits;
vladvana 0:23d1f73bf130 1867
vladvana 0:23d1f73bf130 1868 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
vladvana 0:23d1f73bf130 1869 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
vladvana 0:23d1f73bf130 1870
vladvana 0:23d1f73bf130 1871 return (
vladvana 0:23d1f73bf130 1872 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
vladvana 0:23d1f73bf130 1873 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
vladvana 0:23d1f73bf130 1874 );
vladvana 0:23d1f73bf130 1875 }
vladvana 0:23d1f73bf130 1876
vladvana 0:23d1f73bf130 1877
vladvana 0:23d1f73bf130 1878 /** \brief Decode Priority
vladvana 0:23d1f73bf130 1879
vladvana 0:23d1f73bf130 1880 The function decodes an interrupt priority value with a given priority group to
vladvana 0:23d1f73bf130 1881 preemptive priority value and subpriority value.
vladvana 0:23d1f73bf130 1882 In case of a conflict between priority grouping and available
vladvana 0:23d1f73bf130 1883 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
vladvana 0:23d1f73bf130 1884
vladvana 0:23d1f73bf130 1885 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
vladvana 0:23d1f73bf130 1886 \param [in] PriorityGroup Used priority group.
vladvana 0:23d1f73bf130 1887 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
vladvana 0:23d1f73bf130 1888 \param [out] pSubPriority Subpriority value (starting from 0).
vladvana 0:23d1f73bf130 1889 */
vladvana 0:23d1f73bf130 1890 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
vladvana 0:23d1f73bf130 1891 {
vladvana 0:23d1f73bf130 1892 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
vladvana 0:23d1f73bf130 1893 uint32_t PreemptPriorityBits;
vladvana 0:23d1f73bf130 1894 uint32_t SubPriorityBits;
vladvana 0:23d1f73bf130 1895
vladvana 0:23d1f73bf130 1896 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
vladvana 0:23d1f73bf130 1897 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
vladvana 0:23d1f73bf130 1898
vladvana 0:23d1f73bf130 1899 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
vladvana 0:23d1f73bf130 1900 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
vladvana 0:23d1f73bf130 1901 }
vladvana 0:23d1f73bf130 1902
vladvana 0:23d1f73bf130 1903
vladvana 0:23d1f73bf130 1904 /** \brief System Reset
vladvana 0:23d1f73bf130 1905
vladvana 0:23d1f73bf130 1906 The function initiates a system reset request to reset the MCU.
vladvana 0:23d1f73bf130 1907 */
vladvana 0:23d1f73bf130 1908 __STATIC_INLINE void NVIC_SystemReset(void)
vladvana 0:23d1f73bf130 1909 {
vladvana 0:23d1f73bf130 1910 __DSB(); /* Ensure all outstanding memory accesses included
vladvana 0:23d1f73bf130 1911 buffered write are completed before reset */
vladvana 0:23d1f73bf130 1912 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
vladvana 0:23d1f73bf130 1913 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
vladvana 0:23d1f73bf130 1914 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
vladvana 0:23d1f73bf130 1915 __DSB(); /* Ensure completion of memory access */
vladvana 0:23d1f73bf130 1916 while(1) { __NOP(); } /* wait until reset */
vladvana 0:23d1f73bf130 1917 }
vladvana 0:23d1f73bf130 1918
vladvana 0:23d1f73bf130 1919 /*@} end of CMSIS_Core_NVICFunctions */
vladvana 0:23d1f73bf130 1920
vladvana 0:23d1f73bf130 1921
vladvana 0:23d1f73bf130 1922 /* ########################## FPU functions #################################### */
vladvana 0:23d1f73bf130 1923 /** \ingroup CMSIS_Core_FunctionInterface
vladvana 0:23d1f73bf130 1924 \defgroup CMSIS_Core_FpuFunctions FPU Functions
vladvana 0:23d1f73bf130 1925 \brief Function that provides FPU type.
vladvana 0:23d1f73bf130 1926 @{
vladvana 0:23d1f73bf130 1927 */
vladvana 0:23d1f73bf130 1928
vladvana 0:23d1f73bf130 1929 /**
vladvana 0:23d1f73bf130 1930 \fn uint32_t SCB_GetFPUType(void)
vladvana 0:23d1f73bf130 1931 \brief get FPU type
vladvana 0:23d1f73bf130 1932 \returns
vladvana 0:23d1f73bf130 1933 - \b 0: No FPU
vladvana 0:23d1f73bf130 1934 - \b 1: Single precision FPU
vladvana 0:23d1f73bf130 1935 - \b 2: Double + Single precision FPU
vladvana 0:23d1f73bf130 1936 */
vladvana 0:23d1f73bf130 1937 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
vladvana 0:23d1f73bf130 1938 {
vladvana 0:23d1f73bf130 1939 uint32_t mvfr0;
vladvana 0:23d1f73bf130 1940
vladvana 0:23d1f73bf130 1941 mvfr0 = SCB->MVFR0;
vladvana 0:23d1f73bf130 1942 if ((mvfr0 & 0x00000FF0UL) == 0x220UL) {
vladvana 0:23d1f73bf130 1943 return 2UL; // Double + Single precision FPU
vladvana 0:23d1f73bf130 1944 } else if ((mvfr0 & 0x00000FF0UL) == 0x020UL) {
vladvana 0:23d1f73bf130 1945 return 1UL; // Single precision FPU
vladvana 0:23d1f73bf130 1946 } else {
vladvana 0:23d1f73bf130 1947 return 0UL; // No FPU
vladvana 0:23d1f73bf130 1948 }
vladvana 0:23d1f73bf130 1949 }
vladvana 0:23d1f73bf130 1950
vladvana 0:23d1f73bf130 1951
vladvana 0:23d1f73bf130 1952 /*@} end of CMSIS_Core_FpuFunctions */
vladvana 0:23d1f73bf130 1953
vladvana 0:23d1f73bf130 1954
vladvana 0:23d1f73bf130 1955
vladvana 0:23d1f73bf130 1956 /* ########################## Cache functions #################################### */
vladvana 0:23d1f73bf130 1957 /** \ingroup CMSIS_Core_FunctionInterface
vladvana 0:23d1f73bf130 1958 \defgroup CMSIS_Core_CacheFunctions Cache Functions
vladvana 0:23d1f73bf130 1959 \brief Functions that configure Instruction and Data cache.
vladvana 0:23d1f73bf130 1960 @{
vladvana 0:23d1f73bf130 1961 */
vladvana 0:23d1f73bf130 1962
vladvana 0:23d1f73bf130 1963 /* Cache Size ID Register Macros */
vladvana 0:23d1f73bf130 1964 #define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
vladvana 0:23d1f73bf130 1965 #define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
vladvana 0:23d1f73bf130 1966 #define CCSIDR_LSSHIFT(x) (((x) & SCB_CCSIDR_LINESIZE_Msk ) /*>> SCB_CCSIDR_LINESIZE_Pos*/ )
vladvana 0:23d1f73bf130 1967
vladvana 0:23d1f73bf130 1968
vladvana 0:23d1f73bf130 1969 /** \brief Enable I-Cache
vladvana 0:23d1f73bf130 1970
vladvana 0:23d1f73bf130 1971 The function turns on I-Cache
vladvana 0:23d1f73bf130 1972 */
vladvana 0:23d1f73bf130 1973 __STATIC_INLINE void SCB_EnableICache (void)
vladvana 0:23d1f73bf130 1974 {
vladvana 0:23d1f73bf130 1975 #if (__ICACHE_PRESENT == 1)
vladvana 0:23d1f73bf130 1976 __DSB();
vladvana 0:23d1f73bf130 1977 __ISB();
vladvana 0:23d1f73bf130 1978 SCB->ICIALLU = 0UL; // invalidate I-Cache
vladvana 0:23d1f73bf130 1979 SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; // enable I-Cache
vladvana 0:23d1f73bf130 1980 __DSB();
vladvana 0:23d1f73bf130 1981 __ISB();
vladvana 0:23d1f73bf130 1982 #endif
vladvana 0:23d1f73bf130 1983 }
vladvana 0:23d1f73bf130 1984
vladvana 0:23d1f73bf130 1985
vladvana 0:23d1f73bf130 1986 /** \brief Disable I-Cache
vladvana 0:23d1f73bf130 1987
vladvana 0:23d1f73bf130 1988 The function turns off I-Cache
vladvana 0:23d1f73bf130 1989 */
vladvana 0:23d1f73bf130 1990 __STATIC_INLINE void SCB_DisableICache (void)
vladvana 0:23d1f73bf130 1991 {
vladvana 0:23d1f73bf130 1992 #if (__ICACHE_PRESENT == 1)
vladvana 0:23d1f73bf130 1993 __DSB();
vladvana 0:23d1f73bf130 1994 __ISB();
vladvana 0:23d1f73bf130 1995 SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; // disable I-Cache
vladvana 0:23d1f73bf130 1996 SCB->ICIALLU = 0UL; // invalidate I-Cache
vladvana 0:23d1f73bf130 1997 __DSB();
vladvana 0:23d1f73bf130 1998 __ISB();
vladvana 0:23d1f73bf130 1999 #endif
vladvana 0:23d1f73bf130 2000 }
vladvana 0:23d1f73bf130 2001
vladvana 0:23d1f73bf130 2002
vladvana 0:23d1f73bf130 2003 /** \brief Invalidate I-Cache
vladvana 0:23d1f73bf130 2004
vladvana 0:23d1f73bf130 2005 The function invalidates I-Cache
vladvana 0:23d1f73bf130 2006 */
vladvana 0:23d1f73bf130 2007 __STATIC_INLINE void SCB_InvalidateICache (void)
vladvana 0:23d1f73bf130 2008 {
vladvana 0:23d1f73bf130 2009 #if (__ICACHE_PRESENT == 1)
vladvana 0:23d1f73bf130 2010 __DSB();
vladvana 0:23d1f73bf130 2011 __ISB();
vladvana 0:23d1f73bf130 2012 SCB->ICIALLU = 0UL;
vladvana 0:23d1f73bf130 2013 __DSB();
vladvana 0:23d1f73bf130 2014 __ISB();
vladvana 0:23d1f73bf130 2015 #endif
vladvana 0:23d1f73bf130 2016 }
vladvana 0:23d1f73bf130 2017
vladvana 0:23d1f73bf130 2018
vladvana 0:23d1f73bf130 2019 /** \brief Enable D-Cache
vladvana 0:23d1f73bf130 2020
vladvana 0:23d1f73bf130 2021 The function turns on D-Cache
vladvana 0:23d1f73bf130 2022 */
vladvana 0:23d1f73bf130 2023 __STATIC_INLINE void SCB_EnableDCache (void)
vladvana 0:23d1f73bf130 2024 {
vladvana 0:23d1f73bf130 2025 #if (__DCACHE_PRESENT == 1)
vladvana 0:23d1f73bf130 2026 uint32_t ccsidr, sshift, wshift, sw;
vladvana 0:23d1f73bf130 2027 uint32_t sets, ways;
vladvana 0:23d1f73bf130 2028
vladvana 0:23d1f73bf130 2029 SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache
vladvana 0:23d1f73bf130 2030 ccsidr = SCB->CCSIDR;
vladvana 0:23d1f73bf130 2031 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
vladvana 0:23d1f73bf130 2032 sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
vladvana 0:23d1f73bf130 2033 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
vladvana 0:23d1f73bf130 2034 wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
vladvana 0:23d1f73bf130 2035
vladvana 0:23d1f73bf130 2036 __DSB();
vladvana 0:23d1f73bf130 2037
vladvana 0:23d1f73bf130 2038 do { // invalidate D-Cache
vladvana 0:23d1f73bf130 2039 uint32_t tmpways = ways;
vladvana 0:23d1f73bf130 2040 do {
vladvana 0:23d1f73bf130 2041 sw = ((tmpways << wshift) | (sets << sshift));
vladvana 0:23d1f73bf130 2042 SCB->DCISW = sw;
vladvana 0:23d1f73bf130 2043 } while(tmpways--);
vladvana 0:23d1f73bf130 2044 } while(sets--);
vladvana 0:23d1f73bf130 2045 __DSB();
vladvana 0:23d1f73bf130 2046
vladvana 0:23d1f73bf130 2047 SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; // enable D-Cache
vladvana 0:23d1f73bf130 2048
vladvana 0:23d1f73bf130 2049 __DSB();
vladvana 0:23d1f73bf130 2050 __ISB();
vladvana 0:23d1f73bf130 2051 #endif
vladvana 0:23d1f73bf130 2052 }
vladvana 0:23d1f73bf130 2053
vladvana 0:23d1f73bf130 2054
vladvana 0:23d1f73bf130 2055 /** \brief Disable D-Cache
vladvana 0:23d1f73bf130 2056
vladvana 0:23d1f73bf130 2057 The function turns off D-Cache
vladvana 0:23d1f73bf130 2058 */
vladvana 0:23d1f73bf130 2059 __STATIC_INLINE void SCB_DisableDCache (void)
vladvana 0:23d1f73bf130 2060 {
vladvana 0:23d1f73bf130 2061 #if (__DCACHE_PRESENT == 1)
vladvana 0:23d1f73bf130 2062 uint32_t ccsidr, sshift, wshift, sw;
vladvana 0:23d1f73bf130 2063 uint32_t sets, ways;
vladvana 0:23d1f73bf130 2064
vladvana 0:23d1f73bf130 2065 SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache
vladvana 0:23d1f73bf130 2066 ccsidr = SCB->CCSIDR;
vladvana 0:23d1f73bf130 2067 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
vladvana 0:23d1f73bf130 2068 sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
vladvana 0:23d1f73bf130 2069 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
vladvana 0:23d1f73bf130 2070 wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
vladvana 0:23d1f73bf130 2071
vladvana 0:23d1f73bf130 2072 __DSB();
vladvana 0:23d1f73bf130 2073
vladvana 0:23d1f73bf130 2074 SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; // disable D-Cache
vladvana 0:23d1f73bf130 2075
vladvana 0:23d1f73bf130 2076 do { // clean & invalidate D-Cache
vladvana 0:23d1f73bf130 2077 uint32_t tmpways = ways;
vladvana 0:23d1f73bf130 2078 do {
vladvana 0:23d1f73bf130 2079 sw = ((tmpways << wshift) | (sets << sshift));
vladvana 0:23d1f73bf130 2080 SCB->DCCISW = sw;
vladvana 0:23d1f73bf130 2081 } while(tmpways--);
vladvana 0:23d1f73bf130 2082 } while(sets--);
vladvana 0:23d1f73bf130 2083
vladvana 0:23d1f73bf130 2084
vladvana 0:23d1f73bf130 2085 __DSB();
vladvana 0:23d1f73bf130 2086 __ISB();
vladvana 0:23d1f73bf130 2087 #endif
vladvana 0:23d1f73bf130 2088 }
vladvana 0:23d1f73bf130 2089
vladvana 0:23d1f73bf130 2090
vladvana 0:23d1f73bf130 2091 /** \brief Invalidate D-Cache
vladvana 0:23d1f73bf130 2092
vladvana 0:23d1f73bf130 2093 The function invalidates D-Cache
vladvana 0:23d1f73bf130 2094 */
vladvana 0:23d1f73bf130 2095 __STATIC_INLINE void SCB_InvalidateDCache (void)
vladvana 0:23d1f73bf130 2096 {
vladvana 0:23d1f73bf130 2097 #if (__DCACHE_PRESENT == 1)
vladvana 0:23d1f73bf130 2098 uint32_t ccsidr, sshift, wshift, sw;
vladvana 0:23d1f73bf130 2099 uint32_t sets, ways;
vladvana 0:23d1f73bf130 2100
vladvana 0:23d1f73bf130 2101 SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache
vladvana 0:23d1f73bf130 2102 ccsidr = SCB->CCSIDR;
vladvana 0:23d1f73bf130 2103 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
vladvana 0:23d1f73bf130 2104 sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
vladvana 0:23d1f73bf130 2105 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
vladvana 0:23d1f73bf130 2106 wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
vladvana 0:23d1f73bf130 2107
vladvana 0:23d1f73bf130 2108 __DSB();
vladvana 0:23d1f73bf130 2109
vladvana 0:23d1f73bf130 2110 do { // invalidate D-Cache
vladvana 0:23d1f73bf130 2111 uint32_t tmpways = ways;
vladvana 0:23d1f73bf130 2112 do {
vladvana 0:23d1f73bf130 2113 sw = ((tmpways << wshift) | (sets << sshift));
vladvana 0:23d1f73bf130 2114 SCB->DCISW = sw;
vladvana 0:23d1f73bf130 2115 } while(tmpways--);
vladvana 0:23d1f73bf130 2116 } while(sets--);
vladvana 0:23d1f73bf130 2117
vladvana 0:23d1f73bf130 2118 __DSB();
vladvana 0:23d1f73bf130 2119 __ISB();
vladvana 0:23d1f73bf130 2120 #endif
vladvana 0:23d1f73bf130 2121 }
vladvana 0:23d1f73bf130 2122
vladvana 0:23d1f73bf130 2123
vladvana 0:23d1f73bf130 2124 /** \brief Clean D-Cache
vladvana 0:23d1f73bf130 2125
vladvana 0:23d1f73bf130 2126 The function cleans D-Cache
vladvana 0:23d1f73bf130 2127 */
vladvana 0:23d1f73bf130 2128 __STATIC_INLINE void SCB_CleanDCache (void)
vladvana 0:23d1f73bf130 2129 {
vladvana 0:23d1f73bf130 2130 #if (__DCACHE_PRESENT == 1)
vladvana 0:23d1f73bf130 2131 uint32_t ccsidr, sshift, wshift, sw;
vladvana 0:23d1f73bf130 2132 uint32_t sets, ways;
vladvana 0:23d1f73bf130 2133
vladvana 0:23d1f73bf130 2134 SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache
vladvana 0:23d1f73bf130 2135 ccsidr = SCB->CCSIDR;
vladvana 0:23d1f73bf130 2136 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
vladvana 0:23d1f73bf130 2137 sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
vladvana 0:23d1f73bf130 2138 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
vladvana 0:23d1f73bf130 2139 wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
vladvana 0:23d1f73bf130 2140
vladvana 0:23d1f73bf130 2141 __DSB();
vladvana 0:23d1f73bf130 2142
vladvana 0:23d1f73bf130 2143 do { // clean D-Cache
vladvana 0:23d1f73bf130 2144 uint32_t tmpways = ways;
vladvana 0:23d1f73bf130 2145 do {
vladvana 0:23d1f73bf130 2146 sw = ((tmpways << wshift) | (sets << sshift));
vladvana 0:23d1f73bf130 2147 SCB->DCCSW = sw;
vladvana 0:23d1f73bf130 2148 } while(tmpways--);
vladvana 0:23d1f73bf130 2149 } while(sets--);
vladvana 0:23d1f73bf130 2150
vladvana 0:23d1f73bf130 2151 __DSB();
vladvana 0:23d1f73bf130 2152 __ISB();
vladvana 0:23d1f73bf130 2153 #endif
vladvana 0:23d1f73bf130 2154 }
vladvana 0:23d1f73bf130 2155
vladvana 0:23d1f73bf130 2156
vladvana 0:23d1f73bf130 2157 /** \brief Clean & Invalidate D-Cache
vladvana 0:23d1f73bf130 2158
vladvana 0:23d1f73bf130 2159 The function cleans and Invalidates D-Cache
vladvana 0:23d1f73bf130 2160 */
vladvana 0:23d1f73bf130 2161 __STATIC_INLINE void SCB_CleanInvalidateDCache (void)
vladvana 0:23d1f73bf130 2162 {
vladvana 0:23d1f73bf130 2163 #if (__DCACHE_PRESENT == 1)
vladvana 0:23d1f73bf130 2164 uint32_t ccsidr, sshift, wshift, sw;
vladvana 0:23d1f73bf130 2165 uint32_t sets, ways;
vladvana 0:23d1f73bf130 2166
vladvana 0:23d1f73bf130 2167 SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache
vladvana 0:23d1f73bf130 2168 ccsidr = SCB->CCSIDR;
vladvana 0:23d1f73bf130 2169 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
vladvana 0:23d1f73bf130 2170 sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
vladvana 0:23d1f73bf130 2171 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
vladvana 0:23d1f73bf130 2172 wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
vladvana 0:23d1f73bf130 2173
vladvana 0:23d1f73bf130 2174 __DSB();
vladvana 0:23d1f73bf130 2175
vladvana 0:23d1f73bf130 2176 do { // clean & invalidate D-Cache
vladvana 0:23d1f73bf130 2177 uint32_t tmpways = ways;
vladvana 0:23d1f73bf130 2178 do {
vladvana 0:23d1f73bf130 2179 sw = ((tmpways << wshift) | (sets << sshift));
vladvana 0:23d1f73bf130 2180 SCB->DCCISW = sw;
vladvana 0:23d1f73bf130 2181 } while(tmpways--);
vladvana 0:23d1f73bf130 2182 } while(sets--);
vladvana 0:23d1f73bf130 2183
vladvana 0:23d1f73bf130 2184 __DSB();
vladvana 0:23d1f73bf130 2185 __ISB();
vladvana 0:23d1f73bf130 2186 #endif
vladvana 0:23d1f73bf130 2187 }
vladvana 0:23d1f73bf130 2188
vladvana 0:23d1f73bf130 2189
vladvana 0:23d1f73bf130 2190 /**
vladvana 0:23d1f73bf130 2191 \fn void SCB_InvalidateDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
vladvana 0:23d1f73bf130 2192 \brief D-Cache Invalidate by address
vladvana 0:23d1f73bf130 2193 \param[in] addr address (aligned to 32-byte boundary)
vladvana 0:23d1f73bf130 2194 \param[in] dsize size of memory block (in number of bytes)
vladvana 0:23d1f73bf130 2195 */
vladvana 0:23d1f73bf130 2196 __STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
vladvana 0:23d1f73bf130 2197 {
vladvana 0:23d1f73bf130 2198 #if (__DCACHE_PRESENT == 1)
vladvana 0:23d1f73bf130 2199 int32_t op_size = dsize;
vladvana 0:23d1f73bf130 2200 uint32_t op_addr = (uint32_t)addr;
vladvana 0:23d1f73bf130 2201 uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
vladvana 0:23d1f73bf130 2202
vladvana 0:23d1f73bf130 2203 __DSB();
vladvana 0:23d1f73bf130 2204
vladvana 0:23d1f73bf130 2205 while (op_size > 0) {
vladvana 0:23d1f73bf130 2206 SCB->DCIMVAC = op_addr;
vladvana 0:23d1f73bf130 2207 op_addr += linesize;
vladvana 0:23d1f73bf130 2208 op_size -= (int32_t)linesize;
vladvana 0:23d1f73bf130 2209 }
vladvana 0:23d1f73bf130 2210
vladvana 0:23d1f73bf130 2211 __DSB();
vladvana 0:23d1f73bf130 2212 __ISB();
vladvana 0:23d1f73bf130 2213 #endif
vladvana 0:23d1f73bf130 2214 }
vladvana 0:23d1f73bf130 2215
vladvana 0:23d1f73bf130 2216
vladvana 0:23d1f73bf130 2217 /**
vladvana 0:23d1f73bf130 2218 \fn void SCB_CleanDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
vladvana 0:23d1f73bf130 2219 \brief D-Cache Clean by address
vladvana 0:23d1f73bf130 2220 \param[in] addr address (aligned to 32-byte boundary)
vladvana 0:23d1f73bf130 2221 \param[in] dsize size of memory block (in number of bytes)
vladvana 0:23d1f73bf130 2222 */
vladvana 0:23d1f73bf130 2223 __STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
vladvana 0:23d1f73bf130 2224 {
vladvana 0:23d1f73bf130 2225 #if (__DCACHE_PRESENT == 1)
vladvana 0:23d1f73bf130 2226 int32_t op_size = dsize;
vladvana 0:23d1f73bf130 2227 uint32_t op_addr = (uint32_t) addr;
vladvana 0:23d1f73bf130 2228 uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
vladvana 0:23d1f73bf130 2229
vladvana 0:23d1f73bf130 2230 __DSB();
vladvana 0:23d1f73bf130 2231
vladvana 0:23d1f73bf130 2232 while (op_size > 0) {
vladvana 0:23d1f73bf130 2233 SCB->DCCMVAC = op_addr;
vladvana 0:23d1f73bf130 2234 op_addr += linesize;
vladvana 0:23d1f73bf130 2235 op_size -= (int32_t)linesize;
vladvana 0:23d1f73bf130 2236 }
vladvana 0:23d1f73bf130 2237
vladvana 0:23d1f73bf130 2238 __DSB();
vladvana 0:23d1f73bf130 2239 __ISB();
vladvana 0:23d1f73bf130 2240 #endif
vladvana 0:23d1f73bf130 2241 }
vladvana 0:23d1f73bf130 2242
vladvana 0:23d1f73bf130 2243
vladvana 0:23d1f73bf130 2244 /**
vladvana 0:23d1f73bf130 2245 \fn void SCB_CleanInvalidateDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
vladvana 0:23d1f73bf130 2246 \brief D-Cache Clean and Invalidate by address
vladvana 0:23d1f73bf130 2247 \param[in] addr address (aligned to 32-byte boundary)
vladvana 0:23d1f73bf130 2248 \param[in] dsize size of memory block (in number of bytes)
vladvana 0:23d1f73bf130 2249 */
vladvana 0:23d1f73bf130 2250 __STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
vladvana 0:23d1f73bf130 2251 {
vladvana 0:23d1f73bf130 2252 #if (__DCACHE_PRESENT == 1)
vladvana 0:23d1f73bf130 2253 int32_t op_size = dsize;
vladvana 0:23d1f73bf130 2254 uint32_t op_addr = (uint32_t) addr;
vladvana 0:23d1f73bf130 2255 uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
vladvana 0:23d1f73bf130 2256
vladvana 0:23d1f73bf130 2257 __DSB();
vladvana 0:23d1f73bf130 2258
vladvana 0:23d1f73bf130 2259 while (op_size > 0) {
vladvana 0:23d1f73bf130 2260 SCB->DCCIMVAC = op_addr;
vladvana 0:23d1f73bf130 2261 op_addr += linesize;
vladvana 0:23d1f73bf130 2262 op_size -= (int32_t)linesize;
vladvana 0:23d1f73bf130 2263 }
vladvana 0:23d1f73bf130 2264
vladvana 0:23d1f73bf130 2265 __DSB();
vladvana 0:23d1f73bf130 2266 __ISB();
vladvana 0:23d1f73bf130 2267 #endif
vladvana 0:23d1f73bf130 2268 }
vladvana 0:23d1f73bf130 2269
vladvana 0:23d1f73bf130 2270
vladvana 0:23d1f73bf130 2271 /*@} end of CMSIS_Core_CacheFunctions */
vladvana 0:23d1f73bf130 2272
vladvana 0:23d1f73bf130 2273
vladvana 0:23d1f73bf130 2274
vladvana 0:23d1f73bf130 2275 /* ################################## SysTick function ############################################ */
vladvana 0:23d1f73bf130 2276 /** \ingroup CMSIS_Core_FunctionInterface
vladvana 0:23d1f73bf130 2277 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
vladvana 0:23d1f73bf130 2278 \brief Functions that configure the System.
vladvana 0:23d1f73bf130 2279 @{
vladvana 0:23d1f73bf130 2280 */
vladvana 0:23d1f73bf130 2281
vladvana 0:23d1f73bf130 2282 #if (__Vendor_SysTickConfig == 0)
vladvana 0:23d1f73bf130 2283
vladvana 0:23d1f73bf130 2284 /** \brief System Tick Configuration
vladvana 0:23d1f73bf130 2285
vladvana 0:23d1f73bf130 2286 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
vladvana 0:23d1f73bf130 2287 Counter is in free running mode to generate periodic interrupts.
vladvana 0:23d1f73bf130 2288
vladvana 0:23d1f73bf130 2289 \param [in] ticks Number of ticks between two interrupts.
vladvana 0:23d1f73bf130 2290
vladvana 0:23d1f73bf130 2291 \return 0 Function succeeded.
vladvana 0:23d1f73bf130 2292 \return 1 Function failed.
vladvana 0:23d1f73bf130 2293
vladvana 0:23d1f73bf130 2294 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
vladvana 0:23d1f73bf130 2295 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
vladvana 0:23d1f73bf130 2296 must contain a vendor-specific implementation of this function.
vladvana 0:23d1f73bf130 2297
vladvana 0:23d1f73bf130 2298 */
vladvana 0:23d1f73bf130 2299 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
vladvana 0:23d1f73bf130 2300 {
vladvana 0:23d1f73bf130 2301 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
vladvana 0:23d1f73bf130 2302
vladvana 0:23d1f73bf130 2303 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
vladvana 0:23d1f73bf130 2304 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
vladvana 0:23d1f73bf130 2305 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
vladvana 0:23d1f73bf130 2306 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
vladvana 0:23d1f73bf130 2307 SysTick_CTRL_TICKINT_Msk |
vladvana 0:23d1f73bf130 2308 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
vladvana 0:23d1f73bf130 2309 return (0UL); /* Function successful */
vladvana 0:23d1f73bf130 2310 }
vladvana 0:23d1f73bf130 2311
vladvana 0:23d1f73bf130 2312 #endif
vladvana 0:23d1f73bf130 2313
vladvana 0:23d1f73bf130 2314 /*@} end of CMSIS_Core_SysTickFunctions */
vladvana 0:23d1f73bf130 2315
vladvana 0:23d1f73bf130 2316
vladvana 0:23d1f73bf130 2317
vladvana 0:23d1f73bf130 2318 /* ##################################### Debug In/Output function ########################################### */
vladvana 0:23d1f73bf130 2319 /** \ingroup CMSIS_Core_FunctionInterface
vladvana 0:23d1f73bf130 2320 \defgroup CMSIS_core_DebugFunctions ITM Functions
vladvana 0:23d1f73bf130 2321 \brief Functions that access the ITM debug interface.
vladvana 0:23d1f73bf130 2322 @{
vladvana 0:23d1f73bf130 2323 */
vladvana 0:23d1f73bf130 2324
vladvana 0:23d1f73bf130 2325 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
vladvana 0:23d1f73bf130 2326 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
vladvana 0:23d1f73bf130 2327
vladvana 0:23d1f73bf130 2328
vladvana 0:23d1f73bf130 2329 /** \brief ITM Send Character
vladvana 0:23d1f73bf130 2330
vladvana 0:23d1f73bf130 2331 The function transmits a character via the ITM channel 0, and
vladvana 0:23d1f73bf130 2332 \li Just returns when no debugger is connected that has booked the output.
vladvana 0:23d1f73bf130 2333 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
vladvana 0:23d1f73bf130 2334
vladvana 0:23d1f73bf130 2335 \param [in] ch Character to transmit.
vladvana 0:23d1f73bf130 2336
vladvana 0:23d1f73bf130 2337 \returns Character to transmit.
vladvana 0:23d1f73bf130 2338 */
vladvana 0:23d1f73bf130 2339 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
vladvana 0:23d1f73bf130 2340 {
vladvana 0:23d1f73bf130 2341 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
vladvana 0:23d1f73bf130 2342 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
vladvana 0:23d1f73bf130 2343 {
vladvana 0:23d1f73bf130 2344 while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
vladvana 0:23d1f73bf130 2345 ITM->PORT[0].u8 = (uint8_t)ch;
vladvana 0:23d1f73bf130 2346 }
vladvana 0:23d1f73bf130 2347 return (ch);
vladvana 0:23d1f73bf130 2348 }
vladvana 0:23d1f73bf130 2349
vladvana 0:23d1f73bf130 2350
vladvana 0:23d1f73bf130 2351 /** \brief ITM Receive Character
vladvana 0:23d1f73bf130 2352
vladvana 0:23d1f73bf130 2353 The function inputs a character via the external variable \ref ITM_RxBuffer.
vladvana 0:23d1f73bf130 2354
vladvana 0:23d1f73bf130 2355 \return Received character.
vladvana 0:23d1f73bf130 2356 \return -1 No character pending.
vladvana 0:23d1f73bf130 2357 */
vladvana 0:23d1f73bf130 2358 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
vladvana 0:23d1f73bf130 2359 int32_t ch = -1; /* no character available */
vladvana 0:23d1f73bf130 2360
vladvana 0:23d1f73bf130 2361 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
vladvana 0:23d1f73bf130 2362 ch = ITM_RxBuffer;
vladvana 0:23d1f73bf130 2363 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
vladvana 0:23d1f73bf130 2364 }
vladvana 0:23d1f73bf130 2365
vladvana 0:23d1f73bf130 2366 return (ch);
vladvana 0:23d1f73bf130 2367 }
vladvana 0:23d1f73bf130 2368
vladvana 0:23d1f73bf130 2369
vladvana 0:23d1f73bf130 2370 /** \brief ITM Check Character
vladvana 0:23d1f73bf130 2371
vladvana 0:23d1f73bf130 2372 The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
vladvana 0:23d1f73bf130 2373
vladvana 0:23d1f73bf130 2374 \return 0 No character available.
vladvana 0:23d1f73bf130 2375 \return 1 Character available.
vladvana 0:23d1f73bf130 2376 */
vladvana 0:23d1f73bf130 2377 __STATIC_INLINE int32_t ITM_CheckChar (void) {
vladvana 0:23d1f73bf130 2378
vladvana 0:23d1f73bf130 2379 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
vladvana 0:23d1f73bf130 2380 return (0); /* no character available */
vladvana 0:23d1f73bf130 2381 } else {
vladvana 0:23d1f73bf130 2382 return (1); /* character available */
vladvana 0:23d1f73bf130 2383 }
vladvana 0:23d1f73bf130 2384 }
vladvana 0:23d1f73bf130 2385
vladvana 0:23d1f73bf130 2386 /*@} end of CMSIS_core_DebugFunctions */
vladvana 0:23d1f73bf130 2387
vladvana 0:23d1f73bf130 2388
vladvana 0:23d1f73bf130 2389
vladvana 0:23d1f73bf130 2390
vladvana 0:23d1f73bf130 2391 #ifdef __cplusplus
vladvana 0:23d1f73bf130 2392 }
vladvana 0:23d1f73bf130 2393 #endif
vladvana 0:23d1f73bf130 2394
vladvana 0:23d1f73bf130 2395 #endif /* __CORE_CM7_H_DEPENDANT */
vladvana 0:23d1f73bf130 2396
vladvana 0:23d1f73bf130 2397 #endif /* __CMSIS_GENERIC */