Vladimir Vana / mbed

pro vyuku PSS v Jecne

TARGET_NUCLEO_F103RB/core_cm3.h@0:23d1f73bf130, 2017-09-24 (annotated)

Committer:
vladvana
Date:
Sun Sep 24 12:31:52 2017 +0000
Revision:
0:23d1f73bf130
podklady pro cviceni z PSS

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vladvana 0:23d1f73bf130 1 /**************************************************************************//**
vladvana 0:23d1f73bf130 2 * @file core_cm3.h
vladvana 0:23d1f73bf130 3 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
vladvana 0:23d1f73bf130 4 * @version V4.10
vladvana 0:23d1f73bf130 5 * @date 18. March 2015
vladvana 0:23d1f73bf130 6 *
vladvana 0:23d1f73bf130 7 * @note
vladvana 0:23d1f73bf130 8 *
vladvana 0:23d1f73bf130 9 ******************************************************************************/
vladvana 0:23d1f73bf130 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
vladvana 0:23d1f73bf130 11
vladvana 0:23d1f73bf130 12 All rights reserved.
vladvana 0:23d1f73bf130 13 Redistribution and use in source and binary forms, with or without
vladvana 0:23d1f73bf130 14 modification, are permitted provided that the following conditions are met:
vladvana 0:23d1f73bf130 15 - Redistributions of source code must retain the above copyright
vladvana 0:23d1f73bf130 16 notice, this list of conditions and the following disclaimer.
vladvana 0:23d1f73bf130 17 - Redistributions in binary form must reproduce the above copyright
vladvana 0:23d1f73bf130 18 notice, this list of conditions and the following disclaimer in the
vladvana 0:23d1f73bf130 19 documentation and/or other materials provided with the distribution.
vladvana 0:23d1f73bf130 20 - Neither the name of ARM nor the names of its contributors may be used
vladvana 0:23d1f73bf130 21 to endorse or promote products derived from this software without
vladvana 0:23d1f73bf130 22 specific prior written permission.
vladvana 0:23d1f73bf130 23 *
vladvana 0:23d1f73bf130 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
vladvana 0:23d1f73bf130 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
vladvana 0:23d1f73bf130 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
vladvana 0:23d1f73bf130 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
vladvana 0:23d1f73bf130 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
vladvana 0:23d1f73bf130 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
vladvana 0:23d1f73bf130 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
vladvana 0:23d1f73bf130 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
vladvana 0:23d1f73bf130 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
vladvana 0:23d1f73bf130 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
vladvana 0:23d1f73bf130 34 POSSIBILITY OF SUCH DAMAGE.
vladvana 0:23d1f73bf130 35 ---------------------------------------------------------------------------*/
vladvana 0:23d1f73bf130 36
vladvana 0:23d1f73bf130 37
vladvana 0:23d1f73bf130 38 #if defined ( __ICCARM__ )
vladvana 0:23d1f73bf130 39 #pragma system_include /* treat file as system include file for MISRA check */
vladvana 0:23d1f73bf130 40 #endif
vladvana 0:23d1f73bf130 41
vladvana 0:23d1f73bf130 42 #ifndef __CORE_CM3_H_GENERIC
vladvana 0:23d1f73bf130 43 #define __CORE_CM3_H_GENERIC
vladvana 0:23d1f73bf130 44
vladvana 0:23d1f73bf130 45 #ifdef __cplusplus
vladvana 0:23d1f73bf130 46 extern "C" {
vladvana 0:23d1f73bf130 47 #endif
vladvana 0:23d1f73bf130 48
vladvana 0:23d1f73bf130 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
vladvana 0:23d1f73bf130 50 CMSIS violates the following MISRA-C:2004 rules:
vladvana 0:23d1f73bf130 51
vladvana 0:23d1f73bf130 52 \li Required Rule 8.5, object/function definition in header file.<br>
vladvana 0:23d1f73bf130 53 Function definitions in header files are used to allow 'inlining'.
vladvana 0:23d1f73bf130 54
vladvana 0:23d1f73bf130 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
vladvana 0:23d1f73bf130 56 Unions are used for effective representation of core registers.
vladvana 0:23d1f73bf130 57
vladvana 0:23d1f73bf130 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
vladvana 0:23d1f73bf130 59 Function-like macros are used to allow more efficient code.
vladvana 0:23d1f73bf130 60 */
vladvana 0:23d1f73bf130 61
vladvana 0:23d1f73bf130 62
vladvana 0:23d1f73bf130 63 /*******************************************************************************
vladvana 0:23d1f73bf130 64 * CMSIS definitions
vladvana 0:23d1f73bf130 65 ******************************************************************************/
vladvana 0:23d1f73bf130 66 /** \ingroup Cortex_M3
vladvana 0:23d1f73bf130 67 @{
vladvana 0:23d1f73bf130 68 */
vladvana 0:23d1f73bf130 69
vladvana 0:23d1f73bf130 70 /* CMSIS CM3 definitions */
vladvana 0:23d1f73bf130 71 #define __CM3_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
vladvana 0:23d1f73bf130 72 #define __CM3_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
vladvana 0:23d1f73bf130 73 #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \
vladvana 0:23d1f73bf130 74 __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
vladvana 0:23d1f73bf130 75
vladvana 0:23d1f73bf130 76 #define __CORTEX_M (0x03) /*!< Cortex-M Core */
vladvana 0:23d1f73bf130 77
vladvana 0:23d1f73bf130 78
vladvana 0:23d1f73bf130 79 #if defined ( __CC_ARM )
vladvana 0:23d1f73bf130 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
vladvana 0:23d1f73bf130 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
vladvana 0:23d1f73bf130 82 #define __STATIC_INLINE static __inline
vladvana 0:23d1f73bf130 83
vladvana 0:23d1f73bf130 84 #elif defined ( __GNUC__ )
vladvana 0:23d1f73bf130 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
vladvana 0:23d1f73bf130 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
vladvana 0:23d1f73bf130 87 #define __STATIC_INLINE static inline
vladvana 0:23d1f73bf130 88
vladvana 0:23d1f73bf130 89 #elif defined ( __ICCARM__ )
vladvana 0:23d1f73bf130 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
vladvana 0:23d1f73bf130 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
vladvana 0:23d1f73bf130 92 #define __STATIC_INLINE static inline
vladvana 0:23d1f73bf130 93
vladvana 0:23d1f73bf130 94 #elif defined ( __TMS470__ )
vladvana 0:23d1f73bf130 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
vladvana 0:23d1f73bf130 96 #define __STATIC_INLINE static inline
vladvana 0:23d1f73bf130 97
vladvana 0:23d1f73bf130 98 #elif defined ( __TASKING__ )
vladvana 0:23d1f73bf130 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
vladvana 0:23d1f73bf130 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
vladvana 0:23d1f73bf130 101 #define __STATIC_INLINE static inline
vladvana 0:23d1f73bf130 102
vladvana 0:23d1f73bf130 103 #elif defined ( __CSMC__ )
vladvana 0:23d1f73bf130 104 #define __packed
vladvana 0:23d1f73bf130 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
vladvana 0:23d1f73bf130 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
vladvana 0:23d1f73bf130 107 #define __STATIC_INLINE static inline
vladvana 0:23d1f73bf130 108
vladvana 0:23d1f73bf130 109 #endif
vladvana 0:23d1f73bf130 110
vladvana 0:23d1f73bf130 111 /** __FPU_USED indicates whether an FPU is used or not.
vladvana 0:23d1f73bf130 112 This core does not support an FPU at all
vladvana 0:23d1f73bf130 113 */
vladvana 0:23d1f73bf130 114 #define __FPU_USED 0
vladvana 0:23d1f73bf130 115
vladvana 0:23d1f73bf130 116 #if defined ( __CC_ARM )
vladvana 0:23d1f73bf130 117 #if defined __TARGET_FPU_VFP
vladvana 0:23d1f73bf130 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
vladvana 0:23d1f73bf130 119 #endif
vladvana 0:23d1f73bf130 120
vladvana 0:23d1f73bf130 121 #elif defined ( __GNUC__ )
vladvana 0:23d1f73bf130 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
vladvana 0:23d1f73bf130 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
vladvana 0:23d1f73bf130 124 #endif
vladvana 0:23d1f73bf130 125
vladvana 0:23d1f73bf130 126 #elif defined ( __ICCARM__ )
vladvana 0:23d1f73bf130 127 #if defined __ARMVFP__
vladvana 0:23d1f73bf130 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
vladvana 0:23d1f73bf130 129 #endif
vladvana 0:23d1f73bf130 130
vladvana 0:23d1f73bf130 131 #elif defined ( __TMS470__ )
vladvana 0:23d1f73bf130 132 #if defined __TI__VFP_SUPPORT____
vladvana 0:23d1f73bf130 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
vladvana 0:23d1f73bf130 134 #endif
vladvana 0:23d1f73bf130 135
vladvana 0:23d1f73bf130 136 #elif defined ( __TASKING__ )
vladvana 0:23d1f73bf130 137 #if defined __FPU_VFP__
vladvana 0:23d1f73bf130 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
vladvana 0:23d1f73bf130 139 #endif
vladvana 0:23d1f73bf130 140
vladvana 0:23d1f73bf130 141 #elif defined ( __CSMC__ ) /* Cosmic */
vladvana 0:23d1f73bf130 142 #if ( __CSMC__ & 0x400) // FPU present for parser
vladvana 0:23d1f73bf130 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
vladvana 0:23d1f73bf130 144 #endif
vladvana 0:23d1f73bf130 145 #endif
vladvana 0:23d1f73bf130 146
vladvana 0:23d1f73bf130 147 #include <stdint.h> /* standard types definitions */
vladvana 0:23d1f73bf130 148 #include <core_cmInstr.h> /* Core Instruction Access */
vladvana 0:23d1f73bf130 149 #include <core_cmFunc.h> /* Core Function Access */
vladvana 0:23d1f73bf130 150
vladvana 0:23d1f73bf130 151 #ifdef __cplusplus
vladvana 0:23d1f73bf130 152 }
vladvana 0:23d1f73bf130 153 #endif
vladvana 0:23d1f73bf130 154
vladvana 0:23d1f73bf130 155 #endif /* __CORE_CM3_H_GENERIC */
vladvana 0:23d1f73bf130 156
vladvana 0:23d1f73bf130 157 #ifndef __CMSIS_GENERIC
vladvana 0:23d1f73bf130 158
vladvana 0:23d1f73bf130 159 #ifndef __CORE_CM3_H_DEPENDANT
vladvana 0:23d1f73bf130 160 #define __CORE_CM3_H_DEPENDANT
vladvana 0:23d1f73bf130 161
vladvana 0:23d1f73bf130 162 #ifdef __cplusplus
vladvana 0:23d1f73bf130 163 extern "C" {
vladvana 0:23d1f73bf130 164 #endif
vladvana 0:23d1f73bf130 165
vladvana 0:23d1f73bf130 166 /* check device defines and use defaults */
vladvana 0:23d1f73bf130 167 #if defined __CHECK_DEVICE_DEFINES
vladvana 0:23d1f73bf130 168 #ifndef __CM3_REV
vladvana 0:23d1f73bf130 169 #define __CM3_REV 0x0200
vladvana 0:23d1f73bf130 170 #warning "__CM3_REV not defined in device header file; using default!"
vladvana 0:23d1f73bf130 171 #endif
vladvana 0:23d1f73bf130 172
vladvana 0:23d1f73bf130 173 #ifndef __MPU_PRESENT
vladvana 0:23d1f73bf130 174 #define __MPU_PRESENT 0
vladvana 0:23d1f73bf130 175 #warning "__MPU_PRESENT not defined in device header file; using default!"
vladvana 0:23d1f73bf130 176 #endif
vladvana 0:23d1f73bf130 177
vladvana 0:23d1f73bf130 178 #ifndef __NVIC_PRIO_BITS
vladvana 0:23d1f73bf130 179 #define __NVIC_PRIO_BITS 4
vladvana 0:23d1f73bf130 180 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
vladvana 0:23d1f73bf130 181 #endif
vladvana 0:23d1f73bf130 182
vladvana 0:23d1f73bf130 183 #ifndef __Vendor_SysTickConfig
vladvana 0:23d1f73bf130 184 #define __Vendor_SysTickConfig 0
vladvana 0:23d1f73bf130 185 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
vladvana 0:23d1f73bf130 186 #endif
vladvana 0:23d1f73bf130 187 #endif
vladvana 0:23d1f73bf130 188
vladvana 0:23d1f73bf130 189 /* IO definitions (access restrictions to peripheral registers) */
vladvana 0:23d1f73bf130 190 /**
vladvana 0:23d1f73bf130 191 \defgroup CMSIS_glob_defs CMSIS Global Defines
vladvana 0:23d1f73bf130 192
vladvana 0:23d1f73bf130 193 <strong>IO Type Qualifiers</strong> are used
vladvana 0:23d1f73bf130 194 \li to specify the access to peripheral variables.
vladvana 0:23d1f73bf130 195 \li for automatic generation of peripheral register debug information.
vladvana 0:23d1f73bf130 196 */
vladvana 0:23d1f73bf130 197 #ifdef __cplusplus
vladvana 0:23d1f73bf130 198 #define __I volatile /*!< Defines 'read only' permissions */
vladvana 0:23d1f73bf130 199 #else
vladvana 0:23d1f73bf130 200 #define __I volatile const /*!< Defines 'read only' permissions */
vladvana 0:23d1f73bf130 201 #endif
vladvana 0:23d1f73bf130 202 #define __O volatile /*!< Defines 'write only' permissions */
vladvana 0:23d1f73bf130 203 #define __IO volatile /*!< Defines 'read / write' permissions */
vladvana 0:23d1f73bf130 204
vladvana 0:23d1f73bf130 205 /*@} end of group Cortex_M3 */
vladvana 0:23d1f73bf130 206
vladvana 0:23d1f73bf130 207
vladvana 0:23d1f73bf130 208
vladvana 0:23d1f73bf130 209 /*******************************************************************************
vladvana 0:23d1f73bf130 210 * Register Abstraction
vladvana 0:23d1f73bf130 211 Core Register contain:
vladvana 0:23d1f73bf130 212 - Core Register
vladvana 0:23d1f73bf130 213 - Core NVIC Register
vladvana 0:23d1f73bf130 214 - Core SCB Register
vladvana 0:23d1f73bf130 215 - Core SysTick Register
vladvana 0:23d1f73bf130 216 - Core Debug Register
vladvana 0:23d1f73bf130 217 - Core MPU Register
vladvana 0:23d1f73bf130 218 ******************************************************************************/
vladvana 0:23d1f73bf130 219 /** \defgroup CMSIS_core_register Defines and Type Definitions
vladvana 0:23d1f73bf130 220 \brief Type definitions and defines for Cortex-M processor based devices.
vladvana 0:23d1f73bf130 221 */
vladvana 0:23d1f73bf130 222
vladvana 0:23d1f73bf130 223 /** \ingroup CMSIS_core_register
vladvana 0:23d1f73bf130 224 \defgroup CMSIS_CORE Status and Control Registers
vladvana 0:23d1f73bf130 225 \brief Core Register type definitions.
vladvana 0:23d1f73bf130 226 @{
vladvana 0:23d1f73bf130 227 */
vladvana 0:23d1f73bf130 228
vladvana 0:23d1f73bf130 229 /** \brief Union type to access the Application Program Status Register (APSR).
vladvana 0:23d1f73bf130 230 */
vladvana 0:23d1f73bf130 231 typedef union
vladvana 0:23d1f73bf130 232 {
vladvana 0:23d1f73bf130 233 struct
vladvana 0:23d1f73bf130 234 {
vladvana 0:23d1f73bf130 235 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
vladvana 0:23d1f73bf130 236 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
vladvana 0:23d1f73bf130 237 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
vladvana 0:23d1f73bf130 238 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
vladvana 0:23d1f73bf130 239 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
vladvana 0:23d1f73bf130 240 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
vladvana 0:23d1f73bf130 241 } b; /*!< Structure used for bit access */
vladvana 0:23d1f73bf130 242 uint32_t w; /*!< Type used for word access */
vladvana 0:23d1f73bf130 243 } APSR_Type;
vladvana 0:23d1f73bf130 244
vladvana 0:23d1f73bf130 245 /* APSR Register Definitions */
vladvana 0:23d1f73bf130 246 #define APSR_N_Pos 31 /*!< APSR: N Position */
vladvana 0:23d1f73bf130 247 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
vladvana 0:23d1f73bf130 248
vladvana 0:23d1f73bf130 249 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
vladvana 0:23d1f73bf130 250 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
vladvana 0:23d1f73bf130 251
vladvana 0:23d1f73bf130 252 #define APSR_C_Pos 29 /*!< APSR: C Position */
vladvana 0:23d1f73bf130 253 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
vladvana 0:23d1f73bf130 254
vladvana 0:23d1f73bf130 255 #define APSR_V_Pos 28 /*!< APSR: V Position */
vladvana 0:23d1f73bf130 256 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
vladvana 0:23d1f73bf130 257
vladvana 0:23d1f73bf130 258 #define APSR_Q_Pos 27 /*!< APSR: Q Position */
vladvana 0:23d1f73bf130 259 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
vladvana 0:23d1f73bf130 260
vladvana 0:23d1f73bf130 261
vladvana 0:23d1f73bf130 262 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
vladvana 0:23d1f73bf130 263 */
vladvana 0:23d1f73bf130 264 typedef union
vladvana 0:23d1f73bf130 265 {
vladvana 0:23d1f73bf130 266 struct
vladvana 0:23d1f73bf130 267 {
vladvana 0:23d1f73bf130 268 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
vladvana 0:23d1f73bf130 269 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
vladvana 0:23d1f73bf130 270 } b; /*!< Structure used for bit access */
vladvana 0:23d1f73bf130 271 uint32_t w; /*!< Type used for word access */
vladvana 0:23d1f73bf130 272 } IPSR_Type;
vladvana 0:23d1f73bf130 273
vladvana 0:23d1f73bf130 274 /* IPSR Register Definitions */
vladvana 0:23d1f73bf130 275 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
vladvana 0:23d1f73bf130 276 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
vladvana 0:23d1f73bf130 277
vladvana 0:23d1f73bf130 278
vladvana 0:23d1f73bf130 279 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
vladvana 0:23d1f73bf130 280 */
vladvana 0:23d1f73bf130 281 typedef union
vladvana 0:23d1f73bf130 282 {
vladvana 0:23d1f73bf130 283 struct
vladvana 0:23d1f73bf130 284 {
vladvana 0:23d1f73bf130 285 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
vladvana 0:23d1f73bf130 286 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
vladvana 0:23d1f73bf130 287 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
vladvana 0:23d1f73bf130 288 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
vladvana 0:23d1f73bf130 289 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
vladvana 0:23d1f73bf130 290 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
vladvana 0:23d1f73bf130 291 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
vladvana 0:23d1f73bf130 292 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
vladvana 0:23d1f73bf130 293 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
vladvana 0:23d1f73bf130 294 } b; /*!< Structure used for bit access */
vladvana 0:23d1f73bf130 295 uint32_t w; /*!< Type used for word access */
vladvana 0:23d1f73bf130 296 } xPSR_Type;
vladvana 0:23d1f73bf130 297
vladvana 0:23d1f73bf130 298 /* xPSR Register Definitions */
vladvana 0:23d1f73bf130 299 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
vladvana 0:23d1f73bf130 300 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
vladvana 0:23d1f73bf130 301
vladvana 0:23d1f73bf130 302 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
vladvana 0:23d1f73bf130 303 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
vladvana 0:23d1f73bf130 304
vladvana 0:23d1f73bf130 305 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
vladvana 0:23d1f73bf130 306 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
vladvana 0:23d1f73bf130 307
vladvana 0:23d1f73bf130 308 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
vladvana 0:23d1f73bf130 309 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
vladvana 0:23d1f73bf130 310
vladvana 0:23d1f73bf130 311 #define xPSR_Q_Pos 27 /*!< xPSR: Q Position */
vladvana 0:23d1f73bf130 312 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
vladvana 0:23d1f73bf130 313
vladvana 0:23d1f73bf130 314 #define xPSR_IT_Pos 25 /*!< xPSR: IT Position */
vladvana 0:23d1f73bf130 315 #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
vladvana 0:23d1f73bf130 316
vladvana 0:23d1f73bf130 317 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
vladvana 0:23d1f73bf130 318 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
vladvana 0:23d1f73bf130 319
vladvana 0:23d1f73bf130 320 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
vladvana 0:23d1f73bf130 321 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
vladvana 0:23d1f73bf130 322
vladvana 0:23d1f73bf130 323
vladvana 0:23d1f73bf130 324 /** \brief Union type to access the Control Registers (CONTROL).
vladvana 0:23d1f73bf130 325 */
vladvana 0:23d1f73bf130 326 typedef union
vladvana 0:23d1f73bf130 327 {
vladvana 0:23d1f73bf130 328 struct
vladvana 0:23d1f73bf130 329 {
vladvana 0:23d1f73bf130 330 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
vladvana 0:23d1f73bf130 331 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
vladvana 0:23d1f73bf130 332 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
vladvana 0:23d1f73bf130 333 } b; /*!< Structure used for bit access */
vladvana 0:23d1f73bf130 334 uint32_t w; /*!< Type used for word access */
vladvana 0:23d1f73bf130 335 } CONTROL_Type;
vladvana 0:23d1f73bf130 336
vladvana 0:23d1f73bf130 337 /* CONTROL Register Definitions */
vladvana 0:23d1f73bf130 338 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
vladvana 0:23d1f73bf130 339 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
vladvana 0:23d1f73bf130 340
vladvana 0:23d1f73bf130 341 #define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
vladvana 0:23d1f73bf130 342 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
vladvana 0:23d1f73bf130 343
vladvana 0:23d1f73bf130 344 /*@} end of group CMSIS_CORE */
vladvana 0:23d1f73bf130 345
vladvana 0:23d1f73bf130 346
vladvana 0:23d1f73bf130 347 /** \ingroup CMSIS_core_register
vladvana 0:23d1f73bf130 348 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
vladvana 0:23d1f73bf130 349 \brief Type definitions for the NVIC Registers
vladvana 0:23d1f73bf130 350 @{
vladvana 0:23d1f73bf130 351 */
vladvana 0:23d1f73bf130 352
vladvana 0:23d1f73bf130 353 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
vladvana 0:23d1f73bf130 354 */
vladvana 0:23d1f73bf130 355 typedef struct
vladvana 0:23d1f73bf130 356 {
vladvana 0:23d1f73bf130 357 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
vladvana 0:23d1f73bf130 358 uint32_t RESERVED0[24];
vladvana 0:23d1f73bf130 359 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
vladvana 0:23d1f73bf130 360 uint32_t RSERVED1[24];
vladvana 0:23d1f73bf130 361 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
vladvana 0:23d1f73bf130 362 uint32_t RESERVED2[24];
vladvana 0:23d1f73bf130 363 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
vladvana 0:23d1f73bf130 364 uint32_t RESERVED3[24];
vladvana 0:23d1f73bf130 365 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
vladvana 0:23d1f73bf130 366 uint32_t RESERVED4[56];
vladvana 0:23d1f73bf130 367 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
vladvana 0:23d1f73bf130 368 uint32_t RESERVED5[644];
vladvana 0:23d1f73bf130 369 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
vladvana 0:23d1f73bf130 370 } NVIC_Type;
vladvana 0:23d1f73bf130 371
vladvana 0:23d1f73bf130 372 /* Software Triggered Interrupt Register Definitions */
vladvana 0:23d1f73bf130 373 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
vladvana 0:23d1f73bf130 374 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
vladvana 0:23d1f73bf130 375
vladvana 0:23d1f73bf130 376 /*@} end of group CMSIS_NVIC */
vladvana 0:23d1f73bf130 377
vladvana 0:23d1f73bf130 378
vladvana 0:23d1f73bf130 379 /** \ingroup CMSIS_core_register
vladvana 0:23d1f73bf130 380 \defgroup CMSIS_SCB System Control Block (SCB)
vladvana 0:23d1f73bf130 381 \brief Type definitions for the System Control Block Registers
vladvana 0:23d1f73bf130 382 @{
vladvana 0:23d1f73bf130 383 */
vladvana 0:23d1f73bf130 384
vladvana 0:23d1f73bf130 385 /** \brief Structure type to access the System Control Block (SCB).
vladvana 0:23d1f73bf130 386 */
vladvana 0:23d1f73bf130 387 typedef struct
vladvana 0:23d1f73bf130 388 {
vladvana 0:23d1f73bf130 389 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
vladvana 0:23d1f73bf130 390 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
vladvana 0:23d1f73bf130 391 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
vladvana 0:23d1f73bf130 392 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
vladvana 0:23d1f73bf130 393 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
vladvana 0:23d1f73bf130 394 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
vladvana 0:23d1f73bf130 395 __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
vladvana 0:23d1f73bf130 396 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
vladvana 0:23d1f73bf130 397 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
vladvana 0:23d1f73bf130 398 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
vladvana 0:23d1f73bf130 399 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
vladvana 0:23d1f73bf130 400 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
vladvana 0:23d1f73bf130 401 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
vladvana 0:23d1f73bf130 402 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
vladvana 0:23d1f73bf130 403 __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
vladvana 0:23d1f73bf130 404 __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
vladvana 0:23d1f73bf130 405 __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
vladvana 0:23d1f73bf130 406 __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
vladvana 0:23d1f73bf130 407 __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
vladvana 0:23d1f73bf130 408 uint32_t RESERVED0[5];
vladvana 0:23d1f73bf130 409 __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
vladvana 0:23d1f73bf130 410 } SCB_Type;
vladvana 0:23d1f73bf130 411
vladvana 0:23d1f73bf130 412 /* SCB CPUID Register Definitions */
vladvana 0:23d1f73bf130 413 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
vladvana 0:23d1f73bf130 414 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
vladvana 0:23d1f73bf130 415
vladvana 0:23d1f73bf130 416 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
vladvana 0:23d1f73bf130 417 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
vladvana 0:23d1f73bf130 418
vladvana 0:23d1f73bf130 419 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
vladvana 0:23d1f73bf130 420 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
vladvana 0:23d1f73bf130 421
vladvana 0:23d1f73bf130 422 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
vladvana 0:23d1f73bf130 423 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
vladvana 0:23d1f73bf130 424
vladvana 0:23d1f73bf130 425 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
vladvana 0:23d1f73bf130 426 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
vladvana 0:23d1f73bf130 427
vladvana 0:23d1f73bf130 428 /* SCB Interrupt Control State Register Definitions */
vladvana 0:23d1f73bf130 429 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
vladvana 0:23d1f73bf130 430 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
vladvana 0:23d1f73bf130 431
vladvana 0:23d1f73bf130 432 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
vladvana 0:23d1f73bf130 433 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
vladvana 0:23d1f73bf130 434
vladvana 0:23d1f73bf130 435 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
vladvana 0:23d1f73bf130 436 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
vladvana 0:23d1f73bf130 437
vladvana 0:23d1f73bf130 438 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
vladvana 0:23d1f73bf130 439 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
vladvana 0:23d1f73bf130 440
vladvana 0:23d1f73bf130 441 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
vladvana 0:23d1f73bf130 442 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
vladvana 0:23d1f73bf130 443
vladvana 0:23d1f73bf130 444 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
vladvana 0:23d1f73bf130 445 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
vladvana 0:23d1f73bf130 446
vladvana 0:23d1f73bf130 447 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
vladvana 0:23d1f73bf130 448 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
vladvana 0:23d1f73bf130 449
vladvana 0:23d1f73bf130 450 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
vladvana 0:23d1f73bf130 451 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
vladvana 0:23d1f73bf130 452
vladvana 0:23d1f73bf130 453 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
vladvana 0:23d1f73bf130 454 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
vladvana 0:23d1f73bf130 455
vladvana 0:23d1f73bf130 456 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
vladvana 0:23d1f73bf130 457 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
vladvana 0:23d1f73bf130 458
vladvana 0:23d1f73bf130 459 /* SCB Vector Table Offset Register Definitions */
vladvana 0:23d1f73bf130 460 #if (__CM3_REV < 0x0201) /* core r2p1 */
vladvana 0:23d1f73bf130 461 #define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
vladvana 0:23d1f73bf130 462 #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
vladvana 0:23d1f73bf130 463
vladvana 0:23d1f73bf130 464 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
vladvana 0:23d1f73bf130 465 #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
vladvana 0:23d1f73bf130 466 #else
vladvana 0:23d1f73bf130 467 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
vladvana 0:23d1f73bf130 468 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
vladvana 0:23d1f73bf130 469 #endif
vladvana 0:23d1f73bf130 470
vladvana 0:23d1f73bf130 471 /* SCB Application Interrupt and Reset Control Register Definitions */
vladvana 0:23d1f73bf130 472 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
vladvana 0:23d1f73bf130 473 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
vladvana 0:23d1f73bf130 474
vladvana 0:23d1f73bf130 475 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
vladvana 0:23d1f73bf130 476 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
vladvana 0:23d1f73bf130 477
vladvana 0:23d1f73bf130 478 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
vladvana 0:23d1f73bf130 479 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
vladvana 0:23d1f73bf130 480
vladvana 0:23d1f73bf130 481 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
vladvana 0:23d1f73bf130 482 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
vladvana 0:23d1f73bf130 483
vladvana 0:23d1f73bf130 484 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
vladvana 0:23d1f73bf130 485 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
vladvana 0:23d1f73bf130 486
vladvana 0:23d1f73bf130 487 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
vladvana 0:23d1f73bf130 488 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
vladvana 0:23d1f73bf130 489
vladvana 0:23d1f73bf130 490 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
vladvana 0:23d1f73bf130 491 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
vladvana 0:23d1f73bf130 492
vladvana 0:23d1f73bf130 493 /* SCB System Control Register Definitions */
vladvana 0:23d1f73bf130 494 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
vladvana 0:23d1f73bf130 495 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
vladvana 0:23d1f73bf130 496
vladvana 0:23d1f73bf130 497 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
vladvana 0:23d1f73bf130 498 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
vladvana 0:23d1f73bf130 499
vladvana 0:23d1f73bf130 500 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
vladvana 0:23d1f73bf130 501 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
vladvana 0:23d1f73bf130 502
vladvana 0:23d1f73bf130 503 /* SCB Configuration Control Register Definitions */
vladvana 0:23d1f73bf130 504 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
vladvana 0:23d1f73bf130 505 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
vladvana 0:23d1f73bf130 506
vladvana 0:23d1f73bf130 507 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
vladvana 0:23d1f73bf130 508 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
vladvana 0:23d1f73bf130 509
vladvana 0:23d1f73bf130 510 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
vladvana 0:23d1f73bf130 511 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
vladvana 0:23d1f73bf130 512
vladvana 0:23d1f73bf130 513 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
vladvana 0:23d1f73bf130 514 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
vladvana 0:23d1f73bf130 515
vladvana 0:23d1f73bf130 516 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
vladvana 0:23d1f73bf130 517 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
vladvana 0:23d1f73bf130 518
vladvana 0:23d1f73bf130 519 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
vladvana 0:23d1f73bf130 520 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
vladvana 0:23d1f73bf130 521
vladvana 0:23d1f73bf130 522 /* SCB System Handler Control and State Register Definitions */
vladvana 0:23d1f73bf130 523 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
vladvana 0:23d1f73bf130 524 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
vladvana 0:23d1f73bf130 525
vladvana 0:23d1f73bf130 526 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
vladvana 0:23d1f73bf130 527 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
vladvana 0:23d1f73bf130 528
vladvana 0:23d1f73bf130 529 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
vladvana 0:23d1f73bf130 530 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
vladvana 0:23d1f73bf130 531
vladvana 0:23d1f73bf130 532 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
vladvana 0:23d1f73bf130 533 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
vladvana 0:23d1f73bf130 534
vladvana 0:23d1f73bf130 535 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
vladvana 0:23d1f73bf130 536 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
vladvana 0:23d1f73bf130 537
vladvana 0:23d1f73bf130 538 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
vladvana 0:23d1f73bf130 539 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
vladvana 0:23d1f73bf130 540
vladvana 0:23d1f73bf130 541 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
vladvana 0:23d1f73bf130 542 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
vladvana 0:23d1f73bf130 543
vladvana 0:23d1f73bf130 544 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
vladvana 0:23d1f73bf130 545 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
vladvana 0:23d1f73bf130 546
vladvana 0:23d1f73bf130 547 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
vladvana 0:23d1f73bf130 548 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
vladvana 0:23d1f73bf130 549
vladvana 0:23d1f73bf130 550 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
vladvana 0:23d1f73bf130 551 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
vladvana 0:23d1f73bf130 552
vladvana 0:23d1f73bf130 553 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
vladvana 0:23d1f73bf130 554 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
vladvana 0:23d1f73bf130 555
vladvana 0:23d1f73bf130 556 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
vladvana 0:23d1f73bf130 557 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
vladvana 0:23d1f73bf130 558
vladvana 0:23d1f73bf130 559 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
vladvana 0:23d1f73bf130 560 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
vladvana 0:23d1f73bf130 561
vladvana 0:23d1f73bf130 562 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
vladvana 0:23d1f73bf130 563 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
vladvana 0:23d1f73bf130 564
vladvana 0:23d1f73bf130 565 /* SCB Configurable Fault Status Registers Definitions */
vladvana 0:23d1f73bf130 566 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
vladvana 0:23d1f73bf130 567 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
vladvana 0:23d1f73bf130 568
vladvana 0:23d1f73bf130 569 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
vladvana 0:23d1f73bf130 570 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
vladvana 0:23d1f73bf130 571
vladvana 0:23d1f73bf130 572 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
vladvana 0:23d1f73bf130 573 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
vladvana 0:23d1f73bf130 574
vladvana 0:23d1f73bf130 575 /* SCB Hard Fault Status Registers Definitions */
vladvana 0:23d1f73bf130 576 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
vladvana 0:23d1f73bf130 577 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
vladvana 0:23d1f73bf130 578
vladvana 0:23d1f73bf130 579 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
vladvana 0:23d1f73bf130 580 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
vladvana 0:23d1f73bf130 581
vladvana 0:23d1f73bf130 582 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
vladvana 0:23d1f73bf130 583 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
vladvana 0:23d1f73bf130 584
vladvana 0:23d1f73bf130 585 /* SCB Debug Fault Status Register Definitions */
vladvana 0:23d1f73bf130 586 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
vladvana 0:23d1f73bf130 587 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
vladvana 0:23d1f73bf130 588
vladvana 0:23d1f73bf130 589 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
vladvana 0:23d1f73bf130 590 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
vladvana 0:23d1f73bf130 591
vladvana 0:23d1f73bf130 592 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
vladvana 0:23d1f73bf130 593 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
vladvana 0:23d1f73bf130 594
vladvana 0:23d1f73bf130 595 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
vladvana 0:23d1f73bf130 596 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
vladvana 0:23d1f73bf130 597
vladvana 0:23d1f73bf130 598 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
vladvana 0:23d1f73bf130 599 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
vladvana 0:23d1f73bf130 600
vladvana 0:23d1f73bf130 601 /*@} end of group CMSIS_SCB */
vladvana 0:23d1f73bf130 602
vladvana 0:23d1f73bf130 603
vladvana 0:23d1f73bf130 604 /** \ingroup CMSIS_core_register
vladvana 0:23d1f73bf130 605 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
vladvana 0:23d1f73bf130 606 \brief Type definitions for the System Control and ID Register not in the SCB
vladvana 0:23d1f73bf130 607 @{
vladvana 0:23d1f73bf130 608 */
vladvana 0:23d1f73bf130 609
vladvana 0:23d1f73bf130 610 /** \brief Structure type to access the System Control and ID Register not in the SCB.
vladvana 0:23d1f73bf130 611 */
vladvana 0:23d1f73bf130 612 typedef struct
vladvana 0:23d1f73bf130 613 {
vladvana 0:23d1f73bf130 614 uint32_t RESERVED0[1];
vladvana 0:23d1f73bf130 615 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
vladvana 0:23d1f73bf130 616 #if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
vladvana 0:23d1f73bf130 617 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
vladvana 0:23d1f73bf130 618 #else
vladvana 0:23d1f73bf130 619 uint32_t RESERVED1[1];
vladvana 0:23d1f73bf130 620 #endif
vladvana 0:23d1f73bf130 621 } SCnSCB_Type;
vladvana 0:23d1f73bf130 622
vladvana 0:23d1f73bf130 623 /* Interrupt Controller Type Register Definitions */
vladvana 0:23d1f73bf130 624 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
vladvana 0:23d1f73bf130 625 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
vladvana 0:23d1f73bf130 626
vladvana 0:23d1f73bf130 627 /* Auxiliary Control Register Definitions */
vladvana 0:23d1f73bf130 628
vladvana 0:23d1f73bf130 629 #define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
vladvana 0:23d1f73bf130 630 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
vladvana 0:23d1f73bf130 631
vladvana 0:23d1f73bf130 632 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
vladvana 0:23d1f73bf130 633 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
vladvana 0:23d1f73bf130 634
vladvana 0:23d1f73bf130 635 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
vladvana 0:23d1f73bf130 636 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
vladvana 0:23d1f73bf130 637
vladvana 0:23d1f73bf130 638 /*@} end of group CMSIS_SCnotSCB */
vladvana 0:23d1f73bf130 639
vladvana 0:23d1f73bf130 640
vladvana 0:23d1f73bf130 641 /** \ingroup CMSIS_core_register
vladvana 0:23d1f73bf130 642 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
vladvana 0:23d1f73bf130 643 \brief Type definitions for the System Timer Registers.
vladvana 0:23d1f73bf130 644 @{
vladvana 0:23d1f73bf130 645 */
vladvana 0:23d1f73bf130 646
vladvana 0:23d1f73bf130 647 /** \brief Structure type to access the System Timer (SysTick).
vladvana 0:23d1f73bf130 648 */
vladvana 0:23d1f73bf130 649 typedef struct
vladvana 0:23d1f73bf130 650 {
vladvana 0:23d1f73bf130 651 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
vladvana 0:23d1f73bf130 652 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
vladvana 0:23d1f73bf130 653 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
vladvana 0:23d1f73bf130 654 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
vladvana 0:23d1f73bf130 655 } SysTick_Type;
vladvana 0:23d1f73bf130 656
vladvana 0:23d1f73bf130 657 /* SysTick Control / Status Register Definitions */
vladvana 0:23d1f73bf130 658 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
vladvana 0:23d1f73bf130 659 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
vladvana 0:23d1f73bf130 660
vladvana 0:23d1f73bf130 661 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
vladvana 0:23d1f73bf130 662 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
vladvana 0:23d1f73bf130 663
vladvana 0:23d1f73bf130 664 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
vladvana 0:23d1f73bf130 665 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
vladvana 0:23d1f73bf130 666
vladvana 0:23d1f73bf130 667 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
vladvana 0:23d1f73bf130 668 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
vladvana 0:23d1f73bf130 669
vladvana 0:23d1f73bf130 670 /* SysTick Reload Register Definitions */
vladvana 0:23d1f73bf130 671 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
vladvana 0:23d1f73bf130 672 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
vladvana 0:23d1f73bf130 673
vladvana 0:23d1f73bf130 674 /* SysTick Current Register Definitions */
vladvana 0:23d1f73bf130 675 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
vladvana 0:23d1f73bf130 676 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
vladvana 0:23d1f73bf130 677
vladvana 0:23d1f73bf130 678 /* SysTick Calibration Register Definitions */
vladvana 0:23d1f73bf130 679 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
vladvana 0:23d1f73bf130 680 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
vladvana 0:23d1f73bf130 681
vladvana 0:23d1f73bf130 682 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
vladvana 0:23d1f73bf130 683 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
vladvana 0:23d1f73bf130 684
vladvana 0:23d1f73bf130 685 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
vladvana 0:23d1f73bf130 686 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
vladvana 0:23d1f73bf130 687
vladvana 0:23d1f73bf130 688 /*@} end of group CMSIS_SysTick */
vladvana 0:23d1f73bf130 689
vladvana 0:23d1f73bf130 690
vladvana 0:23d1f73bf130 691 /** \ingroup CMSIS_core_register
vladvana 0:23d1f73bf130 692 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
vladvana 0:23d1f73bf130 693 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
vladvana 0:23d1f73bf130 694 @{
vladvana 0:23d1f73bf130 695 */
vladvana 0:23d1f73bf130 696
vladvana 0:23d1f73bf130 697 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
vladvana 0:23d1f73bf130 698 */
vladvana 0:23d1f73bf130 699 typedef struct
vladvana 0:23d1f73bf130 700 {
vladvana 0:23d1f73bf130 701 __O union
vladvana 0:23d1f73bf130 702 {
vladvana 0:23d1f73bf130 703 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
vladvana 0:23d1f73bf130 704 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
vladvana 0:23d1f73bf130 705 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
vladvana 0:23d1f73bf130 706 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
vladvana 0:23d1f73bf130 707 uint32_t RESERVED0[864];
vladvana 0:23d1f73bf130 708 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
vladvana 0:23d1f73bf130 709 uint32_t RESERVED1[15];
vladvana 0:23d1f73bf130 710 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
vladvana 0:23d1f73bf130 711 uint32_t RESERVED2[15];
vladvana 0:23d1f73bf130 712 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
vladvana 0:23d1f73bf130 713 uint32_t RESERVED3[29];
vladvana 0:23d1f73bf130 714 __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
vladvana 0:23d1f73bf130 715 __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
vladvana 0:23d1f73bf130 716 __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
vladvana 0:23d1f73bf130 717 uint32_t RESERVED4[43];
vladvana 0:23d1f73bf130 718 __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
vladvana 0:23d1f73bf130 719 __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
vladvana 0:23d1f73bf130 720 uint32_t RESERVED5[6];
vladvana 0:23d1f73bf130 721 __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
vladvana 0:23d1f73bf130 722 __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
vladvana 0:23d1f73bf130 723 __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
vladvana 0:23d1f73bf130 724 __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
vladvana 0:23d1f73bf130 725 __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
vladvana 0:23d1f73bf130 726 __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
vladvana 0:23d1f73bf130 727 __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
vladvana 0:23d1f73bf130 728 __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
vladvana 0:23d1f73bf130 729 __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
vladvana 0:23d1f73bf130 730 __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
vladvana 0:23d1f73bf130 731 __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
vladvana 0:23d1f73bf130 732 __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
vladvana 0:23d1f73bf130 733 } ITM_Type;
vladvana 0:23d1f73bf130 734
vladvana 0:23d1f73bf130 735 /* ITM Trace Privilege Register Definitions */
vladvana 0:23d1f73bf130 736 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
vladvana 0:23d1f73bf130 737 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
vladvana 0:23d1f73bf130 738
vladvana 0:23d1f73bf130 739 /* ITM Trace Control Register Definitions */
vladvana 0:23d1f73bf130 740 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
vladvana 0:23d1f73bf130 741 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
vladvana 0:23d1f73bf130 742
vladvana 0:23d1f73bf130 743 #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
vladvana 0:23d1f73bf130 744 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
vladvana 0:23d1f73bf130 745
vladvana 0:23d1f73bf130 746 #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
vladvana 0:23d1f73bf130 747 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
vladvana 0:23d1f73bf130 748
vladvana 0:23d1f73bf130 749 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
vladvana 0:23d1f73bf130 750 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
vladvana 0:23d1f73bf130 751
vladvana 0:23d1f73bf130 752 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
vladvana 0:23d1f73bf130 753 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
vladvana 0:23d1f73bf130 754
vladvana 0:23d1f73bf130 755 #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
vladvana 0:23d1f73bf130 756 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
vladvana 0:23d1f73bf130 757
vladvana 0:23d1f73bf130 758 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
vladvana 0:23d1f73bf130 759 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
vladvana 0:23d1f73bf130 760
vladvana 0:23d1f73bf130 761 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
vladvana 0:23d1f73bf130 762 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
vladvana 0:23d1f73bf130 763
vladvana 0:23d1f73bf130 764 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
vladvana 0:23d1f73bf130 765 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
vladvana 0:23d1f73bf130 766
vladvana 0:23d1f73bf130 767 /* ITM Integration Write Register Definitions */
vladvana 0:23d1f73bf130 768 #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
vladvana 0:23d1f73bf130 769 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
vladvana 0:23d1f73bf130 770
vladvana 0:23d1f73bf130 771 /* ITM Integration Read Register Definitions */
vladvana 0:23d1f73bf130 772 #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
vladvana 0:23d1f73bf130 773 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
vladvana 0:23d1f73bf130 774
vladvana 0:23d1f73bf130 775 /* ITM Integration Mode Control Register Definitions */
vladvana 0:23d1f73bf130 776 #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
vladvana 0:23d1f73bf130 777 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
vladvana 0:23d1f73bf130 778
vladvana 0:23d1f73bf130 779 /* ITM Lock Status Register Definitions */
vladvana 0:23d1f73bf130 780 #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
vladvana 0:23d1f73bf130 781 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
vladvana 0:23d1f73bf130 782
vladvana 0:23d1f73bf130 783 #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
vladvana 0:23d1f73bf130 784 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
vladvana 0:23d1f73bf130 785
vladvana 0:23d1f73bf130 786 #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
vladvana 0:23d1f73bf130 787 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
vladvana 0:23d1f73bf130 788
vladvana 0:23d1f73bf130 789 /*@}*/ /* end of group CMSIS_ITM */
vladvana 0:23d1f73bf130 790
vladvana 0:23d1f73bf130 791
vladvana 0:23d1f73bf130 792 /** \ingroup CMSIS_core_register
vladvana 0:23d1f73bf130 793 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
vladvana 0:23d1f73bf130 794 \brief Type definitions for the Data Watchpoint and Trace (DWT)
vladvana 0:23d1f73bf130 795 @{
vladvana 0:23d1f73bf130 796 */
vladvana 0:23d1f73bf130 797
vladvana 0:23d1f73bf130 798 /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
vladvana 0:23d1f73bf130 799 */
vladvana 0:23d1f73bf130 800 typedef struct
vladvana 0:23d1f73bf130 801 {
vladvana 0:23d1f73bf130 802 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
vladvana 0:23d1f73bf130 803 __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
vladvana 0:23d1f73bf130 804 __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
vladvana 0:23d1f73bf130 805 __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
vladvana 0:23d1f73bf130 806 __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
vladvana 0:23d1f73bf130 807 __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
vladvana 0:23d1f73bf130 808 __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
vladvana 0:23d1f73bf130 809 __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
vladvana 0:23d1f73bf130 810 __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
vladvana 0:23d1f73bf130 811 __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
vladvana 0:23d1f73bf130 812 __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
vladvana 0:23d1f73bf130 813 uint32_t RESERVED0[1];
vladvana 0:23d1f73bf130 814 __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
vladvana 0:23d1f73bf130 815 __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
vladvana 0:23d1f73bf130 816 __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
vladvana 0:23d1f73bf130 817 uint32_t RESERVED1[1];
vladvana 0:23d1f73bf130 818 __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
vladvana 0:23d1f73bf130 819 __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
vladvana 0:23d1f73bf130 820 __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
vladvana 0:23d1f73bf130 821 uint32_t RESERVED2[1];
vladvana 0:23d1f73bf130 822 __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
vladvana 0:23d1f73bf130 823 __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
vladvana 0:23d1f73bf130 824 __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
vladvana 0:23d1f73bf130 825 } DWT_Type;
vladvana 0:23d1f73bf130 826
vladvana 0:23d1f73bf130 827 /* DWT Control Register Definitions */
vladvana 0:23d1f73bf130 828 #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
vladvana 0:23d1f73bf130 829 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
vladvana 0:23d1f73bf130 830
vladvana 0:23d1f73bf130 831 #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
vladvana 0:23d1f73bf130 832 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
vladvana 0:23d1f73bf130 833
vladvana 0:23d1f73bf130 834 #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
vladvana 0:23d1f73bf130 835 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
vladvana 0:23d1f73bf130 836
vladvana 0:23d1f73bf130 837 #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
vladvana 0:23d1f73bf130 838 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
vladvana 0:23d1f73bf130 839
vladvana 0:23d1f73bf130 840 #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
vladvana 0:23d1f73bf130 841 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
vladvana 0:23d1f73bf130 842
vladvana 0:23d1f73bf130 843 #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
vladvana 0:23d1f73bf130 844 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
vladvana 0:23d1f73bf130 845
vladvana 0:23d1f73bf130 846 #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
vladvana 0:23d1f73bf130 847 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
vladvana 0:23d1f73bf130 848
vladvana 0:23d1f73bf130 849 #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
vladvana 0:23d1f73bf130 850 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
vladvana 0:23d1f73bf130 851
vladvana 0:23d1f73bf130 852 #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
vladvana 0:23d1f73bf130 853 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
vladvana 0:23d1f73bf130 854
vladvana 0:23d1f73bf130 855 #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
vladvana 0:23d1f73bf130 856 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
vladvana 0:23d1f73bf130 857
vladvana 0:23d1f73bf130 858 #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
vladvana 0:23d1f73bf130 859 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
vladvana 0:23d1f73bf130 860
vladvana 0:23d1f73bf130 861 #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
vladvana 0:23d1f73bf130 862 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
vladvana 0:23d1f73bf130 863
vladvana 0:23d1f73bf130 864 #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
vladvana 0:23d1f73bf130 865 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
vladvana 0:23d1f73bf130 866
vladvana 0:23d1f73bf130 867 #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
vladvana 0:23d1f73bf130 868 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
vladvana 0:23d1f73bf130 869
vladvana 0:23d1f73bf130 870 #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
vladvana 0:23d1f73bf130 871 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
vladvana 0:23d1f73bf130 872
vladvana 0:23d1f73bf130 873 #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
vladvana 0:23d1f73bf130 874 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
vladvana 0:23d1f73bf130 875
vladvana 0:23d1f73bf130 876 #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
vladvana 0:23d1f73bf130 877 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
vladvana 0:23d1f73bf130 878
vladvana 0:23d1f73bf130 879 #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
vladvana 0:23d1f73bf130 880 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
vladvana 0:23d1f73bf130 881
vladvana 0:23d1f73bf130 882 /* DWT CPI Count Register Definitions */
vladvana 0:23d1f73bf130 883 #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
vladvana 0:23d1f73bf130 884 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
vladvana 0:23d1f73bf130 885
vladvana 0:23d1f73bf130 886 /* DWT Exception Overhead Count Register Definitions */
vladvana 0:23d1f73bf130 887 #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
vladvana 0:23d1f73bf130 888 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
vladvana 0:23d1f73bf130 889
vladvana 0:23d1f73bf130 890 /* DWT Sleep Count Register Definitions */
vladvana 0:23d1f73bf130 891 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
vladvana 0:23d1f73bf130 892 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
vladvana 0:23d1f73bf130 893
vladvana 0:23d1f73bf130 894 /* DWT LSU Count Register Definitions */
vladvana 0:23d1f73bf130 895 #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
vladvana 0:23d1f73bf130 896 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
vladvana 0:23d1f73bf130 897
vladvana 0:23d1f73bf130 898 /* DWT Folded-instruction Count Register Definitions */
vladvana 0:23d1f73bf130 899 #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
vladvana 0:23d1f73bf130 900 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
vladvana 0:23d1f73bf130 901
vladvana 0:23d1f73bf130 902 /* DWT Comparator Mask Register Definitions */
vladvana 0:23d1f73bf130 903 #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
vladvana 0:23d1f73bf130 904 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
vladvana 0:23d1f73bf130 905
vladvana 0:23d1f73bf130 906 /* DWT Comparator Function Register Definitions */
vladvana 0:23d1f73bf130 907 #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
vladvana 0:23d1f73bf130 908 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
vladvana 0:23d1f73bf130 909
vladvana 0:23d1f73bf130 910 #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
vladvana 0:23d1f73bf130 911 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
vladvana 0:23d1f73bf130 912
vladvana 0:23d1f73bf130 913 #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
vladvana 0:23d1f73bf130 914 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
vladvana 0:23d1f73bf130 915
vladvana 0:23d1f73bf130 916 #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
vladvana 0:23d1f73bf130 917 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
vladvana 0:23d1f73bf130 918
vladvana 0:23d1f73bf130 919 #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
vladvana 0:23d1f73bf130 920 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
vladvana 0:23d1f73bf130 921
vladvana 0:23d1f73bf130 922 #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
vladvana 0:23d1f73bf130 923 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
vladvana 0:23d1f73bf130 924
vladvana 0:23d1f73bf130 925 #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
vladvana 0:23d1f73bf130 926 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
vladvana 0:23d1f73bf130 927
vladvana 0:23d1f73bf130 928 #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
vladvana 0:23d1f73bf130 929 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
vladvana 0:23d1f73bf130 930
vladvana 0:23d1f73bf130 931 #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
vladvana 0:23d1f73bf130 932 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
vladvana 0:23d1f73bf130 933
vladvana 0:23d1f73bf130 934 /*@}*/ /* end of group CMSIS_DWT */
vladvana 0:23d1f73bf130 935
vladvana 0:23d1f73bf130 936
vladvana 0:23d1f73bf130 937 /** \ingroup CMSIS_core_register
vladvana 0:23d1f73bf130 938 \defgroup CMSIS_TPI Trace Port Interface (TPI)
vladvana 0:23d1f73bf130 939 \brief Type definitions for the Trace Port Interface (TPI)
vladvana 0:23d1f73bf130 940 @{
vladvana 0:23d1f73bf130 941 */
vladvana 0:23d1f73bf130 942
vladvana 0:23d1f73bf130 943 /** \brief Structure type to access the Trace Port Interface Register (TPI).
vladvana 0:23d1f73bf130 944 */
vladvana 0:23d1f73bf130 945 typedef struct
vladvana 0:23d1f73bf130 946 {
vladvana 0:23d1f73bf130 947 __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
vladvana 0:23d1f73bf130 948 __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
vladvana 0:23d1f73bf130 949 uint32_t RESERVED0[2];
vladvana 0:23d1f73bf130 950 __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
vladvana 0:23d1f73bf130 951 uint32_t RESERVED1[55];
vladvana 0:23d1f73bf130 952 __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
vladvana 0:23d1f73bf130 953 uint32_t RESERVED2[131];
vladvana 0:23d1f73bf130 954 __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
vladvana 0:23d1f73bf130 955 __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
vladvana 0:23d1f73bf130 956 __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
vladvana 0:23d1f73bf130 957 uint32_t RESERVED3[759];
vladvana 0:23d1f73bf130 958 __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
vladvana 0:23d1f73bf130 959 __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
vladvana 0:23d1f73bf130 960 __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
vladvana 0:23d1f73bf130 961 uint32_t RESERVED4[1];
vladvana 0:23d1f73bf130 962 __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
vladvana 0:23d1f73bf130 963 __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
vladvana 0:23d1f73bf130 964 __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
vladvana 0:23d1f73bf130 965 uint32_t RESERVED5[39];
vladvana 0:23d1f73bf130 966 __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
vladvana 0:23d1f73bf130 967 __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
vladvana 0:23d1f73bf130 968 uint32_t RESERVED7[8];
vladvana 0:23d1f73bf130 969 __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
vladvana 0:23d1f73bf130 970 __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
vladvana 0:23d1f73bf130 971 } TPI_Type;
vladvana 0:23d1f73bf130 972
vladvana 0:23d1f73bf130 973 /* TPI Asynchronous Clock Prescaler Register Definitions */
vladvana 0:23d1f73bf130 974 #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
vladvana 0:23d1f73bf130 975 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
vladvana 0:23d1f73bf130 976
vladvana 0:23d1f73bf130 977 /* TPI Selected Pin Protocol Register Definitions */
vladvana 0:23d1f73bf130 978 #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
vladvana 0:23d1f73bf130 979 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
vladvana 0:23d1f73bf130 980
vladvana 0:23d1f73bf130 981 /* TPI Formatter and Flush Status Register Definitions */
vladvana 0:23d1f73bf130 982 #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
vladvana 0:23d1f73bf130 983 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
vladvana 0:23d1f73bf130 984
vladvana 0:23d1f73bf130 985 #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
vladvana 0:23d1f73bf130 986 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
vladvana 0:23d1f73bf130 987
vladvana 0:23d1f73bf130 988 #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
vladvana 0:23d1f73bf130 989 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
vladvana 0:23d1f73bf130 990
vladvana 0:23d1f73bf130 991 #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
vladvana 0:23d1f73bf130 992 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
vladvana 0:23d1f73bf130 993
vladvana 0:23d1f73bf130 994 /* TPI Formatter and Flush Control Register Definitions */
vladvana 0:23d1f73bf130 995 #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
vladvana 0:23d1f73bf130 996 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
vladvana 0:23d1f73bf130 997
vladvana 0:23d1f73bf130 998 #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
vladvana 0:23d1f73bf130 999 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
vladvana 0:23d1f73bf130 1000
vladvana 0:23d1f73bf130 1001 /* TPI TRIGGER Register Definitions */
vladvana 0:23d1f73bf130 1002 #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
vladvana 0:23d1f73bf130 1003 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
vladvana 0:23d1f73bf130 1004
vladvana 0:23d1f73bf130 1005 /* TPI Integration ETM Data Register Definitions (FIFO0) */
vladvana 0:23d1f73bf130 1006 #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
vladvana 0:23d1f73bf130 1007 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
vladvana 0:23d1f73bf130 1008
vladvana 0:23d1f73bf130 1009 #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
vladvana 0:23d1f73bf130 1010 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
vladvana 0:23d1f73bf130 1011
vladvana 0:23d1f73bf130 1012 #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
vladvana 0:23d1f73bf130 1013 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
vladvana 0:23d1f73bf130 1014
vladvana 0:23d1f73bf130 1015 #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
vladvana 0:23d1f73bf130 1016 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
vladvana 0:23d1f73bf130 1017
vladvana 0:23d1f73bf130 1018 #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
vladvana 0:23d1f73bf130 1019 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
vladvana 0:23d1f73bf130 1020
vladvana 0:23d1f73bf130 1021 #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
vladvana 0:23d1f73bf130 1022 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
vladvana 0:23d1f73bf130 1023
vladvana 0:23d1f73bf130 1024 #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
vladvana 0:23d1f73bf130 1025 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
vladvana 0:23d1f73bf130 1026
vladvana 0:23d1f73bf130 1027 /* TPI ITATBCTR2 Register Definitions */
vladvana 0:23d1f73bf130 1028 #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
vladvana 0:23d1f73bf130 1029 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
vladvana 0:23d1f73bf130 1030
vladvana 0:23d1f73bf130 1031 /* TPI Integration ITM Data Register Definitions (FIFO1) */
vladvana 0:23d1f73bf130 1032 #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
vladvana 0:23d1f73bf130 1033 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
vladvana 0:23d1f73bf130 1034
vladvana 0:23d1f73bf130 1035 #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
vladvana 0:23d1f73bf130 1036 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
vladvana 0:23d1f73bf130 1037
vladvana 0:23d1f73bf130 1038 #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
vladvana 0:23d1f73bf130 1039 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
vladvana 0:23d1f73bf130 1040
vladvana 0:23d1f73bf130 1041 #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
vladvana 0:23d1f73bf130 1042 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
vladvana 0:23d1f73bf130 1043
vladvana 0:23d1f73bf130 1044 #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
vladvana 0:23d1f73bf130 1045 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
vladvana 0:23d1f73bf130 1046
vladvana 0:23d1f73bf130 1047 #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
vladvana 0:23d1f73bf130 1048 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
vladvana 0:23d1f73bf130 1049
vladvana 0:23d1f73bf130 1050 #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
vladvana 0:23d1f73bf130 1051 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
vladvana 0:23d1f73bf130 1052
vladvana 0:23d1f73bf130 1053 /* TPI ITATBCTR0 Register Definitions */
vladvana 0:23d1f73bf130 1054 #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
vladvana 0:23d1f73bf130 1055 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
vladvana 0:23d1f73bf130 1056
vladvana 0:23d1f73bf130 1057 /* TPI Integration Mode Control Register Definitions */
vladvana 0:23d1f73bf130 1058 #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
vladvana 0:23d1f73bf130 1059 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
vladvana 0:23d1f73bf130 1060
vladvana 0:23d1f73bf130 1061 /* TPI DEVID Register Definitions */
vladvana 0:23d1f73bf130 1062 #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
vladvana 0:23d1f73bf130 1063 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
vladvana 0:23d1f73bf130 1064
vladvana 0:23d1f73bf130 1065 #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
vladvana 0:23d1f73bf130 1066 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
vladvana 0:23d1f73bf130 1067
vladvana 0:23d1f73bf130 1068 #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
vladvana 0:23d1f73bf130 1069 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
vladvana 0:23d1f73bf130 1070
vladvana 0:23d1f73bf130 1071 #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
vladvana 0:23d1f73bf130 1072 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
vladvana 0:23d1f73bf130 1073
vladvana 0:23d1f73bf130 1074 #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
vladvana 0:23d1f73bf130 1075 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
vladvana 0:23d1f73bf130 1076
vladvana 0:23d1f73bf130 1077 #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
vladvana 0:23d1f73bf130 1078 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
vladvana 0:23d1f73bf130 1079
vladvana 0:23d1f73bf130 1080 /* TPI DEVTYPE Register Definitions */
vladvana 0:23d1f73bf130 1081 #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
vladvana 0:23d1f73bf130 1082 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
vladvana 0:23d1f73bf130 1083
vladvana 0:23d1f73bf130 1084 #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
vladvana 0:23d1f73bf130 1085 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
vladvana 0:23d1f73bf130 1086
vladvana 0:23d1f73bf130 1087 /*@}*/ /* end of group CMSIS_TPI */
vladvana 0:23d1f73bf130 1088
vladvana 0:23d1f73bf130 1089
vladvana 0:23d1f73bf130 1090 #if (__MPU_PRESENT == 1)
vladvana 0:23d1f73bf130 1091 /** \ingroup CMSIS_core_register
vladvana 0:23d1f73bf130 1092 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
vladvana 0:23d1f73bf130 1093 \brief Type definitions for the Memory Protection Unit (MPU)
vladvana 0:23d1f73bf130 1094 @{
vladvana 0:23d1f73bf130 1095 */
vladvana 0:23d1f73bf130 1096
vladvana 0:23d1f73bf130 1097 /** \brief Structure type to access the Memory Protection Unit (MPU).
vladvana 0:23d1f73bf130 1098 */
vladvana 0:23d1f73bf130 1099 typedef struct
vladvana 0:23d1f73bf130 1100 {
vladvana 0:23d1f73bf130 1101 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
vladvana 0:23d1f73bf130 1102 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
vladvana 0:23d1f73bf130 1103 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
vladvana 0:23d1f73bf130 1104 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
vladvana 0:23d1f73bf130 1105 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
vladvana 0:23d1f73bf130 1106 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
vladvana 0:23d1f73bf130 1107 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
vladvana 0:23d1f73bf130 1108 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
vladvana 0:23d1f73bf130 1109 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
vladvana 0:23d1f73bf130 1110 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
vladvana 0:23d1f73bf130 1111 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
vladvana 0:23d1f73bf130 1112 } MPU_Type;
vladvana 0:23d1f73bf130 1113
vladvana 0:23d1f73bf130 1114 /* MPU Type Register */
vladvana 0:23d1f73bf130 1115 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
vladvana 0:23d1f73bf130 1116 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
vladvana 0:23d1f73bf130 1117
vladvana 0:23d1f73bf130 1118 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
vladvana 0:23d1f73bf130 1119 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
vladvana 0:23d1f73bf130 1120
vladvana 0:23d1f73bf130 1121 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
vladvana 0:23d1f73bf130 1122 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
vladvana 0:23d1f73bf130 1123
vladvana 0:23d1f73bf130 1124 /* MPU Control Register */
vladvana 0:23d1f73bf130 1125 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
vladvana 0:23d1f73bf130 1126 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
vladvana 0:23d1f73bf130 1127
vladvana 0:23d1f73bf130 1128 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
vladvana 0:23d1f73bf130 1129 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
vladvana 0:23d1f73bf130 1130
vladvana 0:23d1f73bf130 1131 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
vladvana 0:23d1f73bf130 1132 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
vladvana 0:23d1f73bf130 1133
vladvana 0:23d1f73bf130 1134 /* MPU Region Number Register */
vladvana 0:23d1f73bf130 1135 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
vladvana 0:23d1f73bf130 1136 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
vladvana 0:23d1f73bf130 1137
vladvana 0:23d1f73bf130 1138 /* MPU Region Base Address Register */
vladvana 0:23d1f73bf130 1139 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
vladvana 0:23d1f73bf130 1140 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
vladvana 0:23d1f73bf130 1141
vladvana 0:23d1f73bf130 1142 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
vladvana 0:23d1f73bf130 1143 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
vladvana 0:23d1f73bf130 1144
vladvana 0:23d1f73bf130 1145 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
vladvana 0:23d1f73bf130 1146 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
vladvana 0:23d1f73bf130 1147
vladvana 0:23d1f73bf130 1148 /* MPU Region Attribute and Size Register */
vladvana 0:23d1f73bf130 1149 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
vladvana 0:23d1f73bf130 1150 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
vladvana 0:23d1f73bf130 1151
vladvana 0:23d1f73bf130 1152 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
vladvana 0:23d1f73bf130 1153 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
vladvana 0:23d1f73bf130 1154
vladvana 0:23d1f73bf130 1155 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
vladvana 0:23d1f73bf130 1156 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
vladvana 0:23d1f73bf130 1157
vladvana 0:23d1f73bf130 1158 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
vladvana 0:23d1f73bf130 1159 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
vladvana 0:23d1f73bf130 1160
vladvana 0:23d1f73bf130 1161 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
vladvana 0:23d1f73bf130 1162 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
vladvana 0:23d1f73bf130 1163
vladvana 0:23d1f73bf130 1164 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
vladvana 0:23d1f73bf130 1165 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
vladvana 0:23d1f73bf130 1166
vladvana 0:23d1f73bf130 1167 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
vladvana 0:23d1f73bf130 1168 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
vladvana 0:23d1f73bf130 1169
vladvana 0:23d1f73bf130 1170 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
vladvana 0:23d1f73bf130 1171 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
vladvana 0:23d1f73bf130 1172
vladvana 0:23d1f73bf130 1173 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
vladvana 0:23d1f73bf130 1174 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
vladvana 0:23d1f73bf130 1175
vladvana 0:23d1f73bf130 1176 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
vladvana 0:23d1f73bf130 1177 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
vladvana 0:23d1f73bf130 1178
vladvana 0:23d1f73bf130 1179 /*@} end of group CMSIS_MPU */
vladvana 0:23d1f73bf130 1180 #endif
vladvana 0:23d1f73bf130 1181
vladvana 0:23d1f73bf130 1182
vladvana 0:23d1f73bf130 1183 /** \ingroup CMSIS_core_register
vladvana 0:23d1f73bf130 1184 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
vladvana 0:23d1f73bf130 1185 \brief Type definitions for the Core Debug Registers
vladvana 0:23d1f73bf130 1186 @{
vladvana 0:23d1f73bf130 1187 */
vladvana 0:23d1f73bf130 1188
vladvana 0:23d1f73bf130 1189 /** \brief Structure type to access the Core Debug Register (CoreDebug).
vladvana 0:23d1f73bf130 1190 */
vladvana 0:23d1f73bf130 1191 typedef struct
vladvana 0:23d1f73bf130 1192 {
vladvana 0:23d1f73bf130 1193 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
vladvana 0:23d1f73bf130 1194 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
vladvana 0:23d1f73bf130 1195 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
vladvana 0:23d1f73bf130 1196 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
vladvana 0:23d1f73bf130 1197 } CoreDebug_Type;
vladvana 0:23d1f73bf130 1198
vladvana 0:23d1f73bf130 1199 /* Debug Halting Control and Status Register */
vladvana 0:23d1f73bf130 1200 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
vladvana 0:23d1f73bf130 1201 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
vladvana 0:23d1f73bf130 1202
vladvana 0:23d1f73bf130 1203 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
vladvana 0:23d1f73bf130 1204 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
vladvana 0:23d1f73bf130 1205
vladvana 0:23d1f73bf130 1206 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
vladvana 0:23d1f73bf130 1207 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
vladvana 0:23d1f73bf130 1208
vladvana 0:23d1f73bf130 1209 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
vladvana 0:23d1f73bf130 1210 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
vladvana 0:23d1f73bf130 1211
vladvana 0:23d1f73bf130 1212 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
vladvana 0:23d1f73bf130 1213 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
vladvana 0:23d1f73bf130 1214
vladvana 0:23d1f73bf130 1215 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
vladvana 0:23d1f73bf130 1216 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
vladvana 0:23d1f73bf130 1217
vladvana 0:23d1f73bf130 1218 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
vladvana 0:23d1f73bf130 1219 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
vladvana 0:23d1f73bf130 1220
vladvana 0:23d1f73bf130 1221 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
vladvana 0:23d1f73bf130 1222 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
vladvana 0:23d1f73bf130 1223
vladvana 0:23d1f73bf130 1224 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
vladvana 0:23d1f73bf130 1225 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
vladvana 0:23d1f73bf130 1226
vladvana 0:23d1f73bf130 1227 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
vladvana 0:23d1f73bf130 1228 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
vladvana 0:23d1f73bf130 1229
vladvana 0:23d1f73bf130 1230 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
vladvana 0:23d1f73bf130 1231 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
vladvana 0:23d1f73bf130 1232
vladvana 0:23d1f73bf130 1233 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
vladvana 0:23d1f73bf130 1234 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
vladvana 0:23d1f73bf130 1235
vladvana 0:23d1f73bf130 1236 /* Debug Core Register Selector Register */
vladvana 0:23d1f73bf130 1237 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
vladvana 0:23d1f73bf130 1238 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
vladvana 0:23d1f73bf130 1239
vladvana 0:23d1f73bf130 1240 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
vladvana 0:23d1f73bf130 1241 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
vladvana 0:23d1f73bf130 1242
vladvana 0:23d1f73bf130 1243 /* Debug Exception and Monitor Control Register */
vladvana 0:23d1f73bf130 1244 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
vladvana 0:23d1f73bf130 1245 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
vladvana 0:23d1f73bf130 1246
vladvana 0:23d1f73bf130 1247 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
vladvana 0:23d1f73bf130 1248 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
vladvana 0:23d1f73bf130 1249
vladvana 0:23d1f73bf130 1250 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
vladvana 0:23d1f73bf130 1251 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
vladvana 0:23d1f73bf130 1252
vladvana 0:23d1f73bf130 1253 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
vladvana 0:23d1f73bf130 1254 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
vladvana 0:23d1f73bf130 1255
vladvana 0:23d1f73bf130 1256 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
vladvana 0:23d1f73bf130 1257 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
vladvana 0:23d1f73bf130 1258
vladvana 0:23d1f73bf130 1259 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
vladvana 0:23d1f73bf130 1260 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
vladvana 0:23d1f73bf130 1261
vladvana 0:23d1f73bf130 1262 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
vladvana 0:23d1f73bf130 1263 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
vladvana 0:23d1f73bf130 1264
vladvana 0:23d1f73bf130 1265 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
vladvana 0:23d1f73bf130 1266 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
vladvana 0:23d1f73bf130 1267
vladvana 0:23d1f73bf130 1268 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
vladvana 0:23d1f73bf130 1269 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
vladvana 0:23d1f73bf130 1270
vladvana 0:23d1f73bf130 1271 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
vladvana 0:23d1f73bf130 1272 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
vladvana 0:23d1f73bf130 1273
vladvana 0:23d1f73bf130 1274 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
vladvana 0:23d1f73bf130 1275 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
vladvana 0:23d1f73bf130 1276
vladvana 0:23d1f73bf130 1277 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
vladvana 0:23d1f73bf130 1278 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
vladvana 0:23d1f73bf130 1279
vladvana 0:23d1f73bf130 1280 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
vladvana 0:23d1f73bf130 1281 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
vladvana 0:23d1f73bf130 1282
vladvana 0:23d1f73bf130 1283 /*@} end of group CMSIS_CoreDebug */
vladvana 0:23d1f73bf130 1284
vladvana 0:23d1f73bf130 1285
vladvana 0:23d1f73bf130 1286 /** \ingroup CMSIS_core_register
vladvana 0:23d1f73bf130 1287 \defgroup CMSIS_core_base Core Definitions
vladvana 0:23d1f73bf130 1288 \brief Definitions for base addresses, unions, and structures.
vladvana 0:23d1f73bf130 1289 @{
vladvana 0:23d1f73bf130 1290 */
vladvana 0:23d1f73bf130 1291
vladvana 0:23d1f73bf130 1292 /* Memory mapping of Cortex-M3 Hardware */
vladvana 0:23d1f73bf130 1293 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
vladvana 0:23d1f73bf130 1294 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
vladvana 0:23d1f73bf130 1295 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
vladvana 0:23d1f73bf130 1296 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
vladvana 0:23d1f73bf130 1297 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
vladvana 0:23d1f73bf130 1298 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
vladvana 0:23d1f73bf130 1299 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
vladvana 0:23d1f73bf130 1300 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
vladvana 0:23d1f73bf130 1301
vladvana 0:23d1f73bf130 1302 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
vladvana 0:23d1f73bf130 1303 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
vladvana 0:23d1f73bf130 1304 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
vladvana 0:23d1f73bf130 1305 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
vladvana 0:23d1f73bf130 1306 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
vladvana 0:23d1f73bf130 1307 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
vladvana 0:23d1f73bf130 1308 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
vladvana 0:23d1f73bf130 1309 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
vladvana 0:23d1f73bf130 1310
vladvana 0:23d1f73bf130 1311 #if (__MPU_PRESENT == 1)
vladvana 0:23d1f73bf130 1312 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
vladvana 0:23d1f73bf130 1313 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
vladvana 0:23d1f73bf130 1314 #endif
vladvana 0:23d1f73bf130 1315
vladvana 0:23d1f73bf130 1316 /*@} */
vladvana 0:23d1f73bf130 1317
vladvana 0:23d1f73bf130 1318
vladvana 0:23d1f73bf130 1319
vladvana 0:23d1f73bf130 1320 /*******************************************************************************
vladvana 0:23d1f73bf130 1321 * Hardware Abstraction Layer
vladvana 0:23d1f73bf130 1322 Core Function Interface contains:
vladvana 0:23d1f73bf130 1323 - Core NVIC Functions
vladvana 0:23d1f73bf130 1324 - Core SysTick Functions
vladvana 0:23d1f73bf130 1325 - Core Debug Functions
vladvana 0:23d1f73bf130 1326 - Core Register Access Functions
vladvana 0:23d1f73bf130 1327 ******************************************************************************/
vladvana 0:23d1f73bf130 1328 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
vladvana 0:23d1f73bf130 1329 */
vladvana 0:23d1f73bf130 1330
vladvana 0:23d1f73bf130 1331
vladvana 0:23d1f73bf130 1332
vladvana 0:23d1f73bf130 1333 /* ########################## NVIC functions #################################### */
vladvana 0:23d1f73bf130 1334 /** \ingroup CMSIS_Core_FunctionInterface
vladvana 0:23d1f73bf130 1335 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
vladvana 0:23d1f73bf130 1336 \brief Functions that manage interrupts and exceptions via the NVIC.
vladvana 0:23d1f73bf130 1337 @{
vladvana 0:23d1f73bf130 1338 */
vladvana 0:23d1f73bf130 1339
vladvana 0:23d1f73bf130 1340 /** \brief Set Priority Grouping
vladvana 0:23d1f73bf130 1341
vladvana 0:23d1f73bf130 1342 The function sets the priority grouping field using the required unlock sequence.
vladvana 0:23d1f73bf130 1343 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
vladvana 0:23d1f73bf130 1344 Only values from 0..7 are used.
vladvana 0:23d1f73bf130 1345 In case of a conflict between priority grouping and available
vladvana 0:23d1f73bf130 1346 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
vladvana 0:23d1f73bf130 1347
vladvana 0:23d1f73bf130 1348 \param [in] PriorityGroup Priority grouping field.
vladvana 0:23d1f73bf130 1349 */
vladvana 0:23d1f73bf130 1350 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
vladvana 0:23d1f73bf130 1351 {
vladvana 0:23d1f73bf130 1352 uint32_t reg_value;
vladvana 0:23d1f73bf130 1353 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
vladvana 0:23d1f73bf130 1354
vladvana 0:23d1f73bf130 1355 reg_value = SCB->AIRCR; /* read old register configuration */
vladvana 0:23d1f73bf130 1356 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
vladvana 0:23d1f73bf130 1357 reg_value = (reg_value |
vladvana 0:23d1f73bf130 1358 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
vladvana 0:23d1f73bf130 1359 (PriorityGroupTmp << 8) ); /* Insert write key and priorty group */
vladvana 0:23d1f73bf130 1360 SCB->AIRCR = reg_value;
vladvana 0:23d1f73bf130 1361 }
vladvana 0:23d1f73bf130 1362
vladvana 0:23d1f73bf130 1363
vladvana 0:23d1f73bf130 1364 /** \brief Get Priority Grouping
vladvana 0:23d1f73bf130 1365
vladvana 0:23d1f73bf130 1366 The function reads the priority grouping field from the NVIC Interrupt Controller.
vladvana 0:23d1f73bf130 1367
vladvana 0:23d1f73bf130 1368 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
vladvana 0:23d1f73bf130 1369 */
vladvana 0:23d1f73bf130 1370 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
vladvana 0:23d1f73bf130 1371 {
vladvana 0:23d1f73bf130 1372 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
vladvana 0:23d1f73bf130 1373 }
vladvana 0:23d1f73bf130 1374
vladvana 0:23d1f73bf130 1375
vladvana 0:23d1f73bf130 1376 /** \brief Enable External Interrupt
vladvana 0:23d1f73bf130 1377
vladvana 0:23d1f73bf130 1378 The function enables a device-specific interrupt in the NVIC interrupt controller.
vladvana 0:23d1f73bf130 1379
vladvana 0:23d1f73bf130 1380 \param [in] IRQn External interrupt number. Value cannot be negative.
vladvana 0:23d1f73bf130 1381 */
vladvana 0:23d1f73bf130 1382 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
vladvana 0:23d1f73bf130 1383 {
vladvana 0:23d1f73bf130 1384 NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
vladvana 0:23d1f73bf130 1385 }
vladvana 0:23d1f73bf130 1386
vladvana 0:23d1f73bf130 1387
vladvana 0:23d1f73bf130 1388 /** \brief Disable External Interrupt
vladvana 0:23d1f73bf130 1389
vladvana 0:23d1f73bf130 1390 The function disables a device-specific interrupt in the NVIC interrupt controller.
vladvana 0:23d1f73bf130 1391
vladvana 0:23d1f73bf130 1392 \param [in] IRQn External interrupt number. Value cannot be negative.
vladvana 0:23d1f73bf130 1393 */
vladvana 0:23d1f73bf130 1394 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
vladvana 0:23d1f73bf130 1395 {
vladvana 0:23d1f73bf130 1396 NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
vladvana 0:23d1f73bf130 1397 }
vladvana 0:23d1f73bf130 1398
vladvana 0:23d1f73bf130 1399
vladvana 0:23d1f73bf130 1400 /** \brief Get Pending Interrupt
vladvana 0:23d1f73bf130 1401
vladvana 0:23d1f73bf130 1402 The function reads the pending register in the NVIC and returns the pending bit
vladvana 0:23d1f73bf130 1403 for the specified interrupt.
vladvana 0:23d1f73bf130 1404
vladvana 0:23d1f73bf130 1405 \param [in] IRQn Interrupt number.
vladvana 0:23d1f73bf130 1406
vladvana 0:23d1f73bf130 1407 \return 0 Interrupt status is not pending.
vladvana 0:23d1f73bf130 1408 \return 1 Interrupt status is pending.
vladvana 0:23d1f73bf130 1409 */
vladvana 0:23d1f73bf130 1410 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
vladvana 0:23d1f73bf130 1411 {
vladvana 0:23d1f73bf130 1412 return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
vladvana 0:23d1f73bf130 1413 }
vladvana 0:23d1f73bf130 1414
vladvana 0:23d1f73bf130 1415
vladvana 0:23d1f73bf130 1416 /** \brief Set Pending Interrupt
vladvana 0:23d1f73bf130 1417
vladvana 0:23d1f73bf130 1418 The function sets the pending bit of an external interrupt.
vladvana 0:23d1f73bf130 1419
vladvana 0:23d1f73bf130 1420 \param [in] IRQn Interrupt number. Value cannot be negative.
vladvana 0:23d1f73bf130 1421 */
vladvana 0:23d1f73bf130 1422 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
vladvana 0:23d1f73bf130 1423 {
vladvana 0:23d1f73bf130 1424 NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
vladvana 0:23d1f73bf130 1425 }
vladvana 0:23d1f73bf130 1426
vladvana 0:23d1f73bf130 1427
vladvana 0:23d1f73bf130 1428 /** \brief Clear Pending Interrupt
vladvana 0:23d1f73bf130 1429
vladvana 0:23d1f73bf130 1430 The function clears the pending bit of an external interrupt.
vladvana 0:23d1f73bf130 1431
vladvana 0:23d1f73bf130 1432 \param [in] IRQn External interrupt number. Value cannot be negative.
vladvana 0:23d1f73bf130 1433 */
vladvana 0:23d1f73bf130 1434 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
vladvana 0:23d1f73bf130 1435 {
vladvana 0:23d1f73bf130 1436 NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
vladvana 0:23d1f73bf130 1437 }
vladvana 0:23d1f73bf130 1438
vladvana 0:23d1f73bf130 1439
vladvana 0:23d1f73bf130 1440 /** \brief Get Active Interrupt
vladvana 0:23d1f73bf130 1441
vladvana 0:23d1f73bf130 1442 The function reads the active register in NVIC and returns the active bit.
vladvana 0:23d1f73bf130 1443
vladvana 0:23d1f73bf130 1444 \param [in] IRQn Interrupt number.
vladvana 0:23d1f73bf130 1445
vladvana 0:23d1f73bf130 1446 \return 0 Interrupt status is not active.
vladvana 0:23d1f73bf130 1447 \return 1 Interrupt status is active.
vladvana 0:23d1f73bf130 1448 */
vladvana 0:23d1f73bf130 1449 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
vladvana 0:23d1f73bf130 1450 {
vladvana 0:23d1f73bf130 1451 return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
vladvana 0:23d1f73bf130 1452 }
vladvana 0:23d1f73bf130 1453
vladvana 0:23d1f73bf130 1454
vladvana 0:23d1f73bf130 1455 /** \brief Set Interrupt Priority
vladvana 0:23d1f73bf130 1456
vladvana 0:23d1f73bf130 1457 The function sets the priority of an interrupt.
vladvana 0:23d1f73bf130 1458
vladvana 0:23d1f73bf130 1459 \note The priority cannot be set for every core interrupt.
vladvana 0:23d1f73bf130 1460
vladvana 0:23d1f73bf130 1461 \param [in] IRQn Interrupt number.
vladvana 0:23d1f73bf130 1462 \param [in] priority Priority to set.
vladvana 0:23d1f73bf130 1463 */
vladvana 0:23d1f73bf130 1464 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
vladvana 0:23d1f73bf130 1465 {
vladvana 0:23d1f73bf130 1466 if((int32_t)IRQn < 0) {
vladvana 0:23d1f73bf130 1467 SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
vladvana 0:23d1f73bf130 1468 }
vladvana 0:23d1f73bf130 1469 else {
vladvana 0:23d1f73bf130 1470 NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
vladvana 0:23d1f73bf130 1471 }
vladvana 0:23d1f73bf130 1472 }
vladvana 0:23d1f73bf130 1473
vladvana 0:23d1f73bf130 1474
vladvana 0:23d1f73bf130 1475 /** \brief Get Interrupt Priority
vladvana 0:23d1f73bf130 1476
vladvana 0:23d1f73bf130 1477 The function reads the priority of an interrupt. The interrupt
vladvana 0:23d1f73bf130 1478 number can be positive to specify an external (device specific)
vladvana 0:23d1f73bf130 1479 interrupt, or negative to specify an internal (core) interrupt.
vladvana 0:23d1f73bf130 1480
vladvana 0:23d1f73bf130 1481
vladvana 0:23d1f73bf130 1482 \param [in] IRQn Interrupt number.
vladvana 0:23d1f73bf130 1483 \return Interrupt Priority. Value is aligned automatically to the implemented
vladvana 0:23d1f73bf130 1484 priority bits of the microcontroller.
vladvana 0:23d1f73bf130 1485 */
vladvana 0:23d1f73bf130 1486 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
vladvana 0:23d1f73bf130 1487 {
vladvana 0:23d1f73bf130 1488
vladvana 0:23d1f73bf130 1489 if((int32_t)IRQn < 0) {
vladvana 0:23d1f73bf130 1490 return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
vladvana 0:23d1f73bf130 1491 }
vladvana 0:23d1f73bf130 1492 else {
vladvana 0:23d1f73bf130 1493 return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));
vladvana 0:23d1f73bf130 1494 }
vladvana 0:23d1f73bf130 1495 }
vladvana 0:23d1f73bf130 1496
vladvana 0:23d1f73bf130 1497
vladvana 0:23d1f73bf130 1498 /** \brief Encode Priority
vladvana 0:23d1f73bf130 1499
vladvana 0:23d1f73bf130 1500 The function encodes the priority for an interrupt with the given priority group,
vladvana 0:23d1f73bf130 1501 preemptive priority value, and subpriority value.
vladvana 0:23d1f73bf130 1502 In case of a conflict between priority grouping and available
vladvana 0:23d1f73bf130 1503 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
vladvana 0:23d1f73bf130 1504
vladvana 0:23d1f73bf130 1505 \param [in] PriorityGroup Used priority group.
vladvana 0:23d1f73bf130 1506 \param [in] PreemptPriority Preemptive priority value (starting from 0).
vladvana 0:23d1f73bf130 1507 \param [in] SubPriority Subpriority value (starting from 0).
vladvana 0:23d1f73bf130 1508 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
vladvana 0:23d1f73bf130 1509 */
vladvana 0:23d1f73bf130 1510 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
vladvana 0:23d1f73bf130 1511 {
vladvana 0:23d1f73bf130 1512 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
vladvana 0:23d1f73bf130 1513 uint32_t PreemptPriorityBits;
vladvana 0:23d1f73bf130 1514 uint32_t SubPriorityBits;
vladvana 0:23d1f73bf130 1515
vladvana 0:23d1f73bf130 1516 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
vladvana 0:23d1f73bf130 1517 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
vladvana 0:23d1f73bf130 1518
vladvana 0:23d1f73bf130 1519 return (
vladvana 0:23d1f73bf130 1520 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
vladvana 0:23d1f73bf130 1521 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
vladvana 0:23d1f73bf130 1522 );
vladvana 0:23d1f73bf130 1523 }
vladvana 0:23d1f73bf130 1524
vladvana 0:23d1f73bf130 1525
vladvana 0:23d1f73bf130 1526 /** \brief Decode Priority
vladvana 0:23d1f73bf130 1527
vladvana 0:23d1f73bf130 1528 The function decodes an interrupt priority value with a given priority group to
vladvana 0:23d1f73bf130 1529 preemptive priority value and subpriority value.
vladvana 0:23d1f73bf130 1530 In case of a conflict between priority grouping and available
vladvana 0:23d1f73bf130 1531 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
vladvana 0:23d1f73bf130 1532
vladvana 0:23d1f73bf130 1533 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
vladvana 0:23d1f73bf130 1534 \param [in] PriorityGroup Used priority group.
vladvana 0:23d1f73bf130 1535 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
vladvana 0:23d1f73bf130 1536 \param [out] pSubPriority Subpriority value (starting from 0).
vladvana 0:23d1f73bf130 1537 */
vladvana 0:23d1f73bf130 1538 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
vladvana 0:23d1f73bf130 1539 {
vladvana 0:23d1f73bf130 1540 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
vladvana 0:23d1f73bf130 1541 uint32_t PreemptPriorityBits;
vladvana 0:23d1f73bf130 1542 uint32_t SubPriorityBits;
vladvana 0:23d1f73bf130 1543
vladvana 0:23d1f73bf130 1544 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
vladvana 0:23d1f73bf130 1545 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
vladvana 0:23d1f73bf130 1546
vladvana 0:23d1f73bf130 1547 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
vladvana 0:23d1f73bf130 1548 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
vladvana 0:23d1f73bf130 1549 }
vladvana 0:23d1f73bf130 1550
vladvana 0:23d1f73bf130 1551
vladvana 0:23d1f73bf130 1552 /** \brief System Reset
vladvana 0:23d1f73bf130 1553
vladvana 0:23d1f73bf130 1554 The function initiates a system reset request to reset the MCU.
vladvana 0:23d1f73bf130 1555 */
vladvana 0:23d1f73bf130 1556 __STATIC_INLINE void NVIC_SystemReset(void)
vladvana 0:23d1f73bf130 1557 {
vladvana 0:23d1f73bf130 1558 __DSB(); /* Ensure all outstanding memory accesses included
vladvana 0:23d1f73bf130 1559 buffered write are completed before reset */
vladvana 0:23d1f73bf130 1560 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
vladvana 0:23d1f73bf130 1561 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
vladvana 0:23d1f73bf130 1562 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
vladvana 0:23d1f73bf130 1563 __DSB(); /* Ensure completion of memory access */
vladvana 0:23d1f73bf130 1564 while(1) { __NOP(); } /* wait until reset */
vladvana 0:23d1f73bf130 1565 }
vladvana 0:23d1f73bf130 1566
vladvana 0:23d1f73bf130 1567 /*@} end of CMSIS_Core_NVICFunctions */
vladvana 0:23d1f73bf130 1568
vladvana 0:23d1f73bf130 1569
vladvana 0:23d1f73bf130 1570
vladvana 0:23d1f73bf130 1571 /* ################################## SysTick function ############################################ */
vladvana 0:23d1f73bf130 1572 /** \ingroup CMSIS_Core_FunctionInterface
vladvana 0:23d1f73bf130 1573 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
vladvana 0:23d1f73bf130 1574 \brief Functions that configure the System.
vladvana 0:23d1f73bf130 1575 @{
vladvana 0:23d1f73bf130 1576 */
vladvana 0:23d1f73bf130 1577
vladvana 0:23d1f73bf130 1578 #if (__Vendor_SysTickConfig == 0)
vladvana 0:23d1f73bf130 1579
vladvana 0:23d1f73bf130 1580 /** \brief System Tick Configuration
vladvana 0:23d1f73bf130 1581
vladvana 0:23d1f73bf130 1582 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
vladvana 0:23d1f73bf130 1583 Counter is in free running mode to generate periodic interrupts.
vladvana 0:23d1f73bf130 1584
vladvana 0:23d1f73bf130 1585 \param [in] ticks Number of ticks between two interrupts.
vladvana 0:23d1f73bf130 1586
vladvana 0:23d1f73bf130 1587 \return 0 Function succeeded.
vladvana 0:23d1f73bf130 1588 \return 1 Function failed.
vladvana 0:23d1f73bf130 1589
vladvana 0:23d1f73bf130 1590 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
vladvana 0:23d1f73bf130 1591 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
vladvana 0:23d1f73bf130 1592 must contain a vendor-specific implementation of this function.
vladvana 0:23d1f73bf130 1593
vladvana 0:23d1f73bf130 1594 */
vladvana 0:23d1f73bf130 1595 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
vladvana 0:23d1f73bf130 1596 {
vladvana 0:23d1f73bf130 1597 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
vladvana 0:23d1f73bf130 1598
vladvana 0:23d1f73bf130 1599 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
vladvana 0:23d1f73bf130 1600 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
vladvana 0:23d1f73bf130 1601 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
vladvana 0:23d1f73bf130 1602 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
vladvana 0:23d1f73bf130 1603 SysTick_CTRL_TICKINT_Msk |
vladvana 0:23d1f73bf130 1604 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
vladvana 0:23d1f73bf130 1605 return (0UL); /* Function successful */
vladvana 0:23d1f73bf130 1606 }
vladvana 0:23d1f73bf130 1607
vladvana 0:23d1f73bf130 1608 #endif
vladvana 0:23d1f73bf130 1609
vladvana 0:23d1f73bf130 1610 /*@} end of CMSIS_Core_SysTickFunctions */
vladvana 0:23d1f73bf130 1611
vladvana 0:23d1f73bf130 1612
vladvana 0:23d1f73bf130 1613
vladvana 0:23d1f73bf130 1614 /* ##################################### Debug In/Output function ########################################### */
vladvana 0:23d1f73bf130 1615 /** \ingroup CMSIS_Core_FunctionInterface
vladvana 0:23d1f73bf130 1616 \defgroup CMSIS_core_DebugFunctions ITM Functions
vladvana 0:23d1f73bf130 1617 \brief Functions that access the ITM debug interface.
vladvana 0:23d1f73bf130 1618 @{
vladvana 0:23d1f73bf130 1619 */
vladvana 0:23d1f73bf130 1620
vladvana 0:23d1f73bf130 1621 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
vladvana 0:23d1f73bf130 1622 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
vladvana 0:23d1f73bf130 1623
vladvana 0:23d1f73bf130 1624
vladvana 0:23d1f73bf130 1625 /** \brief ITM Send Character
vladvana 0:23d1f73bf130 1626
vladvana 0:23d1f73bf130 1627 The function transmits a character via the ITM channel 0, and
vladvana 0:23d1f73bf130 1628 \li Just returns when no debugger is connected that has booked the output.
vladvana 0:23d1f73bf130 1629 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
vladvana 0:23d1f73bf130 1630
vladvana 0:23d1f73bf130 1631 \param [in] ch Character to transmit.
vladvana 0:23d1f73bf130 1632
vladvana 0:23d1f73bf130 1633 \returns Character to transmit.
vladvana 0:23d1f73bf130 1634 */
vladvana 0:23d1f73bf130 1635 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
vladvana 0:23d1f73bf130 1636 {
vladvana 0:23d1f73bf130 1637 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
vladvana 0:23d1f73bf130 1638 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
vladvana 0:23d1f73bf130 1639 {
vladvana 0:23d1f73bf130 1640 while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
vladvana 0:23d1f73bf130 1641 ITM->PORT[0].u8 = (uint8_t)ch;
vladvana 0:23d1f73bf130 1642 }
vladvana 0:23d1f73bf130 1643 return (ch);
vladvana 0:23d1f73bf130 1644 }
vladvana 0:23d1f73bf130 1645
vladvana 0:23d1f73bf130 1646
vladvana 0:23d1f73bf130 1647 /** \brief ITM Receive Character
vladvana 0:23d1f73bf130 1648
vladvana 0:23d1f73bf130 1649 The function inputs a character via the external variable \ref ITM_RxBuffer.
vladvana 0:23d1f73bf130 1650
vladvana 0:23d1f73bf130 1651 \return Received character.
vladvana 0:23d1f73bf130 1652 \return -1 No character pending.
vladvana 0:23d1f73bf130 1653 */
vladvana 0:23d1f73bf130 1654 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
vladvana 0:23d1f73bf130 1655 int32_t ch = -1; /* no character available */
vladvana 0:23d1f73bf130 1656
vladvana 0:23d1f73bf130 1657 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
vladvana 0:23d1f73bf130 1658 ch = ITM_RxBuffer;
vladvana 0:23d1f73bf130 1659 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
vladvana 0:23d1f73bf130 1660 }
vladvana 0:23d1f73bf130 1661
vladvana 0:23d1f73bf130 1662 return (ch);
vladvana 0:23d1f73bf130 1663 }
vladvana 0:23d1f73bf130 1664
vladvana 0:23d1f73bf130 1665
vladvana 0:23d1f73bf130 1666 /** \brief ITM Check Character
vladvana 0:23d1f73bf130 1667
vladvana 0:23d1f73bf130 1668 The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
vladvana 0:23d1f73bf130 1669
vladvana 0:23d1f73bf130 1670 \return 0 No character available.
vladvana 0:23d1f73bf130 1671 \return 1 Character available.
vladvana 0:23d1f73bf130 1672 */
vladvana 0:23d1f73bf130 1673 __STATIC_INLINE int32_t ITM_CheckChar (void) {
vladvana 0:23d1f73bf130 1674
vladvana 0:23d1f73bf130 1675 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
vladvana 0:23d1f73bf130 1676 return (0); /* no character available */
vladvana 0:23d1f73bf130 1677 } else {
vladvana 0:23d1f73bf130 1678 return (1); /* character available */
vladvana 0:23d1f73bf130 1679 }
vladvana 0:23d1f73bf130 1680 }
vladvana 0:23d1f73bf130 1681
vladvana 0:23d1f73bf130 1682 /*@} end of CMSIS_core_DebugFunctions */
vladvana 0:23d1f73bf130 1683
vladvana 0:23d1f73bf130 1684
vladvana 0:23d1f73bf130 1685
vladvana 0:23d1f73bf130 1686
vladvana 0:23d1f73bf130 1687 #ifdef __cplusplus
vladvana 0:23d1f73bf130 1688 }
vladvana 0:23d1f73bf130 1689 #endif
vladvana 0:23d1f73bf130 1690
vladvana 0:23d1f73bf130 1691 #endif /* __CORE_CM3_H_DEPENDANT */
vladvana 0:23d1f73bf130 1692
vladvana 0:23d1f73bf130 1693 #endif /* __CMSIS_GENERIC */